Semiconductor module

Abstract

To reduce the size of a module and improve the reliability of inspecting at mounting parts.SOLUTION: A semiconductor module 10 includes an insulating substrate 14, semiconductor chips 16a and 16b, and a printed board 15. The printed board 15 includes a multilayer structure in which an insulating layer 18 and a wiring layer are stacked, and includes a lowermost wiring layer formed in a lowermost layer and bonded to an upper surface of the insulating substrate 14, and an uppermost wiring layer formed in an uppermost layer and including semiconductor chip mount wiring layers 51b and 61b where the semiconductor chips 16a and 16b are mounted. Just under the semiconductor chips 16a and 16b, metal inlays 17a and 17b electrically connected to the semiconductor chips 16a and 16b are embedded.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor module. [Background technology]

[0002] In a semiconductor module, electronic components are mounted on a printed circuit board having multiple laminated conductor layers (see, for example, Patent Document 1). Also, a multilayer wiring structure is provided on a glass epoxy substrate, and electrodes are provided on an insulating layer that forms the surface layer of the multilayer wiring structure (see, for example, Patent Document 2). Furthermore, printed wiring that forms a high-frequency circuit is formed on the front surface, back surface, interior, etc. of the printed circuit board, and copper inlays are placed in openings in the printed circuit board (see, for example, Patent Document 3).

[0003] Also, a copper inlay is fitted in the thickness direction of a substrate having an inner layer sandwiched between a first front surface and a second front surface (see, for example, Patent Document 4). Furthermore, a copper inlay is provided on the printed circuit board below the semiconductor chip, and an insulating sheet is laid between the printed circuit board and the cooler (see, for example, Patent Document 5). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-082652 [Patent Document 2] Japanese Patent Application Publication No. 2020-043249 [Patent Document 3] Japanese Patent Publication No. 2020-191316 [Patent Document 4] Japanese Patent Application Laid-Open No. 2017-103371 [Patent Document 5] Japanese Patent Application Publication No. 2019-009153 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to reduce the size of a module and improve the reliability of inspection during component mounting. [Means for solving the problem]

[0006] To solve the above problems, a semiconductor module is provided. The semiconductor module includes an insulating substrate, a semiconductor chip, and a wiring substrate. The wiring substrate includes a plurality of wiring layers including a bottom wiring layer formed on the bottom layer and bonded to the top surface of the insulating substrate, and a top wiring layer formed on the top layer and including a semiconductor chip mounting wiring layer to which the semiconductor chip is bonded, and an insulating layer provided between the plurality of wiring layers. A metal inlay electrically connected to the semiconductor chip is embedded between the semiconductor chip and the insulating substrate. [Effects of the Invention]

[0007] According to one aspect, it is possible to reduce the size of a module and improve the reliability of inspections when components are mounted. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a plan view of the semiconductor module. [Figure 2] FIG. 2 is a cross-sectional view of a semiconductor module. [Figure 3] FIG. 1 is a diagram illustrating an example of a circuit configuration of a semiconductor chip. [Figure 4] FIG. 2 is a diagram showing a first example of mounting a snubber circuit. [Figure 5] FIG. 10 is a diagram showing a second example of mounting a snubber circuit. [Figure 6] FIG. 2 is a diagram showing an example of a cross-sectional view of a semiconductor module according to a first reference example. [Figure 7] FIG. 10 is a diagram showing an example of a plan view of a semiconductor module according to a second reference example. [Figure 8] FIG. 10 is a diagram showing an example of a cross-sectional view of a semiconductor module according to a second reference example. [Figure 9] FIG. 10 is a plan view of a semiconductor module according to a first modified example. [Figure 10]FIG. 10 is a cross-sectional view of a semiconductor module according to a first modified example. [Figure 11] FIG. 10 is a plan view of a semiconductor module according to a second modified example. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor module according to a second modified example. [Figure 13] FIG. 10 is a cross-sectional view of a semiconductor module according to a third modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the present embodiment will be described with reference to the drawings. Note that in this specification and the drawings, elements having substantially the same functions may be denoted by the same reference numerals, and redundant description may be omitted. In the following description, "top surface" and "front surface" refer to surfaces facing upward as viewed from the paper. Similarly, "top" and "upper side" refer to directions facing upward as viewed from the paper. "bottom surface" and "rear surface" refer to surfaces facing downward as viewed from the paper. Similarly, "bottom" and "lower side" refer to directions facing downward as viewed from the paper. These directions are used in all drawings. "Top surface," "front surface," "top," "upper side," "bottom surface," "rear surface," "lower," and "lower side" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention.

[0010] The semiconductor module will be described with reference to Fig. 1 to Fig. 5. Fig. 1 is a plan view of the semiconductor module. Fig. 2 is a cross-sectional view of the semiconductor module. Fig. 2 is a cross-sectional view taken along dashed line X1-X1 in Fig. 1. Note that Fig. 1 does not show a sealing member.

[0011] The semiconductor module 10 configures a half-bridge circuit including an upper arm portion A and a lower arm portion B. The upper arm portion A of the semiconductor module 10 includes semiconductor chips 16a and 16c, and includes, as external connection terminals, a P terminal 91, an output terminal 92 (external output terminal), a gate terminal 93a, and an auxiliary source terminal 94a. The lower arm portion B of the semiconductor module 10 includes semiconductor chips 16b and 16d, and includes, as external connection terminals, an N terminal 95, a gate terminal 93b, and an auxiliary source terminal 94b.

[0012] The semiconductor chips 16a, 16b, 16c, and 16d may be mainly made of silicon carbide. Such semiconductor chips are, for example, power MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). In this case, the semiconductor chips 16a, 16b, 16c, and 16d each have a drain electrode (first electrode) as an input electrode on the back surface, a gate electrode (control electrode) on the front surface, and a source electrode (second electrode) as an output electrode.

[0013] The semiconductor chips 16a, 16b, 16c, and 16d may be primarily made of silicon. Such semiconductor chips may include RC (Reverse-Conducting)-IGBTs, which combine the functions of an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode). The semiconductor chips each have a collector electrode as an input electrode on the back surface, a gate electrode as a control electrode, and an emitter electrode as an output electrode on the front surface. In this embodiment, the semiconductor chips 16a, 16b, 16c, and 16d are power MOSFETs.

[0014] The thickness of the semiconductor chips 16a, 16b, 16c, and 16d is, for example, 80 μm or more and 500 μm or less, with an average thickness of about 200 μm. The semiconductor chips 16a, 16b, 16c, and 16d are bonded to predetermined wiring layers of the printed circuit board 15 via bonding members. The bonding members may be solder or a sintered metal material. In the following description, solder is used as the bonding member.

[0015] The semiconductor module 10 includes a heat sink (base) 11 disposed on the back surface, and a case 12 disposed on the heat sink 11 and covering the side surfaces. The semiconductor module 10 also houses components in a storage area 12a surrounded by the heat sink 11 and the case 12, and the components in the storage area 12a are sealed with a sealing member 12b. The sealing member 12b is made of a resin or a gel; for example, a silicone gel or a resin with good conformability can be used as the gel.

[0016] The case 12 is molded from a thermoplastic resin, such as polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0017] The storage area 12a is provided with components such as an insulating substrate 14, a printed circuit board 15 (wiring board) arranged on the insulating substrate 14, semiconductor chips 16a, 16b, 16c, and 16d, wires w1 to w10 and wire groups wg1 to wg4 that connect these, and metal inlays 17a and 17b embedded in the printed circuit board 15.

[0018] The heat sink 11 is a plate-like member that is substantially rectangular in plan view. The outer shape of the heat sink 11 may be slightly smaller than the outer shape of the case 12. The corners of the heat sink 11 may be round-chamfered or C-chamfered. The heat sink 11 is made of a metal that has excellent heat dissipation properties. Examples of such metals include copper, aluminum, silicon carbide, or an alloy containing at least one of these. The surface of the heat sink 11 may be plated to improve corrosion resistance. Examples of plating materials that can be used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy.

[0019] An insulating substrate 14 is joined to the front surface of heat sink 11 via solder 13a. Insulating substrate 14 includes insulating plate 14a, metal plates 14b1 and 14b2 formed on the front surface of insulating plate 14a, and metal plate 14c formed on the back surface of insulating plate 14a.

[0020] The insulating plate 14a has a rectangular shape in a plan view. The corners of the insulating plate 14a may be rounded or chamfered. The insulating plate 14a is made of ceramics with high thermal conductivity. Such ceramics are made of a material containing aluminum oxide, silicon nitride, or aluminum nitride as a main component, for example.

[0021] The metal plates 14b1 and 14b2 are made of a metal with excellent electrical conductivity. Such metals include, for example, copper, aluminum, or an alloy containing at least one of these. The metal plate 14c is made primarily of a metal with excellent thermal conductivity. Such metals include, for example, copper, aluminum, or an alloy containing at least one of these. To improve the corrosion resistance of the metal plates 14b1, 14b2, and 14c, a plating process may be performed. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0022] Meanwhile, a printed circuit board 15 having a multilayer structure (three or more layers) formed by laminating an insulating layer 18 and a plurality of wiring layers is disposed on the upper surface of the insulating substrate 14. Semiconductor chips 16a, 16b, 16c, and 16d are disposed on the upper surface of the printed circuit board 15, and metal inlays 17a and 17b (metal blocks) and the like are embedded vertically in the printed circuit board 15 between the semiconductor chips 16a, 16b, 16c, and 16d and the insulating substrate 14 for electrical connection and heat transport.

[0023] Figure 2 shows that a metal inlay 17a is embedded in the printed circuit board 15 between the semiconductor chip 16a and the insulating substrate 14, and a metal inlay 17b is embedded in the printed circuit board 15 between the semiconductor chip 16b and the insulating substrate 14.

[0024] The insulating layer 18 of the printed circuit board 15 can be made of an insulating resin. Examples of insulating resins include phenolic resin, epoxy resin, polyimide resin, and glass epoxy resin. Each wiring layer of the printed circuit board 15 is made of a metal with excellent conductivity. Examples of such metals include copper, aluminum, and alloys containing at least one of these. The surfaces of the wiring layers may be plated to improve corrosion resistance. Examples of plating materials used in this case include aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, and alloys containing at least one of these. The number, arrangement, and shape of the wiring layers can be selected appropriately based on the design.

[0025] The metal inlays 17a and 17b are made of a metal with excellent conductivity. Such metals include, for example, copper, aluminum, or an alloy containing at least one of these. The metal inlays 17a and 17b are embedded in the printed circuit board 15 by being press-fitted into through holes (not shown) provided in the printed circuit board 15. The width of the metal inlays 17a and 17b is preferably equal to or greater than the width of the semiconductor chips 16a and 16b. This allows the heat from the semiconductor chips 16a and 16b to be efficiently conducted to the insulating substrate 14.

[0026] The bottom layer of the printed circuit board 15 is a layer that connects to the insulating substrate 14. Wiring layers 19a, 19b, 19c, 21a, 21b, and 21c (bottom wiring layers) are formed on the bottom layer of the printed circuit board 15. The wiring layers 19a, 19b, and 19c are joined to the metal plate 14b1 via solder 13b. The bottom surface of the metal inlay 17a is joined to the metal plate 14b1 via solder 13b, and the side of the metal inlay 17a facing the insulating substrate 14 is electrically connected to the wiring layer 19b.

[0027] The wiring layers 21a, 21b, and 21c are joined to the metal plate 14b2 via the solder 13c. The back surfaces of the wiring layers 19a, 19b, 19c, 21b, and 21c are joined to the upper surface of the insulating substrate 14. The back surface of the metal inlay 17b is joined to the metal plate 14b2 via the solder 13c, and the lower side surface of the metal inlay 17b is electrically connected to the wiring layer 21b.

[0028] The number of inner layers varies depending on the complexity of the wiring layers and the magnitude of the main current. Field vias (conductive vias) are used to connect the inner wiring layers.

[0029] Wiring layers 31a, 31b, 32a, 32b, 41a, 41b, 42a, and 42b (inner wiring layers) are formed in the inner layers of the printed circuit board 15. The wiring layer 31a is connected to the wiring layer 32a through a field via v1 (first conductive via). The wiring layer 31b is connected to the wiring layer 21a (first bottom wiring layer) through a field via v2 (third conductive via) and to the wiring layer 32b through field vias v3 and v4 (first conductive vias). Note that by arranging the wiring layers so that they interact with each other in the wiring layers 31a, 31b, 32a, 32b, 41a, 41b, 42a, and 42b (inner wiring layers), it is possible to reduce wiring inductance.

[0030] The wiring layer 41a is joined to the wiring layer 42a through a field via v5 (first conductive via). The wiring layer 41b is joined to the wiring layer 42b through a field via v6 (first conductive via).

[0031] The top layer of the printed circuit board 15 has a layer as a bonding area for wires connecting the semiconductor chip and the wiring layer, and a layer on which external connection terminals for connecting external devices to the semiconductor module 10 are arranged.

[0032] In the uppermost layer of printed circuit board 15, wiring layers 51a1, 51a2, 51a3, 51a4, 51b, 51c, 71a, and 71b (uppermost wiring layers) are formed on the upper arm portion A side. Also, wiring layers 61a, 61b, 61c1, 61c2, 61c3, 61c4, 81a, and 81b (uppermost wiring layers) are formed on the lower arm portion B side.

[0033] The semiconductor chips 16a and 16c are bonded to the wiring layer 51b (semiconductor chip mounting wiring layer), and the semiconductor chips 16b and 16d are bonded to the wiring layer 61b (semiconductor chip mounting wiring layer). Fig. 2 shows a state in which the drain electrode of the semiconductor chip 16a is bonded to the wiring layer 51b and the upper surface of the metal inlay 17a via solder 13d. Also, a state in which the drain electrode of the semiconductor chip 16b is bonded to the wiring layer 61b and the upper surface of the metal inlay 17b via solder 13e is also shown. Also, the side of the metal inlay 17a facing the semiconductor chip 16a is electrically connected to the wiring layer 51b, and the side of the metal inlay 17b facing the semiconductor chip 16b is electrically connected to the wiring layer 61b.

[0034] The solders 13a, 13b, 13c, 13d, and 13e are made of lead-free solder. The lead-free solder mainly contains at least one of the following alloys: a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, and a tin-silver-indium-bismuth alloy. Instead of solder, a metal sintered body may be used. The material of the metal sintered body is silver, gold, nickel, copper, or an alloy containing at least one of these.

[0035] The source electrode of the semiconductor chip 16a is bonded to a wiring layer 51a1 (second uppermost wiring layer) via a wire w1 (second wiring member: a second wire connecting the source electrode and the wiring layer), and is further bonded to a wiring layer 51c (third uppermost wiring layer) via a wire group wg1 (third wiring member) consisting of multiple wires including a wire w9. The gate electrode of the semiconductor chip 16a is bonded to a wiring layer 51a2 (first uppermost wiring layer) via a wire w2 (first wiring member: a first wire connecting the gate electrode and the wiring layer).

[0036] The source electrode of the semiconductor chip 16c is bonded to the wiring layer 51a3 (second uppermost wiring layer) via a wire w3 (second wiring member), and is further bonded to the wiring layer 51c (third uppermost wiring layer) via a wire group wg2 (third wiring member) consisting of multiple wires. The gate electrode of the semiconductor chip 16c is bonded to the wiring layer 51a4 (first uppermost wiring layer) via a wire w4 (first wiring member).

[0037] The source electrode of the semiconductor chip 16b is bonded to the wiring layer 61c1 (second uppermost wiring layer) via a wire w5 (second wiring member), and is further bonded to the wiring layer 61a (third uppermost wiring layer) via a wire group wg3 (third wiring member) consisting of a plurality of wires including a wire w10. The gate electrode of the semiconductor chip 16b is bonded to the wiring layer 61c2 (first uppermost wiring layer) via a wire w6 (first wiring member).

[0038] The source electrode of the semiconductor chip 16d is joined to the wiring layer 61c3 (second uppermost wiring layer) via a wire w7 (second wiring member), and further joined to the wiring layer 61a (third uppermost wiring layer) via a wire group wg4 (third wiring member) consisting of multiple wires. The gate electrode of the semiconductor chip 16d is joined to the wiring layer 61c4 (first uppermost wiring layer) via a wire w8 (first wiring member).

[0039] The above-mentioned wires w1, w2, w3, w4, w5, w6, w7, w8, w9, and w10 and wire groups wg1, wg2, wg3, and wg4 are aluminum wires, and wire bonding using ultrasonic waves or load is performed.

[0040] The diameters of the wires w2, w4, w6, and w8 used in the gate electrodes of the semiconductor chips 16a, 16b, 16c, and 16d are, for example, 20 μm or more and 500 μm or less. The diameters of the wires w1, w3, w5, and w7 used in the source electrodes of the semiconductor chips 16a, 16b, 16c, and 16d, and the diameters of the wires w9, w10, etc. constituting the wire groups wg1, wg2, wg3, and wg4 are, for example, 200 μm or more and 500 μm or less.

[0041] At the connection between the external connection terminal and the uppermost wiring layer, a P terminal 91, which serves as the positive terminal in the half-bridge circuit, is connected to the wiring layer 51b, and an N terminal 95, which serves as the negative terminal in the half-bridge circuit, is connected to the wiring layer 61a.

[0042] A gate terminal 93a is bonded to the wiring layer 71a, and an auxiliary source terminal 94a is bonded to the wiring layer 71b. A gate terminal 93b is bonded to the wiring layer 81a, and an auxiliary source terminal 94b is bonded to the wiring layer 81b.

[0043] Meanwhile, in the junction between the uppermost wiring layer and the inner wiring layer, the wiring layer 51a2 is joined to the wiring layer 32a via a field via v7 (second conductive via). The wiring layer 51c is joined to the wiring layer 32b via field vias v8 and v9 (second conductive vias). The wiring layer 61a is joined to the wiring layer 42a via a field via v10 (second conductive via). The wiring layer 61c2 is joined to the wiring layer 42b via a field via v11 (second conductive via).

[0044] 3 is a diagram showing an example of the circuit configuration of a semiconductor chip. The diagram shows an example of the configuration of a semiconductor chip 16a of the upper arm portion A and a semiconductor chip 16b of the lower arm portion B. The switching element of the semiconductor chip 16a is composed of a MOSFET 16a1 and a diode D1 of the MOSFET 16a1. The switching element of the semiconductor chip 16b is composed of a MOSFET 16b1 and a diode D2 of the MOSFET 16b1.

[0045] The drain electrode of MOSFET 16a1 is connected to the P terminal and the cathode of diode D1. The gate electrode of MOSFET 16a1 is connected to gate terminal G1. The source electrode of MOSFET 16a1 is connected to the anode of diode D1, auxiliary source terminal S1, output terminal U, the drain electrode of MOSFET 16b1, and the cathode of diode D2. The gate electrode of MOSFET 16b1 is connected to gate terminal G2. The source electrode of MOSFET 16b1 is connected to auxiliary source terminal S2 and the N terminal.

[0046] The gate terminal G1 corresponds to the gate terminal 93a, and the gate terminal G2 corresponds to the gate terminal 93b. The auxiliary source terminal S1 corresponds to the auxiliary source terminal 94a, and the auxiliary source terminal S2 corresponds to the auxiliary source terminal 94b. The P terminal corresponds to the P terminal 91, the N terminal corresponds to the N terminal 95, and the output terminal U corresponds to the output terminal 92.

[0047] 4 is a diagram showing a first mounting example of a snubber circuit, in which a snubber circuit formed by a combination of a capacitor and a resistor, etc., is mounted between P terminal 91 and N terminal 95 on the top layer of semiconductor module 10a.

[0048] The uppermost layer of the printed circuit board 15 includes wiring layers 51b, 51d, and 61a as circuit element-mounting uppermost wiring layers on which circuit elements such as capacitors and resistors are mounted. One end of the capacitor C1 is bonded to the wiring layer 51b, and the other end of the capacitor C1 is bonded to the wiring layer 51d. One end of the resistor R1 is bonded to the wiring layer 61a, and the other end of the resistor R1 is bonded to the wiring layer 51d.

[0049] 5 is a diagram showing a second example of mounting a snubber circuit, in which a snubber circuit formed by a combination of a capacitor and a resistor is mounted between an upper arm portion A and a lower arm portion B on the top layer of a semiconductor module 10b.

[0050] The top layer of the printed circuit board 15 includes wiring layers 51b, 51c, 51e, 51f, and 61a as circuit element-mounting topmost wiring layers on which circuit elements such as capacitors and resistors are mounted. One end of capacitor C2 is bonded to wiring layer 51b, and the other end of capacitor C2 is bonded to wiring layer 51e. One end of resistor R2 is bonded to wiring layer 51e, and the other end of resistor R2 is bonded to wiring layer 51c. One end of capacitor C3 is bonded to wiring layer 51c, and the other end of capacitor C3 is bonded to wiring layer 51f. One end of resistor R3 is bonded to wiring layer 51f, and the other end of resistor R3 is bonded to wiring layer 61a.

[0051] Next, a semiconductor module according to a first reference example will be described. Fig. 6 is a diagram showing an example of a cross section of a semiconductor module according to a first reference example. The semiconductor module 100 according to the first reference example includes a power semiconductor chip and an insulating substrate, and has a wiring structure using wires.

[0052] In the semiconductor module 100, an insulating substrate 103 is mounted on the upper surface of a copper base (heat sink) 102. The insulating substrate 103 has an insulating layer 104 and copper plates 105 and 106. The copper plate 106 of the insulating substrate 103 is joined to the copper base 102 via solder 107. A power semiconductor chip 108 is joined onto the copper plate 105 of the insulating substrate 103 via solder 109.

[0053] The wires 110 and 111 are bonding wires made of aluminum. The wire 110 joins an electrode on the top surface of the power semiconductor chip 108 to an external terminal 113 provided on the case 112. The wire 111 also joins the copper plate 105 to an external terminal 114 provided on the case 112. The joining using the wires 110 and 111 is performed by wire bonding using ultrasonic waves and load.

[0054] The insulating substrate 103 to which the power semiconductor chip 108 is bonded is housed in a case 112, and the area surrounded by the case 112 and the copper base 102 is filled with a sealing member 115 to seal it.

[0055] Fig. 7 is a diagram showing an example of a plan view of a semiconductor module of the second reference example. Fig. 8 is a diagram showing an example of a cross-sectional view of the semiconductor module of the second reference example. Fig. 8 is a cross-sectional view taken along the dashed dotted line X2-X2 in Fig. 7.

[0056] The semiconductor module 200 of the second reference example includes two circuit units, each including a power semiconductor chip and an insulating substrate, and has a wiring structure using a printed circuit board and conductive pin terminals. Insulating substrates 203a and 203b are mounted on the upper surface of a copper base 202. The insulating substrate 203a includes an insulating layer 204a and copper plates 205a and 206a, while the insulating substrate 203b includes an insulating layer 204b and copper plates 205b, 206b, 207b, and 208b.

[0057] Copper plate 205a of insulating substrate 203a is joined to copper base 202 via solder 209. Copper plate 205b of insulating substrate 203b is joined to copper base 202 via solder 210, and copper plate 207b of insulating substrate 203b is joined to copper base 202 via solder 211.

[0058] A power semiconductor chip 213a is bonded via solder 212 onto copper plate 206a of insulating substrate 203a, and a power semiconductor chip 213b is bonded via solder 214 onto copper plate 206b of insulating substrate 203b.

[0059] The printed circuit board 215 comprises an insulating plate and wiring layers formed on the front and back surfaces of the insulating plate, and also has a plurality of holes 2h penetrating from the front surface to the back surface formed at positions corresponding to the external terminals 220, 221, and 222.

[0060] Furthermore, post electrodes 216a, 216b, and 217 are provided as pin terminals on the wiring layer on the back surface of printed circuit board 215, and by joining post electrodes 216a, 216b, and 217 to the insulating substrate side, printed circuit board 215 is supported and two sets of circuit units are electrically connected through printed circuit board 215.

[0061] The post electrode 216a is joined to an electrode on the front surface of the power semiconductor chip 213a via solder 218, and the post electrode 216b is joined to an electrode on the front surface of the power semiconductor chip 213b via solder 219. The post electrode 217 is directly joined to the copper plate 208b.

[0062] The external terminal 220 is a P terminal that supplies current to the rear surface of the power semiconductor chip 213a, and has one end directly joined to the copper plate 206a and the other end penetrating the hole 2h of the printed circuit board 215 to protrude to the outside.

[0063] The external terminal 221 is an N terminal that passes current from the front surface of the power semiconductor chip 213b to the outside, and one end is directly joined to the copper plate 208b, and the other end passes through a hole 2h in the printed circuit board 215 and protrudes to the outside.

[0064] The external terminal 222 is an output terminal that passes an output current from an intermediate node between the low-potential side wiring of the power semiconductor chip 213a and the high-potential side wiring of the power semiconductor chip 213b, and one end of the external terminal 222 is directly joined to the copper plate 206b, and the other end of the external terminal 222 penetrates the hole 2h of the printed circuit board 215 and protrudes to the outside.

[0065] The external terminal 223 is an external terminal for a gate signal that controls ON / OFF switching of the power semiconductor chips 213a and 213b, and is joined to the wiring layer on the front surface of the printed circuit board 215. The external terminal 224 is an external voltage sense terminal that detects the low potential side voltage of the power semiconductor chips 213a and 213b, and is joined to the wiring layer on the front surface of the printed circuit board 215.

[0066] The insulating substrates 203a, 203b to which the power semiconductor chips 213a, 213b are bonded are housed in a case 230, and the area surrounded by the case 230 and the copper base 202 is filled and sealed with a sealing material 231 up to a predetermined height from the front surface of the printed circuit board 215.

[0067] Here, in the semiconductor module 100 of the first reference example, wires are used as the wiring structure. However, in the case of a wiring structure using wires, a bonding area needs to be provided on the insulating substrate 103 for circuit formation, which poses a problem that it is difficult to reduce the size of the semiconductor module 100.

[0068] On the other hand, the semiconductor module 200 of the second reference example uses a printed circuit board and pin terminals as the wiring structure. In the case of a wiring structure using a printed circuit board and pin terminals, it is not necessary to provide a bonding area as in the case of a wiring structure using wires, and therefore it can be said that miniaturization can be easily achieved.

[0069] However, the printed circuit board placed above the power semiconductor chip hides the power semiconductor chip and other circuit components, making it difficult to inspect the alignment and circuit joints when mounting the components, resulting in reduced inspection reliability.

[0070] On the other hand, the semiconductor module 10 of the present embodiment described above has a configuration in which a multilayer printed circuit board is bonded to the upper surface of an insulating substrate, and a metal inlay is provided directly below the semiconductor chip on the multilayer printed circuit board.

[0071] This allows a layer serving as a bonding area to be provided on the top layer of the printed circuit board 15, and allows the main circuit and the like to be formed by multiple wiring layers of the printed circuit board 15, thereby enabling higher density mounting and miniaturization of the module compared to the semiconductor module 100 of the first reference example, which has a wiring structure using wires. Furthermore, compared to the semiconductor module 200 of the second reference example, which has a wiring structure using a printed circuit board and pin terminals, problems with alignment during component mounting and inspection of joints are reduced, making it possible to improve the reliability of inspection.

[0072] Next, modified examples of the semiconductor module 10 will be described. Fig. 9 is a plan view of a semiconductor module of a first modified example. Fig. 10 is a cross-sectional view of the semiconductor module of the first modified example. Fig. 10 is a cross-sectional view taken along dashed dotted line X3-X3 in Fig. 9. Note that Fig. 9 does not show the sealing member.

[0073] A semiconductor module 10-1 of the first modification uses lead frames 131, 132, 133, and 134 instead of the wire groups wg1, wg2, wg3, and wg4 shown in Fig. 1. The other configurations are the same as those of the semiconductor module 10.

[0074] The source electrode of semiconductor chip 16a is joined to wiring layer 51c via lead frame 131 and to wiring layer 51a1 via wire w1. The source electrode of semiconductor chip 16b is joined to wiring layer 61a via lead frame 133 and to wiring layer 61c1 via wire w5.

[0075] The source electrode of semiconductor chip 16c is joined to wiring layer 51c via lead frame 132 and to wiring layer 51a3 via wire w3. The source electrode of semiconductor chip 16d is joined to wiring layer 61a via lead frame 134 and to wiring layer 61c3 via wire w7.

[0076] The lead frames 131, 132, 133, and 134 can be made of a metal material such as copper and can be connected to the source electrode of the semiconductor chip and the wiring layer via solder or sintered material. By using such a wiring structure with lead frames, it is possible to pass a larger current than with aluminum wire, and further to improve the reliability of the wiring joint.

[0077] Fig. 11 is a plan view of a semiconductor module of a second modified example. Fig. 12 is a cross-sectional view of the semiconductor module of the second modified example. Fig. 12 is a cross-sectional view taken along the dashed dotted line X4-X4 in Fig. 11. Note that Fig. 11 does not show the sealing member.

[0078] A semiconductor module 10-2 of the second modification uses flexible substrates 141, 142, 143, and 144 instead of the wires w1, w2, w3, w4, w5, w6, w7, w8, w9, and w10 and the wire groups wg1, wg2, wg3, and wg4 shown in Fig. 1. The other configurations are the same as those of the semiconductor module 10.

[0079] Flexible substrate 141 has insulating film 141a and conductive patterns 141b, 141c, and 141d, and insulating film 141a insulates conductive patterns 141b, 141c, and 141d from each other. The area of ​​conductive pattern 141c is larger than the areas of conductive patterns 141b and 141d.

[0080] The flexible substrate 142 has an insulating film 142a and conductive patterns 142b, 142c, and 142d, and the insulating film 142a insulates the conductive patterns 142b, 142c, and 142d from each other. The area of ​​the conductive pattern 142c is larger than the areas of the conductive patterns 142b and 142d.

[0081] The flexible substrate 143 has an insulating film 143a and conductive patterns 143b, 143c, and 143d, and the insulating film 143a insulates the conductive patterns 143b, 143c, and 143d from each other. The area of ​​the conductive pattern 143c is larger than the areas of the conductive patterns 143b and 143d.

[0082] The flexible substrate 144 has an insulating film 144a and conductive patterns 144b, 144c, and 144d, and the insulating film 144a insulates the conductive patterns 144b, 144c, and 144d from each other. The area of ​​the conductive pattern 144c is larger than the areas of the conductive patterns 144b and 144d. The conductive patterns are formed of, for example, copper foil.

[0083] In the bonding using the flexible substrate 141, the source electrode of the semiconductor chip 16a is bonded to the wiring layer 51a1 via the conductive pattern 141b (second conductive pattern), and further bonded to the wiring layer 51c via the conductive pattern 141c (third conductive pattern). The gate electrode of the semiconductor chip 16a is bonded to the wiring layer 51a2 via the conductive bump and the conductive pattern 141d (first conductive pattern). Figure 12 shows the state in which the gate electrode of the semiconductor chip 16a is bonded to the wiring layer 51a2 via the conductive bump bp1 and the conductive pattern 141d.

[0084] In the bonding by the flexible substrate 142, the source electrode of the semiconductor chip 16c is bonded to the wiring layer 51a3 via the conductive pattern 142b (second conductive pattern) and further bonded to the wiring layer 51c via the conductive pattern 142c (third conductive pattern). The gate electrode of the semiconductor chip 16c is bonded to the wiring layer 51a4 via the conductive bump and the conductive pattern 142d (first conductive pattern).

[0085] In the bonding using the flexible substrate 143, the source electrode of the semiconductor chip 16b is bonded to the wiring layer 61c1 via the conductive pattern 143b (second conductive pattern) and further bonded to the wiring layer 61a via the conductive pattern 143c (third conductive pattern). The gate electrode of the semiconductor chip 16b is bonded to the wiring layer 61c2 via the conductive bump and the conductive pattern 143d (first conductive pattern). Figure 12 shows the state in which the gate electrode of the semiconductor chip 16b is bonded to the wiring layer 61c2 via the conductive bump bp2 and the conductive pattern 143d.

[0086] In the bonding using the flexible substrate 144, the source electrode of the semiconductor chip 16d is bonded to the wiring layer 61c3 via the conductive pattern 144b (second conductive pattern), and further bonded to the wiring layer 61a via the conductive pattern 144c (third conductive pattern). The gate electrode of the semiconductor chip 16d is bonded to the wiring layer 61c4 via a conductive bump and the conductive pattern 144d (first conductive pattern). By using such a wiring structure using a flexible substrate, it is possible to pass a larger current than with aluminum wire, and further to improve the reliability of the wiring joint.

[0087] The bonding area of ​​the gate electrode of the semiconductor chip is smaller than the bonding area of ​​the conductive pattern of the flexible substrate, so the gate electrode of the semiconductor chip and the conductive pattern of the flexible substrate are bonded via a conductive bump having an area that can be bonded to the gate electrode.

[0088] 13 is a cross-sectional view of a semiconductor module according to a third modification. Semiconductor module 10-3 according to the third modification has a configuration in which insulating substrate 14 and printed circuit board 15 are integrated using resin insulating substrate 150. Wiring layer 50 is provided on the bottom layer of resin insulating substrate 150, and wiring layer 50 is joined to heat sink 11 via solder 13a1.

[0089] The resin insulating substrate 150 has a structure in which a resin insulating layer 18a made of a resin based on epoxy or the like mixed with a thermally conductive filler such as alumina, aluminum nitride, or boron nitride is laminated and bonded to a wiring layer of aluminum, copper, or the like on the heat sink 11, and a semiconductor chip is bonded to the surface of the wiring layer, which has been etched into an arbitrary pattern, using solder or a sintered material.

[0090] By integrating the insulating substrate 14 and the printed circuit board 15 using the resin insulating substrate 150, the difference in the rate of expansion between the components can be reduced, thereby reducing thermal stress, making it possible to make the resin insulating layer 18a thinner, and reducing the number of bonding layers, thereby realizing a module with a heat dissipation structure that is highly reliable and has low thermal resistance.

[0091] In the present embodiment described above, the semiconductor module 1 includes the insulating substrate 14, the semiconductor chips 16a to 16d, the bottom wiring layers 19a, 19b, 19c, 21a, 21b, and 21c formed in the bottom layer and bonded to the top surface of the insulating substrate 14, and the top wiring layers 51a1, 51a2, 51a3, 51a4, and 51a5, which include the wiring layers 51b and 61b (semiconductor chip mounting wiring layers) formed in the top layer and bonded to the semiconductor chips 16a to 16d. b, 51c, 51d, 51e, 51f, 61a, 61b, 61c1, 61c2, 61c3, 61c4, 71a, 71b, 81a, 81b, and an insulating layer 18 provided between the plurality of wiring layers. The printed circuit board 15 (wiring board) has metal inlays 17a and 17b electrically connected to the semiconductor chips 16a to 16d embedded between the semiconductor chips 16a to 16d and the insulating substrate 14.

[0092] As a result, by providing the printed circuit board 15 on the insulating substrate 14, it becomes possible to form multiple circuits under the bonding areas (topmost wiring layers 51a1, 51a2, 51a3, 51a4, 51b, 51c, 51d, 51e, 51f, 61a, 61b, 61c1, 61c2, 61c3, 61c4) of the wires w1 to w10 and the wire groups wg1 to wg4, thereby making it possible to miniaturize the semiconductor module 1.

[0093] Furthermore, because the semiconductor chips 16a to 16d are not hidden by the printed circuit board 15 in a plan view, it is easy to check their placement, and the difficulty of aligning the semiconductor chips 16a to 16d when placing them is reduced. Furthermore, quality can be easily confirmed using conventional inspections. Furthermore, because the printed circuit board 15 is bonded onto the insulating substrate 14, it is also possible to cool the printed circuit board 15. Furthermore, because the structure has the printed circuit board 15 attached to the insulating substrate 14, it has more advantageous insulating and thermal properties than when an insulating sheet is attached to the printed circuit board 15.

[0094] Although the embodiments have been described above, the configuration of each part shown in the embodiments can be replaced with other parts having similar functions. Also, any other components or processes may be added. Furthermore, any two or more configurations (features) of the above-described embodiments may be combined. [Explanation of symbols]

[0095] 10, 10a, 10b, 10-1, 10-2, 10-3 Semiconductor module 11 Heat sink 12 cases 12a Storage area 12b Sealing member 13a, 13a1, 13b, 13c, 13d, 13e solder 14 Insulating substrate 14a Insulating plate 14b1, 14b2, 14c metal plate 15 Printed circuit board 16a, 16b, 16c, 16d Semiconductor chips 16a1, 16b1 MOSFETs 17a, 17b Metal inlay 18 Insulating layer 18a Resin insulation layer 19a, 19b, 19c, 21a, 21b, 21c Bottom wiring layer 50 The lowest wiring layer of the semiconductor module of the third modified example 31a, 31b, 32a, 32b, 41a, 41b, 42a, 42b Inner wiring layers 51a1, 51a2, 51a3, 51a4, 51b, 51c, 51d, 51e, 51f, 61a, 61b, 61c1, 61c2, 61c3, 61c4, 71a, 71b, 81a, 81b Top layer wiring layer 91 P terminal 92 Output terminal 93a, 93b Gate terminals 94a, 94b Auxiliary source terminals 95 N terminal 100 Semiconductor module of first reference example 102 Copper base 103 Insulating substrate 104 Insulating layer 105, 106 copper plate 107, 109 Solder 108 Power Semiconductor Chips 110, 111 wire 112 cases 113, 114 External terminals 115 Sealing member 200 Second Reference Example Semiconductor Module 2h hole 202 Copper base 203a, 203b Insulating substrate 204a, 204b insulating layers 205a, 206a, 205b, 206b, 207b, 208b copper plate 209, 210, 211, 212, 214, 218, 219 Solder 213a, 213b Power semiconductor chip 215 Printed Circuit Board 216a, 216b, 217 Post electrodes 220, 221, 222, 223, 224 external terminals 230 cases 231 Sealing member 131, 132, 133, 134 Lead frame 141, 142, 143, 144 Flexible substrate 141a, 142a, 143a, 144a Insulating film 141b, 141c, 141d, 142b, 142c, 142d, 143b, 143c, 143d, 144b, 144c, 144d Conductive patterns 150 Resin insulating substrate A Upper arm B Lower arm w1, w2, w3, w4, w5, w6, w7, w8, w9, w10 wires wg1, wg2, wg3, wg4 wire groups v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11 conductive vias D1, D2 diodes PP terminal NN terminal U Output terminal G1, G2 gate terminals S1, S2 Auxiliary source terminals C1, C2, C3 capacitors R1, R2, R3 resistance bp1, bp2 conductive bumps

Claims

1. an insulating substrate; A semiconductor chip; a wiring board including a plurality of wiring layers including a bottom wiring layer formed in the bottom layer and bonded to an upper surface of the insulating substrate, and a top wiring layer including a semiconductor chip mounting wiring layer formed in the top layer and bonded to the semiconductor chip; and an insulating layer provided between the plurality of wiring layers, wherein a metal inlay electrically connected to the semiconductor chip is embedded between the semiconductor chip and the insulating substrate; A semiconductor module having:

2. the plurality of wiring layers further include a plurality of inner wiring layers formed between the lowermost wiring layer and the uppermost wiring layer; 2. The semiconductor module according to claim 1, wherein the plurality of inner wiring layers are electrically connected to each other via first conductive vias, and the top layer and the inner wiring layer are electrically connected to each other via second conductive vias.

3. the lowermost wiring layer is a first lowermost wiring layer electrically connected to the inner wiring layer through a third conductive via and having a back surface joined to an upper surface of the insulating substrate; The semiconductor module according to claim 2 , comprising:

4. an upper surface of the metal inlay is bonded to the first electrode of the semiconductor chip, and a lower surface of the metal inlay is bonded to the upper surface of the insulating substrate; a side surface of the metal inlay facing the semiconductor chip contacts the semiconductor chip mounting wiring layer; The semiconductor module according to claim 1 , wherein a side surface of the metal inlay facing the insulating substrate is in contact with the lowermost wiring layer.

5. 2. The semiconductor module according to claim 1, wherein said uppermost wiring layer includes a circuit element mounting uppermost wiring layer on which circuit elements for controlling said semiconductor chip are mounted.

6. the uppermost wiring layer includes a first uppermost wiring layer joined to a control electrode of the semiconductor chip, a second uppermost wiring layer connected to a second electrode of the semiconductor chip, and a third uppermost wiring layer to which the second electrode of the semiconductor chip and an external output terminal are connected; 2. The semiconductor module according to claim 1, wherein the control electrode and the first uppermost wiring layer are electrically connected via a first wiring member, the second electrode and the second uppermost wiring layer are joined via a second wiring member, and the second electrode and the third uppermost wiring layer are joined via a third wiring member.

7. 7. The semiconductor module according to claim 6, wherein the first wiring member, the second wiring member, and the third wiring member are bonding wires.

8. 7. The semiconductor module according to claim 6, wherein the first wiring member is a first wire, the second wiring member is a second wire, and the third wiring member is a lead frame.

9. 7. The semiconductor module according to claim 6, wherein the first wiring member, the second wiring member, and the third wiring member are flexible substrates.

10. 2. The semiconductor module according to claim 1, wherein the insulating layer of the insulating substrate is formed of a resin insulating layer, and the metal inlay is embedded in the resin insulating substrate in which the insulating substrate and the wiring substrate are integrated by laminating the wiring layer on the resin insulating layer.

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