Da conversion device and ad conversion device

Abstract

To provide a DA conversion device or the like capable of reducing a non-linearity of an output voltage by using a range in which voltage dependency of a MOS capacitor is low.SOLUTION: A charge scaling type DA conversion device comprising an upper bit side capacitor array and a lower bit side capacitor array connected via a damping capacitor includes a control circuit for applying a positive bias voltage or a negative bias voltage to all of a plurality of capacitors of an upper bit side capacitor array and a plurality of capacitors of a lower bit side capacitor array at a time of resetting and conversion of a DA conversion device. At least one of a reference voltage of the lower bit side capacitor array and a reset voltage is set to a value different from the reference voltage of the upper bit side capacitor array.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a DA conversion device using, for example, a MOS type semiconductor element, and an AD conversion device including the DA conversion device. [Background technology]

[0002] 12 is a circuit diagram showing the configuration of a charge scaling DA converter according to Conventional Example 1, disclosed in Non-Patent Document 1. In FIG. 12, the charge scaling DA converter includes a plurality of capacitors that are a binary weighted capacitance cell array, and each capacitor is connected to a reference voltage V REF A plurality of N switches S0 to S5 are connected to the N-1 The output reset switch SW101 resets the output voltage, and a buffer circuit including an operational amplifier 101 whose output terminal and inverting input terminal are connected.

[0003] The charge scaling type DA converter configured as above operates as follows. (1) The output reset switch SW101 is turned on, and the output terminal is set to a predetermined reset voltage. (2) Turn off the output reset switch SW101 and return the output terminal to high impedance. (3) In each capacitor of the binary weighted capacitance cell array, the terminal voltage on the side not connected to the DA converter output is controlled by switches S0 to S2 according to the input code. N-1 By controlling and switching between them, the reference voltage V REF The output voltage is obtained according to the capacitance division.

[0004] This charge scaling type DA converter is suitable for low power consumption because no steady current flows. N-1It consists of only SW101 and multiple capacitors, and has been widely used to this day because it benefits from scaling in the manufacturing process. When a load is connected to the output terminal, a buffer circuit including operational amplifier 101 is connected, but when a comparator with high capacitive impedance, such as a successive approximation type AD conversion device, is connected to the output, the output terminal is directly connected to the comparator.

[0005] 13 is a circuit diagram showing the configuration of a charge scaling DA converter according to Conventional Example 2. In the charge scaling DA converter of FIG. 13, when the resolution is increased, the number of unit cells of the capacitive DA converter is two. N-1 In order to reduce the number of unit cells, the capacitor array is divided into two, a high-order bit side capacitor array 121 and a low-order bit side capacitor array 122, and the attenuation capacitor C S where the damping capacitor C S is also referred to as the scaling capacitance or bridge capacitance in some literature. S The lower-order bit capacitor array 122 has the attenuation capacitor C S is expressed by the following equation so as to be scaled to the output voltage range of the most significant bit side capacitor array 121 via

[0006] C S = (Number of unit capacitances of the lower-bit side capacitor array 122) / (Number of unit capacitances of the upper-bit side capacitor array 121)×C u

[0007] where C u is the unit capacity.

[0008] Next, application examples of these charge scaling type DA converters will be briefly described below.

[0009] For example, Patent Document 2 discloses an image recognition system equipped with a solid-state imaging element integrated with a readout circuit. Here, the image recognition system is configured with a solid-state imaging device (image sensor) that is a sensor unit, and an image signal processing device such as an image recognizer. The solid-state imaging device is configured with a pixel unit, a readout circuit unit for reading out pixel signals, and vertical (row) and horizontal (column) scanning circuit units for controlling the reading of pixels arranged in an array. The pixel unit outputs pixel signals to the readout circuit in the following procedure. (1) Input light is converted into an electric charge by photoelectric conversion in the photodiode PD. (2) The RST gate (reset gate) is turned on, and the floating diffusion FD is reset to the power supply voltage. (3) The transfer gate is turned on, and the signal charge generated in the photodiode PD is transferred to the floating diffusion FD, thereby converting it into a voltage signal. (4) The pixel signals of the row selected by the row selection switch SEL are buffered and output via a source follower amplifier connected to the floating diffusion FD.

[0010] In the pixel disclosed in Non-Patent Document 3, in order to maximize the amount of incident light captured by the photodiode PD, it is necessary to reduce the thickness of the wiring layer and the number of wiring layers used, thereby shortening the distance from the chip surface to the photodiode PD. Next, the readout circuit extracts the pixel signal by sampling the difference between the reset signal of the floating diffusion FD and the pixel signal, and performs correlated double sampling (CDS) to remove reset noise (kT / C) and threshold voltage variations of the source follower amplifier. The voltage sampled by the CDS is then converted into a digital signal by an AD converter. Furthermore, the AD converter in the readout circuit may be a successive approximation type, and the aforementioned charge scaling capacitive DA converter is used to generate the reference voltage inside the AD converter. [Prior art documents] [Patent documents]

[0011] [Patent Document 1] U.S. Patent No. 4,077,035 [Patent Document 2] Japanese Patent Publication No. 2022-102604 [Non-patent literature]

[0012] [Non-Patent Document 1] Phillip E. et al., "CMOS Analog Circuit Design", Oxford University Press, pp. 44-46, 2002. [Non-patent document 2] YS Yee et al., "A two-Stage Weighted Capacitor Network for D / AA / D Conversion". IEEE Journal of Solid-state circuits, Vol. SC-14, No. 4, pp. 778-781, Aug. 1979. [Non-patent document 3] Takahashi, "Pixel Reduction Technology for CMOS Image Sensors," Journal of the Institute of Image Information and Television Engineers, Vol. 60, No. 3, pp. 295-298, 2006. Summary of the Invention [Problem to be solved by the invention]

[0013] The readout circuit disclosed in Patent Document 2 requires a capacitance element to perform CDS and AD conversion. When the readout circuit and the sensor unit are mounted together, the number of wiring layers is limited in order to maximize the amount of incident light that can be captured by the photodiode PD. Therefore, there is a problem in that it is difficult to use a capacitance that uses a wiring layer due to wiring constraints.

[0014] To reduce the cost of the semiconductor processes used to fabricate these semiconductor devices, the number of wiring layers is often limited to two or three in order to reduce the number of masks used in the semiconductor process. To use a metal-insulator-metal (MIM) capacitor, which has a structure in which an insulating layer with good characteristics and low voltage and temperature dependence is sandwiched between metal plates, requires an additional mask for element formation, which increases costs. To solve this problem, wiring capacitors with good electrical characteristics could be used, but they are rarely used because the wiring processing accuracy is poor and the capacitance density is low in inexpensive manufacturing processes, resulting in a large area.

[0015] As described above, under the above technical background, there are cases where it is not possible to use capacitance devices such as MIMs with good electrical characteristics, and it is necessary to use MOS capacitances.

[0016] FIG. 14 is a cross-sectional view showing the capacitance of a MOS field effect transistor (MOSFET) used in a semiconductor device according to Conventional Example 3. FIG. 15 is a graph showing the voltage dependence of MOS capacitance, showing the capacitance value versus gate-source and drain voltages in FIG. 14. As shown in FIG. 14, the MOS capacitance used in the semiconductor device is an NMOS transistor or a depletion-type MOS field effect transistor on an N-type well 202 so that a channel exists even when the gate-substrate voltage Vgb=0V. In FIG. 14, after an N-type well 202 is formed in a semiconductor substrate 201, a source electrode 212 and a drain electrode 213 are formed, and a gate electrode 211 is formed via a gate oxide film 203 and polysilicon 204.

[0017] As shown in Figure 15, when the gate-to-substrate voltage Vgb is sufficiently high, a channel consisting of majority carriers is formed under the gate, resulting in an accumulation state, and the capacitance value is determined by the distance between the gate oxide film 203 and the channel under the gate, and the dielectric constant of the gate oxide film 203. On the other hand, when the gate-to-substrate voltage Vgb approaches 0V, minority carriers gather under the channel, forming a depletion layer under the gate. The capacitance value decreases because it is determined by the thickness of the gate oxide film 203 and the thickness of the depletion layer, which is an insulating layer, and there is a possibility that the capacitance value will have voltage dependency on the gate-to-substrate voltage Vgb.

[0018] As explained above, when the number of wiring layers is limited as described above, it is not possible to use capacitive elements with good electrical characteristics, and when MOS capacitors are used, there is a problem that the linearity of the charge scaling capacitive DA converter deteriorates.

[0019] An object of the present invention is to solve the above problems and to provide a DA conversion device using, for example, MOS-type semiconductor elements, which can reduce the nonlinearity of the DA conversion device by using a range in which the voltage dependency of the MOS capacitance is low compared to conventional techniques, and an AD conversion device equipped with the DA conversion device. [Means for solving the problem]

[0020] A DA conversion device according to one aspect of the present invention includes: A charge scaling DA conversion device comprising a most significant bit side capacitor array and a least significant bit side capacitor array connected via an attenuation capacitor, the most significant bit side capacitor array includes a plurality of MOS capacitance capacitors having a binary-weighted capacitance ratio; the least significant bit side capacitor array includes a plurality of MOS capacitance capacitors having a binary-weighted capacitance ratio; The DA conversion device a control circuit that applies a positive bias voltage or a negative bias voltage to the plurality of capacitors in the higher-order bit side capacitor array and the plurality of capacitors in the lower-order bit side capacitor array when the DA conversion device is reset or when the conversion is performed, At least one of the reference voltage and the reset voltage of the lower bit side capacitor array is set to a value different from the reference voltage of the upper bit side capacitor array. DA conversion device. [Effects of the Invention]

[0021] Therefore, according to the DA conversion device of the present invention, in a charge scaling DA conversion device that uses MOS capacitance, by increasing the attenuation capacitor and, for example, lowering the reference voltage of the lower-bit side capacitor array, it is possible to set the bias voltage of the MOS capacitance so that the MOS capacitance operates in a range with substantially low voltage dependency, thereby reducing the nonlinearity of the DA conversion device. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a circuit diagram showing an example of the configuration of a charge scaling DA converter 1 according to a first embodiment. [Figure 2] 2 is a timing chart of each signal illustrating the operation of the charge scaling DA converter 1 of FIG. [Figure 3] 2 is a circuit diagram when the potential difference between capacitances in the upper bit side capacitor array 21 of FIG. 1 becomes the minimum value. [Figure 4] 2 is a circuit diagram when the potential difference across the attenuation capacitors in the charge scaling DA converter 1 of FIG. 1 is at a minimum value. [Figure 5] 2 is a circuit diagram when the potential difference between capacitances in the lower-bit side capacitor array 22 of FIG. 1 becomes the minimum value. [Figure 6] 10 is a circuit diagram showing an example of the configuration of a charge scaling DA conversion device 1A according to a second embodiment. FIG. [Figure 7] 7 is a timing chart of each signal illustrating the operation of the charge scaling DA converter 1A of FIG. 6. [Figure 8] FIG. 10 is a block diagram showing an example of the configuration of a successive approximation type AD conversion device 31 according to a third embodiment. [Figure 9]FIG. 10 is a block diagram showing an example of the configuration of a successive approximation type AD conversion device 32 according to a fourth embodiment. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of a successive approximation type AD conversion device 33 according to a fifth embodiment. [Figure 11] FIG. 10 is a block diagram showing an example of the configuration of a successive approximation type AD conversion device 34 according to a sixth embodiment. [Figure 12] FIG. 1 is a circuit diagram showing a configuration of a charge scaling DA converter according to a first conventional example. [Figure 13] FIG. 10 is a circuit diagram showing the configuration of a charge scaling DA converter according to Conventional Example 2. [Figure 14] 10 is a cross-sectional view showing a capacitance of a MOS field effect transistor (MOSFET) used in a semiconductor device according to Conventional Example 3. FIG. [Figure 15] 15 is a graph showing the voltage dependence of MOS capacitance, showing capacitance values ​​with respect to gate-source and drain voltages in FIG. 14. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments and modifications of the present invention will be described with reference to the drawings, in which the same or similar components are designated by the same reference numerals.

[0024] (Embodiment 1) 1 is a circuit diagram showing an example of the configuration of a charge scaling DA converter 1 according to embodiment 1. In FIG. 1, the charge scaling DA converter 1 has a function of reducing the reference voltage V ref2p ,V ref2m , the reference voltage V of the upper bit side capacitor array 21 ref1p ,V ref1m It is characterized by being separated from the

[0025] In FIG. 1, the plurality of capacitors that are the binary-weighted capacitance cell array are (n+1) capacitors C10 to C11 that belong to the upper bit side capacitor array 21 and have binary-weighted capacitance. nand (m+1) capacitors C20 to C22 that belong to the lower-bit side capacitor array 22 and have a binary-weighted capacitance. m and the termination capacitor C2 connected to the capacitor C20. t where the terminating capacitor C2 t are provided to adjust the full-scale output voltage range of the DA conversion device. n and (m+1) capacitors C20 to C22 belonging to the lower-order bit capacitor array 22. m is the damping capacitor C a are connected via

[0026] Here, the (n+1) capacitors C10 to C11 belonging to the upper bit side capacitor array 21 n and (m+1) capacitors C20 to C22 belonging to the lower-order bit capacitor array 22. m and the terminating capacitor C2 t and the damping capacitor C a The capacitors C10 to C11 are configured with MOS capacitors such as N-channel MOS field effect transistors (hereinafter referred to as NMOS transistors). The MOS capacitors have, for example, the element configuration shown in FIG. 14 and the electrical characteristics shown in FIG. 15. n and capacitors C20 to C2 m As will be described later, the unit capacity C u The NMOS transistor may be configured as one or multiple NMOS transistors connected in parallel.

[0027] The charge scaling DA converter 1 further comprises: (1) (n+1) capacitors C10 to C1 belonging to the upper-bit capacitor array 21 n The other end of each is connected to the reference voltage V ref1p or V ref1m (n+1) switches SW m+1 ~SW n+m+1 and, (2) The connection destinations of the other ends of the (m + 1) capacitors C20 to C2 belonging to the lower-bit capacitor array 22 m are selectively switched to either the reference voltage V ref2p or V ref2m by the (m + 1) switches SW0 to SW m , and (3) A reset switch SW n that switches whether or not each one end of the (n + 1) capacitors C10 to C1 belonging to the upper-bit capacitor array 21 is connected to the reset voltage V rst1 based on the reset signal RST1 of H level rst1 , and (4) A reset switch SW m that switches whether or not each one end of the (m + 1) capacitors C20 to C2 belonging to the lower-bit capacitor array 22 is connected to the reset voltage V rst2 based on the reset signal RST2 of H level rst2 , and includes.

[0028] Note that in this specification, the symbol of each capacitor also indicates the capacitance value. Also, the reset signal RST1 changes from L level to H level at a predetermined time T1 during the reset period, and the reset signal RST2 changes from L level to H level at a predetermined time T2 (<T1) during the reset period. Further, the voltage of each one end of the (m + 1) capacitors C20 to C2 belonging to the lower-bit capacitor array 22 is the output voltage V m , the voltage of each one end of the (n + 1) capacitors C10 to C1 belonging to the upper-bit capacitor array 21 is the output voltage V o2 , and the output voltage V n is the output voltage of the charge scaling type DA conversion device 1 in FIG. 1. o1 The charge scaling type DA conversion device 1 further includes a control circuit 10 that generates bit signals b0 to b o1 for controlling the switching of the switches SW0 to SW

[0029] and the reset signals RST1, RST2. n+m+1 n+m+1 ​​

[0030] Fig. 2 is a timing chart of each signal showing the operation of the charge scaling DA converter 1 of Fig. 1. The operation of the charge scaling DA converter 1 of Fig. 1 will be described below with reference to Fig. 2.

[0031] In FIG. 2, first, bit signals b0 to b1 corresponding to the desired output voltage are n+m+1 Based on the switches SW0 to SW n+m+1 By controlling the capacitors C10 to C1 n ,C20~C2 m The terminal voltages at the other ends of the ref1p ,V ref2p or V ref1m ,V ref2m Here, the bit signals b0 to b n+m+1 When the value of is 1, the capacitors C10 to C1 n ,C20~C2 m The other end of each is the reference voltage V ref1p ,V ref2p and bit signals b0 to b n+m+1 When the value of is 0, the L level, capacitors C10 to C1 n ,C20~C2 m The other end of each is the reference voltage V ref1m ,V ref2m At the same time, by controlling the reset signals RST1 and RST2, the switch SW rst1 ,SW rst2 turns on and the output voltage V o1 ,V o2 are the initial voltage and the reset voltage V rst1 ,V rst2 Set to.

[0032] Then, the output voltage V o1 SW rst2 To prevent errors such as charge injection that occur when switching from ON to OFF, the reset signal RST2 is controlled first, and then the reset signal RST1. rst2 ,SW rst1 This causes the output voltage V o2 ,Vo1 Each terminal is set to high impedance and the reset voltage is sampled.

[0033] Next, bit signals b0 to b corresponding to the desired output voltage are n+m+1 Based on the switches SW0 to SW n+m+1 , capacitor C10~1 n ,C20~C2 m The terminal voltage at the other end of the ref1p ,V ref2p or the reference voltage V ref1m ,V ref2m The capacitance ratio connected to the bit signals b0 to b n+m+1 The output voltage V o1 In order to obtain the following DA conversion output, the output voltage V o1 ,V o2 If each terminal can maintain high impedance, the bit signals b0 to b n+m+1 may be controlled by switching between the above.

[0034] Here, capacitor C1 n ,C2 m are the unit capacitance C1 u ,C2 u are expressed by equations (1) and (2), respectively.

[0035]

number

[0036]

number

[0037] The total capacitance value C1 of the most significant bit capacitor array 21 is expressed by equation (3), and the total capacitance value C2 of the least significant bit capacitor array 22 is expressed by equation (4).

[0038]

number

[0039]

number

[0040] Here, the terminating capacitor C2 t The capacitance value of unit capacitance C2 is set so that the voltage difference between the full code voltage and the zero code voltage is (reference voltage - 1 LSB voltage). u is set to

[0041] Output voltage V of DA converter 1 o1 teeth, (1) Output voltage V o1 When the lower-order bit side capacitor array 22 is viewed from the terminal a and the series capacitance value C12 of the total capacitance value C2 of the lower-bit side capacitor array 22. a and equation (5) which represents (2) Output voltage V o2 When the upper bit side capacitor array 21 is viewed from the terminal a and the series capacitance value C21 of the total capacitance value C1 of the upper bit side capacitor array 21. a and equation (6) which represents (3) Equation (7) expressing the gain G1 of the upper-bit side capacitor array 21; (4) Output voltage V o2 Output voltage V o1 Equation (8) expresses the transfer gain G21a to the terminal of (5) Equation (9) expressing the gain G2 of the lower-order bit capacitor array 22; (6) The output voltage V from the lower-bit capacitor array 22 o1 Equation (10) expresses the transfer gain G21 to the terminal of (7) Equations (11) and (12) expressing the reference voltage difference when switching the reference voltages of the upper-bit side capacitor array 21 and the lower-bit side capacitor array 22, can be expressed as equation (13) using

[0042]

number

[0043]

number

[0044]

number

[0045]

number

[0046]

number

[0047]

number

[0048]

number

[0049]

number

[0050]

number

[0051] where p i indicates the polarity value of the output voltage control of each bit signal, and the reference voltage at reset is the reference voltage V ref1p From the above, the reference voltage V at the output of the DA converter 1 is ref1mIf the polarity value p i is the reference voltage V ref2p to the reference voltage V ref2m If you switch to it, it will be -1, and vice versa, it will be +1, and if you don't switch it will be 0.

[0052] Similarly, the output voltage V of the lower-order bit capacitor array 22 o2 teeth, (1) Output voltage V o1 Output voltage V o2 Equation (14) expresses the transfer gain G12a to the terminal of (2) The output voltage V from the upper bit side capacitor array 21 o2 Equation (15) expresses the transfer gain G21 to the terminal of This can be expressed as equation (16) using

[0053]

number

[0054]

number

[0055]

number

[0056] Additionally, a damping capacitor C a The capacitance value of is the output voltage V o1 is the bit signal b n+m+1 Since it is controlled by a binary weight, the output voltage V o1 and the output voltage V at (full code + 1 LSB) of the lower-bit side capacitor array 22 o1 It is necessary to satisfy the condition (17) that

[0057]

number

[0058] Therefore, by substituting equations (7) and (10) into equation (17), the capacitance value of the attenuation capacitor Ca can be obtained from equation (18).

[0059]

number

[0060] The output voltage range of the DA conversion device 1 in FIG. n ,C2 m All capacitors C10 to C1 n and C20 to C2 m , the reference voltage V ref1p ,V ref2p When connected to reset, the output voltage V o1 The minimum value of V o1min The control of all bits of the bit signal is 1 to 0, and the polarity value p i =-1, which is expressed by the following equation.

[0061] V o1min =V rst1 -V ref1 ×(1-1 / 2 n+m+2 ) ≒V rst1 -V ref1

[0062] Also, the output voltage V o1 The maximum value of V o1max The bit signal is set to 1 with no switching, and the polarity value p i = 0, it is expressed as follows:

[0063] V o1max =V rst1

[0064] On the other hand, capacitor C1 n ,C2 m and the reference voltage Vref1m ,V ref2m When connected to reset, the output voltage V o1 The minimum value of V o1min is the polarity value p i = 0, it is expressed by the following equation.

[0065] V o1min =V rst1

[0066] Also, the output voltage V o1 The maximum value of V o1max is the control of every bit of the bit signal from 0 to 1, and the polarity value p i = 1, which is expressed by the following equation.

[0067] V o1max =V rst1 +V ref1 ×(1-1 / 2 n+m+2 ) ≒V rst1 +V ref1

[0068] In this way, at the time of reset, capacitor C1 n ,C2 m The output voltage range can be set by changing the connection destination of the reference voltage of capacitor C1. n ,C2 m If the capacitance value of has voltage dependency, the charge scaling type capacitive DA converter will have nonlinearity because its output voltage is determined by the binary weighted capacitance ratio. However, in order to reduce the nonlinearity due to voltage dependency, the damping capacitor C a Therefore, it is sufficient to make the bias voltage applied at the time of resetting and outputting only positive or negative. ref2 Or reset voltage V rst2 By setting at least one of these to a value different from that of the upper bit side capacitor array 21 and ensuring a predetermined bias voltage, the MOS capacitance can be operated in a range with low voltage dependency.

[0069] FIG. 3 is a circuit diagram when the potential difference between the capacitances in the upper bit side capacitor array 21 of FIG. 1 becomes the minimum value.

[0070] Here, as an example, (1) The reference voltages are V ref1p >0, V ref2p >0, V ref1m =V ref2m Set =0, (2) All capacitors C10 to C1 n ,C20~C2 m and the reference voltage V ref1p ,V ref2p Connect to and reset, (3) Capacitors C10 to C1 in the upper-bit capacitor array 21 n and one end of the damping capacitor C a The top plate (gate) of the output voltage V o1 Connect to the terminal of (4) Capacitors C20 to C22 of the lower-order bit capacitor array 22 m The top plate (gate) of the output voltage V o2 Connect to the terminal of (5) All capacitors C10 to C1 n ,C20~C2 m Unit capacity C u Consider the case where an NMOS transistor is used in the MOS capacitor shown in FIGS. 15 and 16 and a positive bias voltage is applied so that the potential difference across the capacitance is equal to or greater than a predetermined positive bias voltage Vb higher than the ground voltage (hereinafter referred to as the first case).

[0071] In the first case, in the upper bit side capacitor array 21, only the capacitor C10 is connected to the reference voltage V ref1p The potential difference between the capacitances is smallest when the capacitors are connected to the

[0072] V rst1 -V ref1p ≧V ref1p +Vb (19)

[0073] FIG. 4 is a circuit diagram of charge scaling DA converter 1 of FIG. 1 when the potential difference across the attenuation capacitors is at its minimum value (hereinafter referred to as the second case).

[0074] In the second case, the damping capacitor C a Regarding the capacitors C10 to C1 of the upper bit side capacitor array 21, n The other end of each of these is connected to the reference voltage V ref1m , and the capacitors C20 to C2 of the lower-order bit capacitor array 22 are connected to m The other end of each of these is connected to the reference voltage V ref2p When the capacitor is connected to the resistor, the potential difference between the damping capacitors is minimized and the following equation must be satisfied. The circuit diagram for this is shown in Figure 4.

[0075] V rst1 -V ref1p ≧V rst2 +Vb (20)

[0076] FIG. 5 is a circuit diagram when the potential difference between capacitances in the lower-order bit capacitor array 22 of FIG. 1 is at a minimum value (hereinafter referred to as the third case).

[0077] In the third case, in the lower-bit side capacitor array 22, similarly to the upper-bit side capacitor array 21, only the capacitor C20 is connected to the reference voltage V ref2p When the capacitor is connected to the load, the potential difference between the capacitors is at a minimum and the following equation must be satisfied. The circuit diagram for this is shown in Figure 5.

[0078] V rst2 -V ref2p ≧V ref2p +Vb (21)

[0079] Therefore, the reset voltage V must be set to satisfy all of the following equations: (19), (20), and (21). rst1 ,V rst2 , and the reference voltage V ref1p ,V ref2p Just set it as follows.

[0080] Furthermore, to reduce the voltage, the reset voltage V rst1 To lower the reference voltage V ref2p At this time, it becomes necessary to lower the damping capacitor C a is adjusted to be the equation (18). m The accuracy required for the capacitance value is determined by the capacitance of each of the capacitors C10 to C11 in the upper bit side capacitor array 21. n Therefore, the bias voltage Vb in equation (21) may be set lower than the bias voltage Vb of the upper bit side capacitor array 21, allowing for a higher voltage dependency of the capacitance. Furthermore, in order to reduce the number of terminals, the reference voltage V ref1m and the reference voltage V ref2m By setting them equal, it can be made into a common terminal, and if all of equations (19), (20), and (21) are satisfied, the reset voltage V rst2 and the reference voltage V ref1p may be set equal to each other to form a common terminal.

[0081] As described above, according to the first embodiment, in the charge scaling DA conversion device 1, the unit capacitance C u When there is a voltage dependency like MOS capacitance, the unit capacitance C u By setting the bias voltage so that the operating point is substantially in a range with low voltage dependency, the nonlinearity of the output voltage of the DA conversion device 1 can be reduced.

[0082] In addition, the output voltage V o1 When a load is connected to the output terminal of the input, a buffer circuit including an operational amplifier may be connected, and when a comparator having a high capacitive impedance, such as a successive approximation type AD conversion device, is connected to the output, the output terminal is directly connected to the comparator. This configuration is similar to that in other embodiments.

[0083] In addition, in the first embodiment, (1) Capacitors C10 to C1 of the upper bit side capacitor array 21 nThe top plate (gate) of the output voltage V o1 Connect to the terminal of (2) Damping capacitor C a and the capacitors C20 to C22 of the lower-order bit capacitor array 22. m The top plate (gate) of the output voltage V o2 By connecting to the terminal, Output voltage V o1 ,V o2 damping capacitor C a By reversing the connection direction and setting it as follows, the reset voltage V rst2 may be set higher.

[0084] (1) Capacitors C10 to C1 of the upper bit side capacitor array 21 n At a bias voltage Vb of V rst1 -V ref1p ≧V ref1p +Vb (22) (2) Damping capacitor C a At a bias voltage Vb of V rst2 -V ref2p ≧V rst1 +Vb (23) (3) Capacitors C20 to C22 of the lower-order bit capacitor array 22 m At a bias voltage Vb of V rst2 -V ref2p ≧V ref2p +Vb (24)

[0085] The reset voltage V is set so as to satisfy all of the above equations (22), (23), and (24). rst1 ,V rst2 , and the reference voltage V ref1p ,V ref2p may be set.

[0086] In the first embodiment, even when the capacitance element is used in a negative bias, the reference voltage V ref2p or reset voltage V rst2At least one of the voltages is set to the reference voltage V ref1p or reset voltage V rst1 By setting it to a value different from the unit capacity C u The nonlinearity of the output voltage of the DA conversion device 1 may be reduced by setting the bias voltage so that the operating point is substantially in a range with low voltage dependency.

[0087] (Embodiment 2) Fig. 6 is a circuit diagram showing an example of the configuration of a charge scaling DA converter 1A according to embodiment 2. In Fig. 6, the charge scaling DA converter 1A according to embodiment 2 is characterized in that, compared to the charge scaling DA converter 1 of Fig. 1, a lower-order bit capacitor array 23 having a configuration similar to that of the lower-order bit capacitor array 22 and its peripheral circuits are added to the lower stage side of the lower-order bit capacitor array 22, thereby improving the resolution of the DA converter. The charge scaling DA converter 1A according to embodiment 2 differs from the charge scaling DA converter 1 of Fig. 1 as follows.

[0088] (1) Damping capacitor C in Figure 1 a Code C a1 Let's say. (2) Damping capacitor C a1 The damping capacitor C a2 Further provided are: (3) Capacitors C30 to C33 of the lower-order bit capacitor array 23 k Further provided are: (4) In the lower-bit side capacitor array 23, the termination capacitor C3 t Further provided are: (5) Capacitors C30 to C33 of the lower-order bit capacitor array 23 k are connected to the respective bit signals b0 to b k Switches SW0 to SW k Further provided are: (6) Capacitors C30 to C33 of the lower-order bit capacitor array 23 kOne end of each is connected together to a reset switch SW controlled based on a reset signal RST3. rst3 It is connected to a reset voltage V rst3 through. Note that the output voltage of one end of each of the capacitors C30 to C3 k is set as V o3 . (7) The codes of the switches of the upper-bit side capacitor array 21 are SW m+k+2 ~SW n+m+k+2 , and the codes of the bit signals controlling the switches are b m+k+2 ~b n+m+k+2 . (8) The codes of the switches of the lower-bit side capacitor array 22 are SW k+1 ~SW m+k+1 , and the codes of the bit signals controlling the switches are b k+1 ~b m+k+1 . (9) Instead of the control circuit 10 in FIG. 1, a control circuit 10A that generates bit signals b0 to b n+m+k+2 and reset signals RST1, RST2, and RST3 is provided.

[0089] As described above, in Embodiment 2, a lower-bit side capacitor array 23 is added, and the output voltage V a2 of the lower-bit side capacitor array 22 is further divided and scaled through the attenuation capacitor C o2 and the lower-bit side capacitor array 22 to increase the resolution of the DA conversion device. [[ID=​​​​​​​n+m+k+2 Based on the switches SW0~SW n+m+k+2 By controlling the capacitors C10 to C1 in the capacitor arrays 21, 22, and 23, n ,C20~C2 m ,C30~C3 k The other terminal of each of these is connected to the reference voltage V ref1p ,V ref2p ,V ref3p or the reference voltage V ref1m ,V ref2m ,V ref3m Here, the bit signals b0 to b n+m+k+2 When the value of is 1, the capacitors C10 to C1 n ,C20~C2 m ,C30~C3 k The other end of each is the reference voltage V ref1p ,V ref2p, V ref3p and bit signals b0 to b n+m+k+2 When the value of is 0, the L level, capacitors C10 to C1 n ,C20~C2 m, C30~C3 k The other end of each is the reference voltage V ref1m ,V ref2m ,V ref3m At the same time, by controlling the reset signals RST1, RST2, and RST3, the switches SW rst1 ,SW rst2 ,SW rst3 turns on and the output voltage V o1 ,V o2 ,V o3 are the initial voltage and the reset voltage V rst1 ,V rst2 ,V rst3 Set to.

[0092] Next, the reset signals RST3, RST2, and RST1 are controlled in this order to turn on the switch SW rst3 ,SW rst2 ,SW rst1 are turned off in the appropriate order, and the output voltage V o3 ,V o2 ,V o1Each terminal is set to high impedance and the reset voltage is sampled.

[0093] Next, bit signals b0 to b corresponding to the desired output voltage are n+m+k+2 Based on the switches SW0 to SW n+m+k+2 In each of the capacitor arrays 21, 22, and 23, the capacitors C10 to C1 n ,C20~C2 m, C30~C3 k The other terminal voltage of each of the switches SW0 to SW1 is connected to a reference voltage of the opposite polarity to that at the time of reset. n+m+k+2 By controlling the reference voltage V ref1p ,V ref2p ,V ref3p or the reference voltage V ref1m ,V ref2m ,V ref3m The capacitance ratio connected to the bit signals b0 to b n+m+k+2 The desired output voltage V o1 get.

[0094] for example, (1) Regarding the reference voltage, V ref1p >0 V ref2p >0 V ref3p >0 V ref1m =V ref2m =V ref3m =0 Set it to (2) Capacitors C10 to C1 n ,C20~C2 m, C30~C3 k and the reference voltage V ref1p ,V ref2p ,V ref3p Connect to and reset, (3) Capacitors C10 to C1 of the upper-bit capacitor array 21 n The top plate (gate) of the output voltage V o1 Connect to the terminal of (4) Damping capacitor C a1 ,C a2and the capacitors C20 to C22 of the lower-order bit capacitor array 22. m The top plate (gate) of the output voltage V o2 Connect to the terminal of (5) Capacitors C30 to C33 of the lower-order bit capacitor array 23 k Top plate (gate) to output voltage V o3 Connect to the terminal of (6) When an N-channel field effect transistor is used as a unit capacitor and a positive bias voltage is applied to the unit capacitor so that the potential difference between the capacitors is equal to or greater than the positive bias voltage Vb, the reset voltage V is set to satisfy all of the following equations: rst1 ,V rst2 ,V rst3 and reference voltage V ref1p ,V ref2p ,V ref3p Just set it as follows.

[0095] (1) Capacitors C10 to C1 of the upper bit side capacitor array 21 n At a bias voltage Vb of V rst1 -V ref1p ≧V ref1p +Vb (2) Damping capacitor C a1 At a bias voltage Vb of V rst2 -V ref2p ≧V rst1 +Vb (3) Capacitors C20 to C22 of the lower-order bit capacitor array 22 m At a bias voltage Vb of V rst2 -V ref2p ≧V ref2p +Vb (4) Damping capacitor C a2 At a bias voltage Vb of V rst2 -V ref2p ≧V rst3 +Vb (5) Capacitors C30 to C33 of the lower-order bit capacitor array 23 k At a bias voltage Vb of V rst3 -V ref3p ≧V ref3p +Vb

[0096] where the reference voltage V ref2p ,V ref3p If you want to lower (1) Damping capacitor C a1 is the output voltage V at 1LSB of the most significant bit side capacitor array 21 o1 and the output voltage V at (full code + 1 LSB) of the lower-bit side capacitor array 22 o1 so that is equal, and (2) Damping capacitor C a2 is the output voltage V of the lower bit side capacitor array 22 at 1 LSB of the lower bit side capacitor array 22 o2 and the output voltage V of the lower bit side capacitor array 22 at (full code + 1 LSB) of the lower bit side capacitor array 23. o2 so that is equal to You can set each one individually.

[0097] As described above, according to the charge scaling DA conversion device 1A of the second embodiment, by configuring the three-stage capacitor arrays 21, 22, and 23, it is possible to increase the resolution of the DA conversion device compared to the charge scaling DA conversion device 1 of the first embodiment, and also to reduce the unit capacitance C u When there is a voltage dependency like MOS capacitance, the unit capacitance C u By setting the bias voltage so that the operating point of the DAC 100 is substantially in a range with low voltage dependency, the nonlinearity of the output voltage of the DAC 100 can be reduced. That is, the charge scaling DAC 100 according to the second embodiment has the same effects as the charge scaling DAC 100 according to the first embodiment.

[0098] (Embodiment 3) 8 is a block diagram showing an example of the configuration of a successive approximation type AD conversion device 31 according to the third embodiment. In FIG. 8, the successive approximation type AD conversion device 31 according to the third embodiment includes: (1) A charge scaling DA conversion device 1 according to the first embodiment of FIG. 1; (2) Input voltage V in Sampling capacitor 2 (capacity C s )and, (3) Based on the reset signal RST11, the sampled input voltage V in Reset switch SW to switch whether to pass or block S and, (4) Sampled input voltage V in and the output voltage V from the DA converter 1, which is the reference voltage. o1 a comparator 3 that compares the above and outputs a comparison result signal; (5) In response to the comparison result signal of the comparator 3, the bit signals b0 to b n+m+1 and outputting the result to the DA conversion device 1 via a control circuit 10B; (6) A control circuit 10B provided in place of the control circuit 10 of FIG. 1; The SAR control logic circuit 4 and the control circuit 10B operate based on a clock CLOCK. The differences will be explained below.

[0099] In FIG. 8, the control circuit 10B outputs a reset signal RST11 at H level to the reset switch SW s By outputting to the control terminal of the switch SW s Next, the control circuit 10B turns on the input voltage V in The reset switch SW s After that, the control circuit 10B turns off the input voltage V in is connected to a predetermined fixed potential. As an example, the reset switch SW s The input voltage V in When the fixed potential connected to is 0V, the input terminal of comparator 3 has a voltage (V rst11 -V in ) is sampled and input.

[0100] Here, in order to remove errors in the previous stage of the AD conversion device 31, a predetermined input reset voltage V is first used instead of the input voltage Vin. inrst Enter the reset switch SW s When the input signal voltage V insig Alternatively, correlated double sampling may be used, where the reset voltage V rst11 is the reset voltage V of the charge scaling DA converter 1 rst1 Alternatively, when a comparator 3 with auto-zero function and an input offset storage function is used, the output voltage of the comparator 3 during auto-zero when the input and output terminals of the comparator 3 are shorted may be used. Also, the reset signal RST1 of the charge scaling DA converter 1 may be used as the reset signal RST11.

[0101] Input voltage V in After sampling, the SAR control logic circuit 4 controls the output voltage V o1 to a predetermined voltage (V refp -V refm ) / 2 via the control circuit 10B. refp ,V refm are the reference voltages of the DA conversion device 1, where V refp >V refm Then, the comparator 3 detects the input voltage V in and the output voltage V of the DA converter 1 o1 The SAR control logic circuit 4 then compares the output voltage V of the DA conversion device 1, which becomes the comparison reference voltage for the comparator 3 for the next bit conversion, to obtain the conversion result of the most significant bit MSB. o1 Based on the MSB conversion result, refp -V refm ) / 2±(V refp -V refm ) / 4. After that, the SAR control logic circuit 4 performs the comparison in the same way up to the least significant bit LSB, and updates the output voltage V o1 The output voltage V of the DA converter 1 is updated. o1 and the input voltage V of comparator 3 inAD conversion is performed by sequentially performing a binary search based on the comparison result so that

[0102] The successive approximation type AD conversion device 31 according to the third embodiment configured as described above improves the nonlinearity of the DA conversion device 1 used to generate the reference voltage, thereby improving the linearity of the AD conversion device 31. Furthermore, by making it possible to use a MOS capacitor with the highest capacitance density per unit area in the semiconductor process used for the reference capacitance of the DA conversion device 1, it is possible to achieve the function in a small area.

[0103] In the third embodiment described above, the charge scaling DA converter 1 is used, but the present invention is not limited to this, and the charge scaling DA converter 1A according to the second embodiment may also be used.

[0104] (Embodiment 4) Fig. 9 is a block diagram showing an example of the configuration of a successive approximation type AD conversion device 32 according to embodiment 4. In Fig. 9, the successive approximation type AD conversion device 32 according to embodiment 4 differs from the successive approximation type AD conversion device 31 in Fig. 8 in the following points. (1) Sampling capacitor 2 (capacity C s ) and reset switch SW S Do not use. (2) Instead of the DA conversion device 1, a DA conversion device 1B including a control circuit 10C is provided. (3) The comparator 3 compares a predetermined common voltage Vcm with the output voltage from the DA conversion device 1B. The SAR control logic circuit 4 and the control circuit 10C operate based on the clock CLOCK. The differences will be explained below.

[0105] The DA conversion device 1B is configured such that the switches SW m+1 ~SW n+m+1 In this case, the input voltage V of the AD converter in9. By adding an input terminal (input terminal c in FIG. 9) to which the above signal is input, a comparator 3 and an SAR control logic circuit 4 are added, similarly to the third embodiment, thereby configuring a successive approximation type AD conversion device 32.

[0106] In the AD conversion device 32 configured as above, the input voltage V in The sampling is performed in the most significant bit side capacitor array 21 of the DA conversion device 1B. The SAR control logic circuit 4 controls the control circuit 10C to turn on the reset switch SW rst1 is turned on, and the switch SW m+1 ~SW n+m+1 By switching each to the input terminal c side, the input voltage V in After that, the control circuit 10C connects the L-level reset signal RST1 to the reset switch SW rst1 By outputting to the control terminal of the reset switch SW rst1 Turn it off.

[0107] Next, the input voltage V in After sampling, the SAR control logic circuit 4 controls the DA converter of the lower-bit side capacitor array 22 to output the output voltage V o1 is controlled so that the following equation holds, and the comparator 3 detects the common voltage V cm A comparison is made to the

[0108] V o1 =(V refp -V refm ) / 2-V in

[0109] Then, in the AD conversion of the next bit, the DA converter of the lower-bit side capacitor array 22 is used to obtain the output voltage V o1 is updated based on the DA conversion result in the most significant bit capacitor array 21 so as to satisfy the following equation:

[0110] V o1 =(V refp -V refm ) / 2±(V refp -Vrefm ) / 4-V in

[0111] Thereafter, the comparison is similarly performed up to the least significant bit LSB, and the output voltage of the DA converter of the lower-bit side capacitor array 22 is updated, and the output voltage V o1 is the common voltage V cm Based on the comparison result of the comparator 3, the SAR control logic circuit 4 performs AD conversion by sequentially performing a binary search.

[0112] The successive approximation type AD conversion device 32 according to the fourth embodiment configured as described above has a unique effect compared to the second embodiment in that the input voltage of the comparator 3, which is updated in accordance with the successive approximation operation, does not depend on the input voltage of the AD conversion device but gradually approaches the reference common voltage Vcm, thereby reducing the changes in the offset and kickback noise of the comparator 3 that depend on the input voltage of the comparator 3.

[0113] In the fourth embodiment described above, the charge scaling DA converter 1 is used, but the present invention is not limited to this, and the charge scaling DA converter 1A according to the second embodiment may also be used.

[0114] (Embodiment 5) Fig. 10 is a block diagram showing a configuration example of a successive approximation type AD conversion device 33 according to embodiment 5. In Fig. 10, the successive approximation type AD conversion device 33 according to embodiment 5 is characterized in that the successive approximation type AD conversion device 32 according to embodiment 3 has a differential configuration. Therefore, compared to the successive approximation type AD conversion device 32, the successive approximation type AD conversion device 33 has the following configuration. (1) Sampling capacitor 2 (capacity C s ) is configured by a pair of DA conversion devices 1, 1 according to the first embodiment. (2) The output voltage of the first DA conversion device 1 is output to a first input terminal of a comparator 3A, and the first input terminal is connected to a reset switch SW1 of the first DA conversion device 1, which is connected to a sample and hold signal SH. rst1 Sampling switch SW sp , the reset voltage V rst1 the first input voltage Vinp and based on the sample-and-hold signal SH from the control circuit 10D, inp The sampling switch SW sp Enter via. (3) The output voltage of the second DA conversion device 1 is output to the second input terminal of the comparator 3A, and the reset signal RST1 of the second DA conversion device 1 is connected to the second input terminal as a sample-and-hold signal SH, and the reset switch SW rst1 Sampling switch SW sm , the reset voltage V rst1 to the second input voltage V inm and based on the sample-and-hold signal SH from the control circuit 10D, inm The sampling switch SW sm Enter via. (4) The SAR control logic circuit 4A, which is provided in place of the SAR control logic circuit 4, controls the operation of the DA conversion devices 1, 1 via the control circuit 10D. n+m+1 are the switches SW0 to SW n+m+1 Switch between bm0 and bm n+m+1 are the switches SW0 to SW3 of the second DA conversion device 1. n+m+1 The SAR control logic circuit 4A and the control circuit 10D operate based on a clock CLOCK.

[0115] In the successive approximation type AD converter 33 configured as above, first, the sampling switch SW sp ,SW sm Then, the differential input voltage V inp ,V inm The differential input voltage V inp ,V inmAfter sampling, the comparator 3A compares the pair of differential input voltages from the DA conversion devices 1,1 and outputs a comparison judgment result signal to the SAR control logic circuit 4A. Based on the comparison judgment result signal, the SAR control logic circuit 4A controls each output voltage of the DA conversion devices 1,1 so that the input differential voltage to the comparator 3A becomes smaller. Thereafter, based on the comparison judgment result signal of the comparator 3A, the SAR control logic circuit 4A controls each output voltage of the DA conversion devices 1,1 so that the input differential voltage to the comparator 3A becomes smaller in the same manner, thereby performing AD conversion by sequentially performing a binary search.

[0116] As described above, according to the fifth embodiment, the AD conversion device of the fourth embodiment can be configured in a differential manner, and a pair of differential input voltages V inp ,V inm can be converted to AD.

[0117] In the fifth embodiment described above, the DA conversion devices 1, 1 are used, but the present invention is not limited to this, and the DA conversion devices 1A, 1A may also be used.

[0118] (Embodiment 6) Fig. 11 is a block diagram showing an example of the configuration of a successive approximation type AD conversion device 34 according to the sixth embodiment. In Fig. 11, the successive approximation type AD conversion device 34 according to the sixth embodiment differs from the successive approximation type AD conversion device 33 according to the fifth embodiment shown in Fig. 10 in the following points. (1) The DA converters 1, 1 of the successive approximation type AD converter 33 are configured by the DA converters 1, 1B, 1B shown in FIG. 9, respectively. (2) A control circuit 10E is provided instead of the control circuit 10D. The SAR control logic circuit 4A and the control circuit 10E operate based on a clock CLOCK.

[0119] In the successive approximation type AD conversion device 34 of the sixth embodiment configured as described above, a pair of DA conversion devices 1B, 1B performs a sampling operation similar to that of the DA conversion device 1B of the fourth embodiment, and then performs AD conversion similar to the operation after sampling of the AD conversion device 33 of the fifth embodiment.

[0120] As described above, according to the sixth embodiment, a differential configuration can be achieved using the DA conversion devices 1B, 1B of the third embodiment, and a pair of differential input voltages V inp ,V inm can be converted to AD.

[0121] In the above embodiment, the reference voltage V ref1m ,V ref1p and reference voltage V ref2m ,V ref2p However, the present invention is not limited to this, and two different reference voltages may be used. [Industrial Applicability]

[0122] As described above in detail, according to the semiconductor device of the present invention, in a charge scaling DA converter using MOS capacitance, by increasing the size of the attenuation capacitor and, for example, lowering the reference voltage of the lower-bit capacitor array, it is possible to set the bias voltage of the MOS capacitance so that the MOS capacitance operates in a range with substantially low voltage dependency, thereby reducing the nonlinearity of the output voltage of the DA converter. [Explanation of symbols]

[0123] 1,1A,1B DA conversion device 2 sampling capacitors 3,3A comparator 4,4A Successive Approximation Control Logic Circuit (SAR Control Logic Circuit) 10, 10A, 10B, 10C, 10D, 10E Control circuit 21 High-order bit capacitor array 22,23 Lower-bit capacitor array 31~34 AD conversion device C10~C1 n capacitor C20~C2 m capacitor C a Damping Capacitor SW rst1 ,SW rst2 ,SW rst3 ,SWs Reset switch SW0~SW m ,SW m+1 ~SW n+m+1 ,SW0~SW k ,SW k+1 ~SW m+k+1 ,SW m+k+1 ~SW n+m+k+2 switch SW sp ,SW sm Sampling Switch

Claims

1. A charge scaling DA converter including a most significant bit side capacitor array and a least significant bit side capacitor array connected via an attenuation capacitor, the most significant bit side capacitor array includes a plurality of MOS capacitors having a binary-weighted capacitance ratio; the lower-order bit capacitor array includes a plurality of MOS capacitors having a binary-weighted capacitance ratio; The DA conversion device a control circuit that applies a positive bias voltage or a negative bias voltage to the plurality of capacitors in the most significant bit side capacitor array and the plurality of capacitors in the least significant bit side capacitor array at the time of resetting and conversion of the DA conversion device, At least one of the reference voltage and the reset voltage of the lower bit side capacitor array is set to a value different from the reference voltage of the upper bit side capacitor array. DA conversion device.

2. The DA conversion device a capacitor on the lower bit side of the lower bit side capacitor array via another attenuation capacitor; Further comprising another lower-order bit capacitor array including a plurality of capacitors of MOS capacitance having a binary-weighted capacitance ratio; 2. The DA conversion device according to claim 1.

3. 3. The DA conversion device according to claim 1 or 2, a sampling capacitor for sampling the input voltage; a reset switch for resetting the sampled input voltage; a comparator that compares the sampled input voltage with the output voltage from the DA conversion device and outputs a comparison result signal; a successive approximation control logic circuit that controls the DA conversion device based on a comparison result signal from the comparator to perform AD conversion of the input voltage. AD conversion device.

4. An AD conversion device comprising the DA conversion device according to claim 1 or 2. the DA conversion device further comprises a plurality of switches that selectively switch between inputting an input voltage and inputting two different reference voltages to each of the plurality of capacitors in the most significant bit side capacitor array, The AD conversion device a comparator that compares a predetermined common voltage with an output voltage from the DA conversion device and outputs a comparison result signal; a successive approximation control logic circuit that controls the plurality of switches via the DA conversion device based on a comparison result signal from the comparator to perform AD conversion of the input voltage. AD conversion device.

5. 1. A successive approximation type AD conversion device that performs AD conversion on a pair of differential input voltages including first and second input voltages, a pair of DA conversion devices, each of which is the DA conversion device according to claim 1 or 2; a comparator that samples the first and second input voltages, compares the pair of sampled differential voltages with each other, and outputs a comparison result signal; a successive approximation control logic circuit that controls the pair of DA conversion devices based on a comparison result signal from the comparator to perform AD conversion of the pair of differential input voltages, AD conversion device.

6. 1. A successive approximation type AD conversion device that performs AD conversion on a pair of differential input voltages including first and second input voltages, a pair of DA conversion devices that are the DA conversion device according to claim 4; the first input voltage is input to one of the pair of DA conversion devices, and the second input voltage is input to the other of the pair of DA conversion devices; a comparator that compares the output voltages from the pair of DA converters with each other and outputs a comparison result signal; a successive approximation control logic circuit that controls the pair of DA conversion devices based on a comparison result signal from the comparator to perform AD conversion of the pair of differential input voltages, AD conversion device.

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