Resistance change type random access memory device and manufacturing method thereof

Abstract

To provide an improved resistance change type random access memory device in order to solve deficiencies or disadvantages of the existing technology.SOLUTION: A resistance change type random access memory device includes a first ILD layer on a substrate, a first interconnect structure in the first ILD layer, a capping layer on the first interconnect structure and the first ILD layer, an intermediate dielectric layer on the capping layer, conductive vias in the capping layer and the intermediate dielectric layer, and resistive switching elements on the conductive vias. The resistive switching element includes a lower electrode layer, an upper electrode layer, and a resistive switching material layer interposed between an upper electrode layer and a lower electrode layer. A hard mask layer is disposed on the resistive switching element. The second interconnect structure is disposed on the hard mask layer and the resistive switching element. The second interconnect structure includes a lug portion in direct contact with an upper sidewall of the upper electrode layer of the resistive switching element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor technology, and more particularly to resistive random access memory (RRAM) devices and methods for fabricating the same. [Background technology]

[0002] Resistive random access memory (RRAM) is a memory structure that contains an array of RRAM cells, each of which stores one bit of data using resistance rather than electrical charge. Specifically, each RRAM cell contains a layer of resistive switching material, the resistance of which can be adjusted to represent a logic "0" or a logic "1."

[0003] At advanced technology nodes, feature sizes shrink, and memory device sizes shrink accordingly. However, the shrinkage of RRAM devices is limited by the "formation" operation. During the "formation" process, high voltages are applied to the RRAM device to create a conductive path in the resistive switching material layer.

[0004] During the RRAM fabrication process, the etching process can damage the top electrode of the resistive switching element and cause a non-uniform surface profile on the top electrode, which affects the uniform deposition of the barrier layer in the subsequent top interconnect structure and reduces device reliability. Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved resistive random access memory (RRAM) device and method for fabricating the same to overcome the deficiencies or shortcomings of existing technology. [Means for solving the problem]

[0006] One aspect of the present invention provides a resistive random access memory device including a substrate, a first interlayer dielectric (ILD) layer disposed on the substrate, a first interconnect structure disposed within the first ILD layer, a capping layer disposed on the first interconnect structure and the first ILD layer, an intermediate dielectric layer disposed on the capping layer, and a conductive via disposed within the capping layer and the intermediate dielectric layer. The conductive via is electrically coupled to the first interconnect structure. A resistive switching element is disposed on the conductive via. The resistive switching element includes a bottom electrode layer, an upper electrode layer, and a resistive switching material layer interposed between the top electrode layer and the bottom electrode layer. A hard mask layer is disposed on the resistive switching element. A second interconnect structure is disposed on the hard mask layer and the resistive switching element. The second interconnect structure includes a lug portion in direct contact with an upper sidewall of the upper electrode layer of the resistive switching element.

[0007] According to some embodiments, the resistive random access memory device further includes sidewall spacers surrounding the resistive switching element.

[0008] According to some embodiments, the resistive random access memory device further includes a second inter-level dielectric (ILD) layer disposed around the sidewall spacers and the second interconnect structure.

[0009] According to some embodiments, the sidewall spacers are in direct contact with the resistive switching element and the interlevel dielectric layer.

[0010] According to some embodiments, the sidewall spacers comprise a silicon nitride layer or a silicon oxide layer.

[0011] According to some embodiments, the hard mask layer comprises a silicon oxide layer or a silicon nitride layer.

[0012] According to some embodiments, the conductive via includes a barrier layer and a tungsten layer on the barrier layer.

[0013] According to some embodiments, the barrier layer comprises titanium nitride.

[0014] According to some embodiments, the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.

[0015] According to some embodiments, the interlevel dielectric layer comprises a TEOS-based silicon oxide layer.

[0016] Another aspect of the present invention provides a method for forming a resistive random access memory device. A substrate is provided. A first interlayer dielectric (ILD) layer is formed on the substrate. A first interconnect structure is formed in the first ILD layer. A capping layer is formed on the first interconnect structure and the first ILD layer. An intermediate dielectric layer is formed on the capping layer. A conductive via is formed in the capping layer and the intermediate dielectric layer. The conductive via is electrically coupled to the first interconnect structure. A resistive switching element is formed on the conductive via. The resistive switching element includes a bottom electrode layer, a top electrode layer, and a resistive switching material layer interposed between the top electrode layer and the bottom electrode layer. A hard mask layer is formed on the resistive switching element. A second interconnect structure is formed on the hard mask layer and the resistive switching element. The second interconnect structure includes a lug portion in direct contact with an upper sidewall of the top electrode layer of the resistive switching element.

[0017] According to some embodiments, the method further comprises forming a sidewall spacer surrounding the resistive switching element.

[0018] According to some embodiments, the method further includes forming a second inter-level dielectric (ILD) layer around the sidewall spacers and the second interconnect structure.

[0019] According to some embodiments, the sidewall spacers are in direct contact with the resistive switching element and the interlevel dielectric layer.

[0020] According to some embodiments, the sidewall spacers comprise a silicon nitride layer or a silicon oxide layer.

[0021] According to some embodiments, the hard mask layer comprises a silicon oxide layer or a silicon nitride layer.

[0022] According to some embodiments, the conductive via includes a barrier layer and a tungsten layer on the barrier layer.

[0023] According to some embodiments, the barrier layer comprises titanium nitride.

[0024] According to some embodiments, the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.

[0025] According to some embodiments, the interlevel dielectric layer comprises a TEOS-based silicon oxide layer. [Brief explanation of the drawings]

[0026] These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0027] [Figure 1] 1A to 1C are schematic diagrams illustrating a method for manufacturing a resistive random access memory device according to an embodiment of the present invention. [Figure 2] 1A to 1C are schematic diagrams illustrating a method for manufacturing a resistive random access memory device according to an embodiment of the present invention. [Figure 3] 1A to 1C are schematic diagrams illustrating a method for manufacturing a resistive random access memory device according to an embodiment of the present invention. [Figure 4] 1A to 1C are schematic diagrams illustrating a method for manufacturing a resistive random access memory device according to an embodiment of the present invention. [Figure 5] 1A to 1C are schematic diagrams illustrating a method for manufacturing a resistive random access memory device according to an embodiment of the present invention. [Figure 6]1A to 1C are schematic diagrams illustrating a method for manufacturing a resistive random access memory device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0028] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0029] Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the embodiments contained herein are defined by the appended claims.

[0030] 1 to 6 are schematic diagrams illustrating a method for fabricating a resistive random access memory device according to an embodiment of the present invention. As shown in FIG. 1, a substrate 100 is first provided. According to an embodiment of the present invention, the substrate 100 may be a semiconductor substrate, such as, but not limited to, a silicon substrate. A first interlayer dielectric (ILD) layer 110 is formed on the substrate 100. According to an embodiment of the present invention, the first ILD layer 110 may include, for example, a low-k material layer or an ultra-low-k (ULK) material layer. According to an embodiment of the present invention, the first ILD layer 110 has a thickness of, for example, about 800 to 900 angstroms.

[0031] According to one embodiment of the present invention, a first interconnect structure M1 is then formed in the first ILD layer 110. According to one embodiment of the present invention, for example, the first interconnect structure M1 may be a copper damascene structure formed by a copper damascene process. According to one embodiment of the present invention, a capping layer 120 is formed on the first interconnect structure M1 and the first ILD layer 110. According to one embodiment of the present invention, the capping layer 120 may include, for example, but is not limited to, a nitrogen-doped silicon carbide (NDC) layer. According to one embodiment of the present invention, the thickness of the capping layer 120 is, for example, about 100 angstroms.

[0032] According to one embodiment of the present invention, an intermediate dielectric layer 130 is formed on the capping layer 120. According to one embodiment of the present invention, the intermediate dielectric layer 130 may include, for example, but is not limited to, a tetraethoxysilane (TEOS)-based silicon oxide layer. According to one embodiment of the present invention, the thickness of the intermediate dielectric layer 130 may be, for example, about 100 to 500 angstroms.

[0033] 2, a chemical vapor deposition (CVD) process is then performed to deposit an interlevel dielectric layer 130 on the capping layer 120. According to one embodiment of the present invention, the interlevel dielectric layer 130 comprises, for example, a TEOS-based silicon oxide layer.

[0034] As shown in FIG. 3 , photolithography, etching, and metallization processes are performed to form a conductive via 200 in the interlevel dielectric layer 130 and the capping layer 120, thereby electrically connecting the conductive via 200 to the underlying first interconnect structure M1. According to one embodiment of the present invention, the height of the conductive via 200 is between about 200 and 600 angstroms, e.g., between 400 and 500 angstroms. According to one embodiment of the present invention, for example, the conductive via 200 may include a barrier layer 202 and a tungsten layer 203 located on the barrier layer 202. According to one embodiment of the present invention, the barrier layer 202 may include, for example, but is not limited to, titanium nitride. A tungsten chemical mechanical polishing (WCMP) process may be performed to remove the excess tungsten layer 203 on the interlevel dielectric layer 130.

[0035] As shown in FIG. 4 , a deposition process is then performed to form a film stack structure 300 on the conductive via 200 and the interlayer dielectric layer 130. According to one embodiment of the present invention, for example, the film stack structure 300 may include a bottom electrode layer 310, a resistive switching layer 320, a top electrode layer 330, and a hard mask layer 340. According to one embodiment of the present invention, for example, the bottom electrode layer 310 may include, but is not limited to, TaN, TiN, Pt, Ir, Ru, or W. The resistive switching layer 320 may include, but is not limited to, hafnium oxide, tantalum oxide, titanium, titanium oxide, or a combination thereof. The top electrode layer 330 may include, but is not limited to, TiN, TaN, Pt, Ir, or W. The hard mask layer 340 may include, but is not limited to, a silicon oxide layer or a silicon nitride layer.

[0036] 5, photolithography and etching processes are then performed to pattern the film stack structure 300 to form the resistance-switching element 300a, leaving a hard mask layer 340 with a predetermined thickness on the top electrode layer 330. According to one embodiment of the present invention, the predetermined thickness may be, but is not limited to, a range of 0 to 500 angstroms.

[0037] As shown in FIG. 6 , a deposition process is performed to form sidewall spacers SP surrounding the resistive switching element 300a. According to one embodiment of the present invention, for example, the sidewall spacers SP may comprise a silicon nitride layer or a silicon oxide layer. According to one embodiment of the present invention, the sidewall spacers SP directly contact the resistive switching element 300a and the interlayer dielectric layer 130. Next, a deposition process is performed to form a second interlayer dielectric (ILD) layer 160 on the sidewall spacers SP and the resistive switching element 300a, such that the second ILD layer 160 covers the remaining hard mask layer 340. According to one embodiment of the present invention, for example, the second ILD layer 160 may comprise a low-k material layer or an ultra-low-k material layer.

[0038] Next, using photolithography, etching, and metallization processes, a second interconnect structure M2 is formed on the second ILD layer 160, which is disposed on the hard mask layer 340 and the resistive switching element 300a. The second interconnect structure M2 includes a lug portion LP that directly contacts the upper sidewall S1 of the top electrode layer 330 of the resistive switching element 300a. According to one embodiment of the present invention, for example, the lug portion LP extends downwardly by less than half the thickness of the top electrode layer 330.

[0039] Because all (or at least a majority, e.g., at least 80% or more of the area) of the top surface of the top electrode layer 330 of the resistance-switching element 300a is covered by the remaining hard mask layer 340, the second interconnect structure M2 is in direct contact only with the top sidewall S1 (or the top sidewall S1 and the top corner) of the top electrode layer 330. During operation, current flows through the lug portion LP and the top sidewall S1 of the top electrode layer 330 to complete resistance-state switching of the resistance-switching element 300a.

[0040] 6, the resistive random access memory device 1 includes a substrate 100, a first ILD layer 110 disposed on the substrate 100, a first interconnect structure M1 disposed on the first ILD layer 110, a capping layer 120 disposed on the first interconnect structure M1 and the first ILD layer 110, an intermediate dielectric layer 130 disposed on the capping layer 120, and a conductive via 200 disposed within the capping layer 120 and the intermediate dielectric layer 130. The conductive via 200 is electrically connected to the first interconnect structure M1.

[0041] According to one embodiment of the present invention, the resistive random access memory device 1 further includes a resistive switching element 300a disposed on the conductive via 200. The resistive switching element 300a includes a bottom electrode layer 310, a top electrode layer 330, and a resistive switching layer 320 between the top electrode layer 330 and the bottom electrode layer 310.

[0042] According to one embodiment of the present invention, the resistive random access memory device 1 further includes a hard mask layer 340 disposed on the resistive switching element 300a.

[0043] According to one embodiment of the present invention, the resistive random access memory device 1 further includes a second interconnect structure M2 disposed on the hard mask layer 340 and the resistance-switching element 300a. The second interconnect structure M2 includes a lug portion LP in direct contact with the top sidewall S1 of the top electrode layer 330 of the resistance-switching element 300a.

[0044] According to one embodiment of the present invention, the resistive random access memory device 1 further includes a sidewall spacer SP surrounding the resistance switching element 300a.

[0045] According to one embodiment of the present invention, the resistive random access memory device 1 further includes a second ILD layer 160 disposed around the sidewall spacers SP and the second interconnect structure M2.

[0046] According to one embodiment of the present invention, the sidewall spacers SP are in direct contact with the resistive switching element 300a and the interlevel dielectric layer 130.

[0047] According to one embodiment of the present invention, the sidewall spacers SP comprise a silicon nitride layer or a silicon oxide layer.

[0048] According to one embodiment of the present invention, the hard mask film 340 includes a silicon oxide layer or a silicon nitride layer.

[0049] According to one embodiment of the present invention, conductive via 200 includes a barrier layer 202 and a tungsten layer 203 located on barrier layer 202 .

[0050] According to one embodiment of the present invention, the barrier layer 202 comprises titanium nitride.

[0051] According to one embodiment of the present invention, the capping layer 120 comprises a nitrogen-doped silicon carbide layer.

[0052] According to one embodiment of the present invention, the interlevel dielectric layer 130 comprises a TEOS-based silicon oxide layer.

[0053] Those skilled in the art will readily recognize that numerous modifications and variations of the apparatus and method may be made while retaining the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. A resistive random access memory device, comprising: A substrate; a first interlevel dielectric (ILD) layer disposed on the substrate; a first interconnect structure disposed within the first ILD layer; a capping layer disposed on the first interconnect structure and the first ILD layer; an intermediate dielectric layer disposed on the capping layer; a conductive via disposed within the capping layer and the interlevel dielectric layer, the conductive via electrically coupled to the first interconnect structure; a resistive switching element disposed over the conductive via, the resistive switching element including a bottom electrode layer, a top electrode layer, and a resistive switching material layer interposed between the top electrode layer and the bottom electrode layer; and a hard mask layer disposed over the resistive switching element; a second interconnect structure disposed on the hard mask layer and the resistance-switching element, the second interconnect structure including a lug portion in direct contact with a top sidewall of the top electrode layer of the resistance-switching element.

2. The resistive random access memory device of claim 1 , further comprising a sidewall spacer surrounding the resistive switching element.

3. The resistive random access memory device of claim 2 , further comprising a second inter-level dielectric (ILD) layer disposed around the sidewall spacers and the second interconnect structure.

4. The resistive random access memory device of claim 2 , wherein the sidewall spacers are in direct contact with the resistive switching element and the interlevel dielectric layer.

5. The resistive random access memory device of claim 2 , wherein the sidewall spacers comprise a silicon nitride layer or a silicon oxide layer.

6. The resistive random access memory device of claim 1 , wherein the hard mask layer comprises a silicon oxide layer or a silicon nitride layer.

7. The resistive random access memory device of claim 1 , wherein the conductive via includes a barrier layer and a tungsten layer on the barrier layer.

8. The resistive random access memory device of claim 7 , wherein the barrier layer comprises titanium nitride.

9. The resistive random access memory device of claim 1 , wherein the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.

10. The resistive random access memory device of claim 1 , wherein the intermediate dielectric layer comprises a TEOS-based silicon oxide layer.

11. 1. A method for forming a resistive random access memory device, comprising: providing a substrate; forming a first interlayer dielectric (ILD) layer over the substrate; forming a first interconnect structure in the first ILD layer; forming a capping layer over the first interconnect structure and the first ILD layer; forming an intermediate dielectric layer over the capping layer; forming a conductive via in the capping layer and the interlevel dielectric layer, the conductive via electrically coupled to the first interconnect structure; forming a resistive switching element over the conductive via, the resistive switching element including a bottom electrode layer, a top electrode layer, and a resistive switching material layer interposed between the top electrode layer and the bottom electrode layer; forming a hard mask layer over the resistive switching element; forming a second interconnect structure on the hard mask layer and the resistive switching element, the second interconnect structure including a lug portion in direct contact with a top sidewall of the top electrode layer of the resistive switching element.

12. The method of claim 11 , further comprising forming sidewall spacers surrounding the resistive switching element.

13. 13. The method of claim 12, further comprising forming a second inter-level dielectric (ILD) layer around the sidewall spacers and the second interconnect structure.

14. The method of claim 12 , wherein the sidewall spacers directly contact the resistive switching element and the interlevel dielectric layer.

15. The method of claim 12 , wherein the sidewall spacers comprise a silicon nitride layer or a silicon oxide layer.

16. 12. The method of claim 11, wherein the hard mask layer comprises a silicon oxide layer or a silicon nitride layer.

17. 12. The method of claim 11, wherein the conductive via comprises a barrier layer and a tungsten layer on the barrier layer.

18. 20. The method of claim 17, wherein the barrier layer comprises titanium nitride.

19. The method of claim 11 , wherein the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.

20. The method of claim 11 , wherein the interlevel dielectric layer comprises a TEOS-based silicon oxide layer.

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