Substrate processing method and substrate processing apparatus

Abstract

To reduce roughness of wiring.SOLUTION: (A) in a substrate processing method provides a substrate having a first surface and a second surface. (B) forms a dielectric film. (C) forms, on the dielectric film, a first hard mask of a metal oxide film that contains one or more metal elements and does not include a crystalline film. (F) forms a first film related to a resist for first pattern formation after (C). (G) forms recesses corresponding to a first pattern in the first hard mask by etching the first hard mask after (F). (H) forms recesses corresponding to the first pattern in the dielectric film by etching the dielectric film. (I) removes the first hard mask by cleaning after (H). (J) embeds metal in the recesses of the dielectric film. (K) planarizes the metal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a substrate processing method and a substrate processing apparatus. [Background technology]

[0002] For example, Patent Document 1 discloses that "in a method for forming a dual damascene structure, a layered structure of an organic insulating film and a metal oxide is formed as a hard mask on an inorganic insulating film, and then patterned and etched, and at least one type of metal oxide selected from B, Al, Ga, In, Tl, Si, Ge, Sn, Pb, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Mn, Zn, Cd, P, As, Sb, Bi, and Ce is used as the metal oxide film."

[0003] Patent Document 2 discloses a "dry etching method for an oxide semiconductor film containing at least In, Ga, and Zn, characterized in that the etching is performed in a gas atmosphere containing hydrocarbon."

[0004] Patent Document 3 discloses a "substrate processing method for a hard mask that has a high selectivity to an object to be processed made of an oxide containing one or more of gallium, indium, and zinc and can be thinned." [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-299441 [Patent Document 2] Special Publication No. 2007-335505 [Patent Document 3] Japanese Patent Application Publication No. 2023-127329 Summary of the Invention [Problem to be solved by the invention]

[0006] The present disclosure provides a technique that can reduce the roughness of wiring. [Means for solving the problem]

[0007] One aspect of the present disclosure provides a substrate processing method. The substrate processing method includes steps (A) to (K). In step (A), a substrate having a first surface and a second surface opposite the first surface is provided. In step (B), a dielectric film is formed on the first surface. In step (C), a metal oxide film containing one or more metal elements in a predetermined composition is formed on the dielectric film as a first hard mask, the metal oxide film not including a crystalline film. In step (F), a resist-related first film having a first pattern formed thereon is formed after step (C). In step (G), after step (F), the first hard mask is etched to form recesses in the first hard mask corresponding to the first pattern. In step (H), the dielectric film is etched to form recesses in the dielectric film corresponding to the first pattern. In step (I), the first hard mask is removed by cleaning the substrate after step (H). In step (J), a metal is filled in the recesses formed in the dielectric film. In step (K), the metal is planarized. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to reduce the roughness of wiring. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a flowchart showing an example of a substrate processing method according to the first embodiment. [Figure 2A] FIG. 2A is a schematic cross-sectional view of each step of the damascene structure. [Figure 2B] FIG. 2B is a schematic cross-sectional view of each step of the damascene structure. [Figure 2C] FIG. 2C is a schematic cross-sectional view of each step of the damascene structure. [Figure 3] FIG. 3 is a diagram showing the composition ratio of metal elements in the first hard mask. [Figure 4]FIG. 4 is a graph showing an example of the crystallinity of the first hard mask. [Figure 5] FIG. 5 is a time chart showing an example of the etching process of the first hard mask. [Figure 6] FIG. 6 shows an example of the result of cyclic etching of the first hard mask. [Figure 7] FIG. 7 is a graph showing an example of the results of the cleaning process of the substrate surface. [Figure 8] FIG. 8 is a graph showing another example of the results of the cleaning process of the substrate surface. [Figure 9] FIG. 9 is a flowchart showing an example of a substrate processing method according to the second embodiment. [Figure 10A] FIG. 10A is a schematic cross-sectional view showing each step of the dual damascene structure. [Figure 10B] FIG. 10B is a schematic cross-sectional view of each step of the dual damascene structure. [Figure 11] FIG. 11 is a diagram showing an example of roughness in each step of the substrate processing method. [Figure 12] FIG. 12 is a diagram schematically illustrating the configuration of a film forming apparatus according to an embodiment. [Figure 13] FIG. 13 is a diagram schematically illustrating the configuration of a film forming apparatus according to an embodiment. [Figure 14] FIG. 14 is a diagram schematically illustrating the configuration of an etching apparatus according to an embodiment. [Figure 15] FIG. 15 is a diagram schematically illustrating the configuration of a cleaning device according to one embodiment. [Figure 16] FIG. 16 is a diagram showing the configuration of a cleaning device according to a modified example. [Figure 17] FIG. 17 is a diagram schematically illustrating the configuration of a substrate processing system according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The following describes in detail embodiments of the disclosed substrate processing method and substrate processing apparatus with reference to the drawings. Note that the substrate processing method and substrate processing apparatus according to the present disclosure are not limited to these embodiments, and the following embodiments can be appropriately combined within the scope of the present disclosure, so long as they do not cause any contradiction between the configurations and processing contents.

[0011] The drawings referred to below are schematic diagrams for the convenience of explanation, and therefore some details may be omitted and the dimensional proportions may not necessarily correspond to those of the actual objects.

[0012] As semiconductor devices become more highly integrated and faster, the capacitance between interconnects and the resistance of metal interconnects are decreasing. The resistance of metal interconnects depends not only on the resistivity of the metal material but also on the roughness of the metal interconnect itself. As the roughness of metal interconnects deteriorates, the probability that electromagnetic waves are reflected by the sidewalls of the interconnect increases, ultimately reducing the propagation efficiency of electromagnetic signals, which is manifested as an increase in the resistance of the metal interconnects.

[0013] In recent years, damascene or dual damascene structures have been adopted in semiconductor metal wiring processes. In the fabrication of such structures, the processes that primarily affect the roughness of metal wiring are the etching and cleaning processes of the wiring pattern. In the etching process, resist masks or titanium nitride (TiN) metal masks are sometimes used to etch the wiring pattern. In the etching process of wiring patterns using resist masks, in fine regions with a wiring pattern pitch of 60 nm or less, the resist mask may disappear during the process due to insufficient selectivity of the resist mask to the wiring layer. If a thicker resist mask is formed to prevent the disappearance of the resist mask, the resist mask may fall over due to the high aspect ratio, or adjacent resist masks may collapse against each other, causing kissing, which worsens the roughness. Therefore, metal masks are increasingly being used in such fine regions, and the use of TiN metal masks in particular is increasing.

[0014] However, even when etching wiring patterns using TiN metal masks, a thick TiN metal mask is used due to insufficient selectivity. This can lead to wiggling, a wavy sidewall of the wiring pattern, due to the stress of the metal mask, affecting the roughness of the metal wiring. TiN metal masks also have a reduced transmittance, which can make alignment of multilayer wiring difficult, further affecting the roughness of copper wiring. Furthermore, because TiN is crystalline, grain boundaries tend to increase the roughness of metal wiring. Therefore, if copper is embedded in the wiring pattern without cleaning the substrate surface after the wiring pattern etching process, the roughness of the TiN metal mask can be transferred to the copper wiring, potentially increasing the resistance of the copper wiring. While chemicals exist that selectively clean TiN metal masks without damaging the underlying dielectric film to prevent the increase in copper wiring resistance, these are expensive and increase costs.

[0015] In contrast, one embodiment of the present disclosure provides a substrate processing method in which an IGZO-based metal oxide film having a predetermined composition is used as a mask material to form a wiring pattern on an underlying dielectric film by etching. This reduces the roughness of the metal wiring. Note that the substrate processing method according to the first embodiment of the present disclosure exemplifies the formation of a damascene structure, and the substrate processing method according to the second embodiment exemplifies the formation of a dual damascene structure.

[0016] [First embodiment] A substrate processing method according to a first embodiment of the present disclosure will be described with reference to Figures 1, 2A, 2B, and 2C. Figure 1 is a flowchart showing an example of the substrate processing method according to the first embodiment. Figures 2A to 2C are schematic cross-sectional views of each step of a damascene structure.

[0017] <Step ST1: Preparation of the substrate> In step ST1, a substrate on which metal wiring is to be formed is provided. The substrate is provided in a processing chamber of a film forming apparatus, which will be described later, after its surface is cleaned to remove particles. In the example of FIG. 2A(A), a substrate W having a silicon substrate 101 is prepared in the processing chamber. The substrate W has a first surface 200 and a second surface 201 opposite to the first surface. The first surface 200 is the front surface of the substrate W, and the second surface 201 is the back surface of the substrate W. Step ST1 is an example of step (A).

[0018] <Step ST2: Deposition of dielectric film> Next, in step ST2, a dielectric film is formed on the first surface 200. The dielectric film may be a low-k film with a low dielectric constant. The dielectric film may be a SiCOH film or a SiO film. A SiCN film may be inserted between the dielectric film and the silicon substrate 101. A cap film may be formed on the dielectric film. The cap film may be a SiO film or a SiN film. In the substrate W illustrated in FIG. 2A(B), a SiCN film 102, a dielectric film 103, and a cap film 104 are formed in this order on the silicon substrate 101. The cap film 104 has the function of improving adhesion between the dielectric film 103 and a first hard mask 105 on the cap film 104 and the function of protecting the dielectric film 103 from damage during the formation of the first hard mask 105. The SiCN film 102 has the function of improving adhesion between the silicon substrate 101 and the dielectric film 103. The SiCN film 102 and the cap film 104 may be omitted. Step ST2 is an example of step (B).

[0019] <Step ST3: Deposition of first hard mask> Next, in step ST3, a metal oxide film containing one or more metal elements in a predetermined composition is formed on the dielectric film 103 as a first hard mask 105. The metal oxide film contains one or more metal elements selected from the group consisting of indium (In), gallium (Ga), and zinc (Zn). The formed metal oxide film does not include a crystalline film. For example, the formed metal oxide film may be a non-crystalline film, i.e., an amorphous film. The metal oxide film may be formed by physical vapor deposition (PVD) or atomic layer deposition (ALD), or may be formed at room temperature. The thickness of the metal oxide film is approximately 5 nm to 10 nm. In the example shown in FIG. 2A(C), the first hard mask 105 made of a metal oxide film is formed on the dielectric film 103 via a cap film 104. Step ST3 is an example of step (C). Step ST3 may be performed in the film formation apparatus that formed the dielectric film 103 in step ST2.

[0020] (Composition of the first hard mask) FIG. 3 is a diagram showing the composition ratios of metal elements in the first hard mask. The composition ratios of metal elements contained in the metal oxide film, which is the first hard mask 105, satisfy the conditions within a predetermined region Ar shown in FIG. 3. For example, the composition ratio of one or more metal elements among indium (In), gallium (Ga), and zinc (Zn) contained in the metal oxide film may be within the region Ar shown in FIG. 3. Specifically, the white circles (◯) in FIG. 3 represent examples of the composition ratios of metal elements contained in the metal oxide film when it becomes an amorphous film. For example, the white circles a1, a2, and a3 on the line with indium (In) and gallium (Ga) as vertices represent examples of the composition ratios of metal elements contained in the metal oxide film when it becomes an amorphous film. Among the composition ratios on the line with indium (In) and gallium (Ga) as vertices, the closer to the indium vertex, the higher the composition ratio of indium to gallium contained in the metal oxide film. The closer to the gallium peak, the higher the composition ratio of gallium to indium contained in the metal oxide film.

[0021] The metal oxide film indicated by the white circle a1 is an In2O3 film with a composition ratio of indium, gallium, and zinc of 1:0:0. The metal oxide film indicated by the white circle a3 is a Ga2O3 film with a composition ratio of indium, gallium, and zinc of 0:1:0. The metal oxide film indicated by the white circle a2 on the line is an InGaO3 film with a composition ratio of indium, gallium, and zinc of 1:1:0. The metal oxide film indicated by the white circle a4 at the center is an IGZO film with an indium, gallium, and zinc composition ratio of 1:1:1 and is equidistant from each vertex. The In2O3, Ga2O3, InGaO3, and IGZO metal oxide films with these composition ratios are amorphous films with unclear grain boundaries. Therefore, when the dielectric film 103 is etched using this metal oxide film as the first hard mask 105, the roughness of the copper wiring embedded in the dielectric film 103 becomes small.

[0022] On the other hand, the black circle (●) a5 in Figure 3 indicates an example of the composition ratio of metal elements contained in a metal oxide film when the metal oxide film becomes a crystalline film. The metal oxide film indicated by the black circle a5 is an oxygen-zinc "ZnO film" with a composition ratio of indium, gallium, and zinc of 0:0:1. The ZnO film is a crystalline film with clearly defined grain boundaries. Therefore, when this metal oxide film is used as the first hard mask 105 to etch the dielectric film 103, the sidewall roughness of the recesses formed in the dielectric film 103 increases. As a result, the resistance value of the copper wiring embedded in the recesses increases. Therefore, it is difficult to use a ZnO film as the first hard mask 105.

[0023] In this way, the metal oxide film is formed so that the composition ratio of one or more metal elements contained in the metal oxide film satisfies the condition within the region Ar shown in FIG. 3. As a result, the formed metal oxide film does not contain crystalline film. For example, the formed metal oxide film is a film that is difficult to crystallize. In this specification, a film that is difficult to crystallize is not limited to an amorphous film that does not contain crystals, i.e., an amorphous film that has not been crystallized, but also includes an amorphous film that contains microcrystals with very small grain boundaries in part of the film.

[0024] Fig. 4 is a graph showing an example of the crystallinity of the first hard mask 105. Fig. 4 shows the results of analyzing a sample of the first hard mask 105 formed in step ST3 using an X-ray diffractometer. The horizontal axis of Fig. 4 represents the angle (2θ) between the surface of the sample of the first hard mask 105 and the incident X-rays. The vertical axis represents the intensity of the X-rays generated from the sample.

[0025] When the first hard mask 105 is a ZnO film, there is a peak indicating a grain boundary at around 35 degrees, and the half-width of the peak is considered to be the size of the grain boundary, resulting in a film that is at least partially crystallized. Films shown in the graph of Figure 4 in which the first hard mask 105 is a film other than a ZnO film do not have a sharp peak and are considered to be non-crystallized amorphous films or amorphous films containing microcrystals. In other words, films shown in the graph of Figure 4 other than a ZnO film are considered to be films that are difficult to crystallize.

[0026] For example, an amorphous metal oxide film can be used as the first hard mask 105. Furthermore, if the metal oxide film contains at least one of indium, gallium, and zinc in a predetermined composition and is a film that is difficult to crystallize, such as an amorphous film, the metal oxide film can be used as the first hard mask 105. Furthermore, for example, a metal oxide film containing at least one of indium and gallium as metal elements and zinc, where the composition ratio of zinc to the total metal elements is 80% or less, is considered to be a film that is difficult to crystallize, such as an amorphous film. Therefore, a metal oxide film with such a composition ratio can be used as the first hard mask 105. Even in the case of a ZnO film containing only zinc as a metal element, if the crystallized portions are limited, the crystal grain boundaries are not clearly defined overall, and the film can be considered difficult to crystallize, it can be used as the first hard mask 105.

[0027] (First hard mask deposition conditions) In step ST3, an example of the film formation conditions for the first hard mask 105 by the PVD method will be shown below. Metal oxide film: IGZO Composition ratio of metal oxide film: In:Ga:Zn:O=1:1:1:4 Film formation temperature (stage temperature): 25℃~400℃ DC bias power (bias power supplied to the stage): 800W to 1400W Gas types: O2 gas, Ar gas Flow ratio of O2 gas to Ar gas: 1:9 Metal oxide film thickness: 5 nm Film formation time: 32 seconds Film formation rate: 1.54Å / s

[0028] <Process ST4: Cleaning the substrate> After the first hard mask 105 is formed, in step ST4, the second surface 201, which is the back surface of the substrate W, and the outer periphery of the first surface 200, which is the outer periphery of the front surface of the substrate W, are cleaned. For example, dilute hydrogen fluoride (DHF) or a hydrochloric acid-hydrogen peroxide mixture (HPM) may be used for cleaning. DHF is an aqueous solution of hydrogen fluoride (HF) diluted, for example, at a volume ratio of 1:100. HPM is a chemical solution made by mixing hydrochloric acid (HCl), hydrogen peroxide (H2O2), and deionized water (DIW). This removes metal adhering to the back surface and the outer periphery of the front surface, i.e., the bevel portion, of the substrate during the formation of the first hard mask 105 in step ST3, thereby preventing metal contamination during the subsequent formation of a second hard mask. Step ST4 is an example of step (D). Step ST4 may be performed using a cleaning apparatus described later.

[0029] <Step ST5: Deposition of second hard mask> After cleaning the substrate W, in step ST5, a silicon-containing film is deposited as a second hard mask. The silicon-containing film may be a SiO film or a SiN film. The second hard mask has a thickness of about 10 nm to 30 nm. In the example shown in FIG. 2B(E), a second hard mask 106 made of a SiO film or a SiN film is deposited on the first hard mask 105. Step ST5 is an example of step (E). Step ST5 may be performed in the film deposition apparatus that performed step ST2 or step ST3.

[0030] <Step ST6: Deposition of resist-related films> Next, in step ST6, a resist-related film for pattern formation is formed on the second hard mask 106. The resist-related film for pattern formation formed here is an example of a "resist-related first film having a first pattern formed thereon" for forming recesses corresponding to a predetermined pattern (hereinafter referred to as the "first pattern") in the first hard mask 105. In the example of (F-1) in FIG. 2B(F), a resist-related first film 110 is formed on the second hard mask 106. Hereinafter, the resist-related first film will be referred to as the "first film 110." The first film 110 has a structure in which an SOC (spin-on carbon) film 111, an SOG (spin-on glass) film 112, and a resist film 113 are stacked in this order on the second hard mask 106. In step ST6, a resist coating apparatus (not shown) coats the SOC film 111, the SOG film 112, and the resist film 113 on the substrate W, and then a heat treatment apparatus (not shown) may heat the substrate W. In step ST6, the film forming apparatus may form a carbon film instead of the SOC film 111 by a CVD (Chemical Vapor Deposition) method. The first film 110 is not limited to a three-layer structure. The first film 110 may have a two-layer structure of the SOC film 111 and a metal resist film 113. The first film 110 may have a two-layer structure of the resist film 113 and either the SOC film 111 or the SOG film 112. The first film 110 may be any one of the resist film 113, the SOC film 111, the SOG film 112, or a carbon film. Step ST6 is an example of step (F-1) included in step (F).

[0031] <Step ST7: Exposure and development of resist film> Next, in step ST7, the resist film 113 is exposed to extreme ultraviolet light having a wavelength of 13.5 nm emitted from an EUV (Extreme Ultraviolet) light source. In step ST7, an exposure process is performed on the resist film 113 using an exposure device (not shown). The light source of the exposure device is not limited to an EUV light source, and may be a KrF light source or the like. After the resist film 113 is exposed, a development process is performed on the resist film 113 using a development device (not shown). As a result, a first pattern is formed in the resist film 113. In the example of (F-2-1) in FIG. 2B(F), a first pattern OP having a pitch of 20 nm to 40 nm is formed in the resist film 113. After the development process, the substrate W may be subjected to a heat treatment. Step ST7 is an example of step (F-2) included in step (F).

[0032] <Step ST8: Etching of SOG and SOC> Next, in step ST8, the SOG film 112 and the SOC film 111 are etched to transfer the first pattern to the SOG film 112 and the SOC film 111. The dry etching of the SOG film 112 and the SOC film 111 may be performed using the same etching apparatus. Step ST8 may also be performed using an etching apparatus described below. In the etching apparatus, two high-frequency power supplies outputting high-frequency powers of different wavelengths are connected to the upper electrode and the lower electrode, and a 100-MHz source RF power is supplied to the upper electrode and a 13-MHz bias RF power is supplied to the lower electrode. The SOG film 112 may be etched using, for example, a plasma of CF4 gas and Ar gas. The SOC film 111 may be etched using, for example, a plasma of O2 gas, a plasma of O2 gas and COS gas, or a plasma of H2 gas and N2 gas. The etching in step ST8 involves etching the SOC film 111 until the second hard mask 106 is exposed. During etching, the first hard mask 105 is protected by the second hard mask 106. 2B(F), the first pattern OP of the resist film 113 is transferred to the SOG film 112 and the SOC film 111, and recesses 120 corresponding to the first pattern OP of the first film 110 are formed in the SOG film 112 and the SOC film 111. Step ST8 is an example of step (F-2) included in step (F). The recesses 120 have, for example, a line-and-space shape.

[0033] <Step ST9: Etching of second hard mask> Next, in step ST9, the second hard mask 106 is etched. The etching of the second hard mask 106 may be performed using the same etching apparatus that etched the SOG film 112 and the SOC film 111. The second hard mask 106 is etched using a mixed gas containing a plurality of gas species selected from CF4 gas, C4F8 gas, C4F6 gas, CHF3 gas, CH2F2 gas, O2 gas, and Ar gas. As a result, as shown in (F-3) of FIG. 2B(F), recesses 120 corresponding to the first pattern OP are formed in the second hard mask 106. Step ST9 is an example of step (F-3) included in step (F).

[0034] <Step ST10: Etching of First Hard Mask> After etching the second hard mask 106, the first hard mask 105 is etched in step ST10. As a result, as shown in FIG. 2B(G), recesses 120 corresponding to the first pattern OP are formed in the first hard mask 105. The first hard mask 105 is etched until the cap film 104 is exposed. The first hard mask 105 may be etched using the same etching equipment that etched the second hard mask 106. The first hard mask 105 is etched using, for example, plasma of CH4 gas and H2 gas. Because CH4 gas generates CH deposits, the composition ratio of H2 gas to CH4 gas is set to x:1 (x is 2 or more) so that the etching reaction exceeds the CH deposition reaction. The larger the value of x, the more H2 gas is added.

[0035] However, the gas species is not limited to this, and may be a gas containing CH3Cl or a gas containing C2H6, or may further contain H2 gas. That is, the first hard mask 105 may be etched with a gas capable of generating CH3 radicals. Steps ST9 and ST10 are examples of step (G).

[0036] In step ST10, incomplete reaction products of methyl metal may adhere to the sidewalls of the second hard mask 106, ultimately affecting the sidewall angle of the first hard mask 105. Therefore, a cycle etching process of CH4 gas and H2 gas plasma and O2 gas plasma may be performed to etch the first hard mask 105. FIG. 5 is a time chart showing an example of the first hard mask etching process. In step S1, the first hard mask 105 is etched to a certain extent by the CH4 gas and H2 gas plasma. Then, in step S2, the incomplete reaction products of methyl metal adhering to the second hard mask 106 and the like are ashed by the O2 gas plasma, thereby forming a perpendicular sidewall angle of the first hard mask 105. Steps S1 and S2 are repeated a predetermined number of times. However, in the first hard mask etching process, the first hard mask 105 may be etched by the CH4 gas and H2 gas plasma, and O2 gas may not be used.

[0037] 6 is a diagram showing an example of the result of cyclic etching of the first hard mask 105. As a result of performing the cyclic etching process shown in FIG. 5, the sidewalls of the first hard mask 105 have a vertical shape.

[0038] <Step ST11: Etching of Dielectric Film> Next, in step ST11, the dielectric film 103 is etched. If a cap film 104 is present on the dielectric film 103, the cap film 104 and the dielectric film 103 are etched. The dielectric film 103 is etched using a mixed gas containing a plurality of gas species selected from CF4 gas, C4F8 gas, C4F6 gas, CHF3 gas, CH2F2 gas, O2 gas, N2 gas, and Ar gas. As a result, as shown in FIG. 2C(H), recesses 120 corresponding to the first pattern OP are formed in the dielectric film 103. Step ST11 is an example of step (H).

[0039] <Process ST12: Surface Cleaning> Next, in step ST12, after etching the dielectric film 103, the surface of the substrate W is wet-cleaned to remove the first hard mask 105 remaining on the surface of the substrate W. A chemical solution of DHF or citric acid may be used for the cleaning. Step ST12 is an example of step (I).

[0040] As an example of cleaning conditions, the surface cleaning may include a step of acid-cleaning the substrate, a step of alkaline-cleaning the substrate, and a step of rinsing the substrate with a rinse solution after the acid and alkaline cleaning. For example, in the step of acid-cleaning the substrate, the substrate W is wet-cleaned for one minute with a chemical solution of DHF or HPM. Then, the substrate W is wet-cleaned for one minute with a chemical solution of APM (ammonia-hydrogen peroxide mixture cleaning). In the step of alkaline-cleaning the substrate, APM is a chemical solution made by mixing ammonium hydroxide (NH4OH), hydrogen peroxide (HO2), and deionized water (DIW). Then, the substrate W is rinsed with a rinse solution. As another example of cleaning conditions, the substrate W is wet-cleaned for one minute with a chemical solution of HPM, then wet-cleaned for one minute with a chemical solution of APM, and then rinsed with a rinse solution.

[0041] An example of the chemical solution used is DHF, which is a diluted aqueous solution of hydrogen fluoride (HF) with a concentration of, for example, 0.5%, and is controlled by a concentration meter. However, the concentration of DHF may be diluted to 1:1000 to 1:10000. If DHF of this concentration is used, the dielectric film 103 will not be etched. As a result, as shown in FIG. 2C(I), the first hard mask 105 is removed without damaging the dielectric film 103.

[0042] Examples of chemical solutions used include HPM, which is a mixture of hydrochloric acid (HCl), hydrogen peroxide (H2O2), and deionized water (DIW) in a volume ratio of 1:2:40.APM is a mixture of ammonium hydroxide, hydrogen peroxide, and deionized water in a volume ratio of 1:2:40.The rinse solution is, for example, deionized water (DIW).

[0043] After removing the first hard mask 105 by the above surface cleaning, the flatness (roughness) of the recesses 120 in the dielectric film 103 was 1.6 nm or less in LWR and 1.2 nm or less in LER. LER (Line-Edge Roughness) refers to the average value of the line edge roughness on the left and right sides of the sidewall of the recess (line and space). LWR (Line-Width Roughness) refers to the line width roughness of the sidewall of the recess caused by LER.

[0044] FIG. 7 is a graph showing an example of the results of a substrate surface cleaning process. FIG. 7 shows the DHF concentration dependence of the etching rates of the IGZO film and the dielectric film 103 when the first hard mask 105 is an IGZO film with a composition ratio of In, Ga, Zn, and O of 1:1:1:4. The horizontal axis of the graph in FIG. 7 represents the DHF concentration, and the vertical axis represents the etching rate of each film. Comparing the etching rates of the IGZO film and the dielectric film 103 reveals that within the DHF concentration range shown in FIG. 7, the dielectric film 103 was not etched, and the IGZO film first hard mask 105 was removed. This indicates that the first hard mask 105 was removed without damaging the dielectric film 103.

[0045] FIG. 8 is a graph showing another example of the results of the substrate surface cleaning process. FIG. 8 shows the citric acid concentration dependence of the etching rates of the IGZO film, dielectric film 103, and cap film 104 when the first hard mask 105 is an IGZO film with a composition ratio of In, Ga, Zn, and O of 1:1:1:4. The horizontal axis of the graph in FIG. 8 represents the citric acid concentration, and the vertical axis represents the etching rate of each film. Comparing the etching rates of the IGZO film, dielectric film 103, and cap film 104 reveals that within the citric acid concentration range shown in FIG. 8, the dielectric film 103 and cap film 104 were not etched, and the IGZO film first hard mask 105 was removed. This indicates that the first hard mask 105 was removed without damaging the dielectric film 103 and cap film 104.

[0046] <Step ST13: Copper filling> Next, in step ST13, copper, as an example of a metal, is filled into the recesses 120 formed in the dielectric film 103. The copper is filled into the spaces of the recesses 120 by plating, and is also formed on the top of the cap film 104. As a result, as shown in FIG. 2C(J), a copper wiring layer 130 is formed inside the recesses 120 and on the top of the cap film 104. The copper wiring layer is an example of a metal filled into the recesses. If necessary, a barrier layer may be formed between the copper wiring layer 130 and the dielectric film 103 by PVD or CVD, and a Cu seed may be formed by PVD, and then copper may be filled into the recesses 120 by plating. Step ST13 is an example of step (J).

[0047] <Process ST14: Flattening> Next, in step ST14, the upper copper wiring layer 130 and the cap film 104 are polished using CMP (Chemical Mechanical Polishing). This completes the formation of one copper wiring layer 130 in the damascene structure, as shown in FIG. 2C(K). Step ST14 is an example of step (K).

[0048] The substrate processing method according to the first embodiment of the present disclosure proposes to form a low-resistance copper wiring layer 130 by reducing the roughness of the wiring in the formation of a damascene structure. In contrast, the substrate processing method according to the second embodiment of the present disclosure proposes to form a low-resistance copper wiring layer 130 by reducing the roughness of the wiring in the formation of a dual damascene structure.

[0049] [Second embodiment] A substrate processing method according to a second embodiment of the present disclosure will be described with reference to FIGS. 9, 10A, and 10B. FIG. 9 is a flowchart showing an example of the substrate processing method according to the second embodiment. FIGS. 10A and 10B are schematic cross-sectional views of steps in a dual damascene structure. Note that, in the steps of the substrate processing method according to the second embodiment, the same processing steps as those in the substrate processing method according to the first embodiment shown in FIG. 1 are assigned the same numbers.

[0050] <Steps ST1 to ST10: Substrate Preparation to First Hard Mask Etching> 2A(A) to 2B(G), the steps from preparing the substrate in step ST1 to etching the first hard mask 105 in step ST10 are the same as steps ST1 to ST10 of the substrate processing method according to the first embodiment, and therefore, the description thereof will be omitted.

[0051] <Step ST21: Deposition of resist-related films> In the case of a dual damascene structure, after the recesses 120 are formed in the first hard mask 105, a resist-related film for forming a via pattern is deposited again.

[0052] In step ST21, a resist-related film for via pattern formation is formed on the second hard mask 106. The resist-related film for via pattern formation formed here is an example of a "resist-related second film on which a second pattern is formed" for forming vias according to a predetermined pattern (hereinafter referred to as the "second pattern") in the first hard mask 105 and the second hard mask 106. In the example of (L-1) in FIG. 10A(L), a resist-related second film 210 is formed on the second hard mask 106. Hereinafter, the resist-related second film will be referred to as the "second film 210." The second film 210 has a structure in which an SOC film 211, an SOG film 212, and a resist film 213 are stacked in this order on the second hard mask 106. The method for forming the second film 210 and the layer structure of the second film 210 in step ST21 may be the same as the method for forming the first film 110 and the layer structure of the first film 110 described in step ST6. Step ST21 is an example of step (L-1) included in step (L).

[0053] When the first hard mask 105 is formed of a TiN mask material, a halogen-based gas is used to form recesses in the TiN mask material. As a result, halogen elements remain on the sidewalls of the TiN mask material. The halogen elements damage the SOC film 211 during deposition, which may cause voids in the SOC film 211.

[0054] In contrast, in this substrate processing method, an IGZO mask material is used for the first hard mask 105. In this case, the state of voids in the SOC film 211 was tested. In the test, the presence or absence of voids was confirmed at 20 locations in the SOC film 211 for each of the following cases: no wet cleaning was performed immediately before step ST21; water cleaning was performed immediately before step ST21; and wet cleaning using APM was performed immediately before step ST21. As a result, no voids were generated in the SOC film 211 in any of the cases. In addition, a tape test was performed in which tape was applied to the surface of the SOC film 211 at three locations: the center, middle, and edge of the substrate W. It was confirmed that an SOC film 211 with excellent adhesion was formed in all cases: no cleaning, water cleaning, or APM cleaning.

[0055] <Step ST22: Exposure and development of resist-related films> Next, in step ST22, the recesses 120 and the vias 220 are aligned, and a mask is positioned to form a second pattern on the line-space recesses 120, after which an exposure process is performed on the resist film 113. The exposure method and development method in step ST22 may be the same as the exposure method and development method in step ST7. As a result, a second pattern OP2 is formed in the resist film 213 above the recesses 120, as shown in (L-2-1) of FIG. 10A(L). Step ST22 is an example of step (L-2) included in step (L).

[0056] <Step ST23: Etching SOG and SOC> Next, in step ST23, the SOG film 212 and the SOC film 211 are etched, and vias 220 corresponding to the second pattern OP2 are formed in the SOG film 212 and the SOC film 211. The etching method for the SOG film 212 and the SOC film 211 may be the same as the etching method in step ST8. As a result, as shown in (L-2-2) of FIG. 10A(L), the vias 220 are formed in the SOG film 212 and the SOC film 211. Step ST23 is an example of step (L-2) included in step (L).

[0057] <Step ST24: Etching of First and Second Hard Masks> In step ST24, the first hard mask 105 and the second hard mask 106 are etched. The etching method for the first hard mask 105 and the second hard mask 106 may be the same as the etching method in steps ST9 and ST10. As a result, vias 220 are formed in the first hard mask 105 and the second hard mask 106, as shown in FIG. 10A(M).

[0058] <Step ST25: Etching of Dielectric Film> Next, in step ST25, the dielectric film 103 is etched. The etching in step ST25 is performed using a mixed gas containing multiple gas species selected from the group consisting of CF4 gas, C4F8 gas, C4F6 gas, CHF3 gas, CH2F2 gas, O2 gas, N2 gas, and Ar gas. Furthermore, because the CD (critical dimension) of the via formed in the dielectric film 103 is small and the aspect ratio is high, the etching condition for step ST25 is to apply a high bias power to the stage. Since the via 220 completely penetrates the dielectric film 103 during the subsequent etching of the recess 120, the etching of the via 220 in step ST25 need only extend partway through the dielectric film 103. As a result, the via 220 corresponding to the second pattern OP2 is formed in the dielectric film 103, as shown in FIG. 10A(M). Step ST25 is an example of step (M).

[0059] <Step ST26: Ashing of SOC film> Next, in step ST26, the SOC film 211 is ashed. Ashing of the SOC film 211 is performed using plasma of H gas and N gas, or plasma of CO gas, without using plasma of O gas, in order to avoid damaging the underlying dielectric film 103. As a result, the SOC film 211 is ashed as shown in FIG. 10A(N). Step ST26 is an example of step (N).

[0060] <Step ST27: Etching of Dielectric Film> Ashing of the SOC film 211 exposes the recesses 120 to the surface. Therefore, next, in step ST27, the dielectric film 103 is etched according to the recesses 120 and the vias 220. The etching method may be the same as the etching method in step ST11. In step ST27, the vias 220 completely penetrate the dielectric film 103, exposing the silicon substrate 101. As a result, the vias 220 and the recesses 120 are formed as shown in FIG. 10B(H'). For example, the pitch between the vias 220 and the recesses 120 can be finely processed to about 30 nm. Step ST27 is an example in which, in step (H), after step (N), vias 220 and recesses 120 penetrating the dielectric film 103 are formed in the dielectric film 103.

[0061] <Process ST28: Surface Cleaning> Next, in step ST28, after etching the dielectric film 103, the surface of the substrate W is wet-cleaned to remove the first hard mask 105 remaining on the surface of the substrate W, as shown in FIG. 10B(I'). The cleaning method may be the same as the cleaning method in step ST12. Step ST28 is an example of step (I).

[0062] <Process ST29: Copper filling> Next, in step ST29, copper, as an example of a metal, is filled into the recesses 120 and vias 220 formed in the dielectric film 103. As a result, as shown in FIG. 10B(J'), a copper wiring layer 130 is formed inside the recesses 120, inside the vias 220, and on top of the cap film 104. If necessary, a barrier layer may be formed between the copper wiring layer 130 and the dielectric film 103 by a CVD method. Step ST29 is an example of filling a metal into the recesses 120 and vias 220 formed in the dielectric film 103 in step (J).

[0063] <Process ST30: Flattening> Next, in step ST30, the upper copper wiring layer 130 and the cap film 104 are removed using CMP. This completes the formation of one copper wiring layer 130 in the dual damascene structure, as shown in FIG. 10B(K'). Step ST30 is an example of step (K).

[0064] [effect] According to the substrate processing method according to the first embodiment and the second embodiment of the present disclosure, the dielectric film 103 is etched using an IGZO-based metal oxide film having a predetermined composition ratio within the region Ar shown in FIG. 3 as the mask material for the first hard mask 105. This results in a recess 120 being formed in the dielectric film 103. The metal oxide film having a predetermined composition ratio within the region Ar shown in FIG. 3 becomes an amorphous film, and the grain boundaries are not clearly defined. Therefore, when the dielectric film 103 is etched using the metal oxide film as the first hard mask 105, the LER and LWR values ​​of the recess 120 transferred to the dielectric film 103 are reduced. This allows for a reduction in the resistance of the copper wiring layer 130 embedded in the recess 120.

[0065] For example, in the substrate processing methods according to the first and second embodiments, the material of the first hard mask 105 is changed from TiN to an amorphous metal oxide film. This metal oxide film is an oxide containing one or more elements selected from the group consisting of indium, gallium, and zinc. Metal oxide films of indium, gallium, and zinc have low vapor pressures, resulting in less wear of the first hard mask 105 during etching of the dielectric film 103 and high etching resistance. Taking advantage of this advantage, whereas a TiN mask with a thickness of approximately 20 nm was conventionally formed, the present substrate processing method deposits an amorphous metal oxide film with a thickness of approximately 5 nm as the first hard mask 105. This allows the aspect ratio of the first hard mask 105 to be reduced. This reduces the surface tension of the first hard mask 105, making it less likely for wiring wiggling to occur and reducing the roughness of the recesses 120 formed in the dielectric film 103.

[0066] In fact, in a wiring pattern with a pitch of 40 nm, the dielectric film 103 was etched using a first hard mask 105 made of a metal oxide film with a thickness of 5 nm. As a result, the selectivity of the first hard mask 105 to the dielectric film 103 was approximately 32 times. Compared to a conventional TiN mask with a thickness of approximately 20 nm, the aspect ratio was approximately 1 / 4, and the occurrence of wiggling in the wiring could be reduced.

[0067] Furthermore, the TiN mask is a crystalline film. In contrast, in the substrate processing methods according to the first and second embodiments, the first hard mask 105 can be formed as an amorphous film by adjusting the composition ratio of each metal element in the IGZO-based metal oxide film. The composition ratio region in which the first hard mask 105 becomes an amorphous film is region Ar in FIG. 3 . If a highly crystalline metal oxide is used for the first hard mask 105, the roughness of the recesses 120 and vias 220 formed in the dielectric film 103 deteriorates. Therefore, the composition ratio of the metal elements contained in the metal oxide film is adjusted to make the first hard mask 105 a metal oxide film with a composition that is difficult to crystallize. This improves the roughness of the recesses 120 and vias 220 formed in the dielectric film 103.

[0068] Furthermore, IGZO-based metal oxide films are highly transparent, with a 5-nm-thick IGZO film having a transmittance of 95% or more. In contrast, the transmittance of a 20-nm-thick TiN mask is approximately 60%. Therefore, in the substrate processing methods according to the first and second embodiments, alignment between the vias 220 and the recesses 120 is facilitated in multilayer wiring using the first hard mask 105 made of an IGZO-based metal oxide film.

[0069] Furthermore, in etching the first hard mask 105, a halogen gas such as Cl2 gas was used to etch a conventional TiN mask. In contrast, CH4 gas and H2 gas are used for the first hard mask 105. When the TiN mask is etched using Cl2 gas, it becomes difficult to vertically process the recesses 120 and vias 220, and the TiN mask may become tapered. On the other hand, when a metal oxide film is etched using CH4 gas and H2 gas, the recesses 120 and vias 220 become vertical, as shown in FIG. 6. Because the shape of the first hard mask 105 affects roughness, a vertical first hard mask 105 reduces the roughness of the recesses 120 and the like formed in the dielectric film 103.

[0070] Furthermore, when etching is performed using a halogen gas, halogen atoms tend to remain on the pattern surface, such as the recesses 120. Therefore, when the second SOC film 211 of the dual damascene structure is applied, voids tend to occur in the SOC film 211. In contrast, when an IGZO-based metal oxide film is used for the first hard mask 105, the SOC film 211 can be formed with good adhesion and without voids, even without cleaning before forming the second SOC film 211.

[0071] Furthermore, in the case of a TiN mask, after etching the dielectric film 103, the barrier film and copper filling are performed without cleaning. Therefore, the roughness of the TiN mask is likely to be transferred directly to the copper wiring. In contrast, in the substrate processing method of the present disclosure, an IGZO-based metal oxide film is used as the first hard mask 105. In this case, after etching the dielectric film 103, the first hard mask 105 is completely removed using DHF or citric acid, so the roughness of the metal oxide film that is the first hard mask 105 is hardly transferred to the copper wiring. In this way, by providing a metal oxide film material and a substrate processing method tailored to it, it is possible to reduce the roughness of wiring resulting from conventional wiring construction methods.

[0072] The measurement results of the roughness of wiring obtained by the substrate processing method of the present disclosure will be described with reference to Fig. 11. Fig. 11 is a diagram showing an example of roughness in each step of the substrate processing method. Fig. 11 shows the influence of each step of the substrate processing method on the roughness of wiring, based on the values ​​of LER, which indicates the roughness of the line edge, and LWR, which indicates the roughness of the line width.

[0073] In "(1) NIL" in FIG. 11, the LER of the first pattern OP formed in the resist film 113 after exposure and development was approximately 2.2 nm, and the LWR was approximately 3.0 nm. In "(2) SOG HMO," the LER of the recess 120 formed in the SOG film 112 was approximately 1.5 nm, and the LWR was approximately 2.2 nm. In "(3) SOC HMO," the LER of the recess 120 formed in the SOC film 111 was approximately 1.3 nm, and the LWR was approximately 2.1 nm.

[0074] In "(4) Ox HMO," the LER of the recesses 120 formed in the second hard mask 106 of the SiO film was approximately 1.8 nm, and the LWR was approximately 2.4 nm. In "(5) IGZO HMO," the LER of the recesses 120 formed in the first hard mask 105 of the IGZO film was approximately 1.9 nm, and the LWR was approximately 2.7 nm. In "(6) Sac-SiN," the LER of the recesses 120 formed in the cap film 104 of the SiN film was approximately 1.5 nm, and the LWR was approximately 2.2 nm.

[0075] In "(7) Liner1 to Liner1+2+3+4+Ash," after etching the dielectric film 103, the LER of the recesses 120 formed in the dielectric film 103 before cleaning was approximately 1.5 nm, and the LWR was approximately 2.2 nm. In "(8) DHF 1:1000," after etching the dielectric film 103, the substrate surface was cleaned with a DHF chemical solution, which is an aqueous solution of hydrogen fluoride (HF) diluted at a volume ratio of 1:1000. As a result, the LER of the recesses 120 formed in the dielectric film 103 was improved to approximately 1.1 nm, and the LWR was improved to approximately 1.5 nm. In other words, the surface cleaning after etching the dielectric film 103 reduced the roughness of the recesses 120 in the dielectric film 103 to approximately half of the roughness of the first pattern OP of the resist film 113 after exposure and development.

[0076] One reason for the improvement in roughness using the substrate processing method of the present disclosure is that the selectivity of the first hard mask 105 is high, allowing the aspect ratio of the first hard mask 105 to be lower than that of a conventional TiN mask. As a result, the first hard mask 105 has less roughness due to wiggling. This is thought to have reduced the roughness of the recesses 120 in the dielectric film 103. A second reason is that the first hard mask 105 is a metal oxide film that does not contain a crystalline film such as an amorphous film, so the transfer effect of roughness due to grain boundaries to the dielectric film 103 is low. This is thought to have reduced the roughness of the recesses 120 in the dielectric film 103. A third reason is that residues of the first hard mask 105 are easily cleaned and removed by cleaning after etching the dielectric film 103, which is thought to have significantly improved the roughness of the recesses 120 in the dielectric film 103.

[0077] [Example of film deposition equipment configuration] An example of the configuration of a film formation apparatus will be described with reference to FIG. 12. FIG. 12 is a diagram schematically illustrating the configuration of a film formation apparatus according to one embodiment. The film formation apparatus 300 forms a metal oxide film as a first hard mask 105 on the dielectric film 103, for example, in step (C). However, the film formation apparatus 300 can also be used in other film formation steps. For example, the film formation apparatus 300 may be used in step (B) of forming a dielectric film, step (E) of forming a silicon-containing film as a second hard mask 106, and other film formation steps.

[0078] The film forming apparatus 300 is configured as a sputtering apparatus that forms a metal oxide film by sputtering on the surface of the substrate W. The film forming apparatus 300 is an example of the configuration of a substrate processing apparatus.

[0079] The film forming apparatus 300 includes a processing vessel 320, a stage 330, and a target 334. The stage 330 is provided inside the processing vessel 320, which is controlled to have a vacuum atmosphere, and a substrate W, which is a target for film formation, is placed on the stage 330. The surface of the target 334 is exposed inside the processing vessel 320, and emits metals such as indium, gallium, and zinc toward the substrate W on the stage 330. The processing vessel 320 includes a main body 321, which is a substantially cylindrical container with an open top, and a lid 322 that covers the opening of the main body 321. An opening is formed in the sidewall of the main body 321 for loading and unloading the substrate W, and the opening is opened and closed by a gate valve GV.

[0080] The stage 330 includes a substrate 331 and an electrostatic chuck 332 for electrostatically attracting the substrate W to the stage 330. The electrostatic chuck 332 is disposed on the upper surface of the substrate 331. The substrate 331 is generally disk-shaped and has a diameter larger than that of the substrate W. The substrate 331 includes a temperature control module (not shown) configured to adjust at least one of the stage 330 and the substrate W to a film formation temperature indicated in the film formation conditions. The electrostatic chuck 332 includes an electrode (not shown) disposed within a generally disk-shaped ceramic body having a diameter smaller than that of the substrate W. By applying a voltage from a DC power supply (not shown) to the electrode within the electrostatic chuck 332, the substrate W can be attracted and held on the upper surface of the electrostatic chuck 332. The substrate 331 and the electrostatic chuck 332 are formed with through-holes 335 for passing lift pins 350. A bias power for attracting ions indicated in the film formation conditions is supplied to the stage 330 from a high-frequency power supply (not shown).

[0081] An annular shield ring 338 is disposed on the upper surface of the stage 330 to prevent metal emitted from the target 334 from adhering to the surface of the substrate 331. The shield ring 338 is disposed on the substrate 331 so as to surround the periphery of the electrostatic chuck 332 to prevent the substrate 331 from being exposed toward the opening 362 of the cover member 326.

[0082] A rotation shaft 333 for rotating the stage 330 around the central axis of the stage 330 is connected to the center of the underside of the base material 331 of the stage 330. The rotation shaft 333 is provided to extend vertically downward from the connection portion with the base material 331. The rotation shaft 333 penetrates the bottom wall of the main body 321 of the processing vessel 320 and is connected to the driving unit 324. A seal member for keeping the internal space of the processing vessel 320 airtight is provided at the position where the rotation shaft 333 penetrates the main body 321.

[0083] The driving unit 324 can rotate the rotation shaft 333 around the central axis of the stage 330, thereby rotating the substrate W attracted and held on the electrostatic chuck 332 of the stage 330. The driving unit 324 can also move the rotation shaft 333 up and down to move the stage 330 between a transfer position where the substrate W is transferred between an end effector of the transport device and the stage 330, and a film formation position where a film formation process is performed on the substrate W.

[0084] A cover member 326 is also disposed within the processing vessel 320 to form a non-film formation region (a region where a metal oxide film is not formed) on the edge of the substrate W. The cover member 326 corresponds to the region where a metal oxide film is formed, and is composed of a substantially annular member having a substantially circular opening 362 with a diameter smaller than that of the substrate W. The cover member 326 is provided above the edge of the stage 330. An outer edge 361 of the cover member 326 protrudes downward.

[0085] A mask support 328 is provided inside the processing vessel 320. The mask support 328 removes the cover member 326 from the stage 330 when the stage 330 descends to the transfer position, and supports the removed cover member 326. The mask support 328 is composed of a substantially cylindrical member that is arranged to surround the outer circumferential surface of the cover member 326. A flange 382 that expands outwardly is provided on the upper part of the mask support 328. The flange 382 is fixed to the inner wall of the main body 321.

[0086] The mask support 328 has a generally cylindrical internal space extending vertically so as not to interfere with the movement path of the cover member 326 that accompanies the vertical movement of the stage 330. Furthermore, at the lower end of the mask support 328, a support portion 381 that protrudes toward the inside of the generally cylindrical shape and has a hook-shaped cross section is formed along the circumferential direction of the mask support 328. The support portion 381 is provided above the transfer position. Therefore, when the stage 330 descends to the transfer position, the outer edge portion 361 of the cover member 326 engages with the support portion 381 of the mask support 328, thereby removing the cover member 326 from the stage 330.

[0087] A support portion 351 that supports a plurality of lift pins 350 is provided below the stage 330. A drive portion 352 moves the support portion 351 up and down.

[0088] An exhaust port 355 is formed in the bottom wall of the main body 321. An exhaust device 357 is connected to the exhaust port 355 via an exhaust pipe 356. The exhaust device 357 includes a pressure adjustment valve and a vacuum pump. The pressure adjustment valve adjusts the pressure inside the processing vessel 320. The vacuum pump includes a turbomolecular pump, a dry pump, or a combination thereof.

[0089] A gas supply pipe 329 having a gas supply port for supplying a gas (such as argon gas) serving as a raw material for ions used in sputtering into the internal space of the processing vessel 320 is provided at approximately the center of the lid body 322.

[0090] The cover body 322 is provided with a holder 340 that holds the target 334 and a holder support part 342 for fixing the holder 340 to the cover body 322. The holder support part 342 is made of an insulating material and fixes the holder 340 to the cover body 322 while electrically insulating the metal holder 340 from the metal cover body 322, for example.

[0091] The holder 340 is connected to a power supply 336. The power supply 336 supplies DC or AC power to the holder 340, thereby generating an electric field near the target 334 held by the holder 340. The electric field generated near the target 334 dissociates gases such as O2 gas and Ar gas supplied from the gas supply pipe 329, generating ions, in accordance with the film formation conditions for the first hard mask 105. The generated ions collide with the target 334, thereby releasing metal particles of at least one of indium (In), gallium (Ga), and zinc (Zn), which are raw materials for the metal oxide film, from the target 334. The metal particles released from the target 334 are deposited on the substrate W through the openings 362 in the cover member 326, thereby forming the first hard mask 105, which is a metal oxide film containing one or more metal elements in a predetermined composition, on the surface of the substrate W.

[0092] The control unit 900 processes computer-executable instructions that cause the film forming apparatus 300 to perform the various processes described in this disclosure. The control unit 900 may be configured to control each element of the film forming apparatus 300 to perform the various processes described herein. In one embodiment, part or all of the control unit 900 may be included in the film forming apparatus 300. The control unit 900 may include a processing unit, a storage unit, and a communication interface. The control unit 900 is implemented, for example, by a computer. The processing unit may be configured to read a program from the storage unit and execute the read program to perform various control operations. This program may be stored in the storage unit in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit and read from the storage unit by the processing unit for execution. The medium may be various computer-readable storage media or a communication line connected to the communication interface. The processing unit may be a CPU (Central Processing Unit). The storage unit may include a RAM (Random Access Memory), a ROM (Read Only Memory), a HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof. The communication interface may communicate with the substrate processing apparatus via a communication line such as a LAN (Local Area Network).

[0093] [Example of film deposition equipment configuration] The configuration of another film formation apparatus will be described with reference to Fig. 13. Fig. 13 is a diagram schematically illustrating the configuration of a film formation apparatus according to one embodiment. Like the film formation apparatus 300, the film formation apparatus 400 is used, for example, in step (C) to form a metal oxide film on the dielectric film 103. However, the film formation apparatus 400 can also be used in other film formation steps.

[0094] The film forming apparatus 400 is configured as, for example, an ALD (Atomic Layer Deposition) apparatus that forms a metal oxide film on the surface of the substrate W by an ALD method. The film forming apparatus 400 is an example of the configuration of a substrate processing apparatus.

[0095] The film forming apparatus 400 includes a processing vessel 411, an exhaust device 412, a shower head 416, and a stage 417. The exhaust device 412 includes a vacuum pump that exhausts gas from the processing vessel 411, and a pressure control valve that adjusts the pressure inside the processing vessel 411. The inside of the processing vessel 411 is controlled by the exhaust device 412 to a vacuum atmosphere of a predetermined pressure.

[0096] A plurality of types of gases are supplied to the processing chamber 411 via the shower head 416. In this embodiment, the plurality of types of gases may be, for example, four types of gases including indium (In), gallium (Ga), zinc (Zn), and oxygen (O2). An indium supply source 413a is connected to the shower head 416 via a pipe 414a. A gallium supply source 413b is connected to the shower head 416 via a pipe 414b. A zinc supply source 413c is connected to the shower head 416 via a pipe 414c. An oxygen supply source 413d is connected to the shower head 416 via a pipe 414d.

[0097] The indium source gas supplied from the indium supply source 413a has its flow rate controlled by a flow rate controller 415a provided in a pipe 414a. The indium source gas, whose flow rate has been controlled, is introduced into the shower head 416 from a gas supply port 418a via a pipe 414a. The gallium source gas supplied from the gallium supply source 413b has its flow rate controlled by a flow rate controller 415b provided in a pipe 414b. The gallium source gas, whose flow rate has been controlled, is introduced into the shower head 416 from a gas supply port 418b via a pipe 414b. The zinc source gas supplied from the zinc supply source 413c has its flow rate controlled by a flow rate controller 415c provided in a pipe 414c. The zinc source gas, whose flow rate has been controlled, is introduced into the shower head 416 from a gas supply port 418c via a pipe 414c. The flow rate of oxygen gas supplied from oxygen source 413d is controlled by flow rate controller 415d provided in pipe 414d. The flow rate-controlled oxygen gas is introduced into shower head 416 from gas supply port 418d via pipe 414d. The metal oxide film to be formed contains one or more metal elements selected from the group consisting of indium, gallium, and zinc. Therefore, the opening and closing of on-off valves (not shown) provided in pipes 414a to 414c is controlled so that gas containing the required metal elements is supplied.

[0098] The shower head 416 is provided, for example, in the upper part of the processing vessel 411, and has a number of outlet holes formed on the bottom surface thereof. The shower head 416 discharges multiple types of gases introduced via the pipes 414a to 414d into the processing vessel 411 in a shower-like manner from the separate outlet holes.

[0099] A stage 417 is provided within the processing vessel 411. The stage 417 has a temperature adjustment mechanism (not shown). A substrate W, which is a target for film formation, is placed on the stage 417. The stage 417 controls the temperature of the substrate W using the temperature adjustment mechanism so that the temperature is suitable for film formation according to the film formation conditions. As a result, a first hard mask 105 made of a metal oxide film is formed on the surface of the substrate W.

[0100] The controller 900 processes computer-executable instructions that cause the deposition apparatus 400 to perform the various steps described in this disclosure. The controller 900 can be configured to control each element of the deposition apparatus 400 to perform the various steps described herein.

[0101] [Example of etching equipment configuration] Next, the configuration of an etching apparatus will be described with reference to Fig. 14. Fig. 14 is a diagram schematically illustrating the configuration of an etching apparatus according to one embodiment. The etching apparatus 500 is used, for example, when forming recesses 120 corresponding to the first pattern OP in the first hard mask 105 by etching in step (G). However, the etching apparatus 500 may also be used in step (H) of etching the dielectric film and other etching steps.

[0102] The etching apparatus 500 is configured as a capacitively coupled plasma processing apparatus, and is an example of the configuration of a substrate processing apparatus.

[0103] The etching apparatus 500 includes a plasma processing chamber (processing vessel) 510, a gas supply 520, a power supply 530, and an exhaust system 540. The etching apparatus 500 also includes a substrate support 511 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 510. The gas inlet includes a showerhead 513. The substrate support 511 is disposed within the plasma processing chamber 510. The showerhead 513 is disposed above the substrate support 511. In one embodiment, the showerhead 513 forms at least a portion of the ceiling of the plasma processing chamber 510. The plasma processing chamber 510 has a plasma processing space 510s defined by the showerhead 513, a sidewall 510a of the plasma processing chamber 510, and the substrate support 511. The plasma processing chamber 510 is grounded. The showerhead 513 and the substrate support 511 are electrically isolated from the enclosure of the plasma processing chamber 510 .

[0104] The substrate support 511 includes a main body 555 and a ring assembly 512. The main body 555 has a central region 555a for supporting the substrate W and an annular region 555b for supporting the ring assembly 512. A wafer is an example of the substrate W. The annular region 555b of the main body 555 surrounds the central region 555a of the main body 555 in a plan view. The substrate W is disposed on the central region 555a of the main body 555, and the ring assembly 512 is disposed on the annular region 555b of the main body 555 so as to surround the substrate W on the central region 555a of the main body 555. Therefore, the central region 555a is also called a substrate support surface for supporting the substrate W, and the annular region 555b is also called a ring support surface for supporting the ring assembly 512.

[0105] In one embodiment, the main body 555 includes a base 557 and an electrostatic chuck 556. The base 557 includes a conductive member. The conductive member of the base 557 can function as a lower electrode. The electrostatic chuck 556 is disposed on the base 557. The electrostatic chuck 556 includes a ceramic member 556a and an electrostatic electrode 556b disposed within the ceramic member 556a. The ceramic member 556a has a central region 555a. In one embodiment, the ceramic member 556a also has an annular region 555b. Note that another member surrounding the electrostatic chuck 556, such as an annular electrostatic chuck or an annular insulating member, may also have the annular region 555b. In this case, the ring assembly 512 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 556 and the annular insulating member. At least one RF / DC electrode coupled to an RF power source 531 and / or a DC power source 532, described below, may be disposed within the ceramic member 556a. In this case, at least one RF / DC electrode functions as a lower electrode. When a bias RF signal and / or a DC signal, which will be described later, is supplied to at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 557 and at least one RF / DC electrode may function as multiple lower electrodes. Alternatively, the electrostatic electrode 556b may function as a lower electrode. Therefore, the substrate support 511 includes at least one lower electrode.

[0106] The ring assembly 512 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0107] The substrate support 511 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 556, the ring assembly 512, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 557a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 557a. In one embodiment, the flow passage 557a is formed in the base 557, and one or more heaters are disposed in the ceramic member 556a of the electrostatic chuck 556. The substrate support 511 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 555a.

[0108] The showerhead 513 is configured to introduce at least one processing gas from the gas supply unit 520 into the plasma processing space 510s. The showerhead 513 has at least one gas supply port 513a, at least one gas diffusion chamber 513b, and multiple gas inlets 513c. The processing gas supplied to the gas supply port 513a passes through the gas diffusion chamber 513b and is introduced into the plasma processing space 510s from the multiple gas inlets 513c. The showerhead 513 also includes at least one upper electrode. In addition to the showerhead 513, the gas inlet may include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 510a.

[0109] The gas supply unit 520 may include at least one gas source 521 and at least one flow controller 522. In one embodiment, the gas supply unit 520 is configured to supply at least one process gas from a corresponding gas source 521 through a corresponding flow controller 522 to the showerhead 513. Each flow controller 522 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 520 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0110] The power supply 530 includes an RF power supply 531 coupled to the plasma processing chamber 510 via at least one impedance matching circuit. The RF power supply 531 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 510s. Therefore, the RF power supply 531 can function as at least a part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, and ion components in the formed plasma can be attracted to the substrate W.

[0111] In one embodiment, the RF power supply 531 includes a first RF generating unit 531a and a second RF generating unit 531b. The first RF generating unit 531a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 531a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0112] The second RF generating unit 531b is coupled to at least one lower electrode via at least one impedance matching circuit and configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generating unit 531b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0113] The power supply 530 may also include a DC power supply 532 coupled to the plasma processing chamber 510. The DC power supply 532 includes a first DC generator 532a and a second DC generator 532b. In one embodiment, the first DC generator 532a is connected to at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 532b is connected to at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0114] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof. In one embodiment, a waveform generator (not shown) for generating a sequence of voltage pulses from the DC signal is connected between the first DC generator 532a and at least one lower electrode. Thus, the first DC generator 532a and the waveform generator constitute a voltage pulse generator. When the second DC generator 532b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 532a and 532b may be provided in addition to the RF power supply 531, or the first DC generating unit 532a may be provided instead of the second RF generating unit 531b.

[0115] During plasma processing, the etching apparatus 500 supplies a source RF signal from a first RF generator 531a to an upper electrode of the shower head 513, a lower electrode of a base 557 constituting the substrate support unit 511, or a lower electrode provided on the electrostatic chuck 556. Furthermore, during plasma processing, the etching apparatus 500 applies a pulsed first DC signal from a first DC generator 532a to the lower electrode of the base 557. During plasma processing, the etching apparatus 500 may apply a second DC signal from a second DC generator 532b to the upper electrode of the shower head 513. The first DC generator 532a is capable of changing the duty ratio of one cycle of the pulsed first DC signal. For example, the first DC generator 532a is capable of changing the proportion of the period during which the first DC signal is on during one cycle, under control of the control unit 900.

[0116] The exhaust system 540 may be connected to, for example, a gas outlet 510e provided at the bottom of the plasma processing chamber 510. The exhaust system 540 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 510s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0117] The controller 900 processes computer-executable instructions that cause the etching apparatus 500 to perform the various processes described in this disclosure. The controller 900 can be configured to control each element of the substrate processing apparatus to perform the various processes described herein.

[0118] The operation of the etching apparatus 500 configured as described above is controlled by a control unit 900. The control unit 900 controls plasma etching. For example, the control unit 900 controls the exhaust system 540 to evacuate the plasma processing chamber 510 to a predetermined vacuum level. The control unit 900 controls the gas supply unit 520 to introduce a processing gas for etching from the gas supply unit 520 into the plasma processing space 510s. The control unit 900 controls the power supply 530 to supply power from the power supply 530 in conjunction with the introduction of the processing gas, thereby generating plasma in the plasma processing chamber 510 and performing etching on the substrate W.

[0119] [Example of cleaning equipment configuration] Next, an example of the configuration of a cleaning apparatus will be described with reference to FIG. 15. FIG. 15 is a diagram schematically illustrating the configuration of a cleaning apparatus according to one embodiment. The cleaning apparatus 600 removes the first hard mask 105 by cleaning the substrate W, for example, in step (I). However, the cleaning apparatus 600 can also be used for other cleaning steps. The cleaning apparatus 600 is an example of the configuration of a substrate processing apparatus.

[0120] 15, the cleaning apparatus 600 includes a processing vessel 620, a substrate holding mechanism 630, a liquid supply unit 640, and a collection cup 650. The processing vessel 620 accommodates the substrate holding mechanism 630, the liquid supply unit 640, and the collection cup 650. A fan filter unit (FFU) 621 is provided on the ceiling of the processing vessel 620. The FFU 621 forms a downflow within the processing vessel 620.

[0121] The FFU 621 is connected to a downflow gas supply source 623 via a valve 622. The FFU 621 discharges a downflow gas (for example, dry air) supplied from the downflow gas supply source 623 into the processing chamber 620.

[0122] The substrate holding mechanism 630 includes a rotary holder 631, a support column 632, and a drive unit 633. The rotary holder 631 is provided approximately in the center of the processing vessel 620. A holding member 611 that holds the substrate W from the side is provided on the upper surface of the rotary holder 631. The substrate W is held horizontally by the holding member 611 at a slight distance from the upper surface of the rotary holder 631.

[0123] Support part 632 is a member extending in the vertical direction, and has a base end rotatably supported by drive part 633, and a tip end horizontally supports rotation holder 631. Drive part 633 rotates support part 632 around a vertical axis.

[0124] The substrate holding mechanism 630 rotates the support portion 632 using the drive portion 633, thereby rotating the rotary holder 631 supported by the support portion 632, thereby rotating the substrate W held by the rotary holder 631.

[0125] The rotation holder 631 is not limited to the type that holds the substrate W from the side as described above, but may be a type that holds the substrate W by suction from below, such as a vacuum chuck.

[0126] The liquid supply unit 640 supplies various processing liquids to the substrate W held by the substrate holding mechanism 630. The liquid supply unit 640 has multiple (here, two) nozzles 641a, 641b, an arm 642 that horizontally supports the nozzles 641a, 641b, and a pivoting and lifting mechanism 643 that pivots and raises and lowers the arm 642. Note that the nozzle 641a and the nozzle 641b may be supported by separate arms. The nozzle 641a is an example of a liquid supply port that supplies a cleaning liquid. The nozzle 641b is an example of a liquid supply port that supplies a rinsing liquid.

[0127] Nozzle 641a is connected to a cleaning chemical liquid supply source 645a via a valve 644a and a flow rate regulator 646a, while nozzle 641b is connected to a rinse liquid supply source 645b via a valve 644b and a flow rate regulator 646b.

[0128] A cleaning chemical such as DHF, HPM, or APM is supplied from a cleaning chemical supply source 645a and ejected from the nozzle 641a. A rinse liquid is supplied from a rinse liquid supply source 645b and ejected from the nozzle 641b. The rinse liquid is, for example, deionized water (DIW). DHF, HPM, and APM are examples of cleaning liquids.

[0129] The collection cup 650 is disposed to surround the rotary holder 631, and collects the processing liquid scattered from the substrate W by the rotation of the rotary holder 631. A drain port 651 is formed in the bottom of the collection cup 650, and the processing liquid collected by the collection cup 650 is discharged from the drain port 651 to the outside of the cleaning apparatus 600. In addition, an exhaust port 652 is formed in the bottom of the collection cup 650, through which the downflow gas supplied from the FFU 621 is discharged to the outside of the cleaning apparatus 600.

[0130] The number of nozzles provided in the cleaning device 600 is not limited to the above example, and for example, the cleaning device 600 may be configured to include a single nozzle that ejects the cleaning chemical liquid and the rinse liquid.

[0131] The controller 900 processes computer-executable instructions that cause the cleaning apparatus 600 to perform the various steps described in this disclosure. The controller 900 may be configured to control each element of the cleaning apparatus 600 to perform the various steps described herein.

[0132] In the above-described embodiment, an example has been described in which a cleaning chemical is used in a cleaning apparatus 600 that performs a single-wafer wet etching process (hereinafter simply referred to as "etching process"). However, the cleaning chemical may also be used in a batch etching process in which a plurality of substrates W are processed at once. An example of a cleaning apparatus 600A that performs a batch etching process will be described below with reference to FIG. 16. FIG. 16 is a diagram showing the configuration of a cleaning apparatus according to a modified example. The cleaning apparatus 600A is an example of the configuration of a substrate processing apparatus.

[0133] 16, a cleaning chemical liquid supply system 650A according to the modification includes a cleaning chemical liquid supply source 661, a valve 662, and a flow rate regulator 663. A cleaning apparatus 600A according to the modification includes a processing tank 690, a substrate holding mechanism 630A, and a liquid supply unit 640A.

[0134] The processing tank 690 stores a cleaning chemical liquid. The substrate holding mechanism 630A holds multiple substrates W in a vertical position. The substrate holding mechanism 630A can be raised and lowered by a lifting mechanism (not shown). The liquid supply unit 640A is connected to a cleaning chemical liquid supply source 661 via a valve 662 and a flow rate regulator 663, and supplies the cleaning chemical liquid to the processing tank 690. As a result, the cleaning chemical liquid is stored in the processing tank 690.

[0135] The controller 900 processes computer-executable instructions that cause the cleaning apparatus 600A to perform the various steps described in this disclosure. The controller 900 can be configured to control each element of the cleaning apparatus 600A to perform the various steps described herein.

[0136] In the process according to the modified example, the substrate holding mechanism 630A is lowered, so that the plurality of substrates W held by the substrate holding mechanism 630A are immersed in the cleaning chemical stored in the processing tank 690. This removes the first hard mask 105 formed on the surfaces of the substrates W. In this manner, the cleaning chemical can also be applied to a batch etching process in which a plurality of substrates W are processed at the same time.

[0137] [Example of substrate processing system configuration] The configuration of a substrate processing system according to one embodiment will be described with reference to Fig. 17. Fig. 17 is a diagram schematically illustrating the configuration of a substrate processing system according to one embodiment. In the following, to clarify the positional relationships, mutually orthogonal X-axis, Y-axis, and Z-axis are defined, and the positive direction of the Z-axis is defined as the vertically upward direction.

[0138] The substrate processing system 700 includes a loading / unloading station 702 and a processing station 703. The loading / unloading station 702 and the processing station 703 are provided adjacent to each other.

[0139] The loading / unloading station 702 has a carrier placement section 711 and a transport section 712. The carrier placement section 711 is placed with a plurality of transport containers (hereinafter referred to as "carriers C") capable of accommodating a plurality of substrates W in a horizontal state.

[0140] The transport section 712 is provided adjacent to the carrier placement section 711. Inside the transport section 712, a substrate transport device 721 and a delivery section 722 are provided.

[0141] The substrate transfer device 721 includes a wafer holding mechanism that holds the substrate W. The substrate transfer device 721 is capable of moving in the horizontal and vertical directions and rotating about a vertical axis, and transfers the substrate W between the carrier C and the delivery section 722 using the wafer holding mechanism.

[0142] The processing station 703 is provided adjacent to the transfer section 712. The processing station 703 includes the transfer section 712 and a plurality of substrate processing apparatuses 714. The plurality of substrate processing apparatuses 714 are provided side by side on both sides of the transfer section 713.

[0143] The transfer section 713 includes a substrate transfer device 731 therein. The substrate transfer device 731 includes a wafer holding mechanism that holds the substrate W. The substrate transfer device 731 is capable of moving in the horizontal and vertical directions and rotating about a vertical axis, and transfers the substrate W between the delivery section 722 and the substrate processing apparatus 714 using the wafer holding mechanism.

[0144] Any of the substrate processing apparatuses 714 may be the cleaning apparatus 600 shown in Fig. 15. Any of the substrate processing apparatuses 714 may be the cleaning apparatus 600A shown in Fig. 16. The substrate processing apparatus 714 as the cleaning apparatus 600 or 600A performs an etching process. The etching process may be performed, for example, to remove a metal oxide film constituting the first hard mask 105 disposed on the dielectric film 103.

[0145] In the substrate processing system 700 configured as described above, first, the substrate transfer device 721 in the loading / unloading station 702 takes out the substrate W from the carrier C and places the taken-out substrate W on the passing part 722. The substrate W placed on the passing part 722 is then taken out of the passing part 722 by the substrate transfer device 731 in the processing station 703 and carried into the substrate processing apparatus 714 serving as the cleaning apparatus 600, 600A, where it is subjected to etching processing by the substrate processing apparatus 714. After the etching processing, the substrate W is taken out of the substrate processing apparatus 714 by the substrate transfer device 731 and placed on the passing part 722, and then returned to the carrier C by the substrate transfer device 721.

[0146] The substrate processing system 700 includes a control unit 900. The control unit 900 is a device that controls the operation of the substrate processing system 700. The substrate transfer device 731 may be controlled to a vacuum state. As a result, any one of the substrate processing devices 714 may be the film formation device 300 with a vacuum atmosphere shown in FIG. 12. Alternatively, any one of the substrate processing devices 714 may be the film formation device 400 with a vacuum atmosphere shown in FIG. 13. Alternatively, any one of the substrate processing devices 714 may be the etching device 500 with a vacuum atmosphere shown in FIG. 14. As a result, the substrate processing system 700 can integrally perform the respective steps of the substrate processing method according to the first embodiment and the substrate processing method according to the second embodiment.

[0147] It should be noted that the disclosed embodiments are illustrative in all respects and should not be considered limiting. Indeed, the above-described embodiments may be embodied in various forms. Furthermore, the above-described embodiments may be omitted, substituted, or modified in various forms without departing from the scope and spirit of the appended claims.

[0148] Furthermore, the following supplementary notes are disclosed regarding the above-described embodiment. (Appendix 1) (A) providing a substrate having a first surface and a second surface opposite the first surface; (B) forming a dielectric film on the first surface; (C) forming a metal oxide film containing one or more metal elements in a predetermined composition as a first hard mask on the dielectric film, wherein the metal oxide film does not contain a crystalline film; (F) after (C), forming a resist-related first film having a first pattern formed thereon; (G) after (F), etching the first hard mask to form recesses in the first hard mask according to the first pattern; (H) etching the dielectric film to form recesses in the dielectric film according to the first pattern; (I) after (H), removing the first hard mask by cleaning the substrate; (J) filling the recesses formed in the dielectric film with metal; (K) planarizing the metal; A substrate processing method comprising: (Appendix 2) The metal element includes at least one of indium, gallium, and zinc. 2. The substrate processing method of claim 1. (Appendix 3) the metal element includes at least one of indium and gallium, and zinc; The composition ratio of zinc to the total of the metal elements is 80% or less. 3. The substrate processing method according to claim 1 or 2. (Appendix 4) The metal oxide film is an amorphous film. 4. A substrate processing method according to any one of claims 1 to 3. (Appendix 5) (D) after (C), cleaning the second surface and the outer periphery of the first surface; 5. A substrate processing method according to any one of claims 1 to 4. (Appendix 6) (E) after (D), forming a silicon-containing film as a second hard mask; (G) etching the first hard mask and the second hard mask to form recesses in the first hard mask according to the first pattern; 6. The substrate processing method according to claim 5. (Appendix 7) The (F) is (F-1) forming the first film on the second hard mask; (F-2) forming the first pattern on the first film by exposure and development; (F-3) etching the second hard mask to form recesses in the second hard mask according to the first pattern, 7. The substrate processing method according to claim 6. (Appendix 8) In the step (G), the recesses are formed in the first hard mask using a gas capable of generating CH radicals. 8. A substrate processing method according to any one of claims 1 to 7. (Appendix 9) In the above (C), the metal oxide film contains indium, gallium, zinc, and oxygen in a composition ratio of 1:1:1:4; the temperature of the stage on which the substrate is placed is 25°C to 400°C; The bias power value supplied to the stage is 800 W to 1400 W. 9. A substrate processing method according to any one of claims 1 to 8. (Appendix 10) (L) after (G), forming a resist-related second film having a second pattern formed thereon; (M) after (L), etching the dielectric film to form vias in the dielectric film according to the second pattern; (N) after (M), ashing the second film, In the step (H), after the step (N), the via is formed to penetrate the dielectric film; In the step (J), a metal is embedded in the recess and the via formed in the dielectric film. 7. The substrate processing method according to claim 6. (Appendix 11) The (L) is (L-1) forming the second film on the second hard mask; (L-2) forming the second pattern in the second film by exposure and development, 11. The substrate processing method according to claim 10. (Appendix 12) The above (I) is (I-1) acid-cleaning the substrate; (I-2) a step of alkaline cleaning the substrate; (I-3) rinsing the substrate with a rinse liquid, 12. A substrate processing method according to any one of claims 1 to 11. (Appendix 13) In the above (I), the flatness of the recessed portion of the dielectric film after removing the first hard mask is such that the LWR is 1.6 nm or less and the LER is 1.2 nm or less. 13. The substrate processing method of claim 12. (Appendix 14) A substrate processing apparatus having a processing vessel, a gas supply port, and a control unit, The control unit Providing a substrate having a dielectric film formed thereon into the processing chamber; forming a metal oxide film containing one or more metal elements in a predetermined composition as a first hard mask on the dielectric film by using a gas containing one or more metal elements supplied from the gas supply port, wherein the metal oxide film does not contain a crystalline film; The substrate processing apparatus controls the (Appendix 15) A substrate processing apparatus having a processing vessel, a gas supply port, and a control unit, The control unit providing a substrate having a first hard mask and a resist-related first film having a first pattern formed thereon in this order on a dielectric film into the processing chamber; forming recesses in the first hard mask corresponding to the first pattern formed in the first film by etching the first hard mask with a gas capable of generating CH radicals, which is supplied from the gas supply port; The substrate processing apparatus controls the (Appendix 16) A substrate processing apparatus having a processing vessel, a liquid supply port, and a control unit, The control unit providing a substrate on which a dielectric film having a recess and a first hard mask are formed in this order into the processing chamber; removing the first hard mask by supplying a cleaning liquid and a rinse liquid from the liquid supply port to acid-clean the substrate, alkali-clean the substrate, and rinse the substrate with a rinse liquid; The substrate processing apparatus controls the [Explanation of symbols]

[0149] 101: Silicon substrate 102:SiCN film 103: Dielectric film 104: Cap membrane 105: First hard mask 106: Second hard mask 110: Resist-related first film 111:SOC membrane 112:SOG membrane 113: Resist film 120: Recess 130: Copper wiring layer 200: 1st page 201:Second side 210: Resist-related second film 211:SOC membrane 212:SOG membrane 213: Resist film 220:Beer 300, 400: Film deposition equipment 500: Etching equipment 600, 600A: Cleaning equipment 700: Substrate processing system OP: First Pattern OP2: Second pattern W: Substrate

Claims

1. (A) providing a substrate having a first surface and a second surface opposite the first surface; (B) forming a dielectric film on the first surface; (C) forming a metal oxide film containing one or more metal elements in a predetermined composition as a first hard mask on the dielectric film, the metal oxide film not containing a crystalline film; (F) after (C), forming a resist-related first film having a first pattern formed thereon; (G) after (F), etching the first hard mask to form recesses in the first hard mask according to the first pattern; (H) etching the dielectric film to form recesses in the dielectric film according to the first pattern; (I) after (H), removing the first hard mask by cleaning the substrate; (J) filling the recesses formed in the dielectric film with metal; (K) planarizing the metal; A substrate processing method comprising:

2. The metal element includes at least one of indium, gallium, and zinc. The substrate processing method according to claim 1 .

3. the metal element includes at least one of indium and gallium, and zinc; The composition ratio of zinc to the total metal elements is 80% or less. The substrate processing method according to claim 2 .

4. The metal oxide film is an amorphous film. The substrate processing method according to claim 1 .

5. (D) after (C), cleaning the second surface and the outer periphery of the first surface; The substrate processing method according to any one of claims 1 to 4.

6. (E) after (D), forming a silicon-containing film as a second hard mask; (G) etching the first hard mask and the second hard mask to form recesses in the first hard mask according to the first pattern; The substrate processing method according to claim 5 .

7. The (F) is (F-1) forming the first film on the second hard mask; (F-2) forming the first pattern in the first film by exposure and development; (F-3) etching the second hard mask to form recesses in the second hard mask according to the first pattern; The substrate processing method according to claim 6 .

8. In the above (G), CH ３ forming the recess in the first hard mask with a gas capable of generating radicals; The substrate processing method according to any one of claims 1 to 4.

9. In the above (C), the metal oxide film contains indium, gallium, zinc, and oxygen in a composition ratio of 1:1:1:4; the temperature of the stage on which the substrate is placed is 25°C to 400°C; The bias power value supplied to the stage is 800 W to 1400 W. The substrate processing method according to any one of claims 1 to 4.

10. (L) after (G), forming a resist-related second film having a second pattern formed thereon; (M) after (L), etching the dielectric film to form vias in the dielectric film according to the second pattern; (N) after (M), ashing the second film, In the step (H), after the step (N), the via is formed to penetrate the dielectric film; In the step (J), a metal is embedded in the recess and the via formed in the dielectric film. The substrate processing method according to claim 6 .

11. The (L) is (L-1) forming the second film on the second hard mask; (L-2) forming the second pattern in the second film by exposure and development; The substrate processing method according to claim 10.

12. The above (I) is (I-1) acid-washing the substrate; (I-2) a step of alkaline cleaning the substrate; (I-3) rinsing the substrate with a rinse liquid; The substrate processing method according to any one of claims 1 to 4.

13. In the above (I), the flatness of the recessed portion of the dielectric film after removing the first hard mask is such that the LWR is 1.6 nm or less and the LER is 1.2 nm or less. The substrate processing method according to claim 12.

14. A substrate processing apparatus having a processing vessel, a gas supply port, and a control unit, The control unit Providing a substrate having a dielectric film formed thereon into the processing chamber; forming a metal oxide film containing one or more metal elements in a predetermined composition on the dielectric film as a first hard mask by using a gas containing one or more metal elements supplied from the gas supply port, wherein the metal oxide film does not contain a crystalline film; The substrate processing apparatus controls the

15. A substrate processing apparatus having a processing vessel, a gas supply port, and a control unit, The control unit providing a substrate having a first hard mask and a resist-related first film having a first pattern formed thereon in this order on a dielectric film into the processing chamber; CH supplied from the gas supply port ３ forming recesses in the first hard mask corresponding to the first pattern formed in the first film by etching the first hard mask with a gas capable of generating radicals; The substrate processing apparatus controls the

16. A substrate processing apparatus having a processing vessel, a liquid supply port, and a control unit, The control unit providing a substrate on which a dielectric film having a recess and a first hard mask are formed in this order into the processing chamber; removing the first hard mask by supplying a cleaning liquid and a rinse liquid from the liquid supply port to acid-clean the substrate, alkali-clean the substrate, and rinse the substrate with a rinse liquid; The substrate processing apparatus controls the

Images