Plant output monitoring system and plant output monitoring method

Abstract

To provide a plant output monitoring system capable of reducing a system configuration scale by reducing the number of components.SOLUTION: A plant output monitoring system includes: a signal processing unit to which signals from a plurality of detectors that detects radiation are input, and an averaging calculation device that performs calculation on processing results from the signal processing unit. The signal processing unit includes a signal selection unit that sequentially selects and outputs respective signals output from the plurality of detectors, and a filter processing unit that performs filter processing on the signals output by the signal selection unit and outputs the processed signals to the averaging calculation device. The filter processing unit is constituted by a programmable gate array, and includes a plurality of filters which is provided corresponding to the plurality of detectors, and a control unit for sequentially inputting the signals sequentially selected and output by the signal selection unit into the respective filters.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a plant power monitoring system and a plant power monitoring method. [Background technology]

[0002] Boiling water reactors have a reactor power monitoring system for monitoring the neutron flux inside the reactor core from shutdown to full power operation. Technology related to such a system is described in Patent Document 1 below. Patent Document 1 states that "LPRM values ​​output from multiple local power calculation devices are input to an average calculation unit to determine an APRM value, and these LPRM values ​​and APRM values ​​are monitored to monitor the reactor power, with the local power calculation devices and the reactor average power calculation device each configured as an independent device using an FPGA or the like." [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-3399 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the configuration described in Patent Document 1, signal processing for one detector is performed by one FPGA, which increases the scale of the system configuration and the number of parts.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a plant power monitoring system and a plant power monitoring method that are capable of reducing the scale of the system configuration by reducing the number of parts. [Means for solving the problem]

[0006] In order to solve the above problems, for example, the configurations described in the claims are adopted. The present application includes a plurality of means for solving the above-described problems. One example is a plant output monitoring system including a signal processing unit to which signals from a plurality of detectors that detect radiation are input, and an averaging device that calculates a processing result from the signal processing unit, wherein the signal processing unit includes a signal selection unit that sequentially selects and outputs each of the signals output from the plurality of detectors, and a filter processing unit that filters the signal output by the signal selection unit and outputs the filtered signal to the averaging device, the filter processing unit being configured with a programmable gate array and including a plurality of filters provided corresponding to the plurality of detectors, and a control unit for sequentially inputting the signals sequentially selected and output by the signal selection unit to each of the filters. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a plant power monitoring system and a plant power monitoring method that can reduce the scale of the system configuration by reducing the number of parts. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram of a plant power monitoring system according to a first embodiment. [Figure 2] FIG. 2 is a block diagram of a filter included in the filter processing unit of the first embodiment. [Figure 3] FIG. 3 is a state transition diagram of a control unit included in the filter processing unit of the first embodiment. [Figure 4] FIG. 10 is a circuit diagram for detecting an abnormality in an A / D conversion unit. [Figure 5] 10 is an operation timing chart of an A / D converter abnormality determination unit when the A / D converter is normal. [Figure 6] 10 is an operation timing chart of the A / D converter abnormality determination unit when the A / D converter is abnormal. [Figure 7] FIG. 3 is a state transition diagram of a filter control unit included in the filter of the first embodiment. [Figure 8] FIG. 2 is a circuit diagram of a filter calculation unit included in the filter of the first embodiment. [Figure 9] 10 is a table showing transitions of data stored in A / D data flip-flops of a filter calculation unit. [Figure 10] 10 is a timing chart showing switching of the filter processing state for each detector. [Figure 11] 10 is a timing chart showing the operation of a filter control unit in a filter processing state for each detector. [Figure 12] FIG. 10 is a diagram showing a circuit for detecting an abnormality in a filter corresponding to each detector. [Figure 13] 10 is a timing chart showing another example of switching of the filter processing state for each detector. [Figure 14] FIG. 10 is a block diagram of a plant power monitoring system according to a second embodiment. [Figure 15] FIG. 10 is a block diagram of a filter included in a filter processing unit according to a second embodiment. [Figure 16] FIG. 10 is a circuit diagram of a filter calculation unit included in a filter according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, each embodiment of the plant power monitoring system and plant power monitoring method of the present invention will be described in detail with reference to the drawings. Note that, in each embodiment, the description will be given on the premise that a nuclear reactor is used as an example of a plant, but the plant is not limited to a nuclear reactor. Furthermore, in each embodiment, elements having substantially the same function or the same configuration will be given the same reference numerals, and duplicated descriptions will be omitted.

[0010] (Plant output monitoring system of the first embodiment) Fig. 1 is a block diagram of a plant power monitoring system according to a first embodiment. The plant power monitoring system shown in Fig. 1 is for monitoring radiation output values ​​within a plant. If the plant is a nuclear reactor, the radiation may be, for example, neutron flux. This plant power monitoring system includes multiple detectors 1, a signal processing unit 11, an average calculation unit 12, and a communication unit 13.

[0011] The multiple detectors 1 are any n number of first detectors 1-1 to n-th detector 1-n. These n detectors 1 are connected to one signal processing unit 11. The plant monitoring system may also have any p number of signal processing units 11. The p number of signal processing units 11 are first signal processing unit 11-1 to p-th signal processing unit 11-p, which are connected to one average calculation device 12 via respective communication units 13. Each of the components constituting the plant output monitoring system will be described in detail below.

[0012] <Detector 1> The detector 1 detects neutron flux in the plant and outputs a detector current signal S1, which is a direct current proportional to the neutron flux. The detector current signal S1 is a first detector current signal S1-1 to an n-th detector current signal S1-n detected by the first detector 1-1 to the n-th detector 1-n, respectively. Each detector 1 outputs the detector current signal S1 to a signal processing unit 11.

[0013] <Signal processing unit 11> The signal processing unit 11 processes the detector current signals S1 input from the detectors 1 as signals to be output to the average calculation unit 12. Here, FIR (Finite Impulse Response) filter processing represented by the following equation (1) is performed.

[0014]

number

[0015] In equation (1), F is the value after FIR filter processing. In FIR filter processing, filtering is performed using a finite number of discrete data. An is the filter coefficient. Dn represents A / D data. Equation (1) performs FIR filter processing using m discretely acquired A / D data Dn and the corresponding m filter coefficients An. The filter coefficients are weighting coefficients such that the sum of the m filter coefficients An is 1.

[0016] The signal processing unit 11 that performs such processing has an I / V conversion unit 2, a signal selection unit 3, an A / D conversion unit 4, a filter processing unit 5, a switching unit 6a, and an oscillator 6b. These are as follows.

[0017] The I / V conversion unit 2 is a device that outputs voltage signals S2 obtained by converting the detector current signals S1 input from the detectors 1 into voltages. The voltage signals S2 are first voltage signals S2-1 to n-th voltage signals S2-n corresponding to the first detector current signals S1-1 to n-th detector current signals S1-n. <Signal selection section 3> The signal selection unit 3 is a device that outputs, as a selected voltage signal S3, a specific one of the first voltage signal S2-1 to the n-th voltage signal S2-n output by the I / V conversion unit 2. Which voltage signal S2 is to be output as the selected voltage signal S3 is determined by a signal selection unit control signal S7b output by a control unit 7 in the filter processing unit 5, which will be described later. The procedure for signal selection by the signal selection unit 3 will be described below in <<(1) Control by the control unit 7>> of the plant output monitoring method.

[0018] The A / D conversion unit 4 digitally converts the selected voltage signals S3 sequentially input from the signal selection unit 3 and outputs the converted A / D data S4 to the filter processing unit 5, which will be described next. The timing at which the A / D conversion unit 4 performs digital conversion is the rising edge of an A / D conversion unit trigger signal S7a from the control unit 7 in the filter processing unit 5. The A / D conversion unit 4 also outputs an A / D conversion unit busy signal S4a to the control unit 7, so that the control unit 7 can detect an abnormality in the A / D conversion unit 4. Details of the detection of an abnormality in the A / D conversion unit 4 by the control unit 7 will be described below in <<(1) Control by the control unit 7>> of the plant output monitoring method.

[0019] <Filter processing unit 5> ​​The filter processing unit 5 has a filter function for removing noise superimposed on the A / D data S4, and is capable of removing, for example, sine waves of 50 Hz or 60 Hz, which are commercial frequency bands. The filter processing unit 5 can be realized using a programmable device such as an FPGA (Field Programmable Gate Array), but is not limited to an FPGA and can be realized by any hardware circuit. Such a filter processing unit 5 has a control unit 7, a filter 8, a memory unit 9, and an update count value generation unit 10. These are as follows.

[0020] [Control Unit 7] The control unit 7 controls the filter 8, the memory unit 9, the signal selection unit 3, and the A / D conversion unit 4. Details of the control by the control unit 7 will be explained below in <<(1) Control by the control unit 7>> of the plant output monitoring method.

[0021] [Filter 8] The filters 8 perform FIR filtering to remove noise superimposed on the A / D data S4 input from the A / D conversion unit 4. The filters 8 are a first filter 8-1 to an n-th filter 8-n provided in one-to-one correspondence with the n detectors 1. The A / D data S4 input to each filter 8 is first A / D data S4-1 to n-th A / D data S4-n input in one-to-one correspondence with the n filters 8.

[0022] The filter 8 outputs the calculation results of the FIR filter processing as filter calculation data S8a to the storage unit 9. The filter calculation data S8a is first filter calculation data S8a-1 to n-th filter calculation data S8a-n calculated in each filter 8.

[0023] Each filter 8 starts FIR filter processing in response to a calculation start signal S7 from the control unit 7, and when one FIR filter processing is completed, outputs a calculation end signal S8 to the control unit 7. The calculation start signals S7 from the control unit 7 are first calculation start signals S7-1 to n-th calculation start signals S7-n that are input individually to each filter 8. Furthermore, the calculation end signals S8 output by each filter 8 are first calculation end signals S8-1 to n-th calculation end signals S8-n.

[0024] 2 is a block diagram of the filter 8 included in the filter processing unit 5 of the first embodiment. The filter 8 is made up of a filter control unit 80, an A / D data correction processing unit 81, and a filter calculation unit 82. These are as follows.

[0025] The filter control unit 80 generates the following various signals based on a calculation start signal S7 input from the control unit 7. The filter control unit 80 generates a calculation end signal S8 when calculation in a filter calculation unit 82, which will be described next, has ended, and outputs this signal to the control unit 7. The filter control unit 80 also generates a count-up signal S8b when calculation in the filter calculation unit 82, which will be described next, has ended, and outputs this signal to the update count value generation unit 10. The filter control unit 80 also generates a mode selection signal S80a, an A / D data flip-flop shift signal S80b, an integration value flip-flop latch signal S80c, an integration value flip-flop clear signal S80d, and a filter coefficient address signal S80e, and outputs these signals to the filter calculation unit 82. Details of control, including the generation of various signals, by the filter control unit 80 will be described below in <<(2) Control by the Filter Control Unit 80>> of the plant output monitoring method.

[0026] The A / D data correction processing unit 81 performs offset addition and gain multiplication on the A / D data S4 input from the A / D conversion unit 4, and outputs corrected A / D data S81 to the filter calculation unit .

[0027] The filter calculation unit 82 performs filtering on the corrected A / D data S81 input from the A / D data correction processing unit 81. The filter calculation unit 82 performs filtering based on various signals input from the filter control unit 80. The filter calculation unit 82 also selects which frequency band the filter processing should be performed for based on a filter coefficient table selection signal S6a input from a switching unit 6a, which will be described later. The filter calculation unit 82 outputs filter calculation data S8a obtained by the filtering to a storage unit 9, which will be described later. The processing procedure by the filter calculation unit 82 will be described in detail below in <<(3) Filtering by the filter calculation unit 82>> of the plant power monitoring method.

[0028] [Storage section 9] Returning to FIG. 1, the storage unit 9 stores the A / D conversion unit abnormality signal S7c input from the control unit 7. The storage unit 9 stores the updated count value S10 input from the updated count value generation unit 10. The storage unit 9 also stores the filter calculation data S8a input from each filter 8. The filter calculation data S8a is the first filter calculation data S8a-1 to the n-th filter calculation data S8a-n output from each filter 8.

[0029] [Update count value generation unit 10] The update count value generator 10 is composed of a counter that is incremented by a count-up signal S8b from each filter 8. The count-up signals S8b are a first count-up signal S8b-1 to an n-th count-up signal S8b-n from each filter 8. The counter of the update count value generator 10 has an independent counter for each filter 8. This makes it possible to individually determine abnormalities in the filters 8 that are provided in a one-to-one correspondence with each detector 1, as will be described in detail below. Note that the determination of abnormalities in the filters 8 by providing the update count value generator 10 will be described in detail below in <<(4) Filter abnormality detection method>> of the plant output monitoring method.

[0030] <Switching unit 6a> The switching unit 6a also outputs a filter coefficient table selection signal S6a to each filter 8 provided in the filter processing unit 5, for switching the frequency band to be processed by the filter 8. For example, if the filter 8 is equipped with a 50 Hz and 60 Hz filter function, the device can be used in the same configuration regardless of whether the commercial frequency band in the area where it is used is 50 Hz or 60 Hz, and it is only necessary to switch the switching unit 6a. One method for implementing the switching unit 6a is to switch the signal on and off by connecting or disconnecting a resistor in the circuit, for example.

[0031] <Oscillator 6b> The oscillator 6b outputs a clock signal S6b with a fixed period to the filter processing unit 5. The operation timing of the filter processing unit 5 is determined by the period of the clock signal S6b.

[0032] ≪Averaging calculation device 12≫ The average calculation device 12 is a device that calculates the output of the entire plant or a part of the plant from the neutron flux detected by the n detectors 1. Such an average calculation device 12 has the function of averaging the FIR filter calculation results for each detector 1 output from each signal processing unit 11 via the communication unit 13, and calculating the plant output. The average calculation device 12 is also a device that detects abnormalities in the detectors 1 and the signal processing unit 11. Such an average calculation device 12 has an average calculation processing unit 12a, an update abnormality confirmation unit 12b, and a detector abnormality determination unit 12c, which are as follows:

[0033] <Average calculation processing unit 12a> The average calculation processing unit 12a has a function of averaging the calculation results of the FIR filter processing for each detector 1 output by the signal processing unit 11 via the communication unit 13, and calculating the plant output. The calculation results of the FIR filter processing are filter calculation data S8a held in the storage unit 9 of the filter processing unit 5.

[0034] <Update abnormality confirmation section 12b> The update abnormality confirmation unit 12b monitors the counter for each detector 1 output from the update count value generation unit 10 of the signal processing unit 11, and confirms whether the counter value is being updated at regular intervals. If the counter value is not being updated, the update abnormality confirmation unit 12b determines that there is an abnormality in the filter function of the filter 8 corresponding to that detector 1. The average calculation processing unit 12a performs averaging except for the FIR filter calculation results from the filter determined to be abnormal by the update abnormality confirmation unit 12b, and continues plant output monitoring. The procedure for detecting a filter abnormality by the update abnormality confirmation unit 12b will be described in detail below in <<(4) Filter abnormality detection method>> of the plant output monitoring method.

[0035] <Detector abnormality determination unit 12c> The detector abnormality determination unit 12c monitors the FIR filter calculation results of each detector 1. When the neutron flux of a certain detector 1 becomes a value above or below a certain value, the detector abnormality determination unit 12c determines that the corresponding detector 1 is abnormal. The average calculation processing unit 12a continues to monitor the plant output by performing averaging processing excluding the FIR filter calculation results of the detector 1 determined to be abnormal by the detector abnormality determination unit 12c.

[0036] In addition, if a certain number or more of the n detectors 1 connected to one signal processing unit 11 are judged to be abnormal by the detector abnormality judgment unit 12c, it is judged that plant output monitoring using the detectors 1 inputting to the corresponding signal processing unit 11 is impossible.

[0037] <Communications Department 13> The communication units 13 are provided corresponding to the respective signal processing units 11, and enable bidirectional communication between each signal processing unit 11 and one average calculation device 12.

[0038] (Plant output monitoring method of the first embodiment) Next, a nuclear power monitoring method implemented by the above-mentioned nuclear power monitoring system will be described. This nuclear power monitoring method is a procedure for each control and judgment implemented by a nuclear power monitoring program possessed by each component of the nuclear power monitoring system.

[0039] (1) Control by the control unit 7 Fig. 3 is a state transition diagram of the control unit 7 of the filter processing unit 5 of the first embodiment. The state transition shown in Fig. 3 is executed by a control program held by the computer constituting the control unit 7 shown in Fig. 1. Below, the state transition of control by the control unit 7 will be explained along Fig. 3 with reference to Fig. 1 and other necessary figures.

[0040] 3, the state transition of the control unit 7 is a loop, with the A / D conversion completion waiting state A20 being the head of the loop. After one clock, the control unit 7 transitions from the A / D conversion completion waiting state A20 to the A / D conversion normal completion confirmation state A21.

[0041] In the A / D conversion normal completion confirmation state A21, the control unit 7 determines whether the digital conversion performed by the A / D conversion unit 4 has completed normally. In order to make such a determination, the control unit 7 has the following determination circuit.

[0042] FIG. 4 is a circuit diagram for detecting an abnormality in the A / D converter. As shown in FIG. 4, the control unit 7 of the filter processing unit 5 has an A / D conversion trigger signal generation unit 72. The A / D conversion trigger signal generation unit 72 generates an A / D converter trigger signal S7a at a constant cycle. The A / D conversion trigger signal generation unit 72 generates the A / D converter trigger signal S7a as a pulse signal that changes from "0" to "1" to "0" and outputs the A / D converter trigger signal S7a to the A / D converter 4 and a falling edge detection unit 73, which will be described later. This constant cycle corresponds to the A / D sampling period T1, which will be described later using FIG. 10. The A / D conversion trigger signal generation unit 72 outputs the generated A / D converter trigger signal S7a to the A / D converter 4 and a falling edge detection unit 73, which will be described later.

[0043] ​​The control unit 7 also has an inverter 70. The inverter 70 generates an A / D conversion completion signal S70 by inverting the A / D conversion unit busy signal S4a. The A / D conversion unit busy signal S4a is a signal output by the A / D conversion unit 4, and is a signal that is "1" when A / D conversion is being performed and is "0" when A / D conversion is not being performed. The inverter 70 inverts this A / D conversion unit busy signal S4a, and sets the A / D conversion completion signal S70 to "1" when A / D conversion is not being performed, so that the A / D conversion is considered to be completed at this time.

[0044] The control unit 7 also has a falling edge detection unit 73. When the A / D conversion unit trigger signal S7a changes from "1" to "0", the falling edge detection unit 73 outputs "1" as the A / D conversion unit trigger signal falling detection signal S73. If the A / D conversion unit 4 is operating normally, A / D conversion in the A / D conversion unit 4 should have finished when the A / D conversion unit trigger signal falling detection signal S73 becomes "1".

[0045] The control unit 7 also has an A / D conversion unit abnormality determination unit 74. The A / D conversion unit abnormality determination unit 74 determines whether the A / D conversion unit 4 is operating abnormally based on the A / D conversion unit trigger signal S7a output by the A / D conversion trigger signal generation unit 72 and the A / D conversion unit busy signal S4a output by the A / D conversion unit 4 while it is performing A / D conversion. Fig. 5 is an operation timing chart of the A / D conversion unit abnormality determination unit when the A / D conversion unit is normal. Fig. 6 is an operation timing chart of the A / D conversion unit abnormality determination unit when the A / D conversion unit is abnormal.

[0046] 5, when the A / D converter trigger signal falling detection signal S73 is "1" from the falling edge detection unit 73, the A / D converter abnormality determination unit 74 determines that the A / D converter 4 is in a normal state if the A / D conversion completion signal S70 input from the inverter 70 is "1." In this case, the A / D converter abnormality determination unit 74 outputs the A / D converter abnormality determination result signal S74 as "0."

[0047] 6, when the A / D converter trigger signal falling detection signal S73 is "1" from the falling edge detection unit 73 and the A / D conversion completion signal S70 input from the inverter 70 is "0," the A / D converter abnormality determination unit 74 determines that the A / D converter 4 is operating abnormally. In this case, the A / D converter abnormality determination unit 74 outputs the A / D converter abnormality determination result signal S74 as "1."

[0048] Returning to FIG. 4, the control unit 7 has a state transition unit 71. When the A / D conversion unit abnormality determination result signal S74 input from the A / D conversion unit abnormality determination unit 74 is "1," the state transition unit 71 outputs an A / D conversion unit abnormality signal S7c of "1" to the storage unit 9. In the storage unit 9, the A / D conversion unit abnormality signal S7c of "1" is stored in an A / D conversion unit abnormality determination storage unit 90. Once the A / D conversion unit abnormality determination storage unit 90 stores "1," it continues to store the A / D conversion unit abnormality determination result signal S74 at "1" even if the A / D conversion unit abnormality determination result signal S74 becomes "0" thereafter.

[0049] 3, if the control unit 7 determines that the digital conversion performed by the A / D conversion unit 4 has ended normally, that is, if the A / D conversion unit abnormality determination result signal S74 described with reference to Fig. 4 is "0", the control unit 7 transitions to the signal selection unit control signal output state A22. On the other hand, if the control unit 7 determines that the digital conversion performed by the A / D conversion unit 4 has ended abnormally, that is, if the A / D conversion unit abnormality determination result signal S74 described with reference to Fig. 4 is "1", the control unit 7 transitions to the A / D conversion unit abnormality state A22a.

[0050] ​In the A / D converter abnormal state A22a, the control unit 7 sets the A / D converter abnormal signal S7c to "1." Then, the control unit 7 outputs the A / D converter abnormal signal S7c to the memory unit 9 (see FIG. 4) and notifies the average calculation device 12 of the abnormal state via the communication unit 13. When the A / D converter abnormal state A22a is entered, it is determined that an irreparable failure has occurred in the A / D converter 4, and transition to another state is not possible. Here, as described above, once the A / D converter abnormality determination memory unit 90 (see FIG. 4) of the memory unit 9 holds "1," it continues to hold the A / D converter abnormality determination result signal S74 at "1" even if the A / D converter abnormality determination result signal S74 becomes "0." This makes it possible to detect an abnormality in the A / D converter 4 even if it occurs for a short period of time, thereby improving the reliability of the plant power monitoring system.

[0051] <Signal selection unit control signal output state A22> In the signal selection unit control signal output state A22, the control unit 7 outputs a signal selection unit control signal S7b to the signal selection unit 3. The signal selection unit control signal S7b causes the signal selection unit 3 to determine which of the first voltage signal S2-1 to the n-th voltage signal S2-n input from the I / V conversion unit 2 to output as the selected voltage signal S3. For example, this is possible by outputting the first voltage signal S2-1 as the selected voltage signal S3 when the signal selection unit control signal S7b is "0001" as a signal having multiple bits, and outputting the second voltage signal S2-2 as the selected voltage signal S3 when the signal selection unit control signal S7b is "0010."

[0052] <Calculation start signal output status A23> In the calculation start signal output state A23, the control unit 7 outputs a calculation start signal S7 to the filter 8. At this time, the control unit 7 outputs the calculation start signal S7 to any one of the first filter 8-1 to the n-th filter 8-n. Here, the calculation start signal S7 to be output to a certain filter 8 is fixed; for example, the control unit 7 outputs a first calculation start signal S7-1 to the first filter 8-1 and a second calculation start signal S7-2 to the second filter 8-2. Such a calculation start signal S7 is a signal that is "1" when instructing the filter 8 to start calculation and is "0" otherwise. In other words, which filter 8 the calculation start signal S7 is to be output to is determined in accordance with the signal selection unit control signal S7b that the control unit 7 outputs to the signal selection unit 3.

[0053] <Computation end signal response waiting state A24> In the computation end signal response waiting state A24, the control unit 7 waits for the completion of computation in the filter 8 to which it output the computation start signal S7 in the immediately preceding computation start signal output state A23. For example, if it has output the first computation start signal S7-1, it waits for the input of the first computation end signal S8-1. The computation end signal S8 is a signal that becomes "1" when the computation in the filter 8 has completed, and is "0" otherwise. When "1" is input as the first computation end signal S8-1, the control unit 7 changes the first computation start signal S7-1 from "1" to "0."

[0054] <Signal selection unit control signal update state A25> In the signal selection unit control signal update state A25, the control unit 7 updates the signal selection unit control signal S7b so that the signal selection unit 3 selects the next voltage signal S2. For example, if the signal selection unit control signal S7b is "0001," the control unit 7 sets the signal selection unit control signal S7b to "0010" in this state. This causes the control unit 7 to update the signal that the signal selection unit 3 outputs as the selected voltage signal S3 from the first voltage signal S2-1 to the second voltage signal S2-2. Thereafter, the state transitions to the A / D conversion completion waiting state A20.

[0055] (2) Control by the filter control unit 80 Fig. 7 is a state transition diagram of the filter control unit 80 of the filter 8 of the first embodiment. The state transition shown in Fig. 7 is executed by a control program held by the computer constituting the filter control unit 80 shown in Fig. 2, and shows the procedure for outputting signals necessary for the filter calculation unit 82 to perform filtering. Details of the filtering process in the filter calculation unit 82 will be explained below in the section on the filtering method by the filter calculation unit 82. Below, the state transition of control by the filter control unit 80 will be explained along with Fig. 7, with reference to Fig. 2 and other necessary figures.

[0056] <Initial state A40> 7, the state transition of the filter control unit 80 is in the form of a loop, with the initial state A40 being the beginning of the loop. In the initial state A40, the filter control unit 80 transitions to an A / D data correction processing completion waiting state A41 when a calculation start signal S7 "1" is input from the control unit 7. Note that the control unit 7 outputs the calculation start signal S7 "1" in the calculation start signal output state A23 described with reference to FIG.

[0057] In the A / D data correction processing completion waiting state A41, the filter control unit 80 waits for the time until the A / D data correction processing unit 81 outputs the corrected A / D data S81 to the filter calculation unit 82. This waiting time is the time required for the processing in the A / D data correction processing unit 81, and is the delay time of the output from the A / D data correction processing unit 81.

[0058] In the A / D data flip-flop shift signal output state A42, the filter control unit 80 outputs an A / D data flip-flop shift signal S80b to the filter calculation unit 82. The A / D data flip-flop shift signal S80b is a pulse signal whose width of "0" → "1" → "0" is one clock.

[0059] <Integrated value flip-flop latch signal output state A43>​​ In the accumulation value flip-flop latch signal output state A43, the filter control unit 80 outputs an accumulation value flip-flop latch signal S80c to the filter calculation unit 82. The accumulation value flip-flop latch signal S80c is a pulse signal whose width of "0" → "1" → "0" is one clock.

[0060] <Operation end signal output status A44> In the calculation end signal output state A44, the filter control unit 80 sets the calculation end signal S8 to "1" and outputs it to the control unit 7. The calculation end signal S8 is output when one FIR filter calculation started in the filter calculation unit 82 has ended. At this time, the filter control unit 80 also outputs a count-up signal S8b to the update count value generation unit 10. The count-up signal S8b is a signal that is output when one FIR filter calculation started in the filter calculation unit 82 has ended, and is a pulse signal whose width is one clock from "0" → "1" → "0". One cycle of FIR filter processing is now complete.

[0061] <Integrated value flip-flop clear signal output state A45> In the accumulation value flip-flop clear signal output state A45, the filter control unit 80 outputs an accumulation value flip-flop clear signal S80d. The accumulation value flip-flop clear signal S80d is a pulse signal whose width is "0" → "1" → "0" for one clock.

[0062] <Computation start signal release waiting state A46> In the calculation start signal release waiting state A46, the filter control unit 80 waits until the calculation start signal S7 from the control unit 7 becomes "0." When the calculation start signal S7 becomes "0," the filter control unit 80 transitions to the next mode selection signal output state A47.

[0063] <Mode selection signal output status A47> In mode selection signal output state A47, the filter control unit 80 sets the mode selection signal S80a to "1" and sets the filter coefficient address signal S80e to a value that is one less than the number m of filter coefficients. The filter coefficient address signal S80e has a value that corresponds to the number m of filter coefficients shown in equation (1) above. For example, if there are 100 filter coefficients, the filter coefficient address signal S80e ranges from "0000000" to "1100011," and the filter coefficient address signal S80e output in this state is "1100011."

[0064] Thereafter, the A / D data flip-flop shift signal output state A42' and the accumulation value flip-flop latch signal output state A43' are successively performed, similarly to the A / D data flip-flop shift signal output state A42 and the accumulation value flip-flop latch signal output state A43 described above.

[0065] <Filter coefficient address decrement state A48> In the filter coefficient address decrement state A48, the filter control unit 80 decrements the value of the filter coefficient address signal S80e by one. For example, if the filter coefficient address signal S80e is "10010011," it is set to "10010010" in this state. The filter control unit 80 determines that the pre-filtering process is incomplete and returns to the A / D data flip-flop shift signal output state A42' to repeat the process until the filter coefficient address signal S80e becomes "00000001." This allows m-1 of the product-sum operations of the above equation (1) to be performed in advance. Furthermore, when the filter coefficient address signal S80e becomes "00000001" due to the filter coefficient address decrement, the filter control unit 80 determines that the pre-filtering process is complete and transitions to the initial state A40.

[0066] ​In other words, until it is determined that the pre-filtering process is completed, the A / D data flip-flop shift signal output state A42' and the integrated value flip-flop latch signal output state A43' are repeated to perform the product-sum operation process on the A / D data S4 excluding the A / D data S4 to be input in the next cycle, as part of the FIR filter process for the next cycle.

[0067] Then, in the initial state A40 to which the system returns after determining that the pre-filtering process is complete, the mode selection signal S80a, which was set to "1" in the mode selection signal output state A47, is set to "0." Thereafter, the system transitions to the calculation end signal output state A44 described above, where the calculation end signal S8 is set to "1" and output to the control unit 7, thereby completing one cycle of FIR filtering.

[0068] (3) Filtering by the filter calculation unit 82 Next, a description will be given of the filtering process performed by the filter calculation unit 82. Here, prior to the description of the filtering process, the configuration of the filter calculation unit 82 will be described.

[0069] <Configuration of filter calculation unit 82> 8 is a circuit diagram of the filter calculation unit 82 included in the filter of the first embodiment. The filter calculation unit 82 includes an input selection unit 800, a plurality of A / D data flip-flops 801, a filter coefficient storage unit 805, a multiplier 803, an adder 804, and an integrated value flip-flop 802. These are as follows:

[0070] [Input selection unit 800] The input selection unit 800 outputs a signal selected based on the mode selection signal S80a input from the filter control unit 80 (see FIG. 2) as an A / D data flip-flop input signal S800 to the A / D data flip-flop 801. The signal selected by the input selection unit 800 is either the corrected A / D data S81 input from the A / D data correction processing unit 81 or the A / D data flip-flop output signal S801 input from the A / D data flip-flop 801.

[0071] Specifically, when the mode selection signal S80a is "0," the input selection unit 800 outputs the corrected A / D data S81 as the A / D data flip-flop input signal S800 to the A / D data flip-flop 801. When the mode selection signal S80a is "1," the input selection unit 800 outputs the A / D data flip-flop output signal S801 input from the A / D data flip-flop 801 to the A / D data flip-flop 801 as the A / D data flip-flop input signal S800.

[0072] [A / D Data Flip-Flop 801] The A / D data flip-flop 801 is a circuit that holds information of the necessary bits, and holds discretely acquired A / D data (corrected A / D data S81). The filter calculation unit 82 is equipped with m-1 A / D data flip-flops 801, which is one less than m shown in the above equation (1). These A / D data flip-flops 801 are the first A / D data flip-flop 801-1 to the (m-1)th A / D data flip-flop 801-m-1, arranged in order from the input selection unit 800 side. These A / D data flip-flops 801 can hold A / D data for m-1 cycles. In the initial state A40 after the elapse of m-1 cycles, A / D data for the past m-1 cycles is always held.

[0073] An A / D data flip-flop shift signal S80b from the filter control unit 80 and a clock signal S6b from the oscillator 6b are input to each A / D data flip-flop 801. Furthermore, an A / D data flip-flop input signal S800 is input to the first A / D data flip-flop 801-1 from the input selection unit 800. The (m-1)th A / D data flip-flop 801-m-1 outputs an A / D data flip-flop output signal S801 (S801-m-1) to the input selection unit 800.

[0074] Furthermore, when the A / D data flip-flop shift signal S80b input from the filter control unit 80 is "1," the first A / D data flip-flop 801-1 outputs the A / D data flip-flop input signal S800 as the first A / D data flip-flop output signal S801-1 to the subsequent second A / D data flip-flop 801-2. This operation is similar in the A / D data flip-flop 801.

[0075] For example, when the A / D data flip-flop shift signal S80b is "1", the second A / D data flip-flop 801-2 outputs the first A / D data flip-flop output signal S801-1 that it has held to the third A / D data flip-flop 801-3 as the second A / D data flip-flop output signal S801-2.

[0076] Therefore, when the mode selection signal S80a is "1" and the A / D data flip-flop shift signal S80b becomes "1", the signals held in the first A / D data flip-flop 801-1 through the (m-1)th A / D data flip-flop 801-m-1 are shifted one by one to the second A / D data flip-flop 801-2 through the (m-1)th A / D data flip-flop 801-m-1, and then to the input selection section 800. The timing at which the A / D data flip-flop 801 operates is the timing at which the clock signal S6b changes from "0" to "1".

[0077] [Filter coefficient storage unit 805] The filter coefficient storage unit 805 stores the filter coefficients An shown in equation (1). There is a table for the filter coefficients An for each frequency band. The number m of filter coefficients An required for each frequency band varies, but the largest number is used. For example, if 80 filter coefficients An are required for the 50 Hz band and 100 for the 60 Hz band, 100 filter coefficients An are stored for both 50 Hz and 60 Hz. However, by setting the values ​​of filter coefficients An for 81 to 100 in the 50 Hz band to 0, the filter calculation unit 82 can be shared for FIR filter processing of different frequency bands. The frequency band table to be used is determined by a filter coefficient table selection signal S6a input from the switching unit 6a. In addition, the filter coefficient storage unit 805 outputs the filter coefficients in the table as a filter coefficient signal S805 to the multiplier 803 (described next) in accordance with a filter coefficient address signal S80e input from the filter control unit 80.

[0078] [Multiplier 803] The multiplier 803 multiplies the first A / D data flip-flop output signal S801-1 output from the first A / D data flip-flop 801-1 by the filter coefficient signal S805. The multiplier 803 outputs the multiplied value S803 to the adder 804.

[0079] [adder 804] The adder 804 adds the filter calculation data S8a output from the integration value flip-flop 802, which will be described next, and the multiplication value S803 input from the multiplier 803. The adder 804 outputs the addition value S804 to the integration value flip-flop 802.

[0080] [Integration value flip-flop 802] The integrated value flip-flop 802 holds the filter calculation data S8a based on the sum S804 input from the adder 804, and outputs the held filter calculation data S8a to the storage unit 9 and the adder 804. Specifically, it is as follows.

[0081] When the accumulation value flip-flop latch signal S80c input from the filter control unit 80 is "1" at the timing when the clock signal S6b is input, the accumulation value flip-flop 802 holds the held addition value S804 as filter calculation data S8a and outputs the held filter calculation data S8a to the memory unit 9 and the adder 804. Furthermore, when the accumulation value flip-flop latch signal S80c input from the filter control unit 80 is "0" at the timing when the clock signal S6b is input, the accumulation value flip-flop 802 outputs the filter calculation data S8a it holds as is to the memory unit 9 and the adder 804 without changing it.

[0082] Furthermore, when the accumulation value flip-flop clear signal S80d input from the filter control unit 80 is "1" at the timing when the clock signal S6b is input, the accumulation value flip-flop 802 holds the filter calculation data S8a "0" and outputs the held filter calculation data S8a to the memory unit 9 and the adder 804.

[0083] [Data transition in filter calculation unit 82] 9 is a table showing the transition of data stored in the A / D data flip-flop 801 of the filter calculation unit 82. The transition of data in the filter calculation unit 82 shown in FIG. 9 will be described below with reference to FIGS. 7 and 8.

[0084] 9 corresponds to the calculation end signal output state A44, and the filter coefficient address signal S80e at this time is 0. At the start of calculation, the first A / D data flip-flop data D1 to the (m-1)th A / D data flip-flop data Dm-1 are values ​​held by the A / D data flip-flops 801 in the calculation end signal output state A44, and correspond to the A / D data flip-flop output signal S801.

[0085] The processing counts 1 to (m-1) are the number of times the mode selection signal output state A47 transitions to the A / D data flip-flop shift signal output state A42'. At the time of this transition, the mode selection signal S80a is "1" and the A / D data flip-flop shift signal S80b is "1", and the data in the first A / D data flip-flop 801-1 to the (m-1)th A / D data flip-flop 801-m-1 is shifted by one piece of data each time the mode selection signal S80a transitions to the A / D data flip-flop shift signal output state A42'.

[0086] The signal held by first A / D data flip-flop 801-1 is then shifted to first A / D data flip-flop 801-1 and multiplied by filter coefficient signal S805 by multiplier 803. Therefore, after the first processing cycle, the oldest data held by A / D data flip-flop 801 is multiplied by filter coefficient signal S805 in order. When the number of processing cycles reaches m-1, the multiplication and addition (product-sum operation) of all the data held by A / D data flip-flop 801 by the filter coefficients, i.e., one cycle of filter processing, is completed.

[0087] [Switching timing of filter processing by each filter 8] Fig. 10 is a timing chart showing switching of the filter processing state for each detector, and shows the timing at which each filter 8 corresponding to the n detectors 1 shown in Fig. 1 enters the filter processing state A70. At the rising edge of the A / D converter trigger signal S7a shown in Fig. 10, the A / D converter 4 converts the post-selection voltage signal S3 into A / D data S4. The period of the A / D converter trigger signal S7a is the A / D sampling period T1 at which data is sampled in the A / D converter 4.

[0088] Here, a filter 8 is provided for each detector 1. Therefore, the filter processing time T2 in each filter 8 can be made longer than the A / D sampling period T1. Therefore, the first filter processing state A70-1 to the n-th filter processing state A7-n corresponding to the first detector 1-1 to the n-th detector 1-n may overlap with each other in terms of time.

[0089] The A / D sampling period T1 is also the period of the A / D converter trigger signal S7a, which is also a signal that switches the detector 1 to start filter processing. If the repetition period of the filter processing state in the same detector 1 is defined as the filter period T3, the filter processing time T2 should be shorter than the filter period T3.

[0090] 11 is a timing chart showing the operation of the filter control unit 80 in the filter processing state A70 for each detector, and shows the timing of signal input / output between the filter control unit 80 of each filter 8 shown in FIG. 2 and the control unit 7. As shown in FIG. 11, the filter control unit 80 enters the filter processing state A70 when a calculation start signal S7 is input from the control unit 7. The filter control unit 80 enters the latest A / D data calculation state A71 at the beginning of the filter processing state A70, and then enters the pre-calculation state A72.

[0091] The latest A / D data calculation state A71 corresponds to the period from when the calculation start signal S7 "1" is input from the control unit 7 in the initial state A40 described with reference to FIG. 7 to the calculation end signal output state A44. In this latest A / D data calculation state A71, the filter control unit 80 performs only the mth product-sum calculation of the above-mentioned equation (1) and outputs a calculation end signal S8 to the control unit 7. This completes the filter processing for one cycle, including the pre-calculation state A72 for the cycle immediately preceding the current filter processing state A70, and transitions to the pre-calculation state A72. This also allows the FIR filter calculation of another detector 1 to start.

[0092] The pre-calculation state A72 corresponds to the period from the accumulation value flip-flop clear signal output state A45 described with reference to FIG. 7 to the period when the filter coefficient address decrement state A48 determines that pre-filtering is complete and transitions to the initial state A40. In this pre-calculation state A72, the filter control unit 80 performs product-sum calculations of 1 to m-1 of Equation (1) as pre-calculation for the next cycle of FIR filter processing. By performing pre-calculation in this manner, when the m-th data item is acquired in the next filter cycle T3 (see FIG. 10), only the m-th data item needs to be calculated in the latest A / D data calculation state A71. This improves the processing speed of each filter 8. Note that the transition of data stored in the A / D data flip-flop 801 of the filter calculation unit 82 shown in FIG. 9 corresponds to the pre-calculation state A72.

[0093] In the above, the time required for the latest A / D data calculation state A71 is referred to as latest A / D data calculation state time T4, and the time required for the pre-calculation state A72 is referred to as pre-calculation state time T5. In this case, it is sufficient that the latest A / D data calculation state A71 is completed within the A / D sampling period T1. Also, as explained above with reference to FIG. 10, if the filter processing time T2 (see FIG. 10) of the filter processing state A70, which includes the latest A / D data calculation state A71 and the pre-calculation state A72, is equal to or less than the filter period T3 (see FIG. 10), there is no problem in switching the detector 1 that performs the FIR filter calculation even if it exceeds the A / D sampling period T1.

[0094] (4) Filter abnormality detection method Next, we will explain the method for detecting a filter abnormality by the update abnormality confirmation unit 12b, which was explained using Fig. 1. Before explaining the method for detecting a filter abnormality by the update abnormality confirmation unit 12b, we will explain the configuration of an abnormality detection circuit that generates a detection signal for the update abnormality confirmation unit 12b to determine a filter abnormality.

[0095] <Filter abnormality detection circuit> 12 is a diagram showing a circuit for detecting an abnormality in a filter corresponding to each detector. As shown in FIG. 12, the circuit for detecting an abnormality in a filter is provided in the update count value generation unit 10. As described above, the update count value generation unit 10 is made up of a counter that increments in response to a count-up signal S8b from each filter 8, and an independent counter is provided for each filter 8. Such an update count value generation unit 10 includes a rising edge detection unit 100, an update counter flip-flop 101, and a count-up unit 102.

[0096] When the count-up signal S8b input from each filter 8 changes from "0" to "1", the rising edge detection unit 100 sets the rising edge detection signal S100 to "1" and outputs it to the update counter flip-flop 101. The rising edge detection unit 100 outputs the rising edge detection signal S100 "1" when the clock signal S6b having a fixed period is input from the oscillator 6b.

[0097] When the rising edge detection signal is "1", the update counter flip-flop 101 outputs the count-up data S102 as the update count value S10 to the storage unit 9 and the count-up unit 102. The update counter flip-flop 101 outputs the update count value S10 when a clock signal S6b having a fixed period is input from the oscillator 6b.

[0098] The count-up unit 102 adds 1 to the value of the update count value S10 and outputs the result to the update counter flip-flop 101 as count-up data S102.

[0099] With the above circuit configuration, the memory unit 9 holds an updated count value S10 that is counted up based on the count-up signal S8b output from each filter 8. Here, the count-up signal S8b is a signal that is output when FIR filter processing is performed normally in each filter 8, and therefore, the fact that the updated count value S10 has been updated makes it possible to confirm that the filter 8 is performing normal filter processing.

[0100] <Filter abnormality detection method> The update abnormality confirmation unit 12b determines whether the FIR filter processing is being performed normally in each filter 8 based on whether the update count value S10 corresponding to each filter 8 held in the storage unit 9 has been updated. That is, the update abnormality confirmation unit 12b acquires the update count value S10 of each filter 8 from the storage unit 9 via the communication unit 13. If there is a filter 8 whose acquired update count value S10 has not been updated, the update abnormality confirmation unit 12b determines that the FIR filter calculation is not being performed normally in that filter 8 and that the filter 8 is abnormal.

[0101] (Effects of the first embodiment) According to the first embodiment described above, since the filters corresponding to the multiple detectors 1 are provided in a filter processing unit consisting of a single programmable device, the number of components in the plant power monitoring system can be reduced and the system configuration scale can be reduced compared to a configuration in which a filter is provided in each programmable device corresponding to the multiple detectors. Moreover, since the configuration determines whether each detector and filter is abnormal individually, excludes signals from detectors and filters determined to be abnormal, and performs averaging processing based only on signals from the other detectors and filters, it is possible to prevent loss of processing function of the entire system even if some of the detectors and filters fail.

[0102] (Plant output monitoring system according to the second embodiment) Next, a description will be given of a plant power monitoring system according to a second embodiment. The plant power monitoring system according to the second embodiment is an example of a system configuration that is applied when the filter processing time T2 (see FIG. 10) by the filter 8 described in the first embodiment is shorter than the A / D sampling period T1.

[0103] Fig. 13 is a timing chart showing another example of switching of the filter processing state for each detector, and corresponds to the timing chart of Fig. 10 described in the first embodiment. The timing chart shown in Fig. 13 differs from the timing chart shown in Fig. 10 in that the filter processing time T2 by the filter 8 is short, shorter than the A / D sampling period T1. In this case, the filters 8 corresponding to the multiple detectors 1 do not simultaneously perform FIR filter processing. For this reason, the plant power monitoring system can be configured as in the second embodiment, as follows.

[0104] Fig. 14 is a block diagram of a plant power monitoring system according to the second embodiment. The plant power monitoring system of the second embodiment shown in Fig. 14 differs from the plant power monitoring system of the first embodiment shown in Fig. 1 in that a filter coefficient storage unit 805' common to all filters 8 is provided in the filter processing unit 5.

[0105] That is, in the first embodiment, the filter coefficient storage unit 805 (see FIG. 8) provided in the filter calculation unit 82 of each filter 8 is provided in only one filter processing unit 5' in the second embodiment, and the filter coefficient storage unit 805' is shared by a plurality of filters 8. Note that, similar to the first embodiment, the filter coefficient storage unit 805' stores the filter coefficient An shown in the above equation (1).

[0106] In this case, a filter coefficient table selection signal S6a for switching the frequency band to be processed by the filter 8 is input from the switching unit 6a to the filter coefficient storage unit 805'. A filter coefficient address signal S80e is also input to the filter coefficient storage unit 805' from each filter 8. The filter coefficient storage unit 805 outputs a filter coefficient signal S805 corresponding to the filter coefficient address signal S80e input from each filter 8 to each filter 8.

[0107] Fig. 15 is a block diagram of the filter 8 included in the filter processing unit 5 of the second embodiment. The filter 8 shown in Fig. 15 is configured with a filter control unit 80, an A / D data correction processing unit 81, and a filter calculation unit 82', which is the same as the configuration of the first embodiment described using Fig. 2. However, the signals input to and output from each unit differ as follows.

[0108] The filter control unit 80 generates various signals similar to those described in the first embodiment based on the calculation start signal S7 input from the control unit 7. However, among the various signals generated, the filter coefficient address signal S80e is output to one filter coefficient storage unit 805′ shared by each filter 8′.

[0109] The A / D data correction processing unit 81 performs offset addition and gain multiplication on the A / D data S4 input from the A / D conversion unit 4, and outputs corrected A / D data S81 to the filter calculation unit 82′, as in the first embodiment.

[0110] Similar to the first embodiment, the filter calculation unit 82' performs filtering on corrected A / D data S81 input from the A / D data correction processing unit 81, and performs filtering based on various signals input from the filter control unit 80. At this time, the filter calculation unit 82' performs filtering based on a filter coefficient signal S805 input from a filter coefficient storage unit 805'. Note that, similar to the first embodiment, the filter calculation unit 82 outputs filter operation data S8a obtained by filtering to the storage unit 9.

[0111] <Filtering by Filter Calculation Unit 82'> Next, the filtering process performed by the filter calculation unit 82' will be described. Prior to the description of the filtering process, the configuration of the filter calculation unit 82 will be described.

[0112] <Configuration of filter calculation unit 82> Fig. 16 is a circuit diagram of a filter calculation unit 82' included in the filter of the second embodiment. The filter calculation unit 82 shown in Fig. 16 includes an input selection unit 800, a plurality of A / D data flip-flops 801, a multiplier 803, an adder 804, and an integrated value flip-flop 802, and differs from the first embodiment in that it does not include a filter coefficient storage unit 805'.

[0113] As a result, the multiplier 803 is configured to receive a filter coefficient signal S805 from a filter coefficient storage unit 805' external to the filter calculation unit 82'.

[0114] The filter processing by the filter 8 having the filter calculation unit 82' as described above is performed in the same manner as in the first embodiment.

[0115] (Effects of the second embodiment) According to the second embodiment described above, in addition to the effects of the first embodiment, it is possible to reduce the logic scale by sharing the filter coefficient storage unit 805' among a plurality of filters 8.

[0116] The present invention is not limited to the above-described embodiments and modifications, and includes various other modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0117] 1...Detector 2...I / V conversion section 3...Signal selection section 4...A / D conversion section 5,5'...Filter processing section 6a...Switching section 6b...Oscillator 7...Control unit 8,8'...filter 9…Storage section 10...Update count value generator 11...Signal processing unit 12...Average calculation device 12a...average calculation processing unit 12b…Update abnormality confirmation section 12c...Detector abnormality determination section 13…Communications Department 70...Inverter 71...State transition section 72...A / D conversion trigger signal generation unit 73...Falling edge detector 74...A / D conversion unit abnormality detection unit 80...Filter control section 81...A / D data correction processing section 82, 82'...Filter calculation section 90...A / D conversion unit abnormality judgment memory unit 100...Rising edge detector 101...Update counter flip-flop 102...Count-up section 800...Input selection section 801...A / D data flip-flop 802...accumulator flip-flop 803...Multiplier 804...adder 805, 805'...Filter coefficient storage section S1: Detector current signal S10: Update count value S100: Rising edge detection signal S102…Count-up data S2: Voltage signal S3: Post-selection voltage signal S4...A / D data S4a...A / D converter busy signal S6a...Filter coefficient table selection signal S6b: Clock signal S7…Computation start signal S70…A / D conversion completion signal S73: A / D converter trigger signal falling edge detection signal S74: A / D converter abnormality detection result signal S7a...A / D converter trigger signal S7b...Signal selection section control signal S7c...A / D converter abnormal signal S8: Calculation end signal S800...A / D data flip-flop input signal S801...A / D data flip-flop output signal S803...Multiplication value S804…Additional value S805...Filter coefficient signal S80a...Mode selection signal S80b...A / D data flip-flop shift signal S80c: Accumulation value flip-flop latch signal S80d: Accumulation value flip-flop clear signal S80e...Filter coefficient address signal S81...A / D data after correction S8a...Filter calculation data S8b: Count-up signal T1: A / D sampling period T2: Filter processing time T3: Filter period T4: Latest A / D data calculation state time T5…Precalculation state time

Claims

1. a signal processing unit to which signals from a plurality of detectors that detect radiation are input; an average calculation device that calculates the processing result from the signal processing unit, The signal processing unit a signal selection unit that sequentially selects and outputs each of the signals output from the plurality of detectors; a filter processing unit that filters the signal output from the signal selection unit and outputs the filtered signal to the average calculation device, The filter processing unit It is composed of a programmable gate array, a plurality of filters provided corresponding to the plurality of detectors; a control unit for sequentially inputting the signals sequentially selected and output by the signal selection unit to each of the filters. Plant output monitoring system.

2. Each of the filters individually performs FIR filtering on the signals based on each of the detectors that are sequentially output by the signal selection unit. The plant output monitoring system according to claim 1 .

3. Each of the filters performs a filtering process in advance on the signals whose number is one less than the number of filter coefficients, and completes the filtering process for one period when the next signal is input from the signal selection unit. The plant output monitoring system according to claim 2 .

4. the control unit outputs a signal selection unit control signal to the signal selection unit to select a next signal upon receiving a calculation completion signal from each of the filters; The signal selection unit selects and outputs a next signal from among the signals output from the plurality of detectors in response to the input of the signal selection unit control signal. The plant output monitoring system according to claim 1 .

5. the signal processing unit includes an updated count value generating unit that updates a counter value corresponding to each of the plurality of filters each time a filter process is completed in the respective filters; The average calculation device includes an update abnormality confirmation unit that individually determines an abnormality in each of the filters based on the counter value generated by the update count value generation unit. The plant output monitoring system according to claim 1 .

6. The average calculation device includes an average calculation processing unit that excludes signals from a filter determined to be abnormal by the update abnormality checking unit among the plurality of filters and performs average calculation processing based on signals from the other filters. The plant output monitoring system according to claim 5 .

7. Each of the filters has a filter coefficient storage unit that stores filter coefficients used in the filter processing. The plant output monitoring system according to claim 1 .

8. the filtering processing unit has a filter coefficient storage unit that stores filter coefficients used in the filtering process, The filter coefficient storage unit outputs, to each filter, a filter coefficient corresponding to a filter coefficient address signal output from each filter. The plant output monitoring system according to claim 1 .

9. an I / V conversion unit that converts each signal output from the plurality of detectors into a voltage and outputs the voltage to the signal selection unit; an A / D conversion unit that performs digital conversion on the signals sequentially output from the signal selection unit and outputs the converted signals to the filter processing unit, The control unit an A / D conversion trigger signal generation unit that generates an A / D conversion unit trigger signal at a constant period; an A / D conversion unit abnormality determination unit that determines an abnormality in the A / D conversion unit based on the A / D conversion unit trigger signal output by the A / D conversion trigger signal generation unit and an A / D conversion unit busy signal output by the A / D conversion unit while the A / D conversion unit is performing A / D conversion; The plant output monitoring system according to claim 1 .

10. The signal processing unit a storage unit that, when the AD conversion unit abnormality determination unit determines that the A / D conversion unit is abnormal, continues to hold the determination result and outputs it to an average calculation device; The plant output monitoring system according to claim 9.

11. The average calculation device has a detector abnormality determination unit that individually determines abnormality of each of the detectors corresponding to each of the filters based on the signal from each of the filters. The plant output monitoring system according to claim 1 .

12. The average calculation device has an average calculation processing unit that excludes signals from detectors that are determined to be abnormal by the detector abnormality determination unit among the plurality of detectors and performs average calculation processing based on signals from the remaining detectors. The plant power monitoring system according to claim 11.

13. A plant power monitoring method using a plant power monitoring system comprising: a signal processing unit to which signals from a plurality of detectors that detect radiation are input; and an averaging unit that calculates a processing result from the signal processing unit, wherein the signal processing unit comprises a signal selection unit that sequentially selects and outputs each of the signals output from the plurality of detectors; and a filtering unit that filters the signal output from the signal selection unit and outputs the filtered signal to the averaging unit, and wherein the filtering unit is configured by a programmable gate array, A control unit of the filter processing unit sequentially inputs the signals selected and output by the signal selection unit to a plurality of filters provided corresponding to the plurality of detectors. Plant power monitoring method.

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