Display device

Abstract

To provide a display device capable of allowing higher speed driving.SOLUTION: A display device comprises: a first transistor whose switching is controlled by a first control signal and which is connected to a first node; a second transistor which includes a gate electrode connected to a second node and is connected to a third node; a third transistor whose switching is controlled by a second control signal, and which is connected to the first node and the second node; a fourth transistor whose switching is controlled by a third control signal and which is connected to the second node; a fifth transistor whose switching is controlled by a fourth control signal, and which is connected to the third node; a sixth transistor whose switching is controlled by the third control signal, and which is connected to a fourth node; a first capacitive element connected between the first node and the fourth node; a second capacitive element connected between the third node and the fourth node; and a light-emitting element connected to the second transistor.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices including light-emitting elements have become widespread and are implemented in televisions, smartphones, and the like. For example, a display device includes a plurality of pixels and a control circuit for driving the plurality of pixels. Each of the plurality of pixels includes a plurality of transistors, a capacitance element, and a light-emitting element. The light-emitting element is an element that emits light in a self-luminous manner, such as a light-emitting diode (LED), a micro-light-emitting diode (micro LED), or an organic electroluminescence (EL) element. In a display device, a control circuit supplies a voltage to each of the plurality of pixels, causing a current corresponding to the supplied voltage value to flow through the light-emitting element included in each of the plurality of pixels. Each light-emitting element emits light at a brightness corresponding to the current flowing through the light-emitting element, and the pixel including the light-emitting element can display an image with a gradation corresponding to the brightness.

[0003] For example, Patent Document 1 discloses an organic light-emitting diode display device that drives a light-emitting element. The display device described in Patent Document 1 detects the threshold voltage of a drive transistor included in a pixel and includes a program period in which a voltage corresponding to a data voltage compensated for the threshold voltage is stored in a storage capacitor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-242767 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, if a display device stores a voltage corresponding to a threshold voltage-compensated data voltage in a storage capacitor, both the threshold voltage compensation and the writing of the data voltage are performed within the program period, which may slow down the writing of the data voltage.

[0006] In view of the above problems, one object of an embodiment of the present invention is to provide a display device that can be driven at high speed. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes a first transistor whose switching is controlled by a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a second transistor having a gate electrode electrically connected to a second node and electrically connected between a power supply line to which a first constant voltage is supplied and a third node; a third transistor whose switching is controlled by a second control signal different from the first control signal and electrically connected between the first node and the second node; and a third transistor whose switching is controlled by a third control signal different from the first control signal and the second control signal and electrically connected to the second node and a fourth transistor for supplying a reference voltage; a fifth transistor whose switching is controlled by a fourth control signal different from the first control signal, the second control signal, and the third control signal, and electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node; a sixth transistor whose switching is controlled by the third control signal, electrically connected to the fourth node, and for supplying the reference voltage to the fourth node; a first capacitance element electrically connected between the first node and the fourth node; a second capacitance element electrically connected between the third node and the fourth node; and a light-emitting element electrically connected to the second transistor.

[0008] A display device according to one embodiment of the present invention includes a first transistor whose switching is controlled by a first control signal and electrically connected between a first node and an image data signal line to which a data voltage is supplied; a second transistor having a gate electrode electrically connected to a second node and electrically connected between a third node and a fourth node; a third transistor whose switching is controlled by a second control signal different from the first control signal and electrically connected between the first node and a reference voltage power line to which a reference voltage is supplied; a fourth transistor whose switching is controlled by the second control signal and electrically connected between the second node and the fourth node; and a reset transistor whose switching is controlled by a third control signal different from the first control signal and the second control signal. a fifth transistor electrically connected between a set voltage power supply line and the fourth node; a sixth transistor whose switching is controlled using a fourth control signal different from the first control signal, the second control signal, and the third control signal, and electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node; a seventh transistor whose switching is controlled using a fifth control signal different from the first control signal, the second control signal, the third control signal, and the fourth control signal, and electrically connected between a power supply line to which a constant voltage is supplied and the fourth node; a first capacitance element electrically connected between the first node and the second node; a second capacitance element electrically connected between the first node and the third node; and a light-emitting element electrically connected to the third node.

[0009] A display device according to one embodiment of the present invention includes a first transistor whose switching is controlled by a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a third node; a second transistor having a gate electrode electrically connected to a second node and electrically connected between the third node and a fourth node; a third transistor whose switching is controlled by a second control signal different from the first control signal and electrically connected between the second node and the fourth node; a fourth transistor whose switching is controlled by the second control signal and electrically connected between the third node and a reference voltage power supply line to which a reference voltage that also serves as an initialization voltage is supplied; and a fifth transistor whose switching is controlled by a third control signal different from the first control signal and the second control signal and electrically connected between the fourth node and a fifth node. a sixth transistor whose switching is controlled by a fourth control signal different from the first control signal, the second control signal, and the third control signal and electrically connected between the reference voltage power supply line and the first node; a seventh transistor whose switching is controlled by a fifth control signal different from the first control signal, the second control signal, the third control signal, and the fourth control signal and electrically connected between a reference voltage line to which a reference voltage is supplied and the third node; an eighth transistor whose switching is controlled by the fourth control signal and electrically connected between a power supply line to which a constant voltage is supplied and the fifth node; a first capacitance element electrically connected between the first node and the second node; a second capacitance element electrically connected between the first node and the third node; and a light-emitting element electrically connected between the power supply line and the fifth node. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram illustrating a configuration of a display device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram showing input signals to a pixel circuit according to the first embodiment of the present invention. [Figure 3] 1 is a circuit diagram showing a configuration of a pixel circuit according to a first embodiment of the present invention. [Figure 4] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 5] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 6] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 7] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 8] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 9] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 10] FIG. 10 is an end view showing an end surface cut along A1-A2 in the layout shown in FIG. 9. [Figure 11] FIG. 10 is an end view showing an end surface cut along B1-B2 in the layout shown in FIG. 9. [Figure 12] FIG. 10 is an end view showing an end surface cut along C1-C2 in the layout shown in FIG. 9. [Figure 13] FIG. 3 is a sequence diagram showing a manufacturing method of the display device according to the first embodiment of the present invention. [Figure 14] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 15] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 16] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 17] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a second embodiment of the present invention. [Figure 18] FIG. 4 is a circuit diagram showing a configuration of a pixel circuit according to a second embodiment of the present invention. [Figure 19] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a third embodiment of the present invention. [Figure 20]FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a third embodiment of the present invention. [Figure 21] 10 is a timing chart of a pixel circuit according to a third embodiment of the present invention. [Figure 22] 10 is a timing chart of a pixel circuit according to a third embodiment of the present invention. [Figure 23] 10 is a timing chart of a pixel circuit according to a third embodiment of the present invention. [Figure 24] 10 is a timing chart of a pixel circuit according to a third embodiment of the present invention. [Figure 25] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a fourth embodiment of the present invention. [Figure 26] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a fourth embodiment of the present invention. [Figure 27] FIG. 11 is a schematic diagram showing input signals to a pixel circuit according to a fifth embodiment of the present invention. [Figure 28] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a fifth embodiment of the present invention. [Figure 29] FIG. 13 is a schematic diagram showing input signals to a pixel circuit according to a sixth embodiment of the present invention. [Figure 30] FIG. 10 is a circuit diagram showing the configuration of a pixel circuit according to a sixth embodiment of the present invention. [Figure 31] FIG. 12 is a schematic diagram showing the configuration of a display device according to a seventh embodiment of the present invention. [Figure 32] 13 is a timing chart of a display device according to a seventh embodiment of the present invention. [Figure 33] FIG. 13 is a schematic diagram showing input signals to a pixel circuit according to a seventh embodiment of the present invention. [Figure 34] FIG. 12 is a circuit diagram showing a configuration of a pixel circuit according to a seventh embodiment of the present invention. [Figure 35] 13 is a timing chart of a display device according to a seventh embodiment of the present invention. [Figure 36] 13 is a timing chart of a display device according to a seventh embodiment of the present invention. [Figure 37]FIG. 13 is a schematic diagram showing input signals to a pixel circuit according to an eighth embodiment of the present invention. [Figure 38] FIG. 13 is a circuit diagram showing a configuration of a pixel circuit according to an eighth embodiment of the present invention. [Figure 39] 13 is a timing chart of a pixel circuit according to an eighth embodiment of the present invention. [Figure 40] 13 is a timing chart of a pixel circuit according to an eighth embodiment of the present invention. [Figure 41] 13 is a timing chart of a pixel circuit according to an eighth embodiment of the present invention. [Figure 42] 13 is a timing chart of a pixel circuit according to an eighth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, configuration, etc. of each part schematically compared to the actual form, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element, and have no other meaning unless otherwise specified.

[0012] Furthermore, in this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] For example, a display device according to one embodiment of the present invention is a display device that uses EL elements as self-luminous light-emitting elements. For example, a display device that uses EL elements may be called a self-luminous display device, an EL display device, or the like.

[0014] 1. First Embodiment <1-1. Overview of the display device 10> An overview of a display device 10 according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing the configuration of the display device 10. The configuration of the display device 10 shown in Fig. 1 is an example, and the configuration of the display device 10 is not limited to the configuration shown in Fig. 1.

[0015] The display device 10 includes an array substrate 100, a flexible printed circuit board 200 (FPC 200), and an IC chip 110. The display device 10 also includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0016] In the display region 22, a plurality of pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. The pixel 180 is the smallest unit that constitutes part of an image displayed in the display region 22. For example, each of the plurality of pixels 180 may correspond to a sub-pixel R, a sub-pixel G, and a sub-pixel B. One pixel may also be formed by three sub-pixels. There are no limitations on the arrangement of the pixels 180, and the arrangement of the plurality of pixels 180 may be, for example, a stripe arrangement. The arrangement of the display device 10 may be a delta arrangement, a pentile arrangement, or the like.

[0017] The subpixels R, G, and B are configured to display images of different colors. For example, each of the subpixels R, G, and B includes a light-emitting element including a light-emitting layer that emits red, green, and blue, respectively. When any voltage or current is supplied to each of the three subpixels, the display device 10 can display an image.

[0018] The peripheral region 24 is provided with an IC chip 110 and two control circuits 120. The two control circuits 120 are provided on the left and right sides of the display region 22. The IC chip 110 is connected to the terminal portion 150 using a connection wiring 341. Each of the two control circuits 120 is connected to the IC chip 110 using a connection wiring 342. The peripheral region 24 is sometimes referred to as a frame region. The connection wiring 341 may be referred to individually as the connection wiring 341, and a bundle of multiple connection wirings 341 may be referred to as the connection wiring 341. Like the connection wiring 341, the connection wiring 342 may be referred to individually as the connection wiring 342, and a bundle of multiple connection wirings 342 may be referred to as the connection wiring 342.

[0019] The terminal region 26 is provided with the terminal portion 150 and the FPC 200 electrically connected to the terminal portion 150. The terminal region 26 is on the opposite side of the peripheral region 24 in the first direction D1 from the region in which the display region 22 is provided.

[0020] The FPC 200 is connected to an external device (not shown) outside the display device 10. The display device 10 is connected to the external device via the FPC 200 and a terminal unit 150 connected to the FPC. Control signals and voltages are transmitted from the external device to the display device 10 via the FPC 200 and the terminal unit 150 connected to the FPC. The display device 10 drives each pixel 180 provided on the display device 10 using the control signals and voltages received from the external device. As a result, the display device 10 can display an image in the display area 22.

[0021] The IC chip 110 supplies signals, voltages, and the like for driving each pixel 180 to the two control circuits 120 and each pixel 180 (pixel circuit 181) via the FPC 200, the terminal section 150, and the connection wiring 341.

[0022] In this specification and drawings, IC chip 110, each of the two control circuits 120, and each of IC chip 110 may be referred to individually as a control circuit, and a group of circuits including IC chip 110, each of the two control circuits 120, and part or all of IC chip 110 may be referred to as a control circuit.

[0023] <1-2. Configuration of IC chip 110> 1, an overview of the IC chip 110 will be described. The IC chip 110 is provided at a position adjacent to the display area 22 in the first direction D1. Image data signal lines 321, 322, and 323 extend from the IC chip 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0024] For example, the IC chip 110 includes a plurality of selection circuits (not shown). For example, each of the plurality of selection circuits is a switch controlled based on an on signal and an off signal supplied to a selection signal. The selection circuit is selected by an on signal supplied to the selection signal, and supplies an image data signal SL(m) including a data signal VDATA to the image data signal line 321 and the pixel 180 electrically connected to the image data signal line 321. The selection signal and the image data signal SL(m) are transmitted from an external device to the IC chip 110 via the FPC 200 and the terminal unit 150 connected to the FPC. For example, the data signal VDATA (image data signal SL(m)) includes a data voltage equal to or greater than a voltage VSIGL (see FIG. 5) and equal to or less than a voltage VSIGH (see FIG. 5).

[0025] For example, an on signal is a signal including a voltage that turns on a selection circuit (switch), and an off signal is a signal including a voltage that turns off the selection circuit (switch). In the present invention, the on signal may be a high-level voltage (potential) (high, High, HI) and the off signal may be a low-level voltage (potential) (low, Low, LO), or the on signal may be a low-level voltage (potential) (low, Low, LO) and the off signal may be a high-level voltage (potential) (high, High, HI). A high-level voltage is greater (higher) than a low-level voltage. In addition, in a display device according to one embodiment of this specification, as an example, the on signal is a high-level voltage and the off signal is a low-level voltage.

[0026] <1-3. Configuration of Control Circuit 120> An overview of the control circuit 120 will be described with reference to FIG. 1. Two control circuits 120 are provided adjacent to each other on both sides of the display area 22 in the second direction D2 of the display area 22. Scan signal lines 330, 331, 332, and 333 extend from the control circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. As an example, each scan signal line of the display device 10 shown in FIG. 1 is connected to both of the two control circuits 120. Each scan signal line may be connected to one of the control circuits 120. That is, the nth scan signal line may be electrically connected to the control circuit 120 on the right side of the display area 22 in the second direction D2, and the (n+1)th scan signal line may be electrically connected to the control circuit 120 on the left side of the display area 22 in the second direction D2. The number n is a positive integer.

[0027] The control circuit 120 includes a shift register circuit 130 and a scan driver circuit 160. For example, the control circuit 120 is a gate driver, and receives control signals including a clock signal, a start pulse, and a plurality of enable signals, as well as voltages such as a drive voltage VDDEL (see FIG. 2) and a reference voltage VSSEL (see FIG. 2). The control circuit 120 can sequentially select scan lines based on the input of the control signals and power supply.

[0028] The shift register circuit 130 is electrically connected to the scan driver circuit 160. The shift register circuit 130 includes a plurality of shift registers (not shown). The shift register circuit 130 is also supplied with the above-mentioned control signals via a plurality of connection wirings 342, a drive voltage VDDEL via a drive power supply line PVDD (see FIG. 2), and a reference voltage VSSEL via a reference voltage line PVSS (see FIG. 2). The shift register circuit 130 has a role of generating a plurality of output signals (not shown) shifted at different timings based on the above-mentioned control signals, and sequentially outputting the output signals to the scan driver circuit 160.

[0029] The scan driver circuit 160 includes multiple scan drivers. For example, the multiple scan drivers receive multiple output signals from the shift register circuit 130, the multiple enable signals from the IC chip 110 via multiple connection lines 342, the drive voltage VDDEL via a drive power supply line PVDD, and the reference voltage VSSEL via a reference voltage line PVSS. Based on the multiple output signals and the multiple enable signals, the multiple scan drivers sequentially supply scan signals (e.g., a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), and a fourth scan signal SC4(n)) with different timings to each scan signal line, and drive the pixels 180 (pixel circuits 181) electrically connected to each scan signal line. For example, the fourth scan signal SC4(n) and the scan signal line 333 to which the fourth scan signal SC4(n) is supplied are so-called scan signals and scan signal lines.

[0030] <1-4. Configuration of pixel 180> An overview of the pixel 180 and the pixel circuit 181 will be described with reference to FIGS. 1 to 3. FIG. 2 is a schematic diagram showing input signals to the pixel circuit 181 included in the pixel 180. FIG. 3 is a circuit diagram showing the configuration of the pixel circuit 181. FIGS. 2 and 3 show, as an example, the configuration of the pixel circuit 181 of the pixel 180 shown in FIG. 1. The configurations of the pixel 180 and the pixel circuit 181 are not limited to those shown in FIGS. 1 to 3. Configurations that are the same as or similar to those in FIG. 1 will be described as necessary.

[0031] The pixel circuit 181 is a circuit for driving the pixel 180. The pixel circuits of the sub-pixels R, G, and B included in the pixel 180 are similar to the pixel circuit 181, but the colors emitted by the light-emitting element OLED are different. In the following description, a light-emitting element OLED that emits red light will be described as an example.

[0032] 2, the pixel circuit 181 is supplied with an image data signal SL(m), a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a reference voltage VREF, and an initialization voltage VINI. Furthermore, the pixel circuit 181 is supplied with a driving voltage VDDEL and a reference voltage VSSEL as power supplies for driving the pixel 180. For example, the reference voltage VREF, the initialization voltage VINI, the driving voltage VDDEL, and the reference voltage VSSEL may be constant voltages, or may be variable voltages that fluctuate according to the timing of each signal.

[0033] The reference voltage VREF is supplied to the reference voltage power line SVR, the initialization voltage VINI is supplied to the initialization voltage power line SVI, the drive voltage VDDEL is supplied to the drive power line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS. For example, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the reference voltage line PVSS are each electrically connected to a different connection wiring 342. Also, for example, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the reference voltage line PVSS may each be a different connection wiring 342.

[0034] For example, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from an external device to the IC chip 110 via the FPC 200, the terminal unit 150, and the connection wiring 341. Also, for example, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from the IC chip 110 to the plurality of pixels 180 (pixel circuits 181) via the connection wiring 342, the precharge voltage power line SVP, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the reference voltage line PVSS. Although not shown, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the standard voltage VSSEL may be connected to the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the standard voltage line PVSS from an external device via the FPC 200, the terminal unit 150, and the connection wiring 341, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to the plurality of pixels 180 (pixel circuits 181). For example, the reference voltage VREF, the initialization voltage VINI, and the standard voltage VSSEL are smaller than the drive voltage VDDEL.

[0035] 3, the pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitance element CD, a capacitance element CV, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (a source electrode and a drain electrode) consisting of a first electrode and a second electrode. Each of the capacitance elements CD, CV, and the light-emitting element OLED includes a pair of electrodes consisting of a first electrode and a second electrode.

[0036] For example, the first transistor T1 is a selection transistor. The first transistor T1 has a function of supplying an image data signal SL(m) to the first node N1.

[0037] For example, the second transistor T2 is a drive transistor. A gate voltage in which variations in the threshold voltage VTH are corrected based on a reference voltage VREF and an initialization voltage VINI is applied between the gate electrode 622 and the first electrode (source) 624 of the second transistor T2. Furthermore, the second transistor T2 controls the amount of current flowing from the drive power supply line PVDD to the light-emitting element OLED based on the gate voltage in which variations in the threshold voltage VTH are corrected (the voltage between the gate electrode 622 and the first electrode (source) 624) and the input image data signal SL(m). In other words, the second transistor T2 has the function of supplying a drive voltage VDDEL to the light-emitting element OLED and causing a current to flow therethrough, causing the light-emitting element OLED to emit light.

[0038] The third transistor T3 has a function of connecting the first node N1 and the second node N2 and supplying the image data signal SL(m) to the second node N2.

[0039] The fourth transistor T4 has a function of connecting the second node N2 and the reference voltage power supply line SVR to each other, supplying the reference voltage VREF to the second node N2, and initializing the second node N2.

[0040] The fifth transistor T5 has a function of connecting the third node N3 and the initialization voltage power supply line SVI to each other, supplying the initialization voltage VINI to the third node N3, and initializing the third node N3.

[0041] The sixth transistor T6 has a function of connecting the fourth node N4 and the reference voltage power supply line SVR to supply the reference voltage VREF to the fourth node N4 and initializing the fourth node N4.

[0042] Although the details will be described later, the capacitance element CV has a function of holding (storing) a charge equivalent to the threshold voltage VTH of the second transistor T2.

[0043] The capacitance element CD has the function of holding (storing) a charge equivalent to a data voltage (a voltage equal to or greater than voltage VSIGL (see Figure 5) and equal to or less than voltage VSIGH (see Figure 5)) included in the image data signal SL(m) supplied to the first node N1.

[0044] The light-emitting element OLED has diode characteristics and emits light based on the current flowing through the light-emitting element OLED (that is, the drain current Ion of the second transistor T2).

[0045] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 333. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 634 of the third transistor T3, and the second electrode 54 of the capacitance element CD. As described above, a fourth scan signal SC4(n) is supplied to the scan signal line 333. The switching of the first transistor T1 is controlled using the fourth scan signal SC4(n). In other words, the conductive state (ON state) and non-conductive state (OFF state) of the first transistor T1 are controlled by the fourth scan signal SC4(n). When the signal supplied to the fourth scan signal SC4(n) is LO, the first transistor T1 is in a non-conductive state. When the signal supplied to the fourth scan signal SC4(n) is HI, the first transistor T1 is in a conductive state.

[0046] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the second node N2, the second electrode 636 of the third transistor T3, and the second electrode 646 of the fourth transistor T4. The first electrode 624 is electrically connected to the third node N3, the second electrode 656 of the fifth transistor T5, the first electrode 42 of the capacitor CV, and the second electrode 34 of the light-emitting element OLED. The second electrode 626 is electrically connected to the driving power supply line PVDD. The threshold voltage of the second transistor T2 is a threshold voltage VTH. The conductive state (ON state) and non-conductive state (OFF state) of the second transistor T2 are controlled according to the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624, the potential difference between the second electrode 626 and the first electrode 624, and the threshold voltage VTH. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624 is smaller than the threshold voltage VTH and the potential difference between the second electrode 626 and the first electrode 624 is equal to or smaller than 0 V, the second transistor T2 is in a non-conductive state. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624 is equal to or larger than the threshold voltage VTH and the potential difference between the second electrode 626 and the first electrode 624 is larger than 0 V, the second transistor T2 is in a conductive state.

[0047] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scan signal line 330. As described above, the first scan signal SC1(n) is supplied to the scan signal line 330. The switching of the third transistor T3 is controlled using the first scan signal SC1(n). In other words, the conductive state (on state) and non-conductive state (off state) of the third transistor T3 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is HI, the third transistor T3 is in the conductive state. When the signal supplied to the first scan signal SC1(n) is LO, the third transistor T3 is in the non-conductive state.

[0048] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 331. As described above, the second scan signal SC2(n) is supplied to the scan signal line 331. The first electrode 644 is electrically connected to the first electrode 664 of the sixth transistor T6 and the reference voltage power supply line SVR. The reference voltage power supply line SVR is supplied with a reference voltage VREF. The switching of the fourth transistor T4 is controlled using the second scan signal SC2(n). In other words, the conductive state (on state) and non-conductive state (off state) of the fourth transistor T4 are controlled by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the fourth transistor T4 is in a non-conductive state, and when the signal supplied to the scan signal line 330 is HI, the fourth transistor T4 is in a conductive state.

[0049] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 332. The first electrode 654 is electrically connected to the initialization voltage power supply line SVI. A third scan signal SC3(n) is supplied to the scan signal line 332. The switching of the fifth transistor T5 is controlled using the third scan signal SC3(n). In other words, the fifth transistor T5 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the fifth transistor T5 is in a non-conductive state, and when the signal supplied to the third scan signal SC3(n) is HI, the fifth transistor T5 is in a conductive state.

[0050] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 331. The first electrode 664 is electrically connected to the reference voltage power supply line SVR. The second electrode 666 is electrically connected to the fourth node N4, the first electrode 52 of the capacitance element CD, and the second electrode 44 of the capacitance element CV. A second scan signal SC2(n) is supplied to the scan signal line 331. The switching of the sixth transistor T6 is controlled using the second scan signal SC2(n). In other words, the sixth transistor T6 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the sixth transistor T6 is in a non-conductive state, and when the signal supplied to the second scan signal SC2(n) is HI, the sixth transistor T6 is in a conductive state.

[0051] The first electrode 32 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 32 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 34 of the light-emitting element OLED is, for example, an anode electrode.

[0052] For example, the conductive state of a transistor in the display device 10 means that the source electrode and drain electrode of the transistor are conductive and the transistor is in an on (ON) state, and the non-conductive state of a transistor in the display device 10 means that the source electrode and drain electrode of the transistor are non-conductive and the transistor is in an off (OFF) state. Note that in each transistor, the source electrode and drain electrode may be interchanged depending on the voltage or potential supplied to each electrode. Furthermore, it is easily understood by those skilled in the art that even when a transistor is in an off state, a small amount of current, such as leakage current, still flows.

[0053] Each transistor shown in FIG. 3 is an n-channel field-effect transistor, and its channel region contains a Group 14 element such as silicon or germanium, or an oxide exhibiting semiconducting properties. For example, crystalline silicon can be used as the channel region containing a Group 14 element. The crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon. Furthermore, for example, a metal oxide having semiconducting properties can be used as the oxide exhibiting semiconducting properties. As an example, the metal oxide having semiconducting properties is an oxide semiconductor containing two or more metals including indium (In). The metal oxide having semiconducting properties may be gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanide, in addition to indium. Furthermore, the metal oxide having semiconducting properties may be amorphous, crystalline, or a mixed phase of amorphous and crystalline.

[0054] For example, each transistor in the display device 10 is formed using a thin film transistor (TFT). The channel region of each transistor may be formed using single crystal silicon, such as a silicon wafer or an SOI substrate. Furthermore, when the display device 10 includes both a transistor containing a Group 14 element in its channel region and a transistor containing an oxide exhibiting semiconducting properties in its channel region, the manufacturing method for the display device 10 includes forming a semiconductor layer containing a Group 14 element and forming a semiconductor layer containing an oxide exhibiting semiconducting properties (e.g., an oxide semiconductor layer). The transistor configuration, storage capacitor connection, power supply voltage, etc. of the display device 10 may be appropriately adapted depending on the application and specifications.

[0055] For example, the leakage current of a transistor having a metal oxide with semiconducting properties is extremely small. Therefore, when a transistor having a metal oxide with semiconducting properties is used, the charge corresponding to the voltage (potential) written to a capacitor element is unlikely to escape from the capacitor element. As a result, the use of a transistor having a metal oxide with semiconducting properties enables the charge written to the capacitor element to be retained for a long period of time. Furthermore, under the same conditions of gate-source voltage (potential difference between the gate electrode and the source electrode (Vgs)) and source-drain voltage (e.g., potential difference between the source electrode and the drain electrode (Vds)), the drain current of a transistor having a metal oxide with semiconducting properties may be larger than the drain current of a transistor having crystalline silicon (e.g., low-temperature polysilicon (LTPS)). As a result, under the same conditions of drain current, the gate-source voltage and source-drain voltage of a transistor having a metal oxide with semiconducting properties can be smaller than those of a transistor having crystalline silicon. Therefore, the use of a transistor having a metal oxide with semiconducting properties can reduce the power consumption of the display device 10.

[0056] <1-5. Driving method of the display device 10> A method for driving the display device 10 will be described with reference to Figures 4 to 8. Figures 4 to 8 are schematic diagrams showing timing charts of the display device 10. Configurations that are the same as or similar to those in Figures 1 to 3 will be explained as necessary.

[0057] Note that the horizontal axis of the timing chart in each embodiment represents time (TIME). Furthermore, in the image data signal SL(m) including the data signal VDATA in each embodiment, as an example, the data signal VDATA supplied to a selected pixel (pixel circuit) is indicated by diagonal lines as a data voltage between voltages VSIGL and VSIGH, and the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is omitted and indicated by solid lines. In reality, in the image data signal SL(m) including the data signal VDATA in each embodiment, the voltage of the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is also supplied continuously or intermittently.

[0058] For example, the display device 10 is driven at a frequency of 60 Hz, and one frame (1 FRAME) is driven at 60 Hz. For example, FIG. 4 shows the current frame (Kth FRAME), a portion of the frame immediately before the current frame (K-1st FRAME), and a portion of the frame immediately after the current frame (K+1st FRAME). Also, FIGS. 5 to 8 show the light emission period PEM of the frame immediately before the current frame (K-1st FRAME), and the periods PIN, PWR, and PVH of the current frame (Kth FRAME). Also, FIGS. 5 to 8 show one horizontal period (horizontal period HRP) for one pixel 180 (pixel circuit 181).

[0059] First, an overview of a method for driving the display device 10 will be described with reference to Fig. 4. As shown in Fig. 4, the method for driving the display device 10 includes, in one frame, at least an initialization period PIN (period PIN), a write period PWR (period PWR), and a threshold value acquisition and retention period PVH (period PVH). In the pixel 180 (pixel circuit 181) included in the display device 10, the period PWR and period PVH are executed after the period PIN. Furthermore, the period PIN, period PWR, and period PVH of the current frame are executed after the light emission period PEM of the frame immediately before the current frame, and the period PIN, period PWR, and period PVH of the frame immediately after the current frame are executed after the light emission period PEM of the current frame.

[0060] The period PIN is a period during which the second node N3, the third node N4, and the fourth node N4 are initialized. The period PWR is a period during which the data signal VDATA is written to the pixel 180 (pixel circuit 181). The period PVH is a period during which the threshold voltage of the second transistor T2 is acquired by performing an operation to make the potential difference Vgs of the second transistor T2 equal to the threshold voltage, and a charge corresponding to the threshold voltage is held at the third node N3 (the first electrode 42 of the capacitor CV). Furthermore, the light-emitting period PEM is a period during which the pixel 180 emits light based on the written (supplied) data signal VDATA and the acquired threshold voltage of the second transistor T2 (threshold voltage correction). As an example, the period PWR shown in FIG. 4 overlaps with the period PVH and is executed during the period PVH. The period PWR is not limited to the example shown in FIG. 4. For example, the period PWR may be executed during the period PIN and the period PVH, or may be executed during the period during which the third node N3 and the fourth node N4 are initialized and the period PIN.

[0061] Next, a specific method for driving the pixel 180 (pixel circuit 181) of the display device 10 will be described with reference to FIGS.

[0062] The pixel 180 (pixel circuit 181) receives input of a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), an image data signal SL(m) including a data signal VDATA, an initialization voltage VINI, and a reference voltage VREF. For example, the pixel 180 (pixel circuit 181) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n). The image data signal SL(m), the initialization voltage VINI, and the reference voltage VREF are input to the selected pixel 180 (pixel circuit 181) according to the timing of each signal. A similar operation is performed for all pixels 180 (pixel circuits 181), and based on the image data signals SL(m) input to all pixels 180 (pixel circuits 181), the image of the frame corresponding to one frame is displayed in the display area 22 of the display device 10.

[0063] For example, Table 1 shows the voltages (potentials) supplied to the signals and nodes in each period of each frame in the timing charts shown in FIGS.

[0064] [Table 1]

[0065] <1-5-1. First Example of Driving Method of Display Device 10> A first example of a method for driving the display device 10 will be described with reference to FIG. 5 and Table 1. The driving method shown in the first example involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH of the data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL of the data signal VDATA in the KthFRAME. In other words, the driving method shown in the first example involves displaying images of different colors in successive frames.

[0066] In accordance with each period (period PIN, period PWR (horizontal period HRP), and period PVH), an image data signal SL(m) including a data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data including a voltage greater than or equal to voltage VSIGL and less than or equal to voltage VSIGH. For example, in each period PWR, a voltage greater than or equal to voltage VSIGL and less than or equal to voltage VSIGH is selected using a selection signal (not shown) and supplied to the image data signal SL(m). For example, in a period when data is not selected using a selection signal (period excluding period PWR), a voltage greater than or equal to voltage VSIGL and less than or equal to voltage VSIGH is applied as the data signal VDATA based on the data signal VDATA written to the pixel circuits 181 of the corresponding row (n-* and n+*). As shown in Table 1, for example, the voltage VSIGL is 0.2 V, and the pixel 180 to which the voltage VSIGL is supplied does not emit light and is black. Furthermore, for example, the voltage VSIGH is 4.2 V, and the pixel 180 to which the voltage VSIGH is supplied emits light and produces a white color. For example, the voltage VH(HI) is 10 V, the voltage VL(LO) is −4 V, the reference voltage VREF is 1.4 V, the initialization voltage VINI is −2 V, the voltage VM is 5 V, and the voltage VN is −5 V.

[0067] The light-emitting period PEM of the K-1st FRAME is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the potential difference Vgs of the second transistor T2 (the voltage (voltage V(N2)) supplied to the second node N2 minus the voltage (voltage V(N3)) supplied to the third node N3). For example, the pixel 180 (pixel circuit 181) emits red light, and three pixels, a pixel 180 that emits red light, a pixel 180 that emits blue light, and a pixel 180 that emits green light, emit white light.

[0068] For example, during the light emission period PEM of the (K-1st) frame, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are supplied with LO, and the first scan signal SC1(n) is supplied with HI. The first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are in the OFF state, and the third transistor T3 is in the ON state. Furthermore, for example, the voltage Vna supplied to the first node N1 and the second node N2 is 6.3 V, the voltage Vnb supplied to the third node N3 is 2.5 V, and the potential difference Vgs is 3.8 V. Therefore, the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds according to the voltage VSIGH input during the horizontal period HRP of the (K-1st) frame. Also, when the second transistor T2 is in the on state, the current Ion flows from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light.

[0069] During the initial period of the period PIN of the Kth FRAME, which follows the light-emitting period PEM of the K-1st FRAME, the voltage of the data signal VDATA is supplied to pixels other than the selected pixel 180 (pixel circuit 181). The first scan signal SC1(n) changes from a HI state to a LO state. When the first scan signal SC1(n) changes to a LO state, the second scan signal SC2(n) changes from a LO state to a HI state. The third scan signal SC3(n) and the fourth scan signal SC4(n) are both in a LO state. Therefore, the third transistor T3 changes from an ON state to an OFF state, the fourth transistor T4 and the sixth transistor T6 change from an OFF state to an ON state, and the first transistor T1 and the fifth transistor T5 maintain their OFF states. As a result, the voltage supplied to the first node N1 and the voltage supplied to the third node N3 maintain the voltage Vna, and the voltage supplied to the second node N2 gradually drops from the voltage Vna toward the voltage Vnc (reference voltage VREF, 1.4 V) and becomes the voltage Vnc. Although not shown, the voltage supplied to the fourth node N4 gradually drops toward the voltage Vnc (reference voltage VREF, 1.4 V) and becomes the voltage Vnc. The second transistor T2 changes from an on state to an off state in response to the potential difference Vgs, and the drain current Ion does not flow to the light-emitting element OLED, so that the light-emitting element OLED does not emit light.

[0070] During period PIN following the beginning of period PIN, the voltage of the data signal VDATA is supplied to pixels other than the selected pixel 180 (pixel circuit 181), the second scan signal SC2(n) maintains a HI state, and the first scan signal SC1(n) and the fourth scan signal SC4(n) maintain a LO state. The third scan signal SC3(n) changes from a LO state to a HI state. Therefore, the fifth transistor T5 changes from an OFF state to an ON state, and the second transistor T2 changes from an OFF state to an ON state. The sixth transistor T6 and the fourth transistor T4 maintain an ON state, and the first transistor T1 and the third transistor T2 maintain an OFF state.

[0071] As a result, the voltage supplied to the first node N1 maintains voltage Vna, and the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain voltage Vnc. The voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnd (initialization voltage VINI, -2V) and reaches voltage Vnd. The potential difference Vgs becomes 3.4V (1.4V - (-2V)), and the potential difference Vds becomes 10V (8V - (-2V)). Although the second transistor T2 changes from an off state to an on state, the fifth transistor T5 is on and a current flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, so the light-emitting element OLED does not emit light. At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vna supplied to the first node N1 and the voltage Vnc supplied to the fourth node N4, and maintains this potential difference, while the capacitive element CV holds a charge equivalent to the potential difference between the voltage Vnc supplied to the fourth node N4 and the voltage Vnd supplied to the third node N3, and maintains this potential difference. The voltage supplied to the fourth node N4 is the same as the voltage supplied to the second node N2, and the capacitive element CV maintains the potential difference Vgs (the potential difference between the voltage supplied to the gate electrode 622 of the second transistor T2 and the voltage supplied to the first electrode 624).

[0072] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (−2 V).

[0073] During the period PVH following the period PIN, the voltage of the data signal VDATA is supplied to pixels other than the selected pixel 180 (pixel circuit 181), the second scan signal SC2(n) maintains a HI state, and the first scan signal SC1(n) and the fourth scan signal SC4(n) maintain a LO state. The third scan signal SC3(n) changes from a HI state to a LO state. Therefore, the fifth transistor T5 changes from an ON state to an OFF state, the second transistor T2, the sixth transistor T6, and the fourth transistor T4 maintain an ON state, and the first transistor T1 and the third transistor T4 maintain an OFF state.

[0074] As a result, the voltage supplied to the first node N1 maintains the voltage Vna, and the voltages supplied to the second node N2 and the fourth node N4 maintain the voltage Vnc. When the fifth transistor T5 is turned off, the voltage supplied to the third node N3 is released. The drain current Ion of the second transistor T2 starts charging the third node N3, gradually increasing it from the voltage Vnd toward the voltage Vnf. The voltage supplied to the third node N3 may also become the voltage Vnf. The voltage Vnf (0.4 V) is the voltage at which the potential difference Vgs becomes the threshold voltage VTH (1 V) of the second transistor T2.

[0075] During the period PVH, a period PWR is executed parallel to (overlaps with) the period PVH. During the period PWR, the image data signal SL(m) is supplied with a voltage VSIGL (0.2 V). The first scan signal SC1(n) and the third scan signal SC3(n) maintain a state in which LO is supplied, and the second scan signal SC2(n) maintains a state in which HI is supplied. The fourth scan signal SC4(n) changes from a state in which LO is supplied to a state in which HI is supplied. Therefore, the first transistor T1 changes from an OFF state to an ON state, the fourth transistor T4 and the sixth transistor T6 maintain an ON state, and the third transistor T5 maintains an OFF state. Note that the period in which HI is supplied to the fourth scan signal SC4(n), i.e., the period PWR (horizontal shift HRP), may be longer than the period shown in FIG. 5. For example, the period during which the fourth scan signal SC4(n) is supplied with HI may be shorter than the period during which the second scan signal SC2(n) is supplied with HI and longer than the period PIN, or may be the same as the period PIN, or may be shorter than the period PIN.

[0076] As a result, the voltage supplied to the first node N1 gradually drops toward voltage Vne (voltage VSIGL (0.2 V)) and becomes voltage Vne, while the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain voltage Vnc. The voltage supplied to the third node N3 gradually rises from voltage Vnd toward voltage Vnf. Note that the voltage supplied to the third node N3 may become voltage Vnf. At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vne supplied to the first node N1 and the voltage Vnc supplied to the fourth node N4, and maintains this potential difference. That is, the capacitive element CD holds a charge equivalent to the potential difference between the voltage of the data signal VDATA and the reference voltage VREF, and maintains (holds) the voltage included in the data signal VDATA with reference to the reference voltage VREF.

[0077] In this way, during the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). The capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0078] During the period PVH following the period PWR, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181), the fourth scan signal SC4(n) changes from a HI state to a LO state, and the first scan signal SC1(n) and the third scan signal SC3(n) maintain their LO states. After a predetermined time has elapsed since the fourth scan signal SC4(n) was switched to the LO state, the second scan signal SC2(n) changes from a HI state to a LO state. Therefore, the first transistor T1 changes from an ON state to an OFF state, and the third transistor T5 and the fifth transistor T5 maintain their OFF states. After a predetermined time has elapsed since the first transistor T1 was switched to the OFF state, the fourth transistor T4 and the sixth transistor T6 change from an ON state to an OFF state.

[0079] As a result, the voltage supplied to the first node N1 is maintained at voltage Vne, and the voltages supplied to the second node N2 and the fourth node N4 are maintained at voltage Vnc. The voltage supplied to the third node N3 gradually increases from voltage Vnd to voltage Vnf and reaches voltage Vnf. At this time, the potential difference Vgs is 1 V, which is the same as the threshold voltage VTH (1 V), and the second transistor T2 is in an off state. Therefore, no drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, and the light-emitting element OLED does not emit light. Furthermore, as described above, the voltage supplied to the fourth node N4 is the same as the voltage supplied to the second node N2, and the capacitive element CV maintains the potential difference Vgs (the potential difference between the voltage supplied to the gate electrode 622 and the voltage supplied to the first electrode 624 of the second transistor T2) to maintain the threshold voltage VTH.

[0080] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0081] During the light emission period PEM of KthFRAME following the period PVH of KthFRAME, pixel 180 emits light based on the voltage VSIGL supplied to the first node N1 and the potential difference Vsg between the voltage supplied to the second node N2 and the voltage supplied to the third node.

[0082] For example, during the light emission period PEM of KthFRAME, the voltage of the data signal VDATA is supplied to pixels other than the selected pixel 180 (pixel circuit 181). Also, the first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied, and the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) maintain their states in which LO is supplied. Therefore, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 maintain their off states, and the third transistor T3 changes from their off state to their on state.

[0083] As a result, the first node N1 becomes conductive with the second node N2, the voltage supplied to the second node N2 gradually drops from voltage Vnc toward voltage Vne (0.2V) and becomes voltage Vnf, the voltage supplied to the first node N1 remains at voltage Vne (0.2V), and the voltage supplied to the third node N3 remains at voltage Vnf (0.4V).

[0084] At this time, the potential difference Vgs is the sum of the potential difference held in the capacitance element CD and the potential difference held in the capacitance element CV (the voltage contained in the data signal VDATA (voltage VSIGL (0.2 V) - reference voltage VREF (1.4 V) + threshold voltage VTH (1 V) = -0.2 V). In other words, during the light emission period PEM of KthFRAME, the pixel 180 (pixel circuit 181) can display an image based on the data signal VDATA and the corrected threshold.

[0085] Specifically, since the potential difference Vds is 7.6 V and the potential difference Vgs (-0.2 V) is lower (smaller) than the threshold voltage VTH, the second transistor T2 is in an off state, and no current flows from the drive power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. As a result, for example, the pixel 180 (pixel circuit 181) that emits red light turns black. Similarly to the pixel 180 that emits red light, the pixel 180 that emits blue light and the pixel 180 that emits green light also do not emit light, so the three pixels that use the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light turn black.

[0086] The display device 10 includes a capacitive element CD electrically connected between a first node N1 or a second node N2 and a fourth node N4, a capacitive element CV electrically connected between the fourth node N4 and a third node N3, a fourth transistor T4 for supplying a reference voltage VREF to the second node N2, a fifth transistor T5 for supplying an initialization voltage VINI to the third node N3, a sixth transistor T6 for supplying a reference voltage VREF to the fourth node N4, and a first transistor T1 for supplying a data signal VDATA having a voltage greater than or equal to VSIGL and less than or equal to VSIGH to the first node N1. The driving method of the display device 10 also includes a configuration capable of independently controlling the supplying of the reference voltage VREF to the second node N2 by the fourth transistor T4, the supplying of the initialization voltage VINI to the third node N3 by the fifth transistor T5, the supplying of the reference voltage VREF to the fourth node N4 by the sixth transistor T6, and the supplying of the data signal VDATA between the voltage VSIGL and the voltage VSIGH by the first transistor T1 to the first node N1. That is, the display device 10 can execute, in parallel, the supplying of the reference voltage VREF to the second node N2 by the fourth transistor T4, the supplying of the initialization voltage VINI to the third node N3 by the fifth transistor T5, the supplying of the reference voltage VREF to the fourth node N4 by the sixth transistor T6, and the supplying of the data signal VDATA to the first node N1, using two capacitance elements CD and CV.

[0087] As a result, for example, the display device 10 writes a data signal VDATA to the pixel 180 (pixel circuit 181), and while the capacitive element CD maintains (holds) the voltage included in the data signal VDATA, the capacitive element CV holds a potential difference (charge) corresponding to the threshold voltage VTH. By coupling the capacitive elements CD and CV, a potential difference Vgs of the second transistor T2 can be generated. The potential difference Vgs is a voltage based on the data signal VDATA and the corrected threshold voltage VTH, and the pixel 180 (pixel circuit 181) can display an image in accordance with the voltage based on the data signal VDATA and the corrected threshold voltage VTH. At this time, the period PWR corresponding to the period during which the data signal VDATA is written is shorter than the period PVH corresponding to the period during which the threshold voltage VTH is acquired and the potential difference (charge) corresponding to the threshold voltage VTH is held.

[0088] On the other hand, when a display device including one storage capacitor stores a voltage corresponding to a data voltage whose threshold voltage is compensated, it performs both threshold voltage compensation and data voltage writing within the program period. That is, the display device including one storage capacitor performs charging and discharging of the storage capacitor corresponding to threshold voltage compensation and charging and discharging of the storage capacitor corresponding to data voltage writing within the program period. As a result, in a display device including one storage capacitor, the time required to write the data voltage depends on the time required to compensate the threshold voltage, and therefore the time required to write the data voltage is long.

[0089] As described above, the display device 10 can independently control each node and can make the period PWR shorter than the period PVH, thereby shortening the time required to write the data signal VDATA and increasing the speed at which data is written to the first node N1.

[0090] Furthermore, in the display device 10, the third node N3, the first electrode 42 of the capacitance element CV, and the second electrode 34 of the light-emitting element OLED are directly connected. As a result, when the first node N1 is electrically connected to the second node N2, the potential of the third node N3 after the threshold voltage VTH is acquired becomes the potential after the parasitic capacitance added to the light-emitting element OLED is also charged. Therefore, no charge redistribution occurs between the capacitance elements CD, CV, and the parasitic capacitance added to the light-emitting element OLED. Therefore, the voltage included in the data signal VDATA supplied to the first node N1 and the second node N2 is not affected by the charge redistribution due to the above-mentioned factors, so the display device 10 can suppress a decrease in the voltage included in the data signal VDATA supplied to the first node N1 and the second node N2 due to the charge redistribution. In other words, the display device 10 can efficiently maintain the voltage included in the data signal VDATA supplied to the first node N1 and the second node N2.

[0091] Furthermore, the display device 10 can independently control the period PWR, and can execute the period PWR in parallel with the periods PIN and PVH within the periods PIN and PVH. As a result, the display device 10 is a display device with a high degree of freedom in the period PWR. Therefore, the display device 10 includes a configuration that allows the period PWR to be adjusted depending on the application and specifications of the display device, making it a highly versatile display device.

[0092] <1-5-2. Second Example of the Method for Driving the Display Device 10> A second example of a method for driving the display device 10 will be described with reference to FIG. 6. The driving method shown in the second example involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH included in the data signal VDATA in the frame (K-1st FRAME) immediately preceding the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) also displaying a white image based on the voltage VSIGH included in the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the second example involves displaying images of the same color (white) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 5 will be described as necessary.

[0093] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the first node N1 and other signals during the period PWR of the KthFRAME, the period PVH after the period PWR of the KthFRAME, and the light-emitting period PEM of the KthFRAME are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the second node N2, the third node N3, and the fourth node N4 during the period excluding the light-emitting period PEM of the KthFRAME are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the operation of each transistor during each period is the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Therefore, configurations similar to those described in "1-5-1. First example of method for driving display device 10" will be described as necessary. Note that, as for the image data signal SL(m), a data signal VDATA of VSIGH corresponding to white is supplied during the period PWR of the KthFRAME, and a data signal VDATA similar to the configuration described in "1-5-1. First example of method for driving display device 10" is supplied during periods other than the period PWR of the KthFRAME.

[0094] During the light emission period PEM of the K-1st FRAME, similar to the configuration described in "1-5-1. First example of the method for driving the display device 10", the drain current Ion flows from the driving power supply line PVDD to the light emitting element OLED and the reference voltage line PVSS, and the light emitting element OLED emits light.

[0095] Furthermore, during the initial period and period PIN of the KthFRAME following the light emission period PEM of the K-1stFRAME, the second node N2 and the fourth node N4 are initialized by the reference voltage VREF (1.4V), and the third node N3 is initialized by the initialization voltage VINI (-2V), similar to the configuration described in "1-5-1. First example of the method for driving the display device 10."

[0096] Furthermore, in the period PVH following the period PIN, similar to the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10," the voltage supplied to the first node N1 remains at voltage Vna, and the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 remain at voltage Vnc. The voltage supplied to the third node N3 gradually rises from voltage Vnd toward voltage Vnf.

[0097] During the period PVH, a period PWR is executed that runs parallel to (overlaps with) the period PVH. During the period PWR, the image data signal SL(m) is supplied with a voltage VSIGH (4.2V). The voltage supplied to the first node N1 gradually drops toward voltage Vnh (voltage VSIGH (4.2V)) and reaches voltage Vnh. The voltages supplied to the second node N2 and the fourth node N4 maintain voltage Vnc. The voltage supplied to the third node N3 gradually rises from voltage Vnd toward voltage Vnf. At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage of the data signal VDATA and the reference voltage VREF, and maintains (holds) the voltage included in the data signal VDATA.

[0098] In this way, during the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). The capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0099] During the period PVH following the period PWR, the voltage supplied to the first node N1 maintains the voltage Vnh, and the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain the voltage Vnc. The voltage supplied to the third node N3 gradually increases from the voltage Vnd toward the voltage Vnf and reaches the voltage Vnf. At this time, similar to the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10," the second transistor T2 is in the off state, and no drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light, and the capacitance element CV maintains the potential difference Vgs and holds the threshold voltage VTH.

[0100] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0101] During the light emission period PEM of KthFRAME, the first node N1 is electrically connected to the second node N2, and the voltage at the second node N2 gradually rises from voltage Vnc toward voltage Vnh (4.2 V). As a result, the second transistor T2 is electrically connected, a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, and the voltage at the third node N3 rises to follow the rise in the voltage at the second node N2. As the voltage at the third node N3 rises, the voltage at the second node N2 and the voltage at the first node N1 connected to the second node N2 further rise, and the voltage supplied to the first node N1 and the second node N2 becomes voltage Vna, and the voltage supplied to the third node N3 becomes voltage Vnb.

[0102] At this time, the potential difference Vgs is the sum of the potential difference held in the capacitance element CD and the potential difference held in the capacitance element CV (the voltage included in the data signal VDATA (voltage VSIGH, 4.2 V) - reference voltage VREF (1.4 V) + threshold voltage VTH (1 V) = 3.8 V). That is, during the light emission period PEM of KthFRAME, the pixel 180 (pixel circuit 181) can display an image based on the data signal VDATA and the corrected threshold.

[0103] Specifically, the potential difference Vds is 7.4 V, and the potential difference Vgs (3.8 V) is greater than the threshold voltage VTH (1 V). Therefore, the second transistor T2 is in an on state, and a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180 (pixel circuit 181) emits red light, and three pixels, one using a pixel 180 that emits blue light and one using a pixel 180 that emits green light, emit white light.

[0104] The second example of the method for driving the display device 10 has the same effects as those described in "1-5-1. First example of the method for driving the display device 10."

[0105] <1-5-3. Third Example of the Method for Driving the Display Device 10> A third example of a method for driving the display device 10 will be described with reference to FIG. 7. The driving method shown in the third example involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL included in the data signal VDATA in the frame (K-1st FRAME) immediately preceding the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGH included in the data signal VDATA in the Kth FRAME as well. In other words, the driving method shown in the third example involves displaying images of the same color (black) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 6 will be described as necessary.

[0106] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) and the image data signal SL(m) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the configurations of the first node N1 and the like during the period PVH after the period PWR of the KthFRAME and during the period excluding the light-emitting period PEM of the KthFRAME are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the second node N2, the third node N3, and the fourth node N4 during the period PVH of the KthFRAME, the period PWR of the KthFRAME, and the light-emitting period PEM of the KthFRAME are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the operation of each transistor in each period is the same as the configuration described in "1-5-1. First example of the method for driving the display device 10." Therefore, configurations similar to those described in "1-5-1. First example of the method for driving the display device 10" will be described as necessary.

[0107] During the light emission period PEM of the K-1st FRAME, the voltages supplied to the first node N1 and the second node N2 are voltage Vne, the voltage supplied to the third node N3 is voltage Vnf, and the potential difference Vgs is −0.2 V. Therefore, the second transistor T2 is in an off state, and the drain current Ion does not flow from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, so the pixel 180 (pixel circuit 181) that emits red light is black. Similarly to the pixel 180 that emits red light, the pixel 180 that emits blue light and the pixel 180 that emits green light also do not emit light, so the three pixels that use the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light are black.

[0108] During the initial period of the period PIN of the KthFRAME, which follows the light-emitting period PEM of the (K-1stFRAME), the voltage supplied to the first node N1 maintains the voltage Vne. The voltage supplied to the second node N2 gradually increases from voltage Vne toward voltage Vnc (reference voltage VREF, 1.4V) and reaches voltage Vnc. The voltage supplied to the third node N3 maintains voltage Vnf. Although not shown, the voltage supplied to the fourth node N4 gradually increases toward voltage Vnc (reference voltage VREF, 1.4V) and reaches voltage Vnc. The second transistor T2 is in an off state, and no drain current Ion flows through the light-emitting element OLED, so the light-emitting element OLED does not emit light.

[0109] During the period PIN following the initial period of the period PIN, the voltage supplied to the first node N1 maintains voltage Vne, and the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain voltage Vnc. The voltage supplied to the third node N3 gradually drops from voltage Vnf toward voltage Vnd (initialization voltage VINI, −2V) and reaches voltage Vnd. The potential difference Vgs becomes 3.4V (1.4V − (−2V)), and the potential difference Vds becomes 10V (8V − (−2V)). As in the configuration described in “1-5-1. First Example of the Method for Driving the Display Device 10,” the second transistor T2 changes from an off state to an on state, but the fifth transistor T5 is on, and a current flows from the drive power supply line PVDD to the initialization voltage power supply line SVI, so the light-emitting element OLED does not emit light. At this time, the capacitance element CD holds a charge equivalent to the potential difference between the voltage Vne supplied to the first node N1 and the voltage Vnc supplied to the fourth node N4 and maintains the potential difference, and the capacitance element CV maintains the potential difference Vgs.

[0110] As described above, similar to the configuration described in "1-5-1. First example of the method for driving the display device 10," during the period PIN, the second node N2 and the fourth node N4 are initialized by the reference voltage VREF (1.4V), and the third node N3 is initialized by the initialization voltage VINI (-2V).

[0111] During the period PVH following the period PIN, the voltage supplied to the first node N1 maintains the voltage Vne, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain the voltage Vnc, and the voltage supplied to the third node N3 gradually rises from the voltage Vnd toward the voltage Vnf.

[0112] During the period PWR that is parallel to (overlaps with) the period PVH, the voltage supplied to the first node N1 remains unchanged at voltage Vne (voltage VSIGL (0.2 V)), while the voltages supplied to the second node N2 and the fourth node N4 maintain voltage Vnc. The voltage supplied to the third node N3 gradually rises from voltage Vnd toward voltage Vnf. At this time, similar to the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10," the capacitive element CD holds a charge equivalent to the potential difference between the voltage of the data signal VDATA and the reference voltage VREF, and maintains (holds) the voltage of the data signal VDATA with reference to the reference voltage VREF.

[0113] As described above, in the same manner as in the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10," during the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Furthermore, the capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0114] During the period PVH following the period PWR, similar to the configuration described in "1-5-1. First Example of the Driving Method of the Display Device 10," the voltage supplied to the first node N1 maintains voltage Vne, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain voltage Vnc, and the voltage supplied to the third node N3 gradually increases from voltage Vnd toward voltage Vnf, reaching voltage Vnf. Furthermore, the second transistor T2 is in an off state, and no drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. Furthermore, the capacitance element CV maintains the threshold voltage VTH, so the potential difference Vgs is maintained.

[0115] In this manner, similar to the configuration described in "1-5-1. First example of the method for driving the display device 10," during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0116] During the light emission period PEM of the KthFRAME following the period PVH of the KthFRAME, similar to the configuration described in "1-5-1. First Example of the Method of Driving the Display Device 10," the first node N1 is conductive with the second node N2, the voltage supplied to the second node N2 becomes voltage Vne, and the voltage supplied to the third node N3 becomes voltage Vnf. As a result, the pixel 180 that emits red, the pixel 180 that emits blue, and the pixel 180 that emits green do not emit light, and therefore the three pixels using the pixel 180 that emits red, the pixel 180 that emits blue, and the pixel 180 that emits green appear black.

[0117] The third example of the method for driving the display device 10 has the same effects as those described in "1-5-1. First example of the method for driving the display device 10."

[0118] <1-5-4. Fourth Example of the Method for Driving the Display Device 10> A fourth example of a method for driving the display device 10 will be described with reference to FIG. 8. The driving method shown in the fourth example involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL of the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH of the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the fourth example involves displaying images of different colors in successive frames. Configurations that are the same as or similar to those in FIGS. 1 to 11 will be described as necessary.

[0119] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) and the image data signal SL(m) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the second node N2, the third node N3, and the fourth node N4 during the light-emitting period PEM of the K-1st FRAME to the period PVH of the Kth FRAME, and the period PWR executed in parallel with the period PVH of the Kth FRAME, are the same as those described in "1-5-3. Third Example of the Method for Driving the Display Device 10." Furthermore, the first node N1 during the light-emitting period PEM of the K-1st FRAME, the period PIN of the Kth FRAME, and the period PVH between the period PIN and the period PWR are the same as those described in "1-5-3. Third Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, the third node N3, and the voltage (potential) of the fourth node N4 during the period PVH after the period PWR of KthFRAME to the light emission period PEM of KthFRAME are the same as those described in "1-5-2. Second Example of the Method for Driving the Display Device 10." Furthermore, the operation of each transistor during each period is the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Therefore, configurations similar to those described in "1-5-1. First Example of the Method for Driving the Display Device 10" to "1-5-3. Third Example of the Method for Driving the Display Device 10" will be described as necessary.

[0120] In the light emission period PEM of the (K-1st) frame, the pixel 180 (pixel circuit 181) turns black, as explained in "1-5-3. Third example of the method for driving the display device 10."

[0121] During the period PIN of KthFRAME, as in "1-5-3. Third Example of the Method of Driving the Display Device 10," the light-emitting element OLED does not emit light, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vne supplied to the first node N1 and the voltage Vnc supplied to the fourth node N4 and maintains this potential difference, and the capacitive element CV maintains the potential difference Vgs. Also, during the period PIN, the second node N2 and the fourth node N4 are initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (-2 V).

[0122] During the period PVH between the period PIN and the period PWR of KthFRAME, as in "1-5-3. Third example of the driving method of the display device 10", the voltage supplied to the first node N1 maintains the voltage Vne, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain the voltage Vnc, and the voltage supplied to the third node N3 gradually rises from the voltage Vnd toward the voltage Vnf.

[0123] During the period PWR of KthFRAME, the voltage supplied to the first node N1 gradually increases from voltage Vne toward voltage Vnh (voltage VSIGH (4.2 V)) and reaches voltage Vnh. The voltages supplied to the second node N2 and the fourth node N4 maintain voltage Vnc, and the voltage supplied to the third node N3 gradually increases from voltage Vnd toward voltage Vnf.

[0124] During the period PVH after the period PWR of KthFRAME, similar to "1-5-2. Second Example of the Driving Method of the Display Device 10," the voltage supplied to the first node N1 remains at voltage Vnh, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 remain at voltage Vnc, and the voltage supplied to the third node N3 becomes voltage Vnf. Furthermore, the light-emitting element OLED does not emit light, and the capacitance element CV maintains the potential difference Vgs and holds the threshold voltage VTH. As a result, during the period PVH, the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, thereby acquiring the threshold voltage VTH of the second transistor T2 and holding a charge equivalent to the threshold voltage VTH in the capacitance element CV.

[0125] During the light-emitting period PEM of the KthFRAME, which follows the period PVH after the period PWR of the KthFRAME, similar to "1-5-2. Second Example of the Driving Method of the Display Device 10," the first node N1 and the second node N2 are electrically connected, the voltages supplied to the first node N1 and the second node N2 become voltage Vna, and the voltage supplied to the third node N3 becomes voltage Vnb. The potential difference Vgs is the sum (3.8 V) of the potential difference held in the capacitive element CD and the potential difference held in the capacitive element CV. Therefore, a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, white light is emitted by three pixels: a pixel 180 (pixel circuit 181) that emits red, a pixel 180 that emits blue, and a pixel 180 that emits green.

[0126] The fourth example of the method for driving the display device 10 has the same effects as those described in "1-5-1. First example of the method for driving the display device 10."

[0127] <1-6. Edge structure of pixel 180> The end face structure of pixel 180 will be described with reference to FIGS. 9 to 12. FIG. 9 is a layout diagram of pixel 180. FIG. 10 is an end face diagram showing an end face cut along A1-A2 in the layout shown in FIG. 9. FIG. 11 is an end face diagram showing an end face cut along B1-B2 in the layout shown in FIG. 9. FIG. 12 is an end face diagram showing an end face cut along C1-C2 in the layout shown in FIG. 9. The layout of pixel 180 shown in FIG. 9 and the end faces of pixel 180 shown in FIGS. 10 to 12 are merely examples, and the planar layout and end faces of pixel 180 are not limited to the examples shown in FIGS. 9 to 12. Configurations that are the same as or similar to those in FIGS. 1 to 8 will be described as necessary.

[0128] 11 and 12, the configuration of the layer above the insulating layer 141 (the side opposite to the substrate 101) along the direction D3 is omitted from the end face of the pixel 180.

[0129] 10 is an example of an end face of pixel 180, and is an end face along first wiring 132G, second contact hole opening 138F, second wiring 140C, contact hole opening 147 for the anode electrode, anode electrode 143, and functional layer 148. The end face of pixel 180 shown in FIG. 11 is an example of an end face of pixel 180, and is an end face along first wiring 132C, first contact hole opening 135A, gate wiring 127D, first wiring 132B, first wiring 132K, first contact hole opening 135C, and semiconductor layer 122D. The end face of pixel 180 shown in FIG. 12 is an example of an end face of pixel 180, and is an end face along first wiring 132E, first contact hole opening 135, semiconductor layer 122A, second wiring 140A, gate wiring 127E, and organic insulating film opening 138A for capacitance element CS.

[0130] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is provided on the first surface 101A of the substrate 101 via an underlayer 121. The semiconductor layer 122 includes a semiconductor layer 122A, which includes a channel region 123 and an impurity region 124A. The semiconductor layer 122 also includes a semiconductor layer 122D. For example, the impurity region is called a source region or a drain region. For example, the second transistor T2 includes the semiconductor layer 122A, and the first electrode 624 and the second electrode 626 include the impurity region 124A. In other words, the semiconductor layer 122A includes the channel region of the second transistor T2. Similar to the semiconductor layer 122A, for example, the fourth transistor T4 includes a semiconductor layer 122D, and the first electrode 644 and the second electrode 646 include impurity regions. In other words, the semiconductor layer 122D includes the channel region of the fourth transistor T4.

[0131] A gate insulating layer 125, a conductive layer 126, an insulating layer 128, and a conductive layer 132 are provided on the semiconductor layer 122 in this order. The conductive layer 126 includes a gate wiring 127A (gate electrode 622) and a gate wiring 127D. The conductive layer 132 includes a first wiring 132B (initialization voltage power supply line SVI), a first wiring 132C (reference voltage power supply line SVR), a first wiring 132E (first electrode 42), a first wiring 132G, and a first wiring 132K. The region where the conductive layer 126 and the semiconductor layer 122 overlap is a channel region. In other words, the region where the gate electrode and the semiconductor layer of each transistor overlap is a channel region.

[0132] Each of the transistors of the pixel 180 is formed using a semiconductor layer 122 (channel region 123 and impurity region 124A), a gate insulating layer 125, and a conductive layer 126 (for example, gate wiring 127A).

[0133] First contact hole openings 135, 135A, and 135C reaching the semiconductor layer 122 are provided in the gate insulating layer 125 and the insulating layer 128. The first contact hole opening 135 exposes the semiconductor layer 122A (e.g., the second electrode 626). For example, the first wiring 132E is electrically connected to the semiconductor layer 122A through the first contact hole opening 135. Furthermore, the first contact hole opening 135A exposes the conductive layer 126 (gate wiring 127D), and the first contact hole opening 135C exposes the conductive layer 126 (gate wiring 127D) and the semiconductor layer 122 (semiconductor layer 122D). The first wiring 132C is electrically connected to the gate wiring 127D through the first contact hole opening 135A, and the first wiring 132K is electrically connected to the gate wiring 127D and the semiconductor layer 122D through the first contact hole opening 135C. That is, an opening (not shown) reaching the conductive layer 126 or the semiconductor layer 122 may be provided in the insulating layer 128.

[0134] The insulating layer 131 is provided to cover the conductive layer 132 and the insulating layer 131 that is not exposed from the conductive layer 132. The insulating layer 136 is provided to cover the insulating layer 131.

[0135] Second contact hole openings are provided in the insulating layer 131 and the insulating layer 136. For example, the second contact hole openings include a second contact hole opening 138F. An organic insulating film opening 138A for the capacitor element CS is provided in the insulating layer 136. A conductive layer 139 is provided on the insulating layer 136, in the organic insulating film opening 138A for the capacitor element CS and the second contact hole opening 138F. The conductive layer 139 includes a second wiring 140A (first electrode 52 and second electrode 44) and a second wiring 140C (second electrode 34). The second contact hole opening 138F exposes the conductive layer 132 (for example, the first wiring 132G). The second contact hole opening 138F electrically connects the second wiring 140C (second electrode 34) and the first wiring 132G. The organic insulating film opening 138A for the capacitor element exposes the insulating layer 131. For example, the capacitor element CV is formed using a first wiring 132E (first electrode 42) and a second wiring 140A (first electrode 52 and second electrode 44) with the insulating layer 131 as a dielectric, and the capacitor element CD is formed using a first wiring 132H (second electrode 54) and a second wiring 140A (first electrode 52 and second electrode 44) with the insulating layer 131 as a dielectric. For example, the second wiring 140A also serves as a pixel electrode. Although not shown, the second contact hole opening 138 exposes some of the multiple terminals (not shown) included in the terminal section 150. Some of the exposed terminals are electrically connected to the FPC 200 using a conductive film such as an anisotropic conductive film (not shown). Furthermore, a pixel electrode is provided independently for each pixel.

[0136] An insulating layer 141 is provided over the conductive layer 139 .

[0137] The base layer 121 , the semiconductor layer 122 , the gate insulating layer 125 , the conductive layer 126 , the insulating layer 128 , the conductive layer 132 , the insulating layer 131 , the insulating layer 136 , the conductive layer 139 , and the insulating layer 141 are collectively referred to as an array section 170 .

[0138] Next, a description will be given of layers above the insulating layer 141. An anode electrode contact hole opening 147 is provided in the insulating layer 141. The anode electrode contact hole opening 147 exposes the conductive layer 139 (for example, the second wiring 140A).

[0139] An anode electrode 143 is provided to cover the exposed conductive layer 139, the anode electrode contact hole opening 147, and the insulating layer 141. A functional layer 148 is provided on the anode electrode 143. A common electrode 149 is provided on the functional layer 148 to cover the functional layer 148. The common electrode 149 is electrically connected to the cathode electrode (first electrode 32 of the light-emitting element OLED). Here, the light-emitting element OLED is composed of the anode electrode 143, the functional layer 148, and the common electrode 149 (cathode electrode).

[0140] The configuration of the functional layer 148 can be selected appropriately. For example, the functional layer 148 can be configured by combining a carrier injection layer, a carrier transport layer, an emitting layer, a carrier blocking layer, an exciton blocking layer, and the like. For example, the functional layer 148 shown in FIG. 9 includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (hole) injection and transport layer, the second layer 145 is an emitting layer, and the third layer 146 is a carrier (electron) injection and transport layer. For example, the functional layer 148 is provided independently for each pixel, similar to a pixel electrode.

[0141] A sealing film 165 is provided on the common electrode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. The first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed so as to cover at least the display region 22. A cover film 158 is disposed on the second inorganic insulating layer 156.

[0142] For example, the first layer 144, the second layer 145 (light-emitting layer), and the third layer 146 included in the functional layer 148, as well as the common electrode 149, are not disposed on the IC chip 110 and the control circuit 120. A sealing film 165 and a cover film 158 are disposed on the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED, the transistors, etc. from the outside of the display device 10.

[0143] Common metal materials are used for the conductive layer 126, the conductive layer 132, the conductive layer 139, and the common electrode 149. For example, common metal materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof.

[0144] For example, the semiconductor layer 122 may include crystalline silicon or may include a metal oxide.

[0145] A general insulating material can be used as the material for forming the base layer 121, the gate insulating layer 125, the insulating layer 131, the first inorganic insulating layer 152, and the second inorganic insulating layer 156. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y Inorganic insulating layers such as the above are used.

[0146] For example, an organic compound material with excellent surface flatness can be used as the material for forming the insulating layer 128, the insulating layer 136, the insulating layer 141, and the organic insulating layer 154. The insulating layer 128, the insulating layer 136, and the insulating layer 141 may be referred to as organic insulating layers.

[0147] <1-7. Manufacturing method of display device 10> A method for manufacturing the display device 10 (pixel 180) will be described with reference to Fig. 9 and Fig. 13 to Fig. 16. Fig. 13 is a sequence diagram showing a method for manufacturing the display device 10. Configurations that are the same as or similar to those in Figs. 1 to 12 will be explained as necessary. The manufacturing method shown in Fig. 13 includes, as an example, an oxide semiconductor layer formed using an oxide semiconductor as the semiconductor layer.

[0148] As shown in FIG. 13, when the manufacturing of the display device 10 (pixel 180) starts, the underlayer 121 is formed on the first surface 101A of the substrate 101.

[0149] As shown in FIG. 13 or 14, a semiconductor layer 122 is formed on the base layer 121 (step 10 (S10) of FIG. 13). The semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, 122D, and 122E. The semiconductor layer 122A is a semiconductor layer of the second transistor T2. The semiconductor layer 122B serves as a semiconductor layer of the first transistor T1 and a semiconductor layer of the third transistor T3. The semiconductor layer 122C is a semiconductor layer of the fourth transistor T4. The semiconductor layer 122D is a semiconductor layer of the fifth transistor T5. The semiconductor layer 122E is a semiconductor layer of the sixth transistor T6. In other words, the semiconductor layer 122B includes the channel region of the first transistor T1 and the channel region of the third transistor T3, the semiconductor layer 122C includes the channel region of the fourth transistor T4, the semiconductor layer 122D includes the channel region of the fifth transistor T5, and the semiconductor layer 122E includes the channel region of the sixth transistor T6.

[0150] A gate insulating layer 125 (FIGS. 10 to 12) is formed on the semiconductor layer 122 and on the underlying layer 121 where the semiconductor layer 122 is not formed (step 12 (S12) in FIG. 13).

[0151] A conductive layer 126 (FIGS. 10 to 12) is formed on the gate insulating layer 125 (step 13 (S13) of FIG. 13). As shown in FIG. 13 or 15, the conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (scan signal line 331), a gate wiring 127C, a gate wiring 127D, a gate wiring 127E (scan signal line 332), a scan signal line 330, and a scan signal line 333. The gate wiring 127B (scan signal line 331) includes gate electrodes 642 and 662, and the gate wiring 127E (scan signal line 332) includes a gate electrode 652. The scan signal line 330 includes the gate electrode 632, and the scan signal line 333 includes a gate electrode 612.

[0152] The region where the gate electrode 622 and the semiconductor layer 122A of the second transistor T2 overlap is the channel region 123, and the channel region 123 corresponds to the channel length of the second transistor T2. Similar to the second transistor T2, the region where the gate electrode 612 and the semiconductor layer 122B of the first transistor T1 overlap is the channel region and also corresponds to the channel length of the first transistor T1. Similar to the second transistor T2, the region where the gate electrode and the semiconductor layer overlap is the channel region and also corresponds to the channel length of the transistor for transistors other than the second transistor T2 and the first transistor T1.

[0153] 14 , in a plan view, the channel region 123 of the second transistor T2 is larger (longer) than the channel regions of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. That is, the channel length of the second transistor T2 is longer than the channel lengths of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. Because the second transistor T2 operates in the saturation region, the hot carrier resistance of the second transistor T2 must be higher than the hot carrier resistance of the other transistors in the pixel 180. As a result, the channel length of the second transistor T2 is longer than the channel lengths of the other transistors in the pixel 180.

[0154] An insulating layer 128 (FIGS. 10 to 12) is formed on the conductive layer 126 and on the gate insulating layer 125 where the conductive layer 126 is not formed (step 14 (S14) in FIG. 13).

[0155] As shown in FIG. 13 or 14, first contact hole openings 135, 135A, 135B, 135C, 135D, 135E, 135F, 135G, 135H, 135J, 135K, 135L, 135M, 135N, and 135O are opened (step 15 (S15) of FIG. 13). Each opening opens gate insulating layer 125 and insulating layer 128, exposing a corresponding wiring, semiconductor layer, or electrode. For example, first contact hole opening 135 exposes semiconductor layer 122A, and first contact hole opening 135A exposes gate wiring 127D. The other openings also expose corresponding wiring, semiconductor layers, or electrodes.

[0156] The conductive layer 132 (FIGS. 10 to 12) is formed on the insulating layer 128 (step 16 (S16) of FIG. 13). As shown in FIG. 13 or 15, the conductive layer 132 includes a first wiring 132A (drive power supply line PVDD), a first wiring 132B (initialization voltage power supply line SVI), a first wiring 132C (reference voltage power supply line SVR), a first wiring 132D, a first wiring 132E (first electrode 42), a first wiring 132F, a first wiring 132G, a first wiring 132H (second electrode 54), a first wiring 132J, a first wiring 132K, and an image data signal line 321.

[0157] 15, in a plan view, for example, first wiring 132A is electrically connected to the second transistor T2 through first contact hole opening 135D, and first wiring 132B is electrically connected to the fourth transistor T4 and the sixth transistor T6 through first contact hole openings 135M and 135J. First wiring 132C is electrically connected to the fifth transistor T5 through first contact hole opening 135A, gate wiring 127D, and first contact hole opening 135C. First wiring 132D is electrically connected to the first transistor T1 and the third transistor T3 through first contact hole opening 135G. The other first wirings are also electrically connected to gate wirings or transistors through their corresponding openings.

[0158] 15, the first electrode 42, the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 (its channel region and gate electrode 622) overlaps with the first electrode 42 of the capacitance element CV. The first electrode 42 and the first wiring 132H (second electrode 54) are disposed adjacent to each other on the gate electrode 622.

[0159] An insulating layer 131 (FIGS. 10 to 12) is formed on the conductive layer 132 and on the insulating layer 128 where the conductive layer 132 is not formed (step 17 (S17) in FIG. 13).

[0160] 13 or 15, second contact hole openings 138C, 138D, 138E, and 138F are opened (step 18 (S18) in FIG. 13). Each opening opens the insulating layer 131, exposing the corresponding wiring, semiconductor layer, or electrode.

[0161] An insulating layer 136 (organic insulating layer) (FIGS. 10 to 12) is formed on the insulating layer 131 (step 19 (S19) in FIG. 13).

[0162] As shown in FIG. 13 or 15, holes are opened in the insulating layer 136 (organic insulating layer) (step 20 (S20) in FIG. 13). In the opening of S20, organic insulating film openings 138A and 138B for the capacitor element are opened. In addition, in the opening of S20, second contact hole openings 138C, 138C, 138D, 138E, and 138F are opened, similar to the opening of S18. That is, the second contact hole openings 138C, 138C, 138D, 138E, and 138F are opened twice. Each opening opens the insulating layer 136 and exposes the corresponding insulating layer, wiring, or electrode. For example, the organic insulating film opening 138A for the capacitor element removes only the insulating layer 136 above the first wiring 132E (first electrode 42), exposing the insulating layer 131. On the other hand, the second contact hole opening 138F removes only the insulating layer 136 on the first wiring 132G, exposing the first wiring 132G. The other openings also expose the corresponding insulating layer, wiring, or electrode.

[0163] A conductive layer 139 (FIGS. 10 to 12) is formed on the insulating layer 136, on the insulating layer 131 exposed at the organic insulating film opening 138A for the capacitor element, and on the insulating layer 131 exposed at the organic insulating film opening 138B for the capacitor element (step 21 (S21) in FIG. 13). As shown in FIG. 10, 12, or 16, the conductive layer 139 includes a second wiring 140A (first electrode 52 and second electrode 44), a second wiring 140B, and a second wiring 140C (second electrodes).

[0164] 16, in a plan view, the second wiring 140A (first electrode 52 and second electrode 44) is electrically connected to the first wiring 132J and the sixth transistor T6 via the second contact hole opening 138D and the first contact hole opening 135L. The second wiring 140B is electrically connected to the first wiring 132D, the first wiring 132H (second electrode 54), the first transistor T1, and the third transistor T3 via the second contact hole openings 138C and 138E and the first contact hole opening 135G. The second wiring 140C is electrically connected to the first wiring 132G, the gate wiring 127C, the fifth transistor T5 and the first wiring 132E (first electrode 42) via the second contact hole opening 138F and the first contact hole openings 135B, 135O and 135N.

[0165] 16, the second wiring 140A (first electrode 52 and second electrode 44), the first wiring 132E (first electrode 42), the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 overlaps with the capacitance element CV. The first electrode 42 and the first wiring 132H (second electrode 54) are disposed adjacent to each other on the gate electrode 622. That is, the capacitance elements CV and CD are disposed adjacent to each other.

[0166] An insulating layer 141 (organic insulating layer) (FIGS. 10 to 12) is formed on the conductive layer 139 and on the insulating layer 136 where the conductive layer 139 is not formed (step 22 (S22) in FIG. 13).

[0167] As shown in FIG. 9, an opening is made in the insulating layer 141 (organic insulating layer) (step 23 (S23) in FIG. 13). In the opening in S23, a contact hole opening 147 for the anode electrode is made. The contact hole opening 147 for the anode electrode removes the insulating layer 141 above the second wiring 140A, exposing the second wiring 140A. The contact hole opening 147 for the anode electrode is sometimes called an organic insulating layer opening. Note that, as shown in FIG. 9, the contact hole opening 147 for the anode electrode overlaps the second wiring 140C in a plan view.

[0168] An anode electrode 143 is provided on the exposed second wiring 140C, on the anode electrode contact hole opening 147, and on the insulating layer 141. A functional layer 148 is provided on the anode electrode 143 (FIG. 10). A common electrode 149 is provided on the functional layer 148 (step 24 (S24) in FIG. 13). Note that, for example, the anode electrode 143 and the functional layer 148 are provided for each pixel, and the common electrode 149 is provided so as to overlap the display region 22.

[0169] After S24, the sealing film 165 and the cover film 158 are provided in this order on the common electrode 149 (FIG. 10).

[0170] As shown in FIG. 13, the manufacturing of the display device 10 (pixel 180) is completed in this manner.

[0171] 2. Second Embodiment An overview of a display device according to the second embodiment will be described with reference to Fig. 1, Fig. 4, Fig. 17, and Fig. 18. Fig. 17 is a schematic diagram showing an input signal to a pixel 180A (pixel circuit 181A) according to the second embodiment, and Fig. 18 is a circuit diagram showing the configuration of the pixel circuit 181A.

[0172] The display device according to the second embodiment includes a pixel 180A and a pixel circuit 181A. The configurations of the pixel 180A and the pixel circuit 181A are different from the configurations of the pixel 180 and the pixel circuit 181 of the display device 10 according to the first embodiment. Specifically, the display device according to the second embodiment has a configuration and function in which a seventh transistor T7, an eighth transistor T8, and a reset voltage power supply line SVRE to which a reset voltage VRES is supplied are added to the configurations of the pixel 180 and the pixel circuit 181. The other configurations and functions are the same as those of the display device 10 according to the first embodiment. In describing the configuration and functions of the second embodiment, configurations and functions that are the same as those of the display device 10 according to the first embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 16 will be described as necessary.

[0173] <2-1. Configuration of pixel 180A> The pixel 180A and pixel circuit 181A will be outlined with reference to FIGS.

[0174] The pixel circuit 181A is connected to the reset voltage power supply line SVRE.

[0175] A reset voltage VRES is supplied to the reset voltage power supply line SVRE. For example, the reset voltage power supply line SVRE is electrically connected to a connection line 342 (FIG. 1) that is different from the drive power supply line PVDD and the reference voltage line PVSS. The reset voltage power supply line SVRE may also be one of the connection lines 342. For example, the reset voltage VRES may be supplied from an external device to the IC chip 110 (FIG. 1) in the same manner as the initialization voltage VINI, or may be supplied from the IC chip 110 to the plurality of pixels 180A (pixel circuits 181A) via the connection lines 342 and the reset voltage power supply line SVRE. Although not shown, the reset voltage VRES may be connected to the reset voltage power supply line SVRE from an external device via the FPC 200, the terminal unit 150, and the connection lines 341, rather than via the IC chip 110 and the connection lines 342, and may be supplied to the plurality of pixels 180A (pixel circuits 181A) in the same manner as the initialization voltage VINI.

[0176] The first electrode 624 of the second transistor T2 is separated from the second electrode 34 of the light-emitting element OLED and is electrically connected to the second electrode 676 of the seventh transistor T7. The other configurations of the second transistor T2 are similar to those of the pixel 180 and the pixel circuit 181.

[0177] The seventh transistor T7 functions to electrically connect the third node N3 and the second electrode 34 of the light-emitting element OLED. The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the scan signal line 330 and the gate electrode 632 of the third transistor T3. The first electrode 674 is electrically connected to the second electrode 34 of the light-emitting element OLED and the second electrode 686 of the eighth transistor T8. The second electrode 676 is electrically connected to the third node N3, the second electrode 656 of the fifth transistor T5, and the first electrode 42 of the capacitor CV. Similar to the configurations of the pixel 180 and the pixel circuit 181, a first scan signal SC1(n) is supplied to the scan signal line 330. The switching of the seventh transistor T7 is controlled using the first scan signal SC1(n). In other words, the seventh transistor T7 is controlled to be in a conductive state (ON state) or a non-conductive state (OFF state) by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the seventh transistor T7 is in a non-conductive state. When the signal supplied to the first scan signal SC1(n) is HI, the seventh transistor T7 is in a conductive state.

[0178] The eighth transistor T8 has a function of connecting the second electrode 34 of the light-emitting element OLED and the reset voltage power supply line SVRE to each other, thereby supplying the reset voltage VRES to the second electrode 34 of the light-emitting element OLED and resetting the light-emitting element OLED. Note that resetting can also be referred to as initialization. The eighth transistor T8 includes a gate electrode 682, a first electrode 684, and a second electrode 686. The gate electrode 682 is electrically connected to the scan signal line 331, the gate electrode 642 of the fourth transistor T4, and the gate electrode 662 of the sixth transistor T6. The first electrode 684 is electrically connected to the reset voltage power supply line SVRE. Similar to the configuration of the pixel 180 and the pixel circuit 181, a second scan signal SC2(n) is supplied to the scan signal line 331. The switching of the eighth transistor T8 is controlled using the second scan signal SC2(n). In other words, the eighth transistor T8 is controlled to be in a conductive state (ON state) or a non-conductive state (OFF state) by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the eighth transistor T8 is in a non-conductive state. When the signal supplied to the second scan signal SC2(n) is HI, the eighth transistor T8 is in a conductive state.

[0179] The configuration and functions of the pixel circuit 181A other than those described in "2-1. Configuration of the pixel 180A" are the same as those of the pixel circuit 181.

[0180] <2-2. Driving Method of Pixel Circuit 181A> A method for driving the display device (pixel circuit 181A) according to the second embodiment will be described. Compared with the configurations described in "1-5-1. First example of method for driving display device 10" to "1-5-4. Fourth example of method for driving display device 10", the method for driving the pixel circuit 181A includes the following (1) to (4).

[0181] (1) When HI is supplied to the first scan signal SC1(n), the seventh transistor T7 is in an on state, the third node N3 is electrically connected to the second electrode 34 of the light-emitting element OLED, and the light-emitting element OLED emits light or does not emit light (black) depending on the voltage supplied to the third node N3. (2) When LO is supplied to the first scan signal SC1(n), the seventh transistor T7 is in an off state, the third node N3 is not electrically connected to the second electrode 34 of the light-emitting element OLED, and the voltage supplied to the third node N3 is not supplied to the second electrode 34. (3) When HI is supplied to the second scan signal SC2(n), the eighth transistor T8 is in an on state, the second electrode 34 of the light-emitting element OLED is electrically connected to the reset voltage power supply line SVRE, and the reset voltage VRES is supplied to the second electrode 34 of the light-emitting element OLED. As a result, the light-emitting element OLED is reset. For example, the reset voltage VRES is 0 V, and the potential difference between the voltage supplied to the second electrode 34 of the light-emitting element OLED and the voltage supplied to the first electrode 32 of the light-emitting element OLED is 0 V, so the light-emitting element OLED does not emit light. (4) When LO is supplied to the second scan signal SC2(n), the eighth transistor T8 is in the off state, the second electrode 34 of the light-emitting element OLED is not electrically connected to the reset voltage power supply line SVRE, and the reset voltage VRES is not supplied to the second electrode 34 of the light-emitting element OLED.

[0182] The configurations and functions of the method for driving pixel circuit 181A other than those related to (1) to (4) above are the same as those described in "1-5-1. First example of a method for driving display device 10" to "1-5-4. Fourth example of a method for driving display device 10."

[0183] The driving method of pixel circuit 181A including the configuration described above is a driving method that allows for faster driving, similar to "1-5-1. First example of driving method of display device 10" to "1-5-4. Fourth example of driving method of display device 10", and is a driving method that allows period PWR to be executed within period PIN and period PVH, in parallel with period PIN and period PVH, and is a driving method that has a high degree of freedom for period PWR and is highly versatile.

[0184] 3. Third Embodiment An overview of the display device according to the third embodiment will be described with reference to Fig. 1, Fig. 4, and Fig. 19 to Fig. 24. Fig. 19 is a schematic diagram showing an input signal to a pixel 180B (pixel circuit 181B) according to the third embodiment, Fig. 20 is a circuit diagram showing the configuration of the pixel circuit 181B, and Fig. 21 to Fig. 24 are timing charts of the display device according to the third embodiment.

[0185] The display device according to the third embodiment includes a pixel 180B and a pixel circuit 181B. The configurations of the pixel 180B and the pixel circuit 181B are different from those of the pixel 180 and the pixel circuit 181 of the display device according to the first embodiment. Specifically, the display device according to the third embodiment has a configuration and function in which a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a constant-voltage power supply line SVS to which a constant voltage VSH is supplied are added to the configurations of the pixel 180 and the pixel circuit 181, and the connection of the light-emitting element OLED in the pixel 180 and the pixel circuit 181 is changed. The remaining configuration and function are the same as those of the display device 10 according to the first embodiment. In describing the configuration and function of the third embodiment, configurations and functions similar to those of the display device 10 according to the first embodiment or the display device according to the second embodiment will be described as necessary. Furthermore, configurations identical to or similar to those in FIGS. 1 to 18 will be described as necessary.

[0186] <3-1. Configuration of pixel 180B> The pixel 180B and pixel circuit 181B will be outlined with reference to FIGS.

[0187] The pixel circuit 181B is connected to the constant voltage power supply line SVS.

[0188] A constant voltage VSH is supplied to the constant-voltage power supply line SVS. For example, the constant-voltage power supply line SVS is electrically connected to a connection line 342 (FIG. 1) that is different from the initialization voltage power supply line SVI, the reference voltage power supply line SVR, the drive power supply line PVDD, and the reference voltage line PVSS. The constant-voltage power supply line SVS may also be one of the connection lines 342. For example, the constant voltage VSH may be supplied from an external device to the IC chip 110 (FIG. 1), or may be supplied from the IC chip 110 to the plurality of pixels 180A (pixel circuits 181A) via the connection lines 342 and the constant-voltage power supply line SVS. Although not shown, the constant voltage VSH may be connected to the constant-voltage power supply line SVS from the external device via the FPC 200, the terminal unit 150, and the connection line 341, without passing through the IC chip 110 and the connection line 342, and may be supplied to the plurality of pixels 180A (pixel circuits 181A).

[0189] The first electrode 624 of the second transistor T2 is not connected to the second electrode 34 of the light-emitting element OLED, but is electrically connected to the second electrode 676 of the seventh transistor T7. The second electrode 626 of the second transistor T2 is disconnected from the driving power line PVDD, and is electrically connected to the fifth node N5, the first electrode 694 of the ninth transistor T9, and the second electrode 606 of the tenth transistor T10. The other configurations of the second transistor T2 are similar to those of the pixel 180 and the pixel circuit 181.

[0190] A gate electrode 632 of the third transistor T3 is electrically connected to the scan signal line 330, as well as to a gate electrode 672 of the seventh transistor T7 and a gate electrode 692 of the ninth transistor T9. A second electrode 626 of the second transistor T2 is disconnected from the drive power supply line PVDD and is electrically connected to a fifth node N5, a first electrode 694 of the ninth transistor T9, and a second electrode 606 of the tenth transistor T10. Other configurations of the second transistor T2 are similar to those of the pixel 180 and the pixel circuit 181.

[0191] The seventh transistor T7 functions to connect the third node N3 and the reference voltage line PVSS. The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. As described above, the gate electrode 672 is electrically connected to the scan signal line 330, the gate electrode 632 of the third transistor T3, and the gate electrode 692 of the ninth transistor T9. The first electrode 674 is electrically connected to the reference voltage line PVSS. The switching of the seventh transistor T7 is controlled using a first scan signal SC1(n). In other words, the seventh transistor T7 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the seventh transistor T7 is in a non-conductive state. When the signal supplied to the first scan signal SC1(n) is HI, the seventh transistor T7 is in a conductive state.

[0192] The eighth transistor T8 functions to connect the first electrode 32 and the second electrode 34 of the light-emitting element OLED and supply a driving voltage VDDEL to the second electrode 696 of the ninth transistor T9. The eighth transistor T8 includes a gate electrode 682, a first electrode 684, and a second electrode 686. The gate electrode 682 is electrically connected to the scan signal line 331, the gate electrode 602 of the tenth transistor T10, the gate electrode 642 of the fourth transistor T4, and the gate electrode 662 of the sixth transistor T6. The first electrode 684 is electrically connected to the sixth node N6, the first electrode 32 of the light-emitting element OLED, and the second electrode 696 of the ninth transistor T9. The second electrode 686 is electrically connected to the driving power supply line PVDD. Similar to the configuration of the pixel 180 and the pixel circuit 181, a second scan signal SC2(n) is supplied to the scan signal line 331. The switching of the eighth transistor T8 is controlled using the second scan signal SC2(n). In other words, the conductive state (ON state) and non-conductive state (OFF state) of the eighth transistor T8 are controlled by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the eighth transistor T8 is in a non-conductive state. When the signal supplied to the second scan signal SC2(n) is HI, the eighth transistor T8 is in a conductive state.

[0193] The ninth transistor T9 has a function of connecting the sixth node N6 (the second electrode 696 of the ninth transistor T9) and the fifth node N5 (the first electrode 694 of the ninth transistor T9 and the second electrode 626 of the second transistor T2) to each other, thereby supplying a drive voltage VDDEL to the fifth node N5. The ninth transistor T9 includes a gate electrode 692, a first electrode 694, and a second electrode 696. The gate electrode 692 is electrically connected to the scan signal line 330, the gate electrode 632 of the third transistor T3, and the gate electrode 672 of the seventh transistor T7. The first electrode 694 is electrically connected to the fifth node N5, the second electrode 626 of the second transistor T2, and the second electrode 606 of the tenth transistor T10. Similar to the configuration of the pixel 180 and the pixel circuit 181, a first scan signal SC1(n) is supplied to the scan signal line 330. The switching of the ninth transistor T9 is controlled using the first scan signal SC1(n). In other words, the conductive state (ON state) and non-conductive state (OFF state) of the ninth transistor T9 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the ninth transistor T9 is in a non-conductive state. When the signal supplied to the first scan signal SC1(n) is HI, the ninth transistor T9 is in a conductive state.

[0194] The tenth transistor T10 has a function of connecting the fifth node N5 and the constant-voltage power supply line SVS electrically to supply a constant voltage VSH to the fifth node N5. The tenth transistor T10 includes a gate electrode 602, a first electrode 604, and a second electrode 606. The gate electrode 602 is electrically connected to the scan signal line 331. The first electrode 604 is electrically connected to the constant-voltage power supply line SVS. The second electrode 606 is electrically connected to the constant-voltage power supply line SVS. Similar to the configuration of the pixel 180 and the pixel circuit 181, a second scan signal SC2(n) is supplied to the scan signal line 331. The switching of the tenth transistor T10 is controlled using the second scan signal SC2(n). In other words, the conductive state (on state) and non-conductive state (off state) of the tenth transistor T10 are controlled by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the tenth transistor T10 is in a non-conductive state. When the signal supplied to the second scan signal SC2(n) is HI, the tenth transistor T10 is in a conductive state.

[0195] The configuration and functions of the pixel circuit 181B other than those described in "3-1. Configuration of the pixel 180B" are the same as those of the pixel circuit 181.

[0196] <3-2. Driving method of pixel circuit 181B> A method for driving a display device according to the third embodiment will be described with reference to Figures 21 to 24. Configurations that are the same as or similar to those in Figures 1 to 20 will be described as necessary. The timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the image data signal SL(m) including the data signal VDATA is the same as the configurations described in "1-5-1. First example of a method for driving a display device 10" to "1-5-4. Fourth example of a method for driving a display device 10."

[0197] The method for driving the display device according to the third embodiment includes the same period as the method for driving the display device 10 according to the first embodiment shown in FIG.

[0198] In one horizontal period (horizontal period HRP) in the driving method of the display device according to the third embodiment, the pixel 180B (pixel circuit 181B) receives an image data signal SL(m) including a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), an initialization voltage VINI, a reference voltage VREF, a constant voltage VSH, and a data signal VDATA. For example, the pixel 180B (pixel circuit 181B) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n). The image data signal SL(m) is input to the selected pixel 180B (pixel circuit 181B) according to the timing of each signal. A similar operation is performed for all pixels 180B (pixel circuits 181B), and based on the image data signals SL(m) input to all pixels 180B (pixel circuits 181B), an image of the frame corresponding to one frame is displayed in the display area 22 of the display device 10.

[0199] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0200] [Table 2]

[0201] For example, as shown in Table 2, the constant voltage VSH is 2.5 V. The set values ​​of the other voltages are the same as the set values ​​shown in Table 1 explained in "1-5. Method of driving the display device 10."

[0202] <3-2-1. First Example of Method for Driving Pixel Circuit 181B> 21 and Table 2, a first example of a method for driving the pixel circuit 181B will be described. Similar to the first example of the method for driving the display device 10 according to the first embodiment, this method involves displaying images of different colors in successive frames.

[0203] During the light-emission period PEM of the (K-1st) frame, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 are in an off state, and the third transistor T3, the seventh transistor T7, and the ninth transistor T9 are in an on state. For example, the voltage Vnk supplied to the first node N1 and the second node N2 is 3.8 V, the voltage supplied to the third node N3 is 0 V (reference voltage VSSEL), and the potential difference Vgs is 3.8 V. Therefore, the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds corresponding to the voltage VSIGH input during the horizontal period HRP of the (K-1st) frame. Furthermore, the second transistor T2 is in an on state, and the drain current Ion flows from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, pixel 180B (pixel circuit 181B) emits red light, and three pixels, including pixel 180B that emits red light, pixel 180B that emits blue light, and pixel 180B that emits green light, emit white light.

[0204] During the initial period of the period PIN of the Kth FRAME following the light emission period PEM of the K-1st FRAME, the third transistor T3, the seventh transistor T7, and the ninth transistor T9 change from an ON state to an OFF state, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 change from an OFF state to an ON state, and the first transistor T1 and the fifth transistor T5 maintain their OFF states. As a result, the voltages supplied to the first node N1 and the third node N3 maintain voltage Vnk, and the voltage supplied to the second node N2 gradually drops from voltage Vnk toward voltage Vnc (reference voltage VREF, 1.4V) to become voltage Vnc. Although not shown, the voltage supplied to the fourth node N4 gradually drops toward voltage Vnc (reference voltage VREF, 1.4V) to become voltage Vnc. The fifth node N5 is electrically connected to the constant-voltage power supply line SVS, and the voltage supplied to the fifth node N5 gradually drops from the voltage supplied during the light-emitting period PEM of the K-1st FRAME toward voltage VSH (2.5 V) and becomes voltage VSH. The sixth node N6 (the first electrode 32 of the light-emitting element OLED) is electrically connected to the second electrode 34 (drive voltage power supply line PVDD) of the light-emitting element OLED, and the voltage supplied to the sixth node N6 gradually rises from the voltage supplied during the light-emitting period PEM of the K-1st FRAME toward voltage VDDEL (8 V) and becomes voltage VDDEL. Although the second transistor T2 remains on, the ninth transistor T9 is off, and no current equivalent to the drain current Ion flows through the light-emitting element OLED, so the light-emitting element OLED does not emit light.

[0205] During period PIN following the beginning of period PIN, the fifth transistor T5 changes from an off state to an on state, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 maintain their on states, and the first transistor T1, the third transistor T2, the seventh transistor T7, and the ninth transistor T9 maintain their off states.

[0206] As a result, the voltage supplied to the first node N1 maintains voltage Vnk, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain voltage Vnc, the voltage supplied to the fifth node N5 maintains voltage VSH, and the voltage supplied to the sixth node N6 maintains voltage VDDEL. The voltage supplied to the third node N3 gradually drops from 0 V toward voltage Vnd (initialization voltage VINI, −2 V) and reaches voltage Vnd. The potential difference Vgs becomes 3.4 V (1.4 V − (−2 V)), and the potential difference Vds becomes 4.5 V (2.5 V − (−2 V)). Although the second transistor T2 is in an on state, the ninth transistor T9 is in an off state, and the light-emitting element OLED does not emit light. At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vnk supplied to the first node N1 and the voltage Vnc supplied to the fourth node N4, and maintains this potential difference, and the capacitive element CV holds a charge equivalent to the potential difference between the voltage Vnc supplied to the fourth node N4 and the voltage Vnd supplied to the third node N3, and maintains this potential difference. The voltage supplied to the fourth node N4 is the same as the voltage supplied to the second node N2, and the capacitive element CV maintains the potential difference Vgs (the potential difference between the voltage supplied to the gate electrode 622 and the voltage supplied to the first electrode 624 of the second transistor T2).

[0207] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (−2 V).

[0208] During the period PVH following the period PIN, the fifth transistor T5 changes from the on state to the off state, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 maintain the on state, and the first transistor T1, the third transistor T2, the seventh transistor T7, and the ninth transistor T9 maintain the off state.

[0209] As a result, the voltage supplied to the first node N1 maintains voltage Vnk, and the voltages supplied to the second node N2 and the fourth node N4 maintain voltage Vnc. The voltage supplied to the fifth node N5 maintains voltage VSH, and the voltage supplied to the sixth node N6 maintains voltage VDDEL. The voltage supplied to the third node N3 gradually increases from voltage Vnd toward voltage Vnf. As in "1-5-1. First Example of the Method for Driving the Display Device 10," the voltage supplied to the third node N3 may become voltage Vnf, and voltage Vnf (0.4 V) is the voltage at which the potential difference Vgs becomes the threshold voltage VTH (1 V) of the second transistor T2.

[0210] During the period PWR that is parallel to (overlaps with) the period PVH, the first transistor T1 changes from an OFF state to an ON state, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 maintain an ON state, and the first transistor T1, the third transistor T2, the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 maintain an OFF state. As in "1-5-1. First Example of the Driving Method of the Display Device 10," the period during which the fourth scan signal SC4(n) is supplied HI (period PWR (horizontal shift HRP)) may be longer than the period shown in FIG. 5, shorter than the period during which the second scan signal SC2(n) is supplied HI, longer than period PIN, the same as period PIN, or shorter than period PIN.

[0211] As a result, the voltage supplied to the first node N1 gradually drops toward voltage Vne (voltage VSIGL (0.2 V)) and becomes voltage Vne, while the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain voltage Vnc. The voltage supplied to the third node N3 gradually rises from voltage Vnd toward voltage Vnf. Note that the voltage supplied to the third node N3 may become voltage Vnf. The voltage supplied to the fifth node N5 maintains voltage VSH, and the voltage supplied to the sixth node N6 maintains voltage VDDEL. At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vne supplied to the first node N1 and the voltage Vnc supplied to the fourth node N4, and maintains this potential difference. That is, the capacitive element CD holds a charge equivalent to the potential difference between the voltage of the data signal VDATA and the reference voltage VREF, and maintains (holds) the voltage included in the data signal VDATA.

[0212] In this way, during the period PWR, the data signal VDATA is written to the pixel 180B (pixel circuit 181B). The capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0213] In the period PVH after the period PWR, the first transistor T1 changes from the on state to the off state, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 maintain the on state, and the third transistor T1, the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 maintain the off state. After the first transistor T1 changes to the off state, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 change from the on state to the off state.

[0214] As a result, the voltage supplied to the first node N1 maintains voltage Vne, and the voltages supplied to the second node N2 and the fourth node N4 maintain voltage Vnc. The voltage supplied to the third node N3 gradually increases from voltage Vnd to voltage Vnf, reaching voltage Vnf. The voltage supplied to the fifth node N5 maintains voltage VSH, and the voltage supplied to the sixth node N6 maintains voltage VDDEL. At this time, the potential difference Vgs is equal to the threshold voltage VTH (1 V), and the second transistor T2 is in the off state. Therefore, no current equivalent to the drain current Ion flows, and the light-emitting element OLED does not emit light. Furthermore, as described above, the voltage supplied to the fourth node N4 is equal to the voltage supplied to the second node N2, and the capacitance element CV maintains the potential difference Vgs, so the capacitance element CV maintains the threshold voltage VTH.

[0215] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0216] During the light emission period PEM of the KthFRAME following the period PVH of the KthFRAME, the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 maintain their off states, and the third transistor T3, the seventh transistor T7, and the ninth transistor T9 change from their off states to their on states. At this time, the sixth node N6 is electrically connected to the fifth node N5, the second transistor T2 is electrically connected to the light-emitting element OLED, and the third node N3 is electrically connected to the reference voltage power supply line PVSS.

[0217] As a result, the voltage supplied to the third node N3 drops from voltage Vnf toward the reference voltage VSSEL (0 V) and becomes 0 V. Furthermore, as will be described later, because the second transistor T2 is turned off, the voltage supplied to the fifth node N5 rises from the constant voltage VSH (2.5 V) toward the drive voltage VDDEL (8 V) and becomes 8 V. As the first node N1 and the second node N2 become conductive and the voltage supplied to the third node N3 drops, the voltage supplied to the second node N2 gradually drops from voltage Vne toward voltage Vnj (e.g., −0.2 V) and becomes voltage Vnj, and the voltage supplied to the first node N1 connected to the second node N2 also gradually drops from voltage Vnc toward voltage Vnj and becomes voltage Vnj.

[0218] At this time, the potential difference Vgs is the sum of the potential difference held in the capacitance element CD and the potential difference held in the capacitance element CV (the voltage included in the data signal VDATA (voltage VSIGL, 0.2 V) - the reference voltage VREF (1.4 V) + the threshold voltage VTH (1 V) = -0.2 V). That is, during the light emission period PEM of KthFRAME, the pixel 180B (pixel circuit 181B) can display an image based on the data signal VDATA and the corrected threshold.

[0219] Specifically, since the potential difference Vds is 8 V and the potential difference Vgs (-0.2 V) is lower (smaller) than the threshold voltage VTH, the second transistor T2 is in an off state, and no current flows from the drive power supply line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. As a result, the pixel 180B (pixel circuit 181B) that emits red light turns black. Similarly to the pixel 180B that emits red light, the pixel 180B that emits blue light and the pixel 180B that emits green light also do not emit light, so the three pixels that use the pixel 180B that emits red light, the pixel 180B that emits blue light, and the pixel 180B that emits green light turn black.

[0220] The display device according to the third embodiment, like "1-5-1. First example of a method for driving the display device 10" to "1-5-4. Fourth example of a method for driving the display device 10", is capable of speeding up driving, and the period PWR can be executed within the periods PIN and PVH, in parallel with the periods PIN and PVH, making it a display device with a high degree of freedom for the period PWR and high versatility.

[0221] Furthermore, during the period PVH of the display device according to the third embodiment, the second transistor T2 is not connected (disconnected) from the light-emitting element OLED, the voltage supplied to the second electrode 626 of the second transistor T2 is the constant voltage VSH, and the voltage supplied to the second electrode 44 of the capacitance element CV is the reference voltage VREF. That is, because a constant voltage is supplied to the gate electrode 622 (second node N2) and the second electrode 626 of the second transistor T2 and the second transistor T2 is not connected (disconnected) from the light-emitting element OLED, the parasitic capacitance added to the second transistor T2 is small. Therefore, the time required for the capacitance element CV to hold the potential difference Vgs (charge) corresponding to the threshold voltage VTH is shorter than in a configuration in which the second transistor T2 is connected (not disconnected) from the light-emitting element OLED. Therefore, the driving method of the display device (pixel circuit 181B) according to the third embodiment can shorten the time required for the threshold voltage VTH to be acquired and for the capacitance element CV to hold the charge corresponding to the threshold voltage VTH.

[0222] <3-2-2. Second Example of Method for Driving Pixel Circuit 181B> A second example of a method for driving the pixel circuit 181B will be described with reference to Fig. 22. The driving method shown in the second example of the pixel circuit 181B includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 21 will be described as necessary.

[0223] The first node N1 and other components during the period excluding the KthFRAME period PWR, the period PVH after the KthFRAME period PWR, and the light-emitting period PEM of the KthFRAME are similar to the configurations described in "3-2-1. First Example of a Method for Driving the Pixel Circuit 181B." Furthermore, the voltages (potentials) of the second node N2, the third node N3, and the fourth node N4 during the period excluding the light-emitting period PEM of the KthFRAME are similar to the configurations described in "3-2-1. First Example of a Method for Driving the Pixel Circuit 181B." Furthermore, the operation of each transistor during each period is similar to the configurations described in "3-2-1. First Example of a Method for Driving the Pixel Circuit 181B." Therefore, configurations similar to those described in "3-2-1. First Example of a Method for Driving the Pixel Circuit 181B" will be described as necessary. In addition, as for the image data signal SL(m), during the KthFRAME period PWR, a data signal VDATA including VSIGH corresponding to white is supplied, and during periods other than the KthFRAME period PWR, a data signal VDATA similar to the configuration described in "3-2-1. First example of the driving method for pixel circuit 181B" is supplied.

[0224] During the light emission period PEM of the K-1st FRAME, similar to the configuration described in "3-2-1. First example of the driving method of the pixel circuit 181B", the drain current Ion flows from the driving power supply line PVDD to the light emitting element OLED and the reference voltage line PVSS, and the light emitting element OLED emits light.

[0225] During the initial period and period PIN of the KthFRAME following the light emission period PEM of the K-1stFRAME, similar to the configuration described in "3-2-1. First example of driving method for pixel circuit 181B", the second node N2 and the fourth node N4 are initialized by the reference voltage VREF (1.4V), the third node N3 is initialized by the initialization voltage VINI (-2V), the voltage supplied to the fifth node N5 is the voltage VSH, and the voltage supplied to the sixth node N6 is the voltage VDDEL.

[0226] During the period PVH following the period PIN, similar to the configuration described in "3-2-1. First example of the method for driving the pixel circuit 181B", the voltage supplied to the first node N1 maintains the voltage Vnk, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain the voltage Vnc, the voltage supplied to the fifth node N5 maintains the voltage VSH, the voltage supplied to the sixth node N6 maintains the voltage VDDEL, and the voltage supplied to the third node N3 gradually rises from the voltage Vnd towards the voltage Vnf.

[0227] During the period PVH, a period PWR is executed, which is parallel to (overlaps with) the period PVH. During the period PWR, the image data signal SL(m) is supplied with a voltage VSIGH (4.2V). The voltage supplied to the first node N1 gradually increases toward voltage Vnh (voltage VSIGH (4.2V)) and reaches voltage Vnh. The voltages supplied to the second node N2 and the fourth node N4 maintain voltage Vnc. The voltage supplied to the third node N3 gradually increases from voltage Vnd toward voltage Vnf. At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage contained in the data signal VDATA and the reference voltage VREF, and maintains (holds) the voltage contained in the data signal VDATA. The voltage supplied to the fifth node N5 maintains voltage VSH, and the voltage supplied to the sixth node N6 maintains voltage VDDEL.

[0228] In this way, during the period PWR, the data signal VDATA is written to the pixel 180B (pixel circuit 181B). The capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0229] During the period PVH following the period PWR, the voltage supplied to the first node N1 maintains the voltage Vnh, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain the voltage Vnc, the voltage supplied to the fifth node N5 maintains the voltage VSH, and the voltage supplied to the sixth node N6 maintains the voltage VDDEL. The voltage supplied to the third node N3 gradually increases from the voltage Vnd toward the voltage Vnf and reaches the voltage Vnf. At this time, similar to the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," the second transistor T2 is in the off state, and no drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light, the capacitance element CV maintains the potential difference Vgs, and the threshold voltage VTH is maintained.

[0230] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0231] During the light emission period PEM of the Kth FRAME, the first node N1 is electrically connected to the second node N2, and the voltage supplied to the second node N2 gradually rises from voltage Vnc to voltage Vnh (4.2 V). As a result, the second transistor T2 is electrically connected, and a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS. As will be described later, the sum of the potential difference held in the capacitance element CD and the potential difference held in the capacitance element CV is 3.8 V, and the potential of the first electrode 42 of the low-potential side capacitance element CV is connected to VSSEL and becomes 0 V. Therefore, the potential of the second electrode 54 of the high-potential side capacitance element CD drops from 3.8 V. In other words, the potential of the first node N1 drops from voltage Vnh (4.2 V), and the potential of the second node N2 connected to the first node N1 only rises to 3.8 V (voltage Vnk). Therefore, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 become 3.8V (voltage Vnk). Also, the voltage supplied to the third node N3 drops from voltage Vnf toward the reference voltage VSSEL (0V) and becomes 0V. At this time, the sixth node N6 is electrically connected to the fifth node N5.

[0232] At this time, the potential difference Vgs is the sum of the potential difference held in the capacitance element CD and the potential difference held in the capacitance element CV (the voltage included in the data signal VDATA (voltage VSIGH, 4.2 V) - the reference voltage VREF (1.4 V) + the threshold voltage VTH (1 V) = 3.8 V). That is, during the light emission period PEM of KthFRAME, the pixel 180B (pixel circuit 181B) can display an image based on the data signal VDATA and the corrected threshold. For example, the potential difference Vgs (3.8 V) is greater than the threshold voltage VTH (1 V), the second transistor T2 is in the on state, and a drain current Ion flows from the drive power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180B (pixel circuit 181B) emits red light, and the three pixels, including the pixel 180B that emits blue and the pixel 180B that emits green, emit white light.

[0233] The second example of the method for driving the pixel circuit 181B has the same effects as those described in "3-2-1. First example of the method for driving the pixel circuit 181B."

[0234] <3-2-3. Third Example of Method for Driving Pixel Circuit 181B> A third example of a method for driving the pixel circuit 181B will be described with reference to Fig. 23. The third example of a method for driving the pixel circuit 181B includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 22 will be described as necessary.

[0235] During the light emission period PEM of the K-1st FRAME, the voltages supplied to the first node N1 and the second node N2 are voltage Vnj, the voltage supplied to the third node N3 is 0 V, and the potential difference Vgs is −0.2 V. Therefore, the second transistor T2 is in an off state, the drain current Ion does not flow from the drive power supply line PVDD to the light emitting element OLED and the reference voltage line PVSS, and the pixel 180B (pixel circuit 181B) that emits red light is black. Similarly to the pixel 180B that emits red light, the pixel 180B that emits blue light and the pixel 180B that emits green light also do not emit light, so the three pixels that use the pixel 180B that emits red light, the pixel 180B that emits blue light, and the pixel 180B that emits green light are black.

[0236] During the initial period of the period PIN of the Kth FRAME, which follows the light-emission period PEM of the K-1st FRAME, the voltage supplied to the first node N1 remains at voltage Vnj. The voltage supplied to the second node N2 gradually rises from voltage Vnj toward voltage Vnc (reference voltage VREF, 1.4V) and reaches voltage Vnc. The voltage supplied to the third node N3 remains at 0V. Although not shown, the voltage supplied to the fourth node N4 gradually rises toward voltage Vnc (reference voltage VREF, 1.4V) and reaches voltage Vnc. As with the configuration described in "3-2-1. First Example of the Method for Driving Pixel Circuit 181B," the fifth node N5 is electrically connected to the constant-voltage power supply line SVS, and the voltage supplied to the fifth node N5 gradually drops from the voltage supplied during the light-emission period PEM of the K-1st FRAME toward voltage VSH (2.5V) and reaches voltage VSH. The sixth node N6 (first electrode 32 of the light-emitting element OLED) is electrically connected to the second electrode 34 (driving voltage power supply line PVDD) of the light-emitting element OLED, and the voltage supplied to the sixth node N6 gradually rises from the voltage supplied during the light-emitting period PEM of the K-1st FRAME toward the voltage VDDEL (8 V) and reaches the voltage VDDEL. Since the second transistor T2 is in the off state and no drain current Ion flows through the light-emitting element OLED, the light-emitting element OLED does not emit light.

[0237] During the period PIN following the beginning of the period PIN, the voltage supplied to the first node N1 maintains voltage Vnj, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain voltage Vnc, the voltage supplied to the fifth node N5 maintains voltage VSH, and the voltage supplied to the sixth node N6 maintains voltage VDDEL. The voltage supplied to the third node N3 gradually drops from voltage Vng toward voltage Vnd (initialization voltage VINI, −2V) and reaches voltage Vnd. The potential difference Vgs becomes 3.4V (1.4V−(−2V)), and the potential difference Vds becomes 10V (8V−(−2V)). Similar to the configuration described in “3-2-1. First Example of the Method for Driving the Pixel Circuit 181B,” the second transistor T2 changes from an off state to an on state, but the ninth transistor T9 is in an off state, and the light-emitting element OLED does not emit light. At this time, the capacitance element CD holds a charge equivalent to the potential difference between the voltage Vnj supplied to the first node N1 and the voltage Vnc supplied to the fourth node N4 and maintains the potential difference, and the capacitance element CV maintains the potential difference Vgs.

[0238] As described above, similar to the configuration described in "3-2-1. First example of driving method for pixel circuit 181B", during the period PIN, the second node N2 and the fourth node N4 are initialized by the reference voltage VREF (1.4V), and the third node N3 is initialized by the initialization voltage VINI (-2V).

[0239] During the period PVH following the period PIN, the voltage supplied to the first node N1 maintains the voltage Vnj, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain the voltage Vnc, the voltage supplied to the fifth node N5 maintains the voltage VSH, the voltage supplied to the sixth node N6 maintains the voltage VDDEL, and the voltage supplied to the third node N3 gradually rises from the voltage Vnd toward the voltage Vnf.

[0240] During the period PWR that is parallel to (overlaps with) the period PVH, the voltage supplied to the first node N1 gradually increases toward voltage Vne (voltage VSIGL (0.2 V)) and reaches voltage Vne, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain voltage Vnc, the voltage supplied to the fifth node N5 maintains voltage VSH, the voltage supplied to the sixth node N6 maintains voltage VDDEL, and the voltage supplied to the third node N3 gradually increases from voltage Vnd toward voltage Vnf. At this time, similar to the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," the capacitive element CD holds a charge equivalent to the potential difference between the voltage included in the data signal VDATA and the reference voltage VREF as a reference, and also maintains (holds) the voltage included in the data signal VDATA with reference to the reference voltage VREF.

[0241] As described above, in the same manner as in the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," during the period PWR, the data signal VDATA is written to the pixel 180B (pixel circuit 181B). Also, the capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0242] During the period PVH following the period PWR, similar to the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," the voltage supplied to the first node N1 maintains the voltage Vne, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain the voltage Vnc, the voltage supplied to the fifth node N5 maintains the voltage VSH, the voltage supplied to the sixth node N6 maintains the voltage VDDEL, and the voltage supplied to the third node N3 gradually increases from the voltage Vnd toward the voltage Vnf and reaches the voltage Vnf. Furthermore, the second transistor T2 is in an off state, and no current corresponding to the drain current Ion flows, so the light-emitting element OLED does not emit light. Furthermore, the capacitance element CV maintains the potential difference Vgs, and the capacitance element CV maintains the threshold voltage VTH.

[0243] In this way, similar to the configuration described in "3-2-1. First example of the method for driving the pixel circuit 181B," during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0244] During the light emission period PEM of the KthFRAME following the period PVH of the KthFRAME, similar to the configuration described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B," the first node N1 is electrically connected to the second node N2, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 become voltage Vnj, and the voltage supplied to the third node N3 becomes 0 V. At this time, the sixth node N6 is electrically connected to the fifth node N5. As a result, similar to the configuration described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B," the pixel 180B that emits red, the pixel 180B that emits blue, and the pixel 180B that emits green do not emit light, and therefore the three pixels using the pixel 180B that emits red, the pixel 180B that emits blue, and the pixel 180B that emits green appear black.

[0245] The third example of the method for driving the pixel circuit 181B has the same effects as those described in "3-2-1. First example of the method for driving the pixel circuit 181B."

[0246] <3-2-4. Fourth Example of Method for Driving Pixel Circuit 181B> A fourth example of a method for driving the pixel circuit 181B will be described with reference to Fig. 24. The fourth example of a method for driving the pixel circuit 181B includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 23 will be described as necessary.

[0247] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) and the image data signal SL(m) are the same as those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the voltages (potentials) of the second node N2, the third node N3, and the fourth node N4 during the light-emitting period PEM of the K-1st FRAME to the period PVH of the Kth FRAME, and the period PWR executed in parallel with the period PVH of the Kth FRAME, are the same as those described in "3-2-3. Third Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the first node N1 during the light-emitting period PEM of the K-1st FRAME, the period PIN of the Kth FRAME, and the period PVH between the period PIN and the period PWR are the same as those described in "3-2-3. Third Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2, the third node N3, and the voltage (potential) of the fourth node N4 during the period PVH after the period PWR of the KthFRAME to the light emission period PEM of the KthFRAME are the same as those described in "3-2-2. Second Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the operation of each transistor during each period is the same as those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B." Therefore, configurations similar to those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B" to "3-2-3. Third Example of the Method for Driving the Pixel Circuit 181B" will be described as necessary.

[0248] In the light emission period PEM of the (K-1st) frame, the pixel 180B (pixel circuit 181B) turns black, as explained in "3-2-3. Third example of the method for driving the pixel circuit 181B."

[0249] During the period PIN of KthFRAME, as in "3-2-3. Third Example of the Method of Driving the Pixel Circuit 181B," the light-emitting element OLED does not emit light, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vnj supplied to the first node N1 and the voltage Vnc supplied to the fourth node N4 and maintains this potential difference, and the capacitive element CV maintains the potential difference Vgs. Also, during the period PIN, the second node N2 and the fourth node N4 are initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (-2 V).

[0250] During the period PVH between the period PIN and the period PWR of KthFRAME, as in "3-2-3. Third example of the method for driving pixel circuit 181B," the voltage supplied to the first node N1 maintains the voltage Vnj, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain the voltage Vnc, the voltage supplied to the fifth node N5 maintains the voltage VSH, the voltage supplied to the sixth node N6 maintains the voltage VDDEL, and the voltage supplied to the third node N3 gradually rises from the voltage Vnd toward the voltage Vnf.

[0251] During the period PWR of KthFRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage Vnh (voltage VSIGH (4.2V)) and reaches voltage Vnh. The voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain voltage Vnc, the voltage supplied to the fifth node N5 maintains voltage VSH, the voltage supplied to the sixth node N6 maintains voltage VDDEL, and the voltage supplied to the third node N3 gradually increases from voltage Vnd toward voltage Vnf.

[0252] During the period PVH after the period PWR of KthFRAME, as in "3-2-2. Second Example of the Method for Driving Pixel Circuit 181B," the voltage supplied to the first node N1 maintains the voltage Vnh, the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 maintain the voltage Vnc, the voltage supplied to the fifth node N5 maintains the voltage VSH, the voltage supplied to the sixth node N6 maintains the voltage VDDEL, and the voltage supplied to the third node N3 becomes the voltage Vnf. Furthermore, the light-emitting element OLED does not emit light, and the capacitance element CV maintains the potential difference Vgs and holds the threshold voltage VTH. As a result, during the period PVH, the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, thereby acquiring the threshold voltage VTH of the second transistor T2, and holding a charge equivalent to the threshold voltage VTH in the capacitance element CV.

[0253] During the light-emitting period PEM of the KthFRAME, which follows the period PVH after the period PWR of the KthFRAME, similar to "3-2-2. Second Example of the Driving Method of the Pixel Circuit 181B," the first node N1 and the second node N2 are electrically connected, the second transistor T2 is in a conductive state, and a drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS. The potential difference Vgs is the sum (3.8 V) of the potential difference held in the capacitance element CD and the potential difference held in the capacitance element CV. The voltage supplied to the first node N1 and the voltage supplied to the second node N2 connected to the first node N1 are 3.8 V (voltage Vnk). Therefore, the potential difference Vgs (3.8 V) is greater than the threshold voltage VTH (1 V), and the drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, white light is emitted by three pixels using a pixel 180B (pixel circuit 181B) that emits red light, a pixel 180B that emits blue light, and a pixel 180B that emits green light.

[0254] The fourth example of the method for driving the pixel circuit 181B has the same effects as those described in "3-2-1. First example of the method for driving the pixel circuit 181B."

[0255] 4. Fourth Embodiment An overview of a display device according to the fourth embodiment will be described with reference to Fig. 1, Fig. 4, Fig. 25, and Fig. 26. Fig. 25 is a schematic diagram showing an input signal to a pixel 180C (pixel circuit 181C) according to the fourth embodiment, and Fig. 26 is a circuit diagram showing the configuration of the pixel circuit 181C.

[0256] The display device according to the fourth embodiment includes a pixel 180C and a pixel circuit 181C. The configurations of the pixel 180C and the pixel circuit 181C are different from those of the pixel 180A and the pixel circuit 181A of the display device according to the second embodiment. Specifically, the display device according to the fourth embodiment has a configuration and function obtained by removing the configuration related to the eighth transistor T8 and the reset voltage power supply line SVRE to which the reset voltage VRES is supplied from the configurations of the pixel 180A and the pixel circuit 181A. The other configurations and functions are the same as those of the display device according to the second embodiment. In describing the configuration and functions of the fourth embodiment, configurations and functions similar to those of the display device 10 according to the first embodiment, the display device according to the second embodiment, and the display device according to the third embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 24 will be described as necessary.

[0257] <4-1. Configuration of pixel 180C> The pixel 180C and pixel circuit 181C will be outlined with reference to FIGS.

[0258] As described above, the pixel circuit 181C has a configuration in which the components related to the eighth transistor T8 and the reset voltage power supply line SVRE to which the reset voltage VRES is supplied are removed from the pixel circuit 181A. Therefore, the pixel circuit 181C does not include the eighth transistor T8 and the reset voltage VRES, the seventh transistor T7 and the light-emitting element OLED are not electrically connected to the eighth transistor T8, and the first electrode 674 of the seventh transistor T7 is electrically connected to the second electrode 34 of the light-emitting element OLED.

[0259] The configuration and functions of the pixel circuit 181C other than those described in "4-1. Configuration of the pixel 180C" are the same as those of the pixel circuit 181A.

[0260] <4-2. Driving method of pixel circuit 181C> A method for driving the display device (pixel circuit 181C) according to the fourth embodiment will be described. Compared to the configuration described in "2-2. Method for driving pixel circuit 181A," the method for driving the pixel circuit 181C does not include configurations and functions related to the operation of the eighth transistor T8.

[0261] The configuration and functions other than those related to the operation of the eighth transistor T8 in the method for driving the pixel circuit 181C are the same as those described in "2-2. Method for driving the pixel circuit 181A."

[0262] The driving method of the pixel circuit 181C including the configuration described above is a driving method that can increase the speed at which data is written to the first node N1, similar to "1-5-1. First example of a method for driving the display device 10" to "1-5-4. Fourth example of a method for driving the display device 10", and is a driving method that can execute the period PWR within the periods PIN and PVH, in parallel with the periods PIN and PVH, and is a driving method that has a high degree of freedom for the period PWR and is highly versatile.

[0263] 5. Fifth Embodiment An overview of a display device according to the fifth embodiment will be described with reference to Fig. 1, Fig. 4, Fig. 27, and Fig. 28. Fig. 27 is a schematic diagram showing an input signal to a pixel 180D (pixel circuit 181D) according to the fifth embodiment, and Fig. 28 is a circuit diagram showing the configuration of the pixel circuit 181D.

[0264] The display device according to the fifth embodiment includes a pixel 180D and a pixel circuit 181D. The configurations of the pixel 180D and the pixel circuit 181D are different from the configurations of the pixel 180 and the pixel circuit 181 of the display device 10 according to the first embodiment. Specifically, the display device according to the fifth embodiment has a configuration and function in which the reference voltage power supply line SVR in the configuration of the pixel 180 and the pixel circuit 181 is separated into a first reference voltage power supply line SVR to which a first reference voltage VREF1 is supplied and a reference voltage power supply line SVR2 to which a second reference voltage VREF2 is supplied. The other configurations and functions are the same as those of the display device 10 according to the first embodiment. In describing the configuration and functions of the fifth embodiment, configurations and functions that are the same as those of the display device 10 according to the first embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 26 will be described as necessary.

[0265] <5-1.Configuration of pixel 180D> The pixel 180D and pixel circuit 181D will be outlined with reference to FIGS.

[0266] The pixel circuit 181D is connected to the first reference voltage power supply line SVR and the second reference voltage VREF2.

[0267] The first reference voltage power line SVR is supplied with a first reference voltage VREF1. The second reference voltage power line SVR2 is supplied with a second reference voltage VREF2. For example, each of the first reference voltage power line SVR and the second reference voltage power line SVR2 is electrically connected to a connection wiring 342 (FIG. 1) that is different from the connection wiring 342 that is connected to the initialization voltage power line SVI, the drive power line PVDD, and the reference voltage line PVSS. Furthermore, each of the first reference voltage power line SVR and the second reference voltage power line SVR2 may be one of the connection wirings 342. For example, the first reference voltage VREF1, like the initialization voltage VINI, may be supplied from an external device to the IC chip 110 (FIG. 1), or may be supplied from the IC chip 110 to the plurality of pixels 180D (pixel circuits 181D) via the connection wiring 342 and the first reference voltage power line SVR. The second reference voltage VREF2 may be supplied from an external device to the IC chip 110 (FIG. 1), similar to the initialization voltage VINI, or may be supplied from the IC chip 110 to the plurality of pixels 180D (pixel circuits 181D) via the connection wiring 342 and the second reference voltage power line SVR2. Although not shown, similar to the initialization voltage VINI, the first reference voltage VREF1 and the second reference voltage VREF2 may be connected to the first reference voltage power line SVR and the second reference voltage power line SVR2 from the external device via the FPC 200, the terminal unit 150, and the connection wiring 341, respectively, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to the plurality of pixels 180D (pixel circuits 181D).

[0268] The fourth transistor T4 has a function of electrically connecting the second node N2 and the first reference voltage power line SVR. A first electrode 644 of the fourth transistor T4 is electrically connected to the first reference voltage power line SVR. Other configurations of the fourth transistor T4 are similar to those of the pixel 180 and the pixel circuit 181.

[0269] The sixth transistor T6 has a function of connecting the fourth node N4 and the second reference voltage power line SVR2. A first electrode 664 of the sixth transistor T6 is electrically connected to the second reference voltage power line SVR2. Other configurations of the sixth transistor T6 are similar to those of the pixel 180 and the pixel circuit 181.

[0270] The configuration and functions of the pixel circuit 181D other than those described in "5-1. Configuration of the pixel 180D" are the same as those of the pixel circuit 181.

[0271] <5-2. Driving method of pixel circuit 181D> A method for driving a display device (pixel circuit 181D) according to the fifth embodiment will be described. Compared with the configurations described in "1-5-1. First example of method for driving display device 10" to "1-5-4. Fourth example of method for driving display device 10", the method for driving pixel circuit 181D includes the following (1) to (4).

[0272] (1) When the second scan signal SC2(n) is HI, the fourth transistor T4 is ON, the second node N2 is electrically connected to the first reference voltage power line SVR, and the voltage supplied to the second node N2 is the first reference voltage VREF1. For example, the first reference voltage VREF1 is 1.4 V, the same as the reference voltage VREF. (2) When LO is supplied to the second scan signal SC2(n), the fourth transistor T4 is in the off state, the second node N2 is not electrically connected to the first reference voltage power supply line SVR, and the first reference voltage VREF1 is not supplied to the second node N2. (3) When the second scan signal SC2(n) is HI, the sixth transistor T6 is on, the fourth node N4 is electrically connected to the second reference voltage power supply line SVR2, and the voltage supplied to the fourth node N4 is the second reference voltage VREF2. For example, the second reference voltage VREF2 is 1.9 V. (4) When LO is supplied to the second scan signal SC2(n), the sixth transistor T6 is in the off state, the fourth node N4 is not electrically connected to the second reference voltage power supply line SVR2, and the second reference voltage VREF2 is not supplied to the fourth node N4.

[0273] The configurations and functions of the method for driving pixel circuit 181D other than those related to (1) to (4) above are the same as those described in "1-5-1. First example of a method for driving display device 10" to "1-5-4. Fourth example of a method for driving display device 10."

[0274] The driving method of the pixel circuit 181D including the configuration described above is a driving method that can increase the speed at which data is written to the first node N1, similar to "1-5-1. First example of driving method of the display device 10" to "1-5-4. Fourth example of driving method of the display device 10", and is a driving method that can execute the period PWR within the periods PIN and PVH, in parallel with the periods PIN and PVH, and is a driving method that has a high degree of freedom for the period PWR and is highly versatile.

[0275] Furthermore, the second reference voltage VREF2 is a voltage (intermediate potential) approximately intermediate between the voltage supplied to the first node N1 and the voltage supplied to the fourth node N4. As a result, the potential difference between the voltage supplied to the first electrode 52 of the capacitance element CD and the voltage supplied to the second electrode 54 becomes the same as the potential difference between the voltage supplied to the first electrode 42 of the capacitance element CV and the voltage supplied to the second electrode 44. Therefore, the potential difference of the capacitance element CD in the display device according to the fifth embodiment can be prevented from being significantly different from the potential difference of the capacitance element CV. In other words, the display device according to the fifth embodiment can distribute the voltages applied to the capacitance elements CD and CV, thereby reducing the load on the capacitance elements CD and CV.

[0276] 6. Sixth Embodiment An overview of a display device according to the sixth embodiment will be described with reference to Fig. 1, Fig. 4, Fig. 29, and Fig. 30. Fig. 29 is a schematic diagram showing an input signal to a pixel 180E (pixel circuit 181E) according to the sixth embodiment, and Fig. 30 is a circuit diagram showing the configuration of the pixel circuit 181E.

[0277] The display device according to the sixth embodiment includes a pixel 180E and a pixel circuit 181E. The configurations of the pixel 180E and the pixel circuit 181E are different from the configurations of the pixel 180 and the pixel circuit 181 of the display device 10 according to the first embodiment. Specifically, the display device according to the sixth embodiment has a configuration and function in which the connection of the first electrode 664 of the sixth transistor T6 is changed in the configurations of the pixel 180 and the pixel circuit 181. The other configurations and functions are the same as those of the display device 10 according to the first embodiment. In describing the configuration and functions of the sixth embodiment, configurations and functions that are the same as those of the display device 10 according to the first embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 26 will be described as necessary.

[0278] <6-1. Configuration of pixel 180E> The pixel 180E and pixel circuit 181E will be outlined with reference to FIGS.

[0279] As described above, the pixel circuit 181E has a configuration in which the connection of the first electrode 664 of the sixth transistor T6 is changed from the configurations of the pixel 180 and the pixel circuit 181. Specifically, the first electrode 664 of the sixth transistor T6 of the pixel circuit 181E is disconnected from the reference voltage power supply line SVR and electrically connected to the second electrode 646 of the fourth transistor T4 and the second node N2. The sixth transistor T6 has a function of connecting the fourth node N4 and the second node N2 in response to the second scan signal SC2(n). That is, the fourth transistor T4 supplies the reference voltage VREF to the second node N2 and also supplies the reference voltage VREF to the fourth node N4 via the sixth transistor T6.

[0280] The configuration and functions of the pixel circuit 181E other than those described in "6-1. Configuration of the pixel 180E" are the same as those of the pixel circuit 181.

[0281] <6-2. Driving Method of Pixel Circuit 181E> A method for driving a display device (pixel circuit 181E) according to the sixth embodiment will be described. Compared with the configurations described in "1-5-1. First example of method for driving display device 10" to "1-5-4. Fourth example of method for driving display device 10", the method for driving pixel circuit 181E includes the following (1) and (2).

[0282] (1) When HI is supplied to the second scan signal SC2(n), the fourth transistor T4 and the sixth transistor T6 are in the ON state, the second node N2 is connected to the reference voltage power supply line SVR, the voltage supplied to the second node N2 is the reference voltage VREF, and the fourth node N4 is connected to the reference voltage power supply line SVR, the voltage supplied to the fourth node N4 is the reference voltage VREF. (2) When LO is supplied to the second scan signal SC2(n), the fourth transistor T4 and the sixth transistor T6 are in the off state, the second node N2 is not electrically connected to the reference voltage power supply line SVR, the reference voltage VREF is not supplied to the second node N2, the fourth node N4 is not electrically connected to the reference voltage power supply line SVR, and the reference voltage VREF is not supplied to the fourth node N4.

[0283] The configurations and functions of the driving method of pixel circuit 181E other than those related to (1) and (2) above are the same as those described in "1-5-1. First example of a method for driving display device 10" to "1-5-4. Fourth example of a method for driving display device 10."

[0284] The driving method of the pixel circuit 181E including the configuration described above is a driving method that can increase the speed at which data is written to the first node N1, similar to "1-5-1. First example of driving method of the display device 10" to "1-5-4. Fourth example of driving method of the display device 10", and is a driving method that can execute the period PWR within the periods PIN and PVH, in parallel with the periods PIN and PVH, and is a driving method that has a high degree of freedom for the period PWR and is highly versatile.

[0285] Furthermore, in the pixel circuit 181E, a sixth transistor T6 is electrically connected to the second node N2. As a result, the parasitic capacitance of the second node N2 in the pixel circuit 181E is larger than the parasitic capacitance of the second node N2 in the pixel circuit 181. Therefore, the driving method of the pixel circuit 181E can prevent an excessive rise in the voltage supplied to the second node N2 when the first scan signal SC1(n) changes from a state in which LO is supplied to a state in which Hi is supplied.

[0286] 7. Seventh Embodiment <7-1. Overview of the display device 20> An overview of a display device 20 according to the seventh embodiment will be described with reference to Fig. 31. Fig. 31 is a schematic diagram showing the configuration of the display device 20. The configuration of the display device 20 shown in Fig. 31 is an example, and the configuration of the display device 20 is not limited to the configuration shown in Fig. 31.

[0287] The display device 20 has a configuration in which a scan signal line 334 to which a fifth scan signal SC5(n) is supplied and a reset voltage power supply line SVRE to which a reset voltage VRES is supplied are added to the configuration of the display device 10 according to the first embodiment, and the pixel 180 (pixel circuit 181) in the configuration of the display device 10 is replaced with a pixel 180F (pixel circuit 181F). The configuration of the pixel circuit 181F is different from the configuration of the pixel circuit 181. Other configurations and functions of the display device 20 are similar to those of the display device 10 according to the first embodiment. In describing the configuration and functions of the seventh embodiment, configurations and functions similar to those of the display device 10 according to the first embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 30 will be described as necessary.

[0288] The fifth scan signal SC5(n), like the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n), is one of the scan signals output at different timings by the scan driver circuit 160. The scan signal line 334 to which the fifth scan signal SC5(n) is supplied is electrically connected to the control circuit 120 (scan driver circuit 160) and each pixel circuit 181F.

[0289] <7-2.Configuration of pixel 180F> An overview of pixel 180F and pixel circuit 181F will be described with reference to FIGS. 31, 33, and 34. FIG. 33 is a schematic diagram showing input signals to pixel circuit 181F included in pixel 180F. FIG. 34 is a circuit diagram showing the configuration of pixel circuit 181F. FIGS. 33 and 34 show, as an example, the configuration of pixel circuit 181F of pixel 180F shown in FIG. 31. The configurations of pixel 180F and pixel circuit 181F are not limited to the configurations shown in FIGS. 31, 33, and 34. Configurations that are the same as or similar to those in FIG. 31 will be described as necessary.

[0290] The pixel circuit 181F is a circuit for driving the pixel 180F. As described above, the pixel circuit 181F includes a scan signal line 334 to which the fifth scan signal SC5(n) is supplied, a reset voltage power supply line SVRE to which the reset voltage VRES is supplied, and a circuit configuration different from that of the pixel circuit 181. Other configurations and functions of the pixel circuit 181F are similar to those of the pixel circuit 181.

[0291] For example, the reset voltage VRES may be supplied from an external device to the IC chip 110, similar to the initialization voltage VINI, or may be supplied from the IC chip 110 to the plurality of pixels 180F (pixel circuits 181F) via the connection wiring 342 and the reset voltage power supply line SVRE. Although not shown, the reset voltage VRES may be connected to the reset voltage power supply line SVRE from the external device via the FPC 200, the terminal unit 150, and the connection wiring 341, similar to the initialization voltage VINI, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to the plurality of pixels 180F (pixel circuits 181F).

[0292] 34, the pixel circuit 181F includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitance element CD, a capacitance element CV, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source and drain electrodes) consisting of a first electrode and a second electrode. Each of the capacitance elements CD, CV, and the light-emitting element OLED includes a pair of electrodes consisting of a first electrode and a second electrode.

[0293] For example, the first transistor T1 is a selection transistor. The first transistor T1 has a function of supplying an image data signal SL(m) to the first node N1.

[0294] For example, the second transistor T2 is a drive transistor. A gate voltage in which the threshold voltage VTH is corrected based on the reset voltage VRES, the reference voltage VREF, and the initialization voltage VINI is applied between the gate electrode 622 and the first electrode (source) 624 of the second transistor T2. Furthermore, the second transistor T2 controls the amount of current flowing from the drive power supply line PVDD to the light-emitting element OLED based on the gate voltage (voltage between the gate electrode 622 and the first electrode (source) 624) in which the variation in the threshold voltage VTH has been corrected and the input image data signal SL(m). In other words, the second transistor T2 has the function of supplying a drive voltage VDDEL to the light-emitting element OLED and passing a current therethrough, causing the light-emitting element OLED to emit light.

[0295] The third transistor T3 has a function of connecting the first node N1 and the reference voltage power supply line SVR to each other and supplying the reference voltage VREF to the first node N1.

[0296] The fourth transistor T4 has a function of connecting the second node N2 and the fourth node N4 to each other, supplying the reset voltage VRES supplied to the fourth node N4 to the second node N2, and resetting the second node N2. Note that resetting can also be referred to as initialization.

[0297] The fifth transistor T5 has a function of connecting the fourth node N4 and the reset voltage power supply line SVRE to each other, supplying the reset voltage VRES to the fourth node N4, and resetting the fourth node N4.

[0298] The sixth transistor T6 has a function of connecting the third node N3 and the initialization voltage power supply line SVI to each other, supplying the initialization voltage VINI to the third node N3, and initializing the third node N3.

[0299] The seventh transistor T7 has a function of connecting the fourth node N4 and the drive voltage power supply line PVDD to supply the drive voltage VDDEL to the fourth node N4.

[0300] Although the details will be described later, the capacitance element CV has a function of holding (storing) a charge equivalent to the threshold voltage VTH of the second transistor T2.

[0301] The capacitance element CD has the function of holding (storing) a charge equivalent to the data voltage (a voltage equal to or greater than the voltage VSIGL (see Figure 35) and equal to or less than the voltage VSIGH (see Figure 35)) contained in the image data signal SL(m) supplied to the first node N1.

[0302] The light-emitting element OLED has diode characteristics and emits light based on the current flowing through the light-emitting element OLED (that is, the drain current Ion of the second transistor T2).

[0303] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to a scan signal line 333. The first electrode 614 is electrically connected to an image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the second electrode 636 of the third transistor T3, the first electrode 42 of the capacitance element CV, and the second electrode 54 of the capacitance element CD. A fourth scan signal SC4(n) is supplied to the scan signal line 333. Similar to the first transistor T1 in the display device 10 according to the first embodiment, the switching of the first transistor T1 is controlled using the fourth scan signal SC4(n), and the conductive state (on state) and the non-conductive state (off state) are controlled.

[0304] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the second node N2, the second electrode 44 of the capacitor CV, and the second electrode 646 of the fourth transistor T4. The first electrode 624 is electrically connected to the third node N3, the second electrode 666 of the sixth transistor T6, and the second electrode 34 of the light-emitting element OLED. The second electrode 626 is electrically connected to the fourth node N4, the first electrode 644 of the fourth transistor T4, the second electrode 656 of the fifth transistor T5, and the first electrode 674 of the seventh transistor T7. The threshold voltage of the second transistor T2 is a threshold voltage VTH. The second transistor T2 is controlled to be in a conductive state (ON state) or a non-conductive state (OFF state) depending on the potential difference between the voltage supplied to the gate electrode 622 (second node N2) and the voltage supplied to the first electrode 624 (third node N3) and the potential difference between the second electrode 626 (fourth node N4) and the first electrode 624. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 is smaller than the threshold voltage VTH, the second transistor T2 is in a non-conductive state. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 is equal to or greater than the threshold voltage VTH and the potential difference between the voltage supplied to the fourth node N4 and the voltage supplied to the third node N3 is greater than 0 V, the second transistor T2 is in a conductive state.

[0305] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scan signal line 330. The first electrode 634 is electrically connected to the reference voltage power supply line SVR. A first scan signal SC1(n) is supplied to the scan signal line 330. Similar to the third transistor T3 in the display device 10 according to the first embodiment, the switching of the third transistor T3 is controlled using the first scan signal SC1(n), and the conductive state (on state) and non-conductive state (off state) are controlled.

[0306] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 330. The switching of the fourth transistor T4 is controlled using the first scan signal SC1(n). In other words, the conductive state (ON state) and non-conductive state (OFF state) of the fourth transistor T4 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the fourth transistor T4 is in a non-conductive state, and when the signal supplied to the scan signal line 330 is HI, the fourth transistor T4 is in a conductive state.

[0307] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 332. The first electrode 654 is electrically connected to the reset voltage power supply line SVRE. A third scan signal SC3(n) is supplied to the scan signal line 332. The switching of the fifth transistor T5 is controlled using the third scan signal SC3(n). In other words, the fifth transistor T5 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the fifth transistor T5 is in a non-conductive state, and when the signal supplied to the third scan signal SC3(n) is HI, the fifth transistor T5 is in a conductive state.

[0308] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to a scan signal line 331. The first electrode 664 is electrically connected to an initialization voltage power supply line SVI. A second scan signal SC2(n) is supplied to the scan signal line 331. Similar to the sixth transistor T6 in the display device 10 according to the first embodiment, the switching of the sixth transistor T6 is controlled using the second scan signal SC2(n).

[0309] The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the scan signal line 334. The second electrode 676 is electrically connected to the drive voltage power supply line PVDD. A fifth scan signal SC5(n) is supplied to the scan signal line 334. The switching of the seventh transistor T7 is controlled using the fifth scan signal SC5(n). In other words, the conductive state (on state) and non-conductive state (off state) of the seventh transistor T7 are controlled by the fifth scan signal SC5(n). When the signal supplied to the fifth scan signal SC5(n) is LO, the seventh transistor T7 is in a non-conductive state. When the signal supplied to the fifth scan signal SC5(n) is HI, the seventh transistor T7 is in a conductive state.

[0310] The first electrode 32 of the light-emitting element OLED is electrically connected to a reference voltage line PVSS. A reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 32 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 34 of the light-emitting element OLED is, for example, an anode electrode.

[0311] The configuration and functions of the pixel circuit 181F other than those described in "7-2. Configuration of pixel 180F" are the same as those of the pixel circuit 181. For example, each transistor shown in Fig. 34 may be an n-channel field effect transistor, similar to the display device 10 according to the first embodiment, and may have a group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor properties, in the channel region.

[0312] <7-3. Driving method of the display device 20> A method for driving the display device 20 will be described with reference to Fig. 32 to Fig. 36. Fig. 32, Fig. 35, and Fig. 36 are schematic diagrams showing timing charts of the display device 20. Configurations that are the same as or similar to those in Fig. 1 to Fig. 31, Fig. 33, and Fig. 34 will be described as necessary.

[0313] For example, compared to the method of driving the display device 10 based on the timing chart shown in Fig. 4, the method of driving the display device 20 based on the timing chart shown in Fig. 32 includes executing a threshold value acquisition and holding period PVH (period PVH) after executing an initialization period PIN (period PIN), and including executing a write period PWR (period PWR) after executing the threshold value acquisition and holding period PVH (period PVH). Furthermore, the period PIN in the method of driving the display device 20 is a period for initializing the first node N1, the second node N2, the third node N3, and the fourth node N4. Other configurations and functions in the method of driving the display device 20 are similar to those in the method of driving the display device 10.

[0314] Next, a specific method for driving the pixel 180F (pixel circuit 181F) of the display device 20 will be described.

[0315] The pixel 180F (pixel circuit 181F) receives the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), the image data signal SL(m) including the data signal VDATA, the reset voltage VRES, the initialization voltage VINI, and the reference voltage VREF. For example, the pixel 180F (pixel circuit 181F) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n). The image data signal SL(m), the reset voltage VRES, the initialization voltage VINI, and the reference voltage VREF are input to the selected pixel 180F (pixel circuit 181F) according to the timing of each signal. A similar operation is performed for all pixels 180F (pixel circuits 181F), and based on the image data signals SL(m) input to all pixels 180F (pixel circuits 181F), the image of the frame corresponding to one frame is displayed in the display area 22 of the display device 20.

[0316] For example, Table 3 shows the voltages (potentials) supplied to the signals and nodes in each period of each frame in the timing charts shown in FIGS.

[0317] [Table 3]

[0318] <7-3-1. First Example of the Method for Driving the Display Device 20> A first example of a method for driving the display device 20 will be described with reference to FIG. 35 and Table 3. The driving method shown in the first example involves pixel 180F (pixel circuit 181F) displaying a black image based on the voltage of the data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then pixel 180F (pixel circuit 181F) displaying a white image based on the voltage VSIGH (7V) included in the data signal VDATA in KthFRAME. In other words, the driving method shown in the first example involves displaying images of different colors in successive frames.

[0319] In accordance with each period (period PIN, period PWR (horizontal period HRP), and period PVH), an image data signal SL(m) including a data signal VDATA is input to each pixel 180F (pixel circuit 181F). The data signal VDATA is analog data including a voltage equal to or greater than voltage VSIGL and equal to or less than voltage VSIGH. For example, in each period PWR, a voltage equal to or greater than voltage VSIGL and equal to or less than voltage VSIGH is selected using a selection signal (not shown), and supplied to the image data signal SL(m). For example, in periods other than period PWR, the data signal VDATA is supplied with a voltage that is supplied to pixels other than the selected pixel 180F (pixel circuit 181F). As shown in Table 2, for example, if the voltage VSIGL is 3V, the pixel 180F to which the voltage VSIGL is supplied will not emit light and will be black. For example, if the voltage VSIGH is 7V, the pixel 180F to which the voltage VSIGH is supplied will emit light and produce a white color. For example, the voltage VH(HI) is 12V, the voltage VL(LO) is -2V, the reset voltage VRES is 3.4V, the reference voltage VREF is 4V, the initialization voltage VINI is 0V, the voltage VM is 5V, and the voltage VN is -5V.

[0320] During the light emission period PEM of the (K-1st) frame, the data signal VDATA is supplied with a voltage other than that supplied to the selected pixel 180F (pixel circuit 181F), the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are supplied with LO, and the fifth scan signal SC5(n) is supplied with HI. All transistors except the second transistor T2 and the seventh transistor T7 are in an off state, and the seventh transistor T7 is in an on state. The voltage supplied to the first node N1 is the black display voltage Vnp (3V), the voltage supplied to the second node N2 and the voltage supplied to the third node N3 are 0V, and the potential difference Vgs is 0V. Therefore, the second transistor T2 is in an off state, and the current Ion does not flow from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, so the light-emitting element OLED does not emit light.

[0321] During the period PIN of the Kth FRAME following the light emission period PEM of the K-1st FRAME, the image data signal SL(m) (data signal VDATA) is supplied with a voltage other than that supplied to the selected pixel 180F (pixel circuit 181F). The second scan signal SC2(n) changes from a state in which LO is supplied to a state in which HI is supplied, and the fifth scan signal SC5(n) changes from a state in which HI is supplied to a state in which LO is supplied. When the second scan signal SC2(n) changes to a state in which HI is supplied and the fifth scan signal SC5(n) changes to a state in which LO is supplied, the third scan signal SC3(n) changes from a state in which LO is supplied to a state in which HI is supplied. When the third scan signal SC3(n) changes to a state in which HI is supplied, the first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied. The fourth scan signal SC4(n) is in a state in which LO is supplied. Therefore, the seventh transistor T7 changes from an ON state to an OFF state, the third transistor T3 to the sixth transistor T6 change from an OFF state to an ON state, and the first transistor T1 maintains its OFF state. The voltage supplied to the first node N1 rises from voltage Vnp (3 V) to voltage Vnl (reference voltage VREF, 4 V), the voltage supplied to the second node N2 rises from 0 V to voltage Vnn (reset voltage VRES, 3.4 V), and the voltage supplied to the third node N3 maintains 0 V. Although not shown, the voltage supplied to the fourth node N4 rises toward the reset voltage VRES and becomes the reset voltage VRES. The second transistor T2 changes from an OFF state to an ON state in response to the potential difference Vgs, but the voltage supplied to the third node N3 is the initialization voltage VINI (0 V), and no drain current Ion flows through the light-emitting element OLED, so the light-emitting element OLED does not emit light.

[0322] As described above, during the period PIN, the first node N1 is initialized by the reference voltage VREF (4V), the second node N2 and the fourth node N4 are reset (initialized) by the reset voltage VRES (3.4V), and the third node N3 is initialized by the initialization voltage VINI (0).

[0323] During the period PVH following the period PIN, the image data signal SL(m) is supplied with a voltage other than that supplied to the selected pixel 180F (pixel circuit 181F), the first scan signal SC1(n) and the second scan signal SC2(n) maintain a HI state, and the fourth scan signal SC4(n) and the fifth scan signal SC5(n) maintain a LO state. The third scan signal SC3(n) changes from a HI state to a LO state. Therefore, the fifth transistor T5 changes from an ON state to an OFF state, the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 maintain an ON state, and the first transistor T1 and the seventh transistor T7 maintain an OFF state.

[0324] As a result, the voltage supplied to the first node N1 remains at voltage Vnl, and the voltage supplied to the third node N3 remains at 0V. With the fifth transistor T5 turned off, the voltages supplied to the second node N2 and the fourth node N4 are released, and discharge by the drain current Ion of the second transistor T2 begins. The voltages supplied to the second node N2 and the fourth node N4 drop from voltage Vnn toward voltage Vno (1V) and reach voltage Vno. Voltage Vno corresponds to the threshold voltage VTH. At this time, the capacitive element CD holds a charge equivalent to the potential difference (4V) between the voltage Vnl (4V) supplied to the first node N1 and the voltage (0V) supplied to the third node N3, and maintains this potential difference, while the capacitive element CV holds a charge equivalent to the potential difference (reference voltage VREF (4V) - threshold voltage VTH (1V) = 3V) between the voltage Vnl (4V) supplied to the first node N1 and the voltage (1V) supplied to the second node N2, and maintains this potential difference. Furthermore, the coupled capacitance of the capacitive element CV and the capacitor CD holds a charge equivalent to the potential difference Vgs (threshold voltage VTH, 1V) with the reference voltage VREF (4V) as the reference, and maintains (holds) the threshold voltage VTH with the reference voltage VREF as the reference.

[0325] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0326] During the period PWR following the period PVH, the image data signal SL(m) is supplied with the voltage VSIGH (7V). The second scan signal SC2(n) maintains a HI state, and the third scan signal SC3(n) and the fifth scan signal SC5(n) maintain a LO state. The first scan signal SC1(n) changes from a HI state to a LO state, and the third scan signal SC3(n) changes from a LO state to a HI state. Therefore, the first transistor T1 changes from an OFF state to an ON state, the third transistor T3 and the fourth transistor T4 change from an ON state to an OFF state, the sixth transistor T6 maintains an ON state, and the fifth transistor T5 and the seventh transistor T7 maintain an OFF state.

[0327] As a result, the voltage supplied to the first node N1 gradually increases from voltage Vnl toward voltage Vnm (voltage VSIGH (7V)) and reaches voltage Vnm. When the voltage supplied to the first node N1 increases, the voltage supplied to the second node N2 gradually increases from voltage Vno toward voltage Vnl (4V) and reaches voltage Vnl due to the capacitive element CV. The voltage supplied to the third node N3 remains at 0V. Therefore, the potential difference Vgs is 4V, and the second transistor T2 is in the on state. Although not shown, because the second transistor T2 is in the on state, for example, the voltage supplied to the fourth node N4 becomes 0V. At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vnm (7V) supplied to the first node N1 and the voltage (0V) supplied to the third node N3 (voltage VSIGH (7V) - initialization voltage VINI (0V) = 7V) and maintains this potential difference. That is, the capacitive element CD maintains (holds) the voltage of the data signal VDATA for white display.

[0328] In this way, during the period PWR, the data signal VDATA is written to the pixel 180F (pixel circuit 181F). The capacitance element CD maintains (holds) the voltage of the data signal VDATA.

[0329] During the light emission period PEM of the KthFRAME following the period PVH of the KthFRAME, a voltage is supplied to pixels other than the selected pixel 180F (pixel circuit 181F). Furthermore, the second scan signal SC2(n) changes from a HI state to a LO state. When the second scan signal SC2(n) changes to a LO state, the fifth scan signal SC5(n) changes from a LO state to a HI state. The first scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) maintain their LO states. Therefore, the sixth transistor T6 changes from an ON state to an OFF state, the seventh transistor T7 changes from an OFF state to an ON state, and the first transistor T1, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 maintain their OFF states.

[0330] As a result, the fourth node N4 is electrically connected to the drive voltage power supply line PVDD, and the voltage supplied to the fourth node N4 becomes the drive voltage VDDEL. When the voltage supplied to the fourth node N4 becomes the drive voltage VDDEL and the voltage Vds becomes greater than the threshold voltage VTH, the second transistor T2 flows a drain current Ion. As a result, the potential of the third node N3 rises to voltage Vnp, and accordingly the voltage of the second node N2 capacitively coupled by the capacitive elements CD and CV rises from voltage Vnn toward voltage Vnm and reaches voltage Vnm, and the voltage of the first node N1 capacitively coupled to the third node N3 by the capacitive element CD rises from voltage Vnm toward voltage VH and reaches voltage VH.

[0331] At this time, the potential difference Vgs is the sum of the potential difference held in the capacitance element CD and the potential difference held in the capacitance element CV (the voltage included in the data signal VDATA (voltage VSIGH, 7V) - reference voltage VREF (4V) + threshold voltage VTH (1V)). In other words, during the light emission period PEM of KthFRAME, the pixel 180F (pixel circuit 181F) can display an image based on the data signal VDATA and the corrected threshold.

[0332] Specifically, since the potential difference Vds and the potential difference Vgs are higher (larger) than the threshold voltage VTH, the second transistor T2 is in an on state, a drain current Ion flows from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, and the light-emitting element OLED emits light. For example, the pixel 180F that emits red, the pixel 180F that emits blue, and the pixel 180F that emits green each emit light, and the three pixels using the pixel 180F that emits red, the pixel 180F that emits blue, and the pixel 180F that emits green emit white.

[0333] The display device 20 can control each transistor and independently initialize each node, similar to the display device 10. Furthermore, similar to the display device 10, the display device 20 uses two capacitance elements CD and CV, whereby the capacitance element CD maintains (holds) the voltage included in the data signal VDATA, the capacitance element CV holds a potential difference (charge) equivalent to the threshold voltage VTH, and the capacitance elements CD and CV are coupled together to generate a potential difference Vgs of the second transistor T2.

[0334] <7-3-2. Second Example of the Method for Driving the Display Device 20> A second example of a method for driving the display device 20 will be described with reference to FIG. 36 and Table 3. The driving method shown in the second example involves pixel 180F (pixel circuit 181F) displaying a white image based on the voltage of the data signal VDATA in the frame (K-1stFRAME) immediately preceding the current frame (KthFRAME), and then pixel 180F (pixel circuit 181F) displaying a black image based on the voltage VSIGL included in the data signal VDATA in KthFRAME. In other words, the driving method shown in the second example involves displaying images of different colors in successive frames. Configurations that are the same as or similar to those in FIGS. 1 to 35 will be described as necessary.

[0335] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n) are the same as those described in "7-3-1. First Example of the Method for Driving the Display Device 20." Furthermore, the voltages (potentials) of each node during the light-emitting period of the K-1st FRAME to the period PVH of the Kth FRAME are the same as those described in "7-3-1. First Example of the Method for Driving the Display Device 20." Furthermore, the operation of each transistor during each period is the same as those described in "7-3-1. First Example of the Method for Driving the Display Device 20." Therefore, configurations similar to those described in "7-3-1. First Example of the Method for Driving the Display Device 20" will be described as necessary. In addition, as for the image data signal SL(m), during the KthFRAME period PWR, a data signal VDATA including VSIGH corresponding to white is supplied, and during periods other than the KthFRAME period PWR, a data signal VDATA similar to the configuration described in "7-3-1. First example of the method for driving the display device 20" is supplied.

[0336] During the light emission period PEM of the K-1st FRAME, the first scan signal SC1(n) to the fifth scan signal SC5(n) are applied, similar to the configuration described in "7-3-1. First Example of the Method for Driving the Display Device 20." The voltage supplied to the first node N1 is 10 V during white display, the voltage supplied to the second node N2 is 7 V (voltage Vnm), the voltage supplied to the third node N3 is 3 V, and the potential difference Vgs is 4 V. Therefore, the second transistor T2 is in the on state, and a current Ion flows from the drive power supply line PVDD to the light emitting element OLED and the reference voltage line PVSS, causing the light emitting element OLED to emit light.

[0337] Furthermore, during the period PIN of the KthFRAME following the light emission period PEM of the K-1stFRAME, similar to the configuration described in "7-3-1. First example of the method for driving the display device 20", the first node N1 is initialized by the reference voltage VREF (4V), the second node N2 and the fourth node N4 are reset (initialized) by the reset voltage VRES (3.4V), and the third node N3 is initialized by the initialization voltage VINI (0).

[0338] Furthermore, during the period PVH, similar to the configuration described in "7-3-1. First Example of the Driving Method of the Display Device 20," the voltage supplied to the first node N1 remains at voltage Vnl, the voltage supplied to the third node N3 remains at 0 V, and the voltage supplied to the second node N2 and the voltage supplied to the fourth node N4 become voltage Vno (corresponding to the threshold voltage VTH). The capacitive element CD holds a charge equivalent to the potential difference between the voltage supplied to the first node N1 and the voltage supplied to the third node N3 and maintains this potential difference. The capacitive element CV holds a charge equivalent to the potential difference between the voltage supplied to the first node N1 and the voltage supplied to the second node N2 and maintains this potential difference. Furthermore, the coupling capacitance between the capacitive element CV and the capacitor CD holds a charge equivalent to the potential difference Vgs and maintains (holds) the threshold voltage VTH with respect to the reference voltage VREF. That is, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0339] During the period PWR following the period PVH, the image data signal SL(m) is supplied with a voltage VSIGL (3V). The voltage supplied to the first node N1 gradually drops from voltage Vnl to voltage Vnp (voltage VSIGL (3V)) and reaches voltage Vnp. When the voltage supplied to the first node N1 drops, the voltage supplied to the second node N2 gradually drops from voltage Vno to 0V (reference voltage VREF) due to the capacitive element CV and reaches 0V. The voltage supplied to the third node N3 remains at 0V. Therefore, the potential difference Vgs is 0V, and the second transistor T2 is in an off state. Although not shown, for example, the voltage supplied to the fourth node N4 becomes indefinite. At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vnp (3V) supplied to the first node N1 and the voltage (0V) supplied to the third node N3 (voltage VSIGL (3V) - initialization voltage VINI (0V) = 3V) and maintains this potential difference. That is, the capacitive element CD maintains (holds) the voltage included in the data signal VDATA.

[0340] In this way, during the period PWR, the data signal VDATA is written to the pixel 180F (pixel circuit 181F). The capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0341] During the light-emission period PEM of the KthFRAME following the period PVH of the KthFRAME, the voltage supplied to the first node N1 remains at voltage Vnp, and the voltages supplied to the second node N2 and the third node N3 remain at 0 V. That is, because the potential difference Vgs is 0 V and smaller than the threshold voltage VTH, the second transistor T2 is in an off state. The potential difference Vgs is the sum of the potential difference held in the capacitance element CD and the potential difference held in the capacitance element CV (the voltage included in the data signal VDATA (voltage VSIGL, 3 V) - the reference voltage VREF (4 V) + the threshold voltage VTH (1 V)). That is, during the light-emission period PEM of the KthFRAME, the pixel 180F (pixel circuit 181F) can display an image based on the data signal VDATA and the corrected threshold.

[0342] Specifically, the second transistor T2 is in an off state, and no drain current Ion flows from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, so that the light-emitting element OLED does not emit light. For example, the pixel 180F that emits red, the pixel 180F that emits blue, and the pixel 180F that emits green do not emit light, and the three pixels that use the pixel 180F that emits red, the pixel 180F that emits blue, and the pixel 180F that emits green are black.

[0343] The second example of the method for driving the display device 20 has the same effects as those described in "7-3-1. First example of the method for driving the display device 20."

[0344] 8. Eighth Embodiment An overview of the display device according to the eighth embodiment will be described with reference to Fig. 31, Fig. 32, and Fig. 37 to Fig. 42. Fig. 37 is a schematic diagram showing an input signal to a pixel 180G (pixel circuit 181G) according to the eighth embodiment, Fig. 38 is a circuit diagram showing the configuration of the pixel circuit 181G, and Fig. 39 to Fig. 42 are timing charts of the display device according to the eighth embodiment.

[0345] The display device according to the eighth embodiment includes a pixel 180G and a pixel circuit 181G. The configurations of the pixel 180G and the pixel circuit 181G are different from the circuit configurations of the pixel 180F and the pixel circuit 181F of the display device 20 according to the seventh embodiment. Specifically, the display device according to the eighth embodiment has a configuration and function in which the configurations of the pixel 180F and the pixel circuit 181F in the display device 20 according to the seventh embodiment are replaced with the pixel 180G (pixel circuit 181G). The other configurations and functions are the same as those of the display device 20 according to the seventh embodiment. In describing the configuration and functions of the eighth embodiment, configurations and functions similar to those of the display device 10 according to the first embodiment and the display device 20 according to the seventh embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 31 to 36 will be described as necessary.

[0346] <8-1. Pixel 180G Configuration> The pixel 180G and pixel circuit 181G will be outlined with reference to FIGS.

[0347] Pixel circuit 181G has a configuration in which the initialization voltage power supply line SVI and the reset voltage power supply line SVRE are removed from pixel circuit 181F. That is, pixel circuit 181G is electrically connected to a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a fifth scan signal SC5(n), an image data signal SL(m) including a data signal VDATA, and a reference voltage VREF. Furthermore, as will be described in detail later, the circuit configuration of pixel circuit 181G differs from that of pixel circuit 181F, and the driving method of pixel circuit 181G differs from the driving method of pixel circuit 181F. The first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), the image data signal SL(m) including the data signal VDATA, and the reference voltage VREF are connected to the scan signal lines 330 to 334, the image data signal line 321, and the reference voltage power supply line SVR, which have the same circuit configuration as the pixel circuit 181F.

[0348] 37, the pixel circuit 181G includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a capacitance element CD, a capacitance element CV, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source and drain electrodes) consisting of a first electrode and a second electrode. Each of the capacitance elements CD, CV, and the light-emitting element OLED includes a pair of electrodes consisting of a first electrode and a second electrode.

[0349] For example, the first transistor T1 is a selection transistor. The first transistor T1 has a function of supplying the image data signal SL(m) to the third node N3.

[0350] For example, the second transistor T2 is a drive transistor. A gate voltage in which the threshold voltage VTH is corrected based on a reference voltage VREF is applied between the gate electrode 622 and the first electrode (source) 624 of the second transistor T2. Furthermore, the second transistor T2 controls the amount of current flowing from the drive power supply line PVDD to the light-emitting element OLED based on the gate voltage (voltage between the gate electrode 622 and the first electrode (source) 624) in which variations in the threshold voltage VTH have been corrected and the input image data signal SL(m). In other words, the second transistor T2 has the function of supplying a drive voltage VDDEL to the light-emitting element OLED and passing a current therethrough, causing the light-emitting element OLED to emit light.

[0351] The third transistor T3 has a function of bringing the second node N2 and the fourth node N4 into conduction, and making the potential difference between the gate electrode 622 and the second electrode 626 of the second transistor T2 0V.

[0352] The fourth transistor T4 has a function of connecting the third node N3 and the reference voltage power supply line SVR to supply the reference voltage VREF to the third node N3 and initializing the third node N3.

[0353] The fifth transistor T5 has a function of electrically connecting the fourth node N4 (the second electrode 626 of the second transistor T2) and the fifth node N5 (the first electrode 32 of the light-emitting element OLED).

[0354] The sixth transistor T6 has a function of connecting the first node N1 and the reference voltage power supply line SVR to each other, supplying the reference voltage power supply line SVR to the first node N1, and initializing the first node N1.

[0355] The seventh transistor T7 has a function of connecting the third node N3 and the reference voltage line PVSS to each other and supplying the reference voltage VSSEL to the third node N3.

[0356] The eighth transistor T8 has a function of electrically connecting the first electrode 32 and the second electrode 34 of the light-emitting element OLED and supplying the driving voltage VDDEL to the second electrode 656 of the fifth transistor T5.

[0357] Although the details will be described later, the capacitance element CV has a function of holding (storing) a charge equivalent to the threshold voltage VTH of the second transistor T2.

[0358] The capacitance element CD has the function of holding (storing) a charge equivalent to the data voltage (a voltage equal to or greater than voltage VSIGL (see Figure 39) and equal to or less than voltage VSIGH (see Figure 39)) contained in the image data signal SL(m) supplied to the third node N3.

[0359] The light-emitting element OLED has diode characteristics and emits light based on the current flowing through it (i.e., the drain current Ion of the second transistor T2). The first electrode 32 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 34 of the light-emitting element OLED is, for example, an anode electrode.

[0360] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to a scan signal line 333. The first electrode 614 is electrically connected to an image data signal line 321. The second electrode 616 is electrically connected to a third node N3, a first electrode 624 of the second transistor T2, a second electrode 646 of the fourth transistor T4, and a second electrode 44 of the capacitance element CD. A fourth scan signal SC4(n) is supplied to the scan signal line 333. Similar to the first transistor T1 in the display device 10 according to the first embodiment, the switching of the first transistor T1 is controlled using the fourth scan signal SC4(n), and the conductive state (on state) and the non-conductive state (off state) of the first transistor T1 are controlled.

[0361] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the second node N2, the first electrode 42 of the capacitance element CV, and the first electrode 634 of the third transistor T3. The second electrode 626 is electrically connected to the fourth node N4, the second electrode 636 of the third transistor T3, and the first electrode 654 of the fifth transistor T5. The threshold voltage of the second transistor T2 is a threshold voltage VTH. The conductive state (ON state) and non-conductive state (OFF state) of the second transistor T2 are controlled in accordance with a potential difference Vgs between the voltage supplied to the gate electrode 622 (second node N2) and the voltage supplied to the first electrode 624 (third node N3), and a potential difference Vds between the second electrode 626 (fourth node N4) and the first electrode 624. For example, when the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 is smaller than the threshold voltage VTH, the second transistor T2 is in a non-conductive state. For example, when the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 is equal to or greater than the threshold voltage VTH and the potential difference Vds between the voltage supplied to the fourth node N4 and the voltage supplied to the third node N3 is greater than 0 V, the second transistor T2 is in a conductive state.

[0362] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the scan signal line 330. The first electrode 634 is electrically connected to the reference voltage power supply line SVR. A first scan signal SC1(n) is supplied to the scan signal line 330. Similar to the third transistor T3 in the display device 10 according to the first embodiment, the switching of the third transistor T3 is controlled using the first scan signal SC1(n), and the conductive state (on state) and non-conductive state (off state) are controlled.

[0363] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 330. The first electrode 644 is electrically connected to the reference voltage power supply line SVR. The switching of the fourth transistor T4 is controlled using a first scan signal SC1(n). In other words, the conductive state (on state) and non-conductive state (off state) of the fourth transistor T4 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the fourth transistor T4 is in a non-conductive state, and when the signal supplied to the scan signal line 330 is HI, the fourth transistor T4 is in a conductive state.

[0364] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 331. The second electrode 656 is electrically connected to the first electrode 684 of the eighth transistor T8. A second scan signal SC2(n) is supplied to the scan signal line 331. The switching of the fifth transistor T5 is controlled using the second scan signal SC2(n). In other words, the fifth transistor T5 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the fifth transistor T5 is in a non-conductive state, and when the signal supplied to the second scan signal SC2(n) is HI, the fifth transistor T5 is in a conductive state.

[0365] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 332. The first electrode 664 is electrically connected to the reference voltage power supply line SVR. A third scan signal SC3(n) is supplied to the scan signal line 332. The sixth transistor T6 has its switching controlled using the third scan signal SC3(n). In other words, the sixth transistor T6 has its conductive state (ON state) and non-conductive state (OFF state) controlled by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the sixth transistor T6 is in a non-conductive state, and when the signal supplied to the third scan signal SC3(n) is HI, the sixth transistor T6 is in a conductive state.

[0366] The seventh transistor T7 includes a gate electrode 672, a first electrode 674, and a second electrode 676. The gate electrode 672 is electrically connected to the scan signal line 334. The first electrode 674 is electrically connected to the reference voltage line PVSS. A fifth scan signal SC5(n) is supplied to the scan signal line 334. Similar to the seventh transistor T7 described in "7-2. Configuration of pixel 180F," the conductive state (on state) and non-conductive state (off state) of the seventh transistor T7 are controlled using the fifth scan signal SC5(n).

[0367] The eighth transistor T8 includes a gate electrode 682, a first electrode 684, and a second electrode 686. The gate electrode 682 is electrically connected to the scan signal line 332 and the gate electrode 662 of the sixth transistor T6. The second electrode 686 is electrically connected to the second electrode 34 of the light-emitting element OLED and the driving power line PVDD. A third scan signal SC3(n) is supplied to the scan signal line 332. The switching of the eighth transistor T8 is controlled using the third scan signal SC3(n). In other words, the conductive state (ON state) and non-conductive state (OFF state) of the eighth transistor T8 are controlled by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the eighth transistor T8 is in a non-conductive state. When the signal supplied to the third scan signal SC3(n) is HI, the eighth transistor T8 is in a conductive state.

[0368] The configuration and functions of the pixel circuit 181G other than those described in "8-1. Configuration of pixel 180G" are the same as those of the pixel circuit 181F. For example, each transistor shown in Fig. 38 may be an n-channel field effect transistor, similar to the display device 10 according to the first embodiment, and may have a group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor properties, in the channel region.

[0369] <8-2. Driving method of pixel circuit 181G> A method for driving a display device according to the eighth embodiment will be described with reference to Figures 39 to 42. Configurations that are the same as or similar to those in Figures 31 to 38 will be described as necessary.

[0370] The method for driving the display device according to the eighth embodiment includes the same period as the method for driving the display device 20 according to the seventh embodiment shown in FIG.

[0371] In one horizontal period (horizontal period HRP) in the driving method of the display device according to the eighth embodiment, the pixel 180G (pixel circuit 181G) receives the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), the fifth scan signal SC5(n), the image data signal SL(m) including the data signal VDATA, and the reference voltage VREF. For example, the pixel 180G (pixel circuit 181G) is selected in accordance with the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), the fourth scan signal SC4(n), and the fifth scan signal SC5(n). The image data signal SL(m) is input to the selected pixel 180G (pixel circuit 181G) in accordance with the timing of each signal. A similar operation is performed for all pixels 180G (pixel circuits 181G), and based on the image data signals SL(m) input to all pixels 180G (pixel circuits 181G), an image of the frame corresponding to one frame is displayed in the display area 22 of the display device 20.

[0372] For example, the voltages (potentials) supplied to the signals and nodes in each frame in the timing charts shown in FIGS.

[0373] [Table 4]

[0374] For example, as shown in Table 4, when the voltage VSIGH is 4V, the pixel 180 to which the voltage VSIGH is supplied does not emit light and is black. Also, when the voltage VSIGL is 0V, the pixel 180 to which the voltage VSIGL is supplied emits light and produces a white color. For example, the voltage VH(HI) is 8V, the voltage VL(LO) is −4V, the reference voltage VREF is 3V, the drive voltage VDDEL is 6V, the standard voltage VSSEL is −2V, the voltage VM is 5V, and the voltage VN is −5V. The constant voltage VSH is 2.5V.

[0375] <8-2-1. First Example of Driving Method of Pixel Circuit 181G> 39 and Table 2, a first example of a method for driving the pixel circuit 181G will be described. Similar to the first example of the method for driving the display device 10 according to the first embodiment, this method involves displaying images of different colors in successive frames.

[0376] During the light emission period PEM of the (K-1st) frame, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180G (pixel circuit 181G), the first scan signal SC1(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are supplied with LO, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are supplied with HI. The first transistor T1, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are in the OFF state, and the fifth transistor T5 and the seventh transistor T7 are in the ON state. For example, the voltage supplied to the third node N3 is voltage Vnd (-2V), the voltage supplied to the second node N2 is voltage Vnq (2V), and the potential difference Vgs is 4V. Therefore, the second transistor T2 is in the ON state, and a drain current Ion based on the potential difference Vgs and the potential difference Vds corresponding to the voltage VSIGH input during the horizontal period HRP of the (K-1st) frame can be passed from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. Note that the voltage supplied to the second node N2 is 1 V due to the capacitive coupling of the capacitance elements CV and CD. For example, the pixel 180G (pixel circuit 181G) emits red light, and three pixels, including the pixel 180G that emits red light, the pixel 180G that emits blue light, and the pixel 180G that emits green light, emit white light.

[0377] During the period PIN of the Kth FRAME following the light emission period PEM of the K-1st FRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180G (pixel circuit 181G). First, the fifth scan signal SC5(n) changes from a HI state to a LO state. When the fifth scan signal SC5(n) changes to a LO state, the third scan signal SC3(n) changes from a LO state to a HI state. When the third scan signal SC3(n) changes to a HI state, the first scan signal SC1(n) changes from a LO state to a HI state. The second scan signal SC2(n) is in a HI state, and the fourth scan signal SC4(n) is in a LO state.

[0378] The seventh transistor T7 changes from an on state to an off state, and the drain current Ion stops flowing from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS. The sixth transistor T6 and the eighth transistor T8 change from an off state to an on state, the potential difference between the first electrode 32 and the second electrode 34 of the light-emitting element OLED becomes 0 V, the light emission of the light-emitting element OLED stops, and the voltage supplied to the first node N1 increases from voltage Vno (1 V) toward voltage Vnp (reference voltage VREF, 3 V) and reaches voltage Vnp. The third transistor T3 and the fourth transistor T4 change from an off state to an on state, the fifth transistor T5 maintains an on state, the first transistor T1 maintains an off state, the voltage supplied to the first node N1 rises from voltage Vno (1 V) toward voltage Vnp (reference voltage VREF, 3 V), the second node N2 and the fourth node N4 become conductive, and voltage Vnr (drive voltage VDDEL, 6 V) is supplied to the second node N2 (gate electrode 622 of the second transistor T2) and the fourth node N4 (second electrode 626 of the second transistor T2). The potential difference Vgs is 3 V (6 V - 3 V), and the second transistor T2 is in an on state.

[0379] As described above, during the period PIN, the second node N2 and the fourth node N4 are initialized by the drive voltage VDDEL, and the first node N1 and the third node N3 are initialized by the reference voltage VREF.

[0380] During the period PVH following the period PIN, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180G (pixel circuit 181G). The second scan signal SC2(n) changes from a state in which HI is supplied to a state in which LO is supplied. The other scan signals are in the same state as during the period PIN. The fifth transistor T5 changes from an on state to an off state, and the other transistors are in the same state as during the period PIN. Furthermore, the first node N1 and the third node N3 maintain the voltage Vnp. The second transistor T2 is in the on state, the drain electrode Ion flows, and the first node N1 and the third node N3 maintain the voltage Vnp. Therefore, due to the off state of the fifth transistor T5, the voltage supplied to the second node N2 and the fourth node N4 is released and gradually decreases (discharges) from the voltage Vnr. When the potential difference Vgs between the voltage supplied to the second node N2 and the fourth node N4 and the voltage supplied to the third node N3 becomes equal to the threshold voltage VTH, the second transistor T2 is turned off. At this time, the voltage supplied to the second node N2 and the fourth node N4 is the voltage Vnl (4 V).

[0381] In this way, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0382] During the period PWR following the period PVH, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGH (4V). Initially, the first scan signal SC1(n) changes from a HI state to a LO state. When the first scan signal SC1(n) changes to a LO state, the fourth scan signal SC4(n) changes from a LO state to a HI state. The third scan signal SC4(n) is in a HI state, and the second scan signal SC2(n) and the fifth scan signal SC5(n) are in a LO state. The third transistor T3 and the fourth transistor T4 change from an ON state to an OFF state. The other transistors are in the same state as during the period PVH. The voltage supplied to the second node N2 is maintained at a voltage Vnl (4V), and the voltage supplied to the first node N1 is maintained at a voltage Vnp (reference voltage VREF, 3V). The voltage supplied to the third node N3 gradually rises from voltage Vnp to voltage Vnl (voltage VSIGH, 4V). At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vnp (reference voltage VREF, 3V) supplied to the first node N1 and the voltage Vnl (voltage VSIGH, 4V) supplied to the third node N3, and maintains this potential difference (-1V). In other words, the potential difference Vgs is 0V.

[0383] In this way, during the period PWR, the data signal VDATA is written to the pixel 180G (pixel circuit 181G). Also, the capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0384] During the period following the PWR period, the fourth scan signal SC4(n) changes from a HI state to a LO state. When the fourth scan signal SC4(n) changes to a LO state, the third scan signal SC3(n) changes from a HI state to a LO state. When the third scan signal SC3(n) changes to a LO state, the fifth scan signal SC5(n) changes from a LO state to a HI state. The first transistor T1, the sixth transistor T6, and the eighth transistor T8 change from an ON state to an OFF state, and the seventh transistor T7 changes from an OFF state to an ON state. The other scan signals and other transistors remain in the same states as during the PWR period. The voltage supplied to the second node N2 and the voltage supplied to the third node N3 drop from voltage Vnl to voltage Vnd (-2V). That is, the potential difference Vgs is maintained at 0V. At this time, the voltage supplied to the first node N1 capacitively coupled by the capacitive elements CV and CD drops from the voltage Vnp to the voltage Vns (-3V).

[0385] During the light emission period PEM of the KthFRAME, which follows the period after the period PWR of the KthFRAME, the image data signal SL(m) (data signal VDATA) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180G (pixel circuit 181G). Furthermore, the second scan signal SC2(n) changes from a state in which it was supplied LO to a state in which it was supplied HI. Therefore, the fifth transistor T5 changes from an OFF state to an ON state. The other scan signals and other transistors are in the same states as in the period after the period PWR of the KthFRAME. The fifth transistor T5 turns ON, and the first electrode 32 of the light-emitting element OLED is electrically connected to the second electrode 626 (fourth node N4) of the second transistor T2. The potential difference Vgs is the sum of the potential difference held in the capacitance element CD and the potential difference held in the capacitance element CV (reference voltage VREF(3V) - voltage of the data signal VDATA (voltage VSIGH, 4V) + threshold voltage VTH(1V) = 0V). In the pixel 180G (pixel circuit 181G) in which the data signal VDATA includes the voltage VSIGH, the potential difference Vgs is 0 V and the second transistor T2 is in the off state, so no current flows through the drain electrode Ion. Therefore, the light-emitting element OLED does not emit light. As a result, the pixel 180G (pixel circuit 181G) that emits red is black. Similarly to the pixel 180G that emits red, the pixel 180G that emits blue and the pixel 180G that emits green also do not emit light, so the three pixels that use the pixel 180G that emits red, the pixel 180G that emits blue, and the pixel 180G that emits green are black.

[0386] The display device according to the eighth embodiment is capable of independently controlling each node, similar to the display device 10 according to the first embodiment.

[0387] The display device according to the eighth embodiment includes a configuration in which the first node N1, the second node N2, the third node N3, the capacitive element CV, and the capacitive element CD are not directly connected to the light-emitting element OLED. The voltages supplied to the first node N1, the second node N2, the third node N3, the capacitive element CV, and the capacitive element CD are constant voltages such as the drive voltage VDDEL, the reference voltage VREF, or the data signal VDATA. Therefore, for example, charge redistribution does not occur between the first node N1, the second node N2, and the third node N3 and the capacitive element CD, the capacitive element CV, and the parasitic capacitances added to the light-emitting element OLED. As a result, the display device according to the eighth embodiment can suppress fluctuations in the voltages of the first node N1, the second node N2, and the third node N3 due to charge redistribution, and can acquire the threshold voltage VTH at high speed.

[0388] <8-2-2. Second Example of Driving Method of Pixel Circuit 181G> A second example of a method for driving the pixel circuit 181G will be described with reference to Fig. 40. The driving method shown in the second example of the pixel circuit 181G includes displaying images of the same color (for example, white) in consecutive frames, similar to the second example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 31 to 39 will be described as necessary.

[0389] The voltages (potentials) of each node during the light emission period PEM of the K-1th FRAME to the period PWR of the Kth FRAME are the same as those described in "8-2-1. First Example of the Method for Driving the Pixel Circuit 181G." The configurations of each scan signal and the operation of each transistor during each period are the same as those described in "8-2-1. First Example of the Method for Driving the Pixel Circuit 181G." Therefore, configurations similar to those described in "8-2-1. First Example of the Method for Driving the Pixel Circuit 181G" will be described as necessary. Note that, as for the image data signal SL(m), a data signal VDATA including VSIGL (0V) corresponding to white is supplied during the period PWR of the Kth FRAME, and a data signal VDATA similar to the configuration described in "8-2-1. First Example of the Method for Driving the Pixel Circuit 181G" is supplied during periods other than the period PWR of the Kth FRAME.

[0390] During the light emission period PEM of K-1stFRAME, similar to the configuration described in "8-2-1. First example of driving method for pixel circuit 181G", pixel 180G (pixel circuit 181G) emits red light, and three pixels, namely pixel 180G that emits red light, pixel 180G that emits blue light, and pixel 180G that emits green light, emit white light.

[0391] During the period PIN of the KthFRAME following the light emission period PEM of the K-1stFRAME, the second node N2 and the fourth node N4 are initialized by the drive voltage VDDEL, and the first node N1 and the third node N3 are initialized by the reference voltage VREF, similar to the configuration described in "8-2-1. First example of the driving method of the pixel circuit 181G".

[0392] During the period PVH following the period PIN, similar to the configuration described in "8-2-1. First example of the method for driving the pixel circuit 181G", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0393] During the period PWR following the period PVH, the image data signal SL(m) (data signal VDATA) is supplied with a voltage VSIGL (0V). The voltage supplied to the second node N2 is maintained at a voltage Vnl (4V), and the voltage supplied to the first node N1 is maintained at a voltage Vnp (reference voltage VREF, 3V). The voltage supplied to the third node N3 gradually drops from voltage Vnp to 0V (voltage VSIGL). At this time, the capacitive element CD holds a charge equivalent to the potential difference between the voltage Vnp (reference voltage VREF, 3V) supplied to the first node N1 and 0V (voltage VSIGL) supplied to the third node N3, and maintains this potential difference (3V). In other words, the potential difference Vgs is 4V.

[0394] In this way, during the period PWR, the data signal VDATA is written to the pixel 180G (pixel circuit 181G). Also, the capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0395] During the period following the period PWR, the fifth scan signal SC5(n) is set to HI, causing the seventh transistor T5 to change from an OFF state to an ON state. The third node N3 is connected to the reference voltage VSSEL, causing the voltage supplied to the third node N3 to drop from 0 V to a voltage Vnd (-2 V). Accordingly, the voltage at the second node N2, which is capacitively coupled by the capacitive elements CV and CD, drops from a voltage Vnl to a voltage Vnq (2 V). That is, the potential difference Vgs is maintained at 4 V. At this time, the voltage supplied to the first node N1, which is capacitively coupled by the capacitive elements CV and CD, drops from a voltage Vnp to a voltage Vno (1 V).

[0396] During the light-emitting period PEM of the KthFRAME that follows the period PWR of the KthFRAME, the potential difference Vgs is the sum of the potential difference held in the capacitive element CD and the potential difference held in the capacitive element CV (reference voltage VREF (3V) - voltage included in the data signal VDATA (voltage VSIGL, 0V) + threshold voltage VTH (1V) = 4V). That is, based on the data signal VDATA and the corrected threshold, the pixel 180G (pixel circuit 181G) can display an image. When the data signal VDATA includes the voltage VSIGL, the potential difference Vgs is 4V and the second transistor T2 is in the on state, so that a drain current Ion flows from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, pixel 180F that emits red light, pixel 180F that emits blue light, and pixel 180F that emits green light each emit light, and the three pixels using pixel 180F that emits red light, pixel 180F that emits blue light, and pixel 180F that emits green light form white.

[0397] The second example of the method for driving the pixel circuit 181G has the same effects as those described in "8-2-1. First example of the method for driving the pixel circuit 181G."

[0398] <8-2-3. Third Example of Method for Driving Pixel Circuit 181G> A third example of a method for driving the pixel circuit 181G will be described with reference to Fig. 41. The third example of the method for driving the pixel circuit 181G includes displaying images of the same color (for example, black) in consecutive frames, similar to the third example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 31 to 40 will be described as necessary.

[0399] The voltages (potentials) of each node during the light emission period PEM of the period PIN to KthFRAM of the KthFRAME following the light emission period PEM of the K-1stFRAME are the same as the configurations described in "8-2-1. First Example of the Method for Driving the Pixel Circuit 181G." In addition, the configurations of each scan signal and the operation of each transistor during each period are the same as the configurations described in "8-2-1. First Example of the Method for Driving the Pixel Circuit 181G." Therefore, configurations similar to those described in "8-2-1. First Example of the Method for Driving the Pixel Circuit 181G" will be described as necessary.

[0400] During the light emission period PEM of the K-1st FRAME, for example, the voltage supplied to the second node N2 and the third node N3 is the voltage Vnd (-2 V), and the potential difference Vgs is 0 V. Therefore, the second transistor T2 is in the off state, no current flows through the drain electrode Ion, and the light emitting element OLED does not emit light.

[0401] As a result, the pixel 180G (pixel circuit 181G) that emits red light turns black. Similarly to the pixel 180G that emits red light, the pixel 180G that emits blue light and the pixel 180G that emits green light also do not emit light, so the three pixels that use the pixel 180G that emits red light, the pixel 180G that emits blue light, and the pixel 180G that emits green light turn black.

[0402] During the period PIN of the KthFRAME following the light emission period PEM of the K-1stFRAME, the second node N2 and the fourth node N4 are initialized by the drive voltage VDDEL, and the first node N1 and the third node N3 are initialized by the reference voltage VREF, similar to the configuration described in "8-2-1. First example of the driving method of the pixel circuit 181G".

[0403] During the period PVH following the period PIN, similar to the configuration described in "8-2-1. First example of the method for driving the pixel circuit 181G", the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held in the capacitance element CV.

[0404] During the period PWR following the period PVH, a data signal VDATA is written to the pixel 180G (pixel circuit 181G) in the same manner as in the configuration described in "8-2-1. First Example of the Method for Driving the Pixel Circuit 181G." The capacitance element CD maintains (holds) the voltage included in the data signal VDATA.

[0405] In the period after the period PWR and in the light-emitting period PEM of the KthFRAME that follows the period after the period PWR, the pixel circuit 181G operates in the same manner as the configuration described in "8-2-1. First Example of the Method for Driving the Pixel Circuit 181G," and because the potential difference Vgs is 0 V and the second transistor T2 is in the off state, no current flows through the drain electrode Ion and the light-emitting element OLED does not emit light. As a result, the three pixels, which are the pixel 180G that emits red, the pixel 180G that emits blue, and the pixel 180G that emits green, are black.

[0406] The third example of the method for driving the pixel circuit 181G has the same effects as those described in "8-2-1. First example of the method for driving the pixel circuit 181G."

[0407] <8-2-4. Fourth Example of Driving Method of Pixel Circuit 181G> A fourth example of a method for driving the pixel circuit 181G will be described with reference to Fig. 42. The fourth example of a method for driving the pixel circuit 181G includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 31 to 41 will be described as necessary.

[0408] The voltage (potential) of each node, the configuration of each scan signal, and the operation of each transistor from the light emission period PEM of the K-1st FRAME to the period PVH of the Kth FRAME are the same as the configurations explained in "8-2-3. Third example of the driving method for the pixel circuit 181G." Also, the voltage (potential) of each node, the configuration of each scan signal, and the operation of each transistor from the period after the period PVH of the Kth FRAME to the light emission period PEM of the Kth FRAME are the same as the configurations explained in "8-2-2. Second example of the driving method for the pixel circuit 181G." Therefore, the explanation here will be omitted.

[0409] The fourth example of the method for driving the pixel circuit 181G has the same effects as those described in "8-2-1. First example of the method for driving the pixel circuit 181G."

[0410] The above-described embodiments of the present invention or parts of the embodiments can be combined as appropriate as long as they are not mutually inconsistent.

[0411] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0412] 10: display device, 20: display device, 22: display region, 24: peripheral region, 26: terminal region, 32: first electrode, 34: second electrode, 42: first electrode, 44: second electrode, 52: first electrode, 54: second electrode, 100: array substrate, 101: substrate, 101A: first surface, 101B: second surface, 110: IC chip, 120: control circuit, 121: base layer, 122: semiconductor layer, 122A: semiconductor layer, 122B: semiconductor layer, 122C: semiconductor layer, 122D: semiconductor layer, 122E: semiconductor layer, 123: channel region, 124A: impurity region, 125: gate insulating layer , 126: conductive layer, 127A: gate wiring, 127B: gate wiring, 127C: gate wiring, 127D: gate wiring, 127E: gate wiring, 128: insulating layer, 130: shift register circuit, 131: insulating layer, 132: conductive layer, 132A: first wiring, 132B: first wiring, 132C: first wiring, 132D: first wiring, 132E: first wiring, 132F: first wiring, 132G: first wiring, 132H: first wiring, 132J: first wiring, 132K: first wiring, 135: first contact hole opening, 135A: first contact hole opening , 135B: first contact hole opening, 135C: first contact hole opening, 135D: first contact hole opening, 135E: first contact hole opening, 135F: first contact hole opening, 135G: first contact hole opening, 135H: first contact hole opening, 135J: first contact hole opening, 135K: first contact hole opening, 135L: first contact hole opening, 135M: first contact hole opening, 135N: first contact hole opening, 135O: first Contact hole opening, 136: insulating layer, 138: second contact hole opening, 138A: organic insulating film opening, 138B: organic insulating film opening, 138C: second contact hole opening, 138D: second contact hole opening, 138E: second contact hole opening, 138F: second contact hole opening, 139: conductive layer, 140A: second wiring, 140B: second wiring, 140C: second wiring, 141: insulating layer, 143: anode electrode, 144: first layer, 145: second layer, 146: third layer, 147: contact hole opening,148: functional layer, 149: common electrode, 150: terminal portion, 152: first inorganic insulating layer, 154: organic insulating layer, 156: second inorganic insulating layer, 158: cover film, 160: scan driver circuit, 165: sealing film, 170: array portion, 180: pixel, 180A: pixel, 180B: pixel, 180C: pixel, 180D: pixel, 180E: pixel, 180F: pixel, 180G: pixel, 18 1: pixel circuit, 181A: pixel circuit, 181B: pixel circuit, 181C: pixel circuit, 181D: pixel circuit, 181E: pixel circuit, 181F: pixel circuit, 181G: pixel circuit, 200: flexible printed circuit board, 321: image data signal line, 322: image data signal line, 323: image data signal line, 330: scan signal line, 331: scan signal line, 332: scan signal line, 333: scan signal line, 334: scan signal line, 341: connection wiring, 342: connection wiring, 602: gate electrode, 604: first electrode, 606: second electrode, 612: gate electrode, 614: first electrode, 616: second electrode, 622: gate electrode, 624: first electrode, 626: second electrode, 632: gate electrode, 634: first electrode, 636: second electrode, 642: gate electrode , 644: first electrode, 646: second electrode, 652: gate electrode, 654: first electrode, 656: second electrode, 662: gate electrode, 664: first electrode, 666: second electrode, 672: gate electrode, 674: first electrode, 676: second electrode, 682: gate electrode, 684: first electrode, 686: second electrode, 692: gate electrode, 694: first electrode, 696: second electrode,

Claims

1. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between a power supply line to which the first constant voltage is supplied and a third node; a third transistor whose switching is controlled using a second control signal different from the first control signal, the third transistor being electrically connected between the first node and the second node; a fourth transistor whose switching is controlled using a third control signal different from the first control signal and the second control signal, the fourth transistor being electrically connected to the second node and supplying a reference voltage to the second node; a fifth transistor whose switching is controlled using a fourth control signal different from the first control signal, the second control signal, and the third control signal, and which is electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node; a sixth transistor whose switching is controlled using the third control signal, electrically connected to a fourth node, and configured to supply the reference voltage to the fourth node; a first capacitance element electrically connected between the first node and the fourth node; a second capacitance element electrically connected between the third node and the fourth node; a light-emitting element electrically connected to the second transistor; Including, Display device.

2. the light-emitting element is electrically connected to the third node; The display device according to claim 1 .

3. the light-emitting element is electrically connected to the third node; the value of the reference voltage supplied to the second node is different from the value of the reference voltage supplied to the fourth node; The display device according to claim 1 .

4. further comprising a seventh transistor; the seventh transistor is electrically connected between the third node and the light-emitting element, and switching of the seventh transistor is controlled using the second control signal; the light-emitting element is electrically connected to the third node; The display device according to claim 1 .

5. an eighth transistor and a reset voltage power supply line to which a reset voltage is supplied; the eighth transistor is controlled to be switched using the third control signal, and is electrically connected between the reset voltage power supply line and the light-emitting element; the light-emitting element is electrically connected to the third node; The display device according to claim 4 .

6. further comprising a reference voltage power supply line to which the reference voltage is supplied; the light-emitting element is electrically connected to the third node; the fourth transistor is electrically connected between the second node and the reference voltage power supply line; the sixth transistor is electrically connected between the fourth node and the fourth transistor and the second node; The display device according to claim 1 .

7. the power supply circuit further includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a constant voltage power supply line to which a second constant voltage is supplied, and a reference voltage power supply line to which a reference voltage is supplied; the second transistor is electrically connected between the third node and a fifth node; the seventh transistor is controlled to switch using the second control signal, and is electrically connected between the third node and the reference voltage power supply line; the eighth transistor is electrically connected between the power supply line and a sixth node, and switching of the eighth transistor is controlled using the third control signal; the ninth transistor is electrically connected between the fifth node and the sixth node, and switching of the ninth transistor is controlled using the second control signal; the tenth transistor is electrically connected between the fifth node and the constant voltage power supply line, and switching of the tenth transistor is controlled using the third control signal; the light-emitting element is electrically connected between the power supply line and the sixth node; The display device according to claim 1 .

8. the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-channel field effect transistors, a channel region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor includes an oxide semiconductor; The display device according to claim 1 .

9. the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are n-channel field effect transistors, a channel region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor includes an oxide semiconductor; The display device according to claim 5 .

10. the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are n-channel field effect transistors, a channel region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor includes an oxide semiconductor; The display device according to claim 7 .

11. a control circuit that outputs the first control signal, the second control signal, the third control signal, and a fourth control signal; The control circuit controlling the first control signal to be supplied with a high-level voltage, the first transistor to be turned on, and the first transistor to supply the data voltage to the first node so that a part of the period in which the third control signal is supplied with a high-level voltage, the sixth transistor to be turned on, and the sixth transistor to supply the reference voltage to the fourth node overlaps with the period in which the third control signal is supplied with a high-level voltage, the sixth transistor to be turned on, and the sixth transistor to supply the reference voltage to the fourth node; controlling the first capacitance element to hold a potential difference corresponding to the data voltage, and the second capacitance element to hold a potential difference corresponding to a threshold voltage of the second transistor; The display device according to claim 1 .

12. the gate electrode overlaps with the first capacitance element and the second capacitance element in a plan view; The display device according to claim 1 .

13. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a second transistor having a gate electrode electrically connected to the second node and electrically connected between the third node and the fourth node; a third transistor whose switching is controlled using a second control signal different from the first control signal, the third transistor being electrically connected between a reference voltage power supply line to which a reference voltage is supplied and the first node; a fourth transistor whose switching is controlled using the second control signal and electrically connected between the second node and the fourth node; a fifth transistor whose switching is controlled using a third control signal different from the first control signal and the second control signal, and which is electrically connected between a reset voltage power supply line to which a reset voltage is supplied and the fourth node; a sixth transistor whose switching is controlled using a fourth control signal different from the first control signal, the second control signal, and the third control signal, and which is electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node; a seventh transistor whose switching is controlled using a fifth control signal different from the first control signal, the second control signal, the third control signal, and the fourth control signal, and which is electrically connected between a power supply line to which a constant voltage is supplied and the fourth node; a first capacitance element electrically connected between the first node and the second node; a second capacitance element electrically connected between the first node and the third node; a light-emitting element electrically connected to the third node; Including, Display device.

14. the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are n-channel field effect transistors, a channel region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor includes an oxide semiconductor; The display device according to claim 13.

15. a control circuit that outputs the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal; the control circuit controls the first capacitance element to hold a potential difference corresponding to a threshold voltage of the second transistor, and then controls the second capacitance element to hold a potential difference corresponding to the data voltage; The display device according to claim 13.

16. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a third node; a second transistor having a gate electrode electrically connected to a second node and electrically connected between the third node and a fourth node; a third transistor whose switching is controlled using a second control signal different from the first control signal, the third transistor being electrically connected between the second node and the fourth node; a fourth transistor whose switching is controlled using the second control signal and electrically connected between a reference voltage power supply line to which a reference voltage serving also as an initialization voltage is supplied and the third node; a fifth transistor whose switching is controlled using a third control signal different from the first control signal and the second control signal, the fifth transistor being electrically connected between the fourth node and a fifth node; a sixth transistor whose switching is controlled by a fourth control signal different from the first control signal, the second control signal, and the third control signal, and which is electrically connected between the reference voltage power supply line and a first node; a seventh transistor whose switching is controlled using a fifth control signal different from the first control signal, the second control signal, the third control signal, and the fourth control signal, and which is electrically connected between a reference voltage line to which a reference voltage is supplied and the third node; an eighth transistor whose switching is controlled using the fourth control signal and which is electrically connected between a power supply line to which a constant voltage is supplied and the fifth node; a first capacitance element electrically connected between the first node and the second node; a second capacitance element electrically connected between the first node and the third node; a light-emitting element electrically connected between the power supply line and the fifth node; Including, Display device.

17. the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are n-channel field effect transistors, a channel region of each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor includes an oxide semiconductor; The display device according to claim 16.

18. a control circuit that outputs the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal; the control circuit controls the first capacitance element to hold a potential difference corresponding to a threshold voltage of the second transistor, and then controls the second capacitance element to hold a potential difference corresponding to the data voltage; The display device according to claim 16.

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