Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device and a manufacturing method of the semiconductor device that improve short circuit resistance.SOLUTION: A semiconductor device includes a gate oxide film 120 provided on a first base layer 40, a second base layer 50, a source layer 60, and a contact layer 70, a gate electrode 110 provided on the gate oxide film, a plurality of first contact holes 90a provided on the semiconductor substrate 10 so as to cover the gate oxide film and the gate electrode and exposing a part of the source layer, an interlayer insulating film 130 having a plurality of second contact holes exposing a part of the contact layer, a source electrode 100 connected to the source layer through the first contact hole and connected to the contact layer through the second contact hole, and a drain electrode 140 connected to the lower surface side of the substrate layer 20 on the lower surface of a drift layer 30. Further, the first contact hole and the second contact hole are separated by the interlayer insulating film.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] A planar SiC-MOSFET is disclosed in Patent Document 1. Planar MOSFETs have smaller parasitic capacitance than trench MOSFETs, and are therefore suitable for high-speed drive applications. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-233503 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in planar MOSFETs, the cell repeat direction and the channel length direction are the same, so when shrinking the cell pitch, the channel length must be shortened, which results in a problem of reduced short-circuit resistance.

[0005] In order to solve the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve short-circuit resistance. [Means for solving the problem]

[0006] a gate electrode provided on the gate oxide film; an interlayer insulating film provided on the semiconductor substrate to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; a source electrode connected to the source layer via the first contact hole and connected to the contact layer via the second contact hole; and a drain electrode connected to the lower surface side of the drift layer, wherein the first contact hole and the second contact hole are separated by the interlayer insulating film.

[0007] A second aspect of the present disclosure provides a semiconductor substrate having a first conductivity type drift layer, a first base layer of the first conductivity type and a second base layer of a second conductivity type provided side by side on an upper surface of the drift layer, a first conductivity type source layer selectively provided on an upper surface of the second base layer and having a higher impurity concentration than the first base layer, and a second conductivity type contact layer selectively provided on an upper surface of the second base layer and having a higher impurity concentration than the second base layer, a gate oxide film provided on the first base layer, the second base layer, the source layer, and the contact layer, a gate electrode provided on the gate oxide film, and a gate electrode provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode. and an interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer, a source electrode connected to the source layer via the first contact holes and connected to the contact layer via the second contact hole, and a drain electrode connected to the underside of the drift layer, wherein openings of the first contact holes and openings of the second contact holes are alternately arranged in a first direction in a plan view, and the width of the openings of the first contact holes in the first direction is smaller than the width of the openings of the second contact holes in the first direction.

[0008] a step of forming a first conductivity type drift layer in a semiconductor substrate; a step of forming a first conductivity type first base layer by ion implanting a first impurity into an upper surface side of the drift layer; a step of forming a first conductivity type second base layer provided alongside the first base layer on the upper surface side of the drift layer by forming a first mask on the upper surface side of the first base layer and ion implanting a second impurity into the first mask; a step of forming a thin film on the upper surface and sidewalls of the first mask and on the upper surface of the second base layer; a step of etching the thin film to form a second mask having the first mask; a step of forming a first conductivity type source layer selectively provided on the upper surface side of the second base layer by ion implanting the first impurity into the second base layer and the upper surface side of the second mask; a step of forming a contact layer of a second conductivity type selectively provided on an upper surface side of the base layer; a step of forming a gate oxide film on the first base layer, the second base layer, the source layer, and the contact layer; a step of forming a gate electrode on the gate oxide film; a step of forming an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; a step of forming a source electrode connected to the source layer via the first contact holes and connected to the contact layer via the second contact hole; and a step of forming a drain electrode on the lower surface side of the drift layer, wherein the first contact hole and the second contact hole are separated by the interlayer insulating film.

[0009] a step of forming a first conductivity type drift layer in a semiconductor substrate; a step of forming a first conductivity type first base layer by ion implanting a first impurity into an upper surface side of the drift layer; a step of forming a second conductivity type second base layer arranged alongside the first base layer on the upper surface side of the drift layer by forming a first mask on the upper surface side of the first base layer and ion implanting a second impurity into the upper surface side of the first base layer; a step of forming a thin film on the upper surface and sidewalls of the first mask and on the upper surface of the second base layer by etching the thin film to form a second mask having the first mask; a step of forming a first conductivity type source layer selectively arranged on the upper surface side of the second base layer by ion implanting the first impurity into the second base layer and the upper surface side of the second mask; a step of removing the second mask; forming a gate electrode on the gate oxide film; forming an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; forming a source electrode connected to the source layer via the first contact holes and to the contact layer via the second contact holes; and forming a drain electrode on the underside of the drift layer, wherein openings of the first contact holes and openings of the second contact holes are alternately arranged in a first direction in a plan view, and the width of the openings of the first contact holes in the first direction is smaller than the width of the openings of the second contact holes in the first direction. [Effects of the Invention]

[0010] According to the first to fourth aspects of the present disclosure, the area of ​​the source layer connected to the source electrode by the plurality of first contact holes is reduced, thereby improving the short-circuit resistance. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view illustrating a configuration of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along the line AA′ in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along the line BB′ in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along CC′ in FIG. [Figure 5] 1A to 1C are first diagrams illustrating a manufacturing process of a semiconductor device according to a first embodiment of the present disclosure. [Figure 6] FIG. 4 is a second diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 7] FIG. 10 is a third diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 8] FIG. 10 is a fourth diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 9] FIG. 10 is a fifth diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 10] FIG. 6 is a sixth diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 11] FIG. 10 is a seventh diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 12] FIG. 10 is an eighth view showing the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 13] FIG. 9 is a ninth diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 14] FIG. 10 is a tenth diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. [Figure 15] FIG. 10 is a plan view showing a configuration of a semiconductor device according to a second embodiment of the present disclosure. [Figure 16] FIG. 16 is a cross-sectional view taken along the line AA′ in FIG. [Figure 17] FIG. 16 is a cross-sectional view taken along the line BB′ in FIG. [Figure 18]FIG. 16 is a cross-sectional view taken along CC′ in FIG. [Figure 19] FIG. 10 is a plan view showing a configuration of a semiconductor device according to a third embodiment of the present disclosure. [Figure 20] FIG. 20 is a cross-sectional view taken along the line AA′ in FIG. 19. [Figure 21] FIG. 20 is a cross-sectional view taken along the line BB′ in FIG. [Figure 22] FIG. 20 is a cross-sectional view taken along CC′ in FIG. 19. [Figure 23] FIG. 10 is a plan view showing a configuration of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 24] FIG. 24 is a cross-sectional view taken along the line AA′ in FIG. 23. [Figure 25] FIG. 24 is a cross-sectional view taken along the line BB′ in FIG. 23. [Figure 26] FIG. 24 is a cross-sectional view taken along CC′ in FIG. 23. [Figure 27] FIG. 11 is a plan view showing a configuration of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 28] FIG. 28 is a cross-sectional view taken along the line AA′ in FIG. 27. [Figure 29] FIG. 28 is a cross-sectional view taken along the line BB′ in FIG. 27. [Figure 30] FIG. 28 is a cross-sectional view taken along CC′ in FIG. 27. [Figure 31] FIG. 13 is a plan view showing a configuration of a semiconductor device according to a sixth embodiment of the present disclosure. [Figure 32] FIG. 32 is a cross-sectional view taken along the line AA′ in FIG. 31. [Figure 33] FIG. 32 is a cross-sectional view taken along the line BB′ in FIG. [Figure 34] FIG. 32 is a cross-sectional view taken along CC′ in FIG. 31. [Figure 35] FIG. 13 is a plan view showing a configuration of a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 36] FIG. 36 is a cross-sectional view taken along the line AA′ in FIG. 35. [Figure 37] FIG. 36 is a cross-sectional view taken along the line BB′ in FIG. 35. [Figure 38] FIG. 36 is a cross-sectional view taken along CC′ in FIG. [Figure 39] FIG. 13 is a plan view showing a configuration of a semiconductor device according to an eighth embodiment of the present disclosure. [Figure 40] FIG. 40 is a cross-sectional view taken along the line AA′ in FIG. 39. [Figure 41] FIG. 40 is a cross-sectional view taken along the line BB′ in FIG. 39. [Figure 42] FIG. 40 is a cross-sectional view taken along CC′ in FIG. 39. [Figure 43] FIG. 10 is a plan view showing a configuration of a semiconductor device according to a first modified example of the second embodiment of the present disclosure. [Figure 44] FIG. 10 is a plan view showing a configuration of a semiconductor device according to a second modification of the second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] A semiconductor device and a method for manufacturing the semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0013] 1 is a plan view showing the configuration of a semiconductor device according to a first embodiment of the present disclosure, showing the planar layout of a cell region of a semiconductor device 1000 that is a planar MOSFET.

[0014] For convenience of explanation, the source electrode, the interlayer insulating film, the gate electrode, and the passivation film are not shown in Fig. 1. The same applies to the plan views showing the configuration of the semiconductor device shown below.

[0015] The semiconductor device 1000 includes an n-type base layer 40 extending in a first direction 2. On both sides of the n-type base layer 40 in the second direction 4, p-type base layers 50 extending in the first direction 2 are arranged. The width of the p-type base layer 50 in the second direction 4 is referred to as a channel length 6. On the side of the p-type base layer 50 in the second direction 4 where the n-type base layer 40 is not arranged, an n+-type source layer 60 extending in the first direction 2 is arranged. The n+-type source layer 60 has a higher impurity concentration than the n-type base layer 40.

[0016] The n+ type source layer 60 is partially covered with a p+ type contact layer 70. The p+ type contact layer 70 has a higher impurity concentration than the p-type base layer 50. The p+ type contact layers 70 are arranged at regular intervals in the first direction 2 so as to discretely cover the n+ type source layer 60.

[0017] Here, the n-type base layer 40, the p-type base layer 50, the n+ type source layer 60, and the p+ type contact layer 70 are referred to as an active region. The active region is a region through which current flows when the semiconductor device 1000, which is a MOSFET, is switched on.

[0018] The p+ type contact layer 70 is provided to stabilize the potential of the p type base layer 50 at 0 V, the same potential as the source electrode 100, by making ohmic contact with the source electrode 100 described below. If the potential of the p type base layer 50 is unstable, the voltage applied to the region of the gate oxide film 120 between the p type base layer 50 and the gate electrode 110 will fluctuate, causing fluctuations in the on characteristics during switching. The p+ type contact layer 70 suppresses this fluctuation.

[0019] A p-contact hole 90a is arranged in a region of the n+ type source layer 60 that is covered with the p+ type contact layer 70. An n-contact hole 90b is arranged in a region of the n+ type source layer 60 that is not covered with the p+ type contact layer 70. That is, the p-contact hole 90a and the n-contact hole 90b are separated by an interlayer insulating film 130, which will be described later.

[0020] The openings of the p contact hole 90a and the n contact hole 90b are rectangular and have the same shape and size. The p contact holes 90a and the n contact holes 90b are alternately arranged at regular intervals in the first direction 2 in plan view so that the centers of the p contact holes 90a and the n contact holes 90b overlap the center of the width of the n+ type source layer 60 in the second direction 4. The area of ​​the n contact holes 90b in the entire active region is smaller than the area when the n contact holes 90b are not separated by an interlayer insulating film 130, which will be described later.

[0021] While the example shown here shows that the openings of the p contact hole 90a and the n contact hole 90b are rectangular, the shape is not limited thereto and may be circular or elliptical, for example. Furthermore, when the openings of the p contact hole 90a and the n contact hole 90b are rectangular, their lengths in the first direction 2 and the second direction 4 may all be equal. Alternatively, in the above-described case, the width of the n contact hole 90b in the first direction 2 may be smaller than the width of the p contact hole 90a in the first direction 2. This allows the area of ​​the n contact hole 90b to be made even smaller than when it is not separated by the interlayer insulating film 130 described below.

[0022] Furthermore, the number of n-contact holes 90b in the entire semiconductor device 1000 may be reduced by increasing the distance between the n-contact hole 90b and the p-contact hole 90a.

[0023] Fig. 2 is a cross-sectional view taken along line AA' in Fig. 1. For the sake of convenience, the passivation film is not shown in Fig. 2. The same applies to the cross-sectional views taken along line AA' shown below.

[0024] The semiconductor device 1000 includes a semiconductor substrate 10. The semiconductor substrate 10 may be made of a wide bandgap semiconductor, such as silicon carbide, a gallium nitride-based material, or diamond.

[0025] The semiconductor substrate 10 has an n+ type substrate layer 20. The n+ type substrate layer 20 is formed of, for example, silicon carbide. A drain electrode 140 is connected to the lower surface side of the n+ type substrate layer 20. An n- type drift layer 30 is connected to the upper surface side of the n+ type substrate layer 20.

[0026] An n-type base layer 40 is provided on the upper surface side of the n-type drift layer 30. P-type base layers 50 are provided on both sides of the n-type base layer 40. That is, the n-type base layer 40 and the p-type base layer 50 are provided side by side on the upper surface side of the n-type drift layer 30.

[0027] An n+ type source layer 60 is selectively provided on the upper surface side of the p-type base layer 50. The n+ type source layer 60 is a source layer having a higher impurity concentration than the n-type base layer 40. Furthermore, a p+ type contact layer 70 is selectively provided on the upper surface side of the p-type base layer 50, on the side of the n+ type source layer 60 that is not connected to the p-type base layer 50. The p+ type contact layer 70 is a contact layer having a higher impurity concentration than the p-type base layer 50.

[0028] That is, the p-type base layer 50 is thicker than the n+ type source layer 60 and the p+ type contact layer 70. The p+ type contact layer 70 is also thicker than the n+ type source layer 60. Furthermore, the thickness of the n-type base layer 40 may be equal to that of the p-type base layer 50, for example.

[0029] A gate oxide film 120 is provided on the n-type base layer 40, the p-type base layer 50, the n+ type source layer 60, and the p+ type contact layer 70. A gate electrode 110 is provided on the gate oxide film 120.

[0030] The upper surfaces of the gate electrode 110 and the gate oxide film 120 are covered with an interlayer insulating film 130. The upper surfaces of the interlayer insulating film 130 and the p+ type contact layer 70 are covered with a source electrode 100.

[0031] 2, the multiple p contact holes 90a shown in Fig. 1 are provided so as to expose a portion of the p+ type contact layer 70 from the interlayer insulating film 130. In other words, the p contact holes 90a electrically connect the p+ type contact layer 70 and the source electrode 100.

[0032] Fig. 3 is a cross-sectional view taken along line BB' in Fig. 1. For convenience of explanation, the passivation film is not shown in Fig. 3. The same applies to the cross-sectional views taken along line BB' shown below.

[0033] The cross-sectional view shown in Figure 3 differs from the cross-sectional view shown in Figure 2 in that it does not pass through the p+ type contact layer 70. Therefore, only the parts that are different in configuration from the cross-sectional view shown in Figure 2 will be described here, and other descriptions will be omitted.

[0034] An n+ type source layer 60 is selectively provided on the upper surface side of the p type base layer 50. That is, the p type base layer 50 is thicker than the n+ type source layer 60.

[0035] A gate oxide film 120 is provided on the n-type base layer 40, the p-type base layer 50, and the n+ type source layer 60. The upper surfaces of the interlayer insulating film 130 and the n+ type source layer 60 are covered with a source electrode 100.

[0036] 1 is provided so as to expose the n+ type source layer 60 from the interlayer insulating film 130, as shown in Fig. 3. That is, the n+ type source layer 60 and the source electrode 100 are electrically connected by the n contact hole 90b.

[0037] Fig. 4 is a cross-sectional view taken along CC' in Fig. 1. For convenience of explanation, the passivation film is not shown in Fig. 4. The same applies to the cross-sectional views taken along CC' shown below.

[0038] The semiconductor device 1000 includes a semiconductor substrate 10. The semiconductor substrate 10 has an n+ type substrate layer 20. A drain electrode 140 is connected to the lower surface side of the n+ type substrate layer 20. An n- type drift layer 30 is connected to the upper surface side of the n+ type substrate layer 20.

[0039] A p-type base layer 50 is provided on the upper surface side of the n- type drift layer 30. N+ type source layers 60 and p+ type contact layers 70 are alternately provided on the upper surface side of the p-type base layer 50. The upper surfaces of the boundaries between the n+ type source layers 60 and the p+ type contact layers 70 are covered with an interlayer insulating film 130. The upper surfaces of the interlayer insulating film 130, the n+ type source layers 60, and the p+ type contact layers 70 are covered with a source electrode 100.

[0040] 2, the p-type contact hole 90a electrically connects the p+-type contact layer 70 and the source electrode 100. Also, as shown in FIG. 3, the n-type contact hole 90b electrically connects the n+-type source layer 60 and the source electrode 100.

[0041] Furthermore, the area of ​​the n + -type source layer 60 connected to the source electrode 100 by the plurality of n-contact holes 90b is smaller than the area when the n-contact holes 90b are not separated by the interlayer insulating film 130.

[0042] Next, a method for manufacturing a semiconductor device according to this embodiment will be described. Here, a method for manufacturing a semiconductor device 1000 will be described, but the basic configuration of the method for manufacturing a semiconductor device according to this disclosure is the same for all of them. The method for manufacturing a semiconductor device according to each embodiment is shown by substituting the size of a component or the type of ions to be implanted in the method for manufacturing the semiconductor device 1000 to correspond to the component to be replaced.

[0043] 5 is a first diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. The semiconductor device 1000 is formed on an n+ type substrate layer 20.

[0044] Hereinafter, in the drawings showing the manufacturing process of the semiconductor device 1000, a cross-sectional structure corresponding to the cross-sectional view taken along line AA' in FIG. 1 is shown.

[0045] 6 is a second diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, an n- type drift layer 30 is formed on the upper surface of an n+ type substrate layer 20 by, for example, epitaxial growth.

[0046] 7 is a third diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, n-type impurities such as N are ion-implanted into the upper surface side of the n-type drift layer 30 to form the n-type base layer 40. The n-type base layer 40 may be selectively formed on a portion of the upper surface of the n-type drift layer 30 by using a photomask, for example, or may be formed on the entire upper surface of the n-type drift layer 30 by not using a photomask.

[0047] 8 is a fourth diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, a first mask 42 is formed on the upper surface of the n-type base layer 40 so as to leave an opening in a portion corresponding to a region where the p-type base layer 50 will be formed. The first mask 42 is formed by depositing a thin film 44, such as a CVD film, followed by photolithography and dry etching.

[0048] 9 is a fifth diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, p-type impurities such as Al are ion-implanted into the upper surface side of the n-type base layer 40 to form a p-type base layer 50 provided alongside the n-type base layer 40 on the upper surface side of the n-type drift layer 30. Note that in this ion implantation, n-type impurities such as N may be implanted shallowly.

[0049] As a result of the above-described ion implantation, the region covered by the first mask 42 remains as the n-type base layer 40, and the region not covered by the first mask 42 forms a p-type base layer 50. That is, the outermost surface of the channel region of the finally obtained semiconductor device 1000 becomes the n-type base layer 40. As a result, a channel is more easily induced, and the threshold voltage can be reduced.

[0050] 10 is a sixth diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, a thin film 52 is formed on the upper surface and sidewalls of the first mask 42 and on the upper surface of the p-type base layer 50. The thin film 52 is, for example, a CVD film.

[0051] 11 is a seventh diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, thin film 52 is etched to form second mask 54 having first mask 42. Specifically, thin film 52 is etched until spacers 52a are formed on the sidewalls of first mask 42. This etching is achieved by anisotropic etching, such as dry etching, under conditions that cause almost no etching in the direction of the sidewalls of first mask 42.

[0052] 12 is an eighth diagram illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, n-type impurities such as N are ion-implanted into the upper surfaces of the p-type base layer 50 and the second mask 54 to form n+-type source layers 60 selectively provided on the upper surface of the p-type base layer 50.

[0053] In the above-described ion implantation, the region covered by the second mask 54 is maintained, and the n+ type source layer 60 is formed in the region not covered by the second mask 54. The second mask 54 is formed in a self-aligned manner with respect to the first mask 42. Therefore, no misalignment occurs between the p-type base layer 50 and the n+ type source layer 60, and the length of the channel region does not fluctuate. As a result, fluctuations in threshold voltage caused by misalignment can be eliminated. That is, the semiconductor device 1000 according to this embodiment can not only improve the short-circuit withstand capability itself, but also suppress variations in short-circuit withstand capability.

[0054] 13 is a ninth view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, second mask 54 is removed by wet etching using, for example, HF.

[0055] 14 is a tenth diagram illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present disclosure. Here, p-type impurities such as Al are selectively ion-implanted into the upper surface of the n+ type source layer 60 to form the p+ type contact layer 70 selectively provided on the upper surface of the p-type base layer 50.

[0056] The above-described ion implantation is performed after forming a mask having an opening corresponding to the region where the p+-type contact layer 70 is to be formed. When ion implantation is performed at a high temperature to increase the implantation dose, the mask may be formed by, for example, forming a CVD film, photolithography, and dry etching. When ion implantation is performed at room temperature, the mask may be formed by, for example, a photomask. After the ion implantation is completed, the mask formed before the ion implantation is removed by, for example, wet etching using HF or the like.

[0057] Subsequently, a gate oxide film 120 is formed on the n-type base layer 40, the p-type base layer 50, the n+ type source layer 60, and the p+ type contact layer 70 by a typical method. Next, a gate electrode 110 is formed on the gate oxide film 120 by a typical method. Next, an interlayer insulating film 130 is formed on the semiconductor substrate 10 by a typical method so as to cover the gate oxide film 120 and the gate electrode 110, and has a plurality of n contact holes 90b exposing portions of the n+ type source layer 60 and a plurality of p contact holes 90a exposing portions of the p+ type contact layer 70.

[0058] Next, a source electrode 100 is formed by a general method. The source electrode 100 is connected to the n+ type source layer 60 through the n contact hole 90b and to the p+ type contact layer 70 through the p contact hole 90a. A drain electrode 140 is also formed on the lower surface side of the n- type drift layer 30 by a general method. A passivation film or the like may also be formed by a general method. Through the above steps, the semiconductor device 1000 is formed.

[0059] The effects of the semiconductor device 1000 according to this embodiment will be described. The contact holes in conventional semiconductor devices simultaneously expose the p+ type contact layer 70 and the n+ type source layer 60. That is, the p+ type contact layer 70 and the n+ type source layer 60 are both electrically connected to the source electrode 100.

[0060] On the other hand, the semiconductor device 1000 according to this embodiment has a p-contact hole 90a electrically connecting the p+-type contact layer 70 and the source electrode 100, and an n-contact hole 90b electrically connecting the n+-type source layer 60 and the source electrode 100.

[0061] As the area of ​​the n-type contact hole 90b is reduced, the contact resistance in the current path between the drain electrode 140 and the source electrode 100 becomes non-negligible. That is, a voltage drop occurs between the source electrode 100 and the adjacent layer. Specifically, a potential difference occurs between the source electrode 100 and the n+ type source layer 60.

[0062] In the semiconductor device 1000 according to this embodiment, the area of ​​the n contact hole 90b in the entire active region is made smaller than the area in the case where the n contact hole 90b is not separated by the interlayer insulating film 130. In other words, the area of ​​the n+ type source layer 60 connected to the source electrode 100 by the n contact hole 90b is made smaller than the area in the case where the n contact hole 90b is not separated by the interlayer insulating film 130.

[0063] As a result, the voltage drop in the source electrode 100-n+ type source layer 60 can be made larger than when the n contact hole 90b is not separated by the interlayer insulating film 130. Here, the potential of the p+ type contact layer 70 is the same as the potential of the p type base layer 50. In other words, the potential of the n+ type source layer 60 can be made higher than the potential of the p type base layer 50 by the amount of the voltage drop in the source electrode 100-n+ type source layer 60.

[0064] When the potential of the n+ type source layer 60 is made higher than the potential of the p-type base layer 50, a substrate bias effect can be generated. The substrate bias effect is an effect that makes inversion less likely to occur. More specifically, when the potential of the n+ type source layer 60 is first made higher than the potential of the p-type base layer 50, a reverse bias is applied to the PN junction between the n+ type source layer 60 and the p-type base layer 50, causing the depletion layer to expand. As a result, negative fixed charges are generated in the depletion layer of the p-type base layer 50, neutralizing the positive charges that are generated when switching is turned on. In other words, inversion becomes less likely to occur.

[0065] The substrate bias effect caused by the potential difference between the n+ type source layer 60 and the p-type base layer 50 varies depending on the value of the current flowing through the n+ type source layer 60. This variation increases as the current increases, resulting in a greater effect of lowering the effective gate voltage. In other words, the substrate bias effect is small under normal conditions, but is highly effective under abnormal conditions where an overcurrent flows, such as during a short circuit. Therefore, the short-circuit current can be effectively reduced without significantly affecting losses under normal conditions.

[0066] Furthermore, the semiconductor device 1000 according to this embodiment is a planar MOSFET. In a planar MOSFET, when the channel density is increased to improve the characteristics, it is necessary to perform cell pitch shrinking. In cell pitch shrinking, the longitudinal direction of the channel length 6 and the shrinking direction are the same. Therefore, when performing cell pitch shrinking, it is necessary to shorten the channel length 6.

[0067] However, shortening the channel length 6 lowers the threshold voltage. This increases the saturation current, which creates the problem of reduced short-circuit capability. Therefore, in planar MOSFETs, in order to compensate for the issues that arise from shortening the channel length 6, it is necessary to improve short-circuit capability in a way that does not hinder cell pitch shrink.

[0068] The semiconductor device 1000 according to this embodiment can improve the short-circuit resistance without hindering cell pitch shrinking. That is, the semiconductor device 1000 according to this embodiment can achieve both improved characteristics due to cell pitch shrinking and increased short-circuit resistance in a planar MOSFET.

[0069] When shrinking the cell pitch in a trench MOSFET, the length direction of the channel length is different from the shrinking direction. Therefore, in a trench MOSFET, there is no need to shorten the channel length when shrinking the cell pitch. In other words, the semiconductor device 1000 according to this embodiment is particularly effective in a planar MOSFET.

[0070] As described above, in the semiconductor device 1000 according to this embodiment, the area of ​​the n+ type source layer 60 connected to the source electrode 100 by the n contact hole 90b is made smaller than the area when the n contact hole 90b is not separated by the interlayer insulating film 130. As a result, the short-circuit resistance can be improved.

[0071] In this embodiment, the openings of the p contact holes 90a and the n contact holes 90b have the same shape and size, and are periodically arranged alternately in the first direction 2 in plan view. As a result, in the manufacturing process of the semiconductor device 1000, dimensional variations within a chip or wafer can be suppressed, thereby achieving stable dimensional control.

[0072] As a further modification of this embodiment, the area of ​​the n-contact hole 90b relative to the entire active region may be reduced. For example, the width of the n-contact hole 90b in the first direction 2 may be made smaller than the width of the p-contact hole 90a in the first direction 2. This modification can further improve the short-circuit resistance.

[0073] Embodiment 2 15 is a plan view illustrating a configuration of a semiconductor device according to a second embodiment of the present disclosure. Fig. 15 illustrates a planar layout of a cell region of a semiconductor device 2000, which is a planar MOSFET. The semiconductor device 2000 differs from the semiconductor device 1000 in that the length of the p+ type contact layer 70 in the first direction 2 is long, and that two p contact holes 90a and two n contact holes 90b are alternately arranged.

[0074] The openings of the p contact hole 90a and the n contact hole 90b are rectangular and have the same shape and size. The p contact holes 90a and the n contact holes 90b are alternately arranged two by two at regular intervals in the first direction 2 in plan view so that their centers coincide with the center of the width of the n+ type source layer 60 in the second direction 4. The area of ​​the n contact holes 90b in the entire active region is smaller than the area of ​​the p contact holes 90a in the entire active region.

[0075] Here, the n contact holes 90b and p contact holes 90a are shown as being arranged two by two in a plane view in the first direction 2 at regular intervals, but this is not limited to this and they may be arranged periodically, for example.

[0076] 43 shows an example in which the openings of n contact hole 90b and the openings of p contact holes 90a are periodically arranged. Fig. 43 is a plan view showing the configuration of a semiconductor device according to a first modification of the second embodiment of the present disclosure. In semiconductor device 2000a, the openings of one n contact hole 90b and the openings of two p contact holes 90a are alternately arranged at regular intervals in first direction 2 in plan view.

[0077] 44 is a plan view illustrating a configuration of a semiconductor device according to a second modification of the second embodiment of the present disclosure. In the semiconductor device 2000b, openings of two n-contact holes 90b and openings of three p-contact holes 90a are alternately arranged at regular intervals in the first direction 2 in plan view.

[0078] Here, m n contact holes 90b arranged at regular intervals in the first direction 2 are defined as a first contact hole group, and n p contact holes 90a arranged at regular intervals in the first direction 2 are defined as a second contact hole group. In this case, the semiconductor device according to the present embodiment is a semiconductor device in which the first contact hole group and the second contact hole group are arranged at regular intervals in the first direction 2 in a plan view. Note that m is a value between 1 and n. This aspect makes it possible to make the area of ​​the n contact holes 90b even smaller than the area when they are not separated by the interlayer insulating film 130.

[0079] Fig. 16 is a cross-sectional view taken along the line AA' in Fig. 15. Fig. 16 is the same as Fig. 2, and therefore the explanation will be omitted.

[0080] Fig. 17 is a cross-sectional view taken along line BB' in Fig. 15. Fig. 17 is the same as Fig. 3, and therefore the description will be omitted.

[0081] Fig. 18 is a cross-sectional view taken along CC' in Fig. 15. Fig. 18 differs from Fig. 4 in that the lengths of the n+ type source layer 60 and the p+ type contact layer 70 in the first direction 2 are long.

[0082] As described above, in the semiconductor device 2000 according to this embodiment, the area of ​​the n+ type source layer 60 connected to the source electrode 100 by the multiple n contact holes 90b is made smaller than the area when the n contact holes 90b are not separated by the interlayer insulating film 130. As a result, the short-circuit resistance can be improved.

[0083] In addition, in the semiconductor device 2000 according to this embodiment, the openings of the p contact holes 90a and the n contact holes 90b are rectangular and have the same shape and size, and are arranged two by two at regular intervals in the first direction 2 in a plan view. As a result, in the manufacturing process of the semiconductor device 1000, dimensional variations within a chip or wafer can be suppressed, thereby realizing stable dimensional control.

[0084] Embodiment 3 19 is a plan view illustrating a configuration of a semiconductor device according to a third embodiment of the present disclosure. Fig. 19 illustrates a planar layout of a cell region of a semiconductor device 3000, which is a planar MOSFET. The semiconductor device 3000 differs from the semiconductor device 1000 in that the length of the p+ type contact layer 70 in the second direction 4 is longer.

[0085] The n+ type source layer 60 and the p-type base layer 50 are partially covered with a p+ type contact layer 70. The p+ type contact layer 70 is arranged in the first direction 2 so as to discretely cover the n+ type source layer 60 and the p-type base layer 50. The length of the p+ type contact layer 70 in the second direction 4 is longer than the length of the n+ type source layer 60 in the second direction 4.

[0086] Fig. 20 is a cross-sectional view taken along the line AA' in Fig. 19. Fig. 20 differs from Fig. 2 in that the n + -type source layer 60 is not provided.

[0087] An n-type base layer 40 is provided on the upper surface of the n-type drift layer 30. P-type base layers 50 are provided on both sides of the n-type base layer 40. A p+-type contact layer 70 is selectively provided on the upper surface of the p-type base layer 50. That is, the p-type base layer 50 is thicker than the p+-type contact layer 70. A gate oxide film 120 is provided on the n-type base layer 40, the p-type base layer 50, and the p+-type contact layer 70.

[0088] Fig. 21 is a cross-sectional view taken along line BB' in Fig. 19. Fig. 21 is the same as Fig. 3, and therefore the explanation will be omitted.

[0089] Fig. 22 is a cross-sectional view taken along CC' in Fig. 19. Fig. 22 is the same as Fig. 4, and therefore the description will be omitted.

[0090] As described above, in the semiconductor device 3000 according to this embodiment, the area of ​​the n+ type source layer 60 connected to the source electrode 100 by the n contact hole 90b is made smaller than the area when the n contact hole 90b is not separated by the interlayer insulating film 130. As a result, the short-circuit resistance can be improved.

[0091] Furthermore, the semiconductor device 3000 according to this embodiment does not have an n+ type source layer 60 in the region shown in FIG. 20 . That is, the semiconductor device 3000 has a region in which the p-type base layer 50 and the p+ type contact layer 70 are connected only by a path that does not pass through the n+ type source layer 60. In this region, no channel is generated when switching is turned on. As a result, the semiconductor device 3000 can reduce the channel region occupying the entire active region, thereby reducing the saturation current and further improving the short-circuit resistance.

[0092] Embodiment 4 23 is a plan view illustrating a configuration of a semiconductor device according to a fourth embodiment of the present disclosure. The planar layout of a cell region of a semiconductor device 4000, which is a planar MOSFET, is shown. The semiconductor device 4000 differs from the semiconductor device 1000 in that it includes a JFET region 8.

[0093] The JFET region 8 is disposed between the first region 7 and the second region 9. The JFET region 8 includes an n-type base layer 40 extending in the first direction 2. A portion of the n-type base layer 40 is replaced with a p-type diffusion layer 80. Specifically, the p-type diffusion layers 80 and the n-type base layers 40 are disposed alternately at regular intervals in the first direction 2 in a plan view. Furthermore, the p-type diffusion layers 80 and the p+ type contact layers 70 are disposed alternately at regular intervals in the second direction 4 in a plan view.

[0094] The p-type diffusion layer 80 is arranged in the first direction 2 so as to discretely cover the n-type base layer 40. The length of the p-type diffusion layer 80 in the second direction 4 is longer than the width of the n-type base layer 40 in the second direction 4. Therefore, the p-type diffusion layer 80 is connected to the p-type base layer 50.

[0095] Fig. 24 is a cross-sectional view taken along the line AA' in Fig. 23. Fig. 24 differs from Fig. 2 in that a p-type diffusion layer 80 is provided instead of the n-type base layer 40.

[0096] A p-type diffusion layer 80 is provided on the upper surface side of the n- type drift layer 30. A p-type base layer 50 is provided on both sides of the p-type diffusion layer 80. A gate oxide film 120 is provided on the p-type diffusion layer 80, the p-type base layer 50, the n+ type source layer 60, and the p+ type contact layer 70.

[0097] Fig. 25 is a cross-sectional view taken along line BB' in Fig. 23. Fig. 25 is the same as Fig. 3, and therefore the explanation will be omitted.

[0098] Fig. 26 is a cross-sectional view taken along CC' in Fig. 23. Fig. 26 differs from Fig. 4 in that a part of the n+ type source layer 60 is replaced with a p+ type contact layer 70.

[0099] As described above, in the semiconductor device 4000 according to this embodiment, the area of ​​the n+ type source layer 60 connected to the source electrode 100 by the n contact hole 90b is made smaller than the area when the n contact hole 90b is not separated by the interlayer insulating film 130. As a result, the short-circuit resistance can be improved.

[0100] Furthermore, the semiconductor device 4000 according to this embodiment does not have an n-type base layer 40 in the region shown in FIG. 24 . That is, the semiconductor device 4000 has a region in which the p-type base layer 50 and the n − -type drift layer 30 are connected only by a path that does not pass through the n-type base layer 40. In this region, no channel is generated when switching is turned on. As a result, the semiconductor device 4000 can reduce the channel region occupying the entire active region, thereby reducing the saturation current and further improving the short-circuit resistance.

[0101] Fifth embodiment 27 is a plan view showing the configuration of a semiconductor device according to a fifth embodiment of the present disclosure. Fig. 27 shows a planar layout of a cell region of a semiconductor device 5000, which is a planar MOSFET. The semiconductor device 5000 differs from the semiconductor device 1000 in that the area of ​​the p+ type contact layer 70 is larger and that the semiconductor device 5000 has contact holes 90 instead of the p contact holes 90a and the n contact holes 90b.

[0102] The n+ type source layer 60 is partially covered with a p+ type contact layer 70. The p+ type contact layers 70 are arranged at regular intervals in the first direction 2 so as to discretely cover the n+ type source layer 60.

[0103] Furthermore, contact holes 90 are arranged in the n+ type source layer 60. The contact holes 90 extend in the first direction 2 across the region covered with the p+ type contact layer 70 and the region not covered with the p+ type contact layer 70. That is, the contact holes 90 are made up of p contact holes 90a and n contact holes 90b arranged alternately in the first direction 2. The width of the contact holes 90 in the second direction 4 is smaller than the length of the p+ type contact layer 70 in the second direction 4, for example.

[0104] Here, the width of the opening of n contact hole 90b in the first direction 2 is shorter than the width of the opening of p contact hole 90a in the first direction 2. Therefore, the area of ​​n+ type source layer 60 connected to source electrode 100 by contact hole 90 is smaller than the area of ​​p+ type contact layer 70 connected to source electrode 100 by contact hole 90.

[0105] Fig. 28 is a cross-sectional view taken along the line AA' in Fig. 27. Fig. 28 differs from Fig. 2 in that a contact hole 90 is provided instead of the p-contact hole 90a, and that the length of the p+-type contact layer 70 in the first direction 2 is longer.

[0106] Fig. 29 is a cross-sectional view taken along the line BB' in Fig. 27. Fig. 29 differs from Fig. 3 in that a contact hole 90 is provided instead of the n-contact hole 90b.

[0107] Fig. 30 is a cross-sectional view taken along CC' in Fig. 27. Fig. 30 differs from Fig. 4 in that the lengths of the n+ type source layer 60 and the p+ type contact layer 70 in the first direction 2 are different, and in that the interlayer insulating film 130 is not provided.

[0108] A p-type base layer 50 is provided on the upper surface side of the n- type drift layer 30. N+ type source layers 60 and p+ type contact layers 70 are alternately provided on the upper surface side of the p-type base layer 50. The upper surfaces of the n+ type source layers 60 and the p+ type contact layers 70 are covered with a source electrode 100.

[0109] Next, the effects of the semiconductor device 5000 according to this embodiment will be described. In the semiconductor device 5000 according to this embodiment, the width in the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is made smaller than the width in the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 through the contact hole 90. As a result, the potential of the n+ type source layer 60 can be made higher than the potential of the p-type base layer 50 by the amount of the voltage drop between the source electrode 100 and the n+ type source layer 60 via the contact hole 90.

[0110] Therefore, the semiconductor device 5000 according to this embodiment exhibits the same effects as those shown in the first embodiment. That is, the semiconductor device 5000 according to this embodiment can improve short-circuit resistance. Furthermore, the semiconductor device 5000 according to this embodiment can achieve both improved characteristics due to a cell pitch shrink and increased short-circuit resistance in a planar MOSFET.

[0111] Furthermore, in this embodiment, the resistance in the path indicated by resistor 55b is greater than the resistance in the path indicated by resistor 55a. That is, in this embodiment, the voltage drop in the path indicated by resistor 55b can be made greater than the voltage drop in the path indicated by resistor 55a. As a result, the potential of the n+ type source layer 60 can be made even higher than the potential of the p-type base layer 50.

[0112] As described above, in the semiconductor device 5000 according to this embodiment, the width in the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is set smaller than the width in the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 through the contact hole 90. As a result, the short-circuit resistance can be improved.

[0113] Sixth embodiment 31 is a plan view illustrating a configuration of a semiconductor device according to a sixth embodiment of the present disclosure. The planar layout of a cell region of a semiconductor device 6000, which is a planar MOSFET, is shown. The semiconductor device 6000 differs from the semiconductor device 5000 in that it includes a JFET region 8.

[0114] The JFET region 8 is disposed between the first region 7 and the second region 9. The JFET region 8 includes an n-type base layer 40 extending in the first direction 2. A portion of the n-type base layer 40 is replaced with a p-type diffusion layer 80. Specifically, the p-type diffusion layers 80 and the n-type base layers 40 are disposed alternately at regular intervals in the first direction 2 in a plan view. Furthermore, the p-type diffusion layers 80 and the p+ type contact layers 70 are disposed alternately at regular intervals in the second direction 4 in a plan view.

[0115] The p-type diffusion layer 80 is arranged in the first direction 2 so as to discretely cover the n-type base layer 40. The length of the p-type diffusion layer 80 in the second direction 4 is longer than the width of the n-type base layer 40 in the second direction 4. Therefore, the p-type diffusion layer 80 is connected to the p-type base layer 50.

[0116] Fig. 32 is a cross-sectional view taken along the line AA' in Fig. 31. Fig. 32 differs from Fig. 28 in that a p-type diffusion layer 80 is provided instead of the n-type base layer 40.

[0117] A p-type diffusion layer 80 is provided on the upper surface side of the n- type drift layer 30. A p-type base layer 50 is provided on both sides of the p-type diffusion layer 80. A gate oxide film 120 is provided on the p-type diffusion layer 80, the p-type base layer 50, the n+ type source layer 60, and the p+ type contact layer 70.

[0118] Fig. 33 is a cross-sectional view taken along line BB' in Fig. 31. Fig. 33 is the same as Fig. 29, and therefore the explanation will be omitted.

[0119] Fig. 34 is a cross-sectional view taken along CC' in Fig. 31. Fig. 34 is the same as Fig. 30, and therefore the explanation will be omitted.

[0120] As described above, in the semiconductor device 6000 according to this embodiment, the width in the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 by the contact hole 90 is set smaller than the width in the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 by the contact hole 90. As a result, the short-circuit resistance can be improved.

[0121] Furthermore, the semiconductor device 6000 according to this embodiment does not have an n-type base layer 40 in the region shown in FIG. 32 . That is, the semiconductor device 6000 has a region in which the p-type base layer 50 and the n − -type drift layer 30 are connected only by a path that does not pass through the n-type base layer 40. In this region, no channel is generated when switching is turned on. As a result, the semiconductor device 6000 can reduce the channel region occupying the entire active region, thereby reducing the saturation current and further improving the short-circuit resistance.

[0122] Embodiment 7 35 is a plan view illustrating a configuration of a semiconductor device according to a seventh embodiment of the present disclosure. This figure illustrates a planar layout of a cell region of a semiconductor device 7000, which is a planar MOSFET. The semiconductor device 7000 differs from the semiconductor device 5000 in that it includes a JFET region 8 a.

[0123] The JFET region 8a is disposed between the first region 7 and the second region 9. The JFET region 8a includes an n-type base layer 40 extending in the first direction 2. A portion of the n-type base layer 40 is covered with a p-type diffusion layer 80. Specifically, the p-type diffusion layers 80 and the n-type base layers 40 are disposed alternately at regular intervals in the first direction 2 in a plan view. Furthermore, the p-type diffusion layers 80 and regions sandwiched between the p+-type contact layers 70 and other p+-type contact layers 70 are disposed alternately at regular intervals in the second direction 4 in a plan view.

[0124] The length of the p-type diffusion layer 80 in the first direction 2 is greater than the length of the opening of the n contact hole 90b in the first direction 2. That is, one end of the p-type diffusion layer 80 in the first direction 2 is arranged side by side with one end of the p+ type contact layer 70 in the first direction 2 in the second direction 4. In this side-by-side region, no channel is generated when switching is turned on. This region is in contact with the n+ type source layer 60 connected to the source electrode 100 by the contact hole 90.

[0125] Fig. 36 is a cross-sectional view taken along the line AA' in Fig. 35. Fig. 36 is the same as Fig. 28, and therefore the explanation will be omitted.

[0126] Fig. 37 is a cross-sectional view taken along line BB' of Fig. 35. Fig. 37 differs from Fig. 29 in that a p-type diffusion layer 80 is provided instead of the n-type base layer 40.

[0127] A p-type diffusion layer 80 is provided on the upper surface side of the n- type drift layer 30. A p-type base layer 50 is provided on both sides of the p-type diffusion layer 80. A gate oxide film 120 is provided on the p-type diffusion layer 80, the p-type base layer 50, and the n+ type source layer 60.

[0128] Fig. 38 is a cross-sectional view taken along CC' in Fig. 35. Fig. 38 is the same as Fig. 30, and therefore the explanation will be omitted.

[0129] As described above, in the semiconductor device 7000 according to this embodiment, the width in the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 by the contact hole 90 is set smaller than the width in the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 by the contact hole 90. As a result, the short-circuit resistance can be improved.

[0130] Furthermore, the semiconductor device 7000 according to this embodiment does not have an n-type base layer 40 in the region shown in FIG. 37 . That is, the semiconductor device 7000 has a region in which the p-type base layer 50 and the n − -type drift layer 30 are connected only by a path that does not pass through the n-type base layer 40. In this region, no channel is generated when switching is turned on. As a result, the semiconductor device 7000 can reduce the channel region occupying the entire active region, thereby reducing the saturation current and further improving the short-circuit resistance.

[0131] Furthermore, in the semiconductor device 7000 according to this embodiment, a channel is not generated in a region in contact with the n+ type source layer 60 connected to the source electrode 100 via the contact hole 90 when the switching is turned on. The region of the n+ type source layer 60 connected to the source electrode 100 via the contact hole 90 is a region through which current flows most easily when the switching is turned on. Therefore, the semiconductor device 7000 can prevent current from concentrating in one place by not generating a channel in the region through which current flows most easily when the switching is turned on.

[0132] Embodiment 8 39 is a plan view illustrating a configuration of a semiconductor device according to an eighth embodiment of the present disclosure. Fig. 39 illustrates a planar layout of a cell region of a semiconductor device 8000, which is a planar MOSFET. The semiconductor device 8000 differs from the semiconductor device 5000 in that the length of the p+ type contact layer 70 in the second direction 4 is longer.

[0133] The n+ type source layer 60 and the p-type base layer 50 are partially covered with a p+ type contact layer 70. The p+ type contact layer 70 is arranged in the first direction 2 so as to discretely cover the n+ type source layer 60 and the p-type base layer 50. The length of the p+ type contact layer 70 in the second direction 4 is longer than the length of the n+ type source layer 60 in the second direction 4.

[0134] Fig. 40 is a cross-sectional view taken along the line AA' in Fig. 39. Fig. 40 is the same as Fig. 20, and therefore the explanation will be omitted.

[0135] Fig. 41 is a cross-sectional view taken along line BB' in Fig. 39. Fig. 41 is the same as Fig. 29, and therefore the explanation will be omitted.

[0136] Fig. 42 is a cross-sectional view taken along CC' in Fig. 39. Fig. 42 is the same as Fig. 30, and therefore the explanation will be omitted.

[0137] As described above, in the semiconductor device 8000 according to this embodiment, the width in the first direction 2 of the n+ type source layer 60 connected to the source electrode 100 through the contact hole 90 is set smaller than the width in the first direction 2 of the p+ type contact layer 70 connected to the source electrode 100 through the contact hole 90. As a result, the short-circuit resistance can be improved.

[0138] Furthermore, the semiconductor device 8000 according to this embodiment does not have the n+ type source layer 60 in the region shown in FIG. 40. That is, the semiconductor device 8000 has a region in which the p-type base layer 50 and the p+ type contact layer 70 are connected only by a path that does not pass through the n+ type source layer 60. In this region, no channel is generated when switching is turned on. As a result, the semiconductor device 8000 can reduce the channel region occupying the entire active region, thereby reducing the saturation current and further improving the short-circuit resistance.

[0139] Below, the aspects of the present disclosure will be summarized as appendices.

[0140] (Appendix 1) a semiconductor substrate including: a drift layer of a first conductivity type; a first base layer of a first conductivity type and a second base layer of a second conductivity type provided side by side on an upper surface of the drift layer; a source layer of the first conductivity type selectively provided on the upper surface of the second base layer and having an impurity concentration higher than that of the first base layer; and a contact layer of a second conductivity type selectively provided on the upper surface of the second base layer and having an impurity concentration higher than that of the second base layer; a gate oxide film provided on the first base layer, the second base layer, the source layer, and the contact layer; a gate electrode provided on the gate oxide film; an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; a source electrode connected to the source layer through the first contact hole and connected to the contact layer through the second contact hole; a drain electrode connected to a lower surface side of the drift layer; Equipped with The first contact hole and the second contact hole are separated by the interlayer insulating film. Semiconductor device. (Appendix 2) the openings of the first contact holes and the openings of the second contact holes are alternately arranged in a first direction in a plan view; The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole. 2. The semiconductor device according to claim 1. (Appendix 3) The opening of the first contact hole and the opening of the second contact hole are The same shape and size, are arranged alternately at regular intervals in a first direction in a plan view 3. The semiconductor device according to claim 1 or 2. (Appendix 4) the opening of the first contact hole and the opening of the second contact hole have the same shape and size; the first contact holes form a first contact hole group in which m first contact holes are arranged at regular intervals in a first direction; the second contact holes form a second contact hole group in which n second contact holes are arranged at regular intervals in the first direction; the first contact hole group and the second contact hole group are alternately arranged at regular intervals in the first direction in a plan view; m is a value between 1 and n 4. The semiconductor device according to claim 1. (Appendix 5) a semiconductor substrate including: a drift layer of a first conductivity type; a first base layer of a first conductivity type and a second base layer of a second conductivity type provided side by side on an upper surface of the drift layer; a source layer of the first conductivity type selectively provided on the upper surface of the second base layer and having an impurity concentration higher than that of the first base layer; and a contact layer of a second conductivity type selectively provided on the upper surface of the second base layer and having an impurity concentration higher than that of the second base layer; a gate oxide film provided on the first base layer, the second base layer, the source layer, and the contact layer; a gate electrode provided on the gate oxide film; an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; a source electrode connected to the source layer through the first contact hole and connected to the contact layer through the second contact hole; a drain electrode connected to a lower surface side of the drift layer; Equipped with the openings of the first contact holes and the openings of the second contact holes are alternately arranged in a first direction in a plan view; The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction. Semiconductor device. (Appendix 6) The second base layer and the contact layer have a region where they are connected only by a path that does not pass through the source layer. 6. The semiconductor device according to any one of claims 1 to 5. (Appendix 7) the semiconductor substrate further includes a diffusion layer of a second conductivity type provided on the drift layer and under the gate oxide film, a plurality of the contact layers are arranged at regular intervals in a first direction in a plan view; the diffusion layers and the first base layers are alternately arranged at regular intervals in the first direction in a plan view, the diffusion layers and the contact layers are alternately arranged at regular intervals in a second direction that is perpendicular to the first direction in a plan view, The second base layer and the drift layer have a region where they are connected only by a path that does not pass through the first base layer. 7. The semiconductor device according to any one of claims 1 to 6. (Appendix 8) the semiconductor substrate further includes a diffusion layer of a second conductivity type provided on the drift layer and under the gate oxide film, a plurality of the contact layers are arranged at regular intervals in a first direction in a plan view; the diffusion layers and the first base layers are alternately arranged at regular intervals in the first direction in a plan view, the diffusion layer and the region sandwiched between the contact layer and another contact layer are alternately arranged at regular intervals in a second direction that is a direction perpendicular to the first direction in a plan view, The contact layer and the drift layer have a region where they are connected only by a path that does not pass through the first base layer. 8. A semiconductor device according to any one of claims 1 to 7. (Appendix 9) The semiconductor substrate is formed from a wide bandgap semiconductor. 9. A semiconductor device according to any one of claims 1 to 8. (Appendix 10) forming a drift layer of a first conductivity type on a semiconductor substrate; forming a first base layer of a first conductivity type by ion-implanting a first impurity into the upper surface side of the drift layer; forming a first mask on an upper surface of the first base layer and ion-implanting a second impurity into the first base layer to form a second base layer of a second conductivity type on an upper surface of the drift layer, the second base layer being adjacent to the first base layer; forming a thin film on the top surface and sidewalls of the first mask and on the top surface of the second base layer; etching the thin film to form a second mask having the first mask; forming a first conductivity type source layer selectively provided on the upper surface side of the second base layer by ion-implanting a first impurity into the second base layer and the upper surface side of the second mask; removing the second mask; a step of selectively ion-implanting the second impurity into an upper surface side of the source layer to form a contact layer of a second conductivity type selectively provided on the upper surface side of the base layer; forming a gate oxide film on the first base layer, the second base layer, the source layer, and the contact layer; forming a gate electrode on the gate oxide film; forming an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; forming a source electrode connected to the source layer through the first contact hole and connected to the contact layer through the second contact hole; forming a drain electrode on the lower surface side of the drift layer; Equipped with The first contact hole and the second contact hole are separated by the interlayer insulating film. A method for manufacturing a semiconductor device. (Appendix 11) forming a drift layer of a first conductivity type on a semiconductor substrate; forming a first base layer of a first conductivity type by ion-implanting a first impurity into the upper surface side of the drift layer; forming a first mask on an upper surface of the first base layer and ion-implanting a second impurity into the first base layer to form a second base layer of a second conductivity type on an upper surface of the drift layer, the second base layer being adjacent to the first base layer; forming a thin film on the top surface and sidewalls of the first mask and on the top surface of the second base layer; etching the thin film to form a second mask having the first mask; forming a first conductivity type source layer selectively provided on the upper surface side of the second base layer by ion-implanting a first impurity into the second base layer and the upper surface side of the second mask; removing the second mask; a step of selectively ion-implanting the second impurity into an upper surface side of the source layer to form a contact layer of a second conductivity type selectively provided on the upper surface side of the base layer; forming a gate oxide film on the first base layer, the second base layer, the source layer, and the contact layer; forming a gate electrode on the gate oxide film; forming an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; forming a source electrode connected to the source layer through the first contact hole and connected to the contact layer through the second contact hole; forming a drain electrode on the lower surface side of the drift layer; Equipped with the openings of the first contact holes and the openings of the second contact holes are alternately arranged in a first direction in a plan view; The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction. A method for manufacturing a semiconductor device. [Explanation of symbols]

[0141] 2 First direction 4 Second direction 10. Semiconductor substrate 30 n-type drift layer 40 n-type base layer 50 p-type base layer 60 n+ type source layer 70 p+ type contact layer 80 p-type diffusion layer 90 Contact Holes 90a p contact hole 90b n contact hole 100 Source electrode 110 gate electrode 120 Gate oxide 130 Interlayer insulating film 140 drain electrode 1000 Semiconductor device 2000 Semiconductor Devices 2000a Semiconductor Device 2000b Semiconductor Device 3000 Semiconductor Devices 4000 Semiconductor Equipment 5000 Semiconductor Devices 6000 Semiconductor Equipment 7000 Semiconductor Equipment 8000 Semiconductor Equipment

Claims

1. a semiconductor substrate including: a drift layer of a first conductivity type; a first base layer of a first conductivity type and a second base layer of a second conductivity type provided side by side on an upper surface of the drift layer; a source layer of the first conductivity type selectively provided on the upper surface of the second base layer and having an impurity concentration higher than that of the first base layer; and a contact layer of a second conductivity type selectively provided on the upper surface of the second base layer and having an impurity concentration higher than that of the second base layer; a gate oxide film provided on the first base layer, the second base layer, the source layer, and the contact layer; a gate electrode provided on the gate oxide film; an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; a source electrode connected to the source layer through the first contact hole and connected to the contact layer through the second contact hole; a drain electrode connected to a lower surface side of the drift layer; Equipped with The first contact hole and the second contact hole are separated by the interlayer insulating film. Semiconductor device.

2. the openings of the first contact holes and the openings of the second contact holes are alternately arranged in a first direction in a plan view; The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole. The semiconductor device according to claim 1 .

3. The opening of the first contact hole and the opening of the second contact hole are The same shape and size, are arranged alternately at regular intervals in a first direction in a plan view The semiconductor device according to claim 1 .

4. the opening of the first contact hole and the opening of the second contact hole have the same shape and size; the first contact holes form a first contact hole group in which m first contact holes are arranged at regular intervals in a first direction; the second contact holes form a second contact hole group in which n second contact holes are arranged at regular intervals in the first direction; the first contact hole group and the second contact hole group are alternately arranged at regular intervals in the first direction in a plan view; m is a value between 1 and n The semiconductor device according to claim 1 .

5. a semiconductor substrate including: a drift layer of a first conductivity type; a first base layer of a first conductivity type and a second base layer of a second conductivity type provided side by side on an upper surface of the drift layer; a source layer of the first conductivity type selectively provided on the upper surface of the second base layer and having an impurity concentration higher than that of the first base layer; and a contact layer of a second conductivity type selectively provided on the upper surface of the second base layer and having an impurity concentration higher than that of the second base layer; a gate oxide film provided on the first base layer, the second base layer, the source layer, and the contact layer; a gate electrode provided on the gate oxide film; an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; a source electrode connected to the source layer through the first contact hole and connected to the contact layer through the second contact hole; a drain electrode connected to a lower surface side of the drift layer; Equipped with the openings of the first contact holes and the openings of the second contact holes are alternately arranged in a first direction in a plan view; The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction. Semiconductor device.

6. The second base layer and the contact layer have a region where they are connected only by a path that does not pass through the source layer. The semiconductor device according to claim 1 or 5.

7. the semiconductor substrate further includes a diffusion layer of a second conductivity type provided on the drift layer and under the gate oxide film, a plurality of the contact layers are arranged at regular intervals in a first direction in a plan view; the diffusion layers and the first base layers are alternately arranged at regular intervals in the first direction in a plan view, the diffusion layers and the contact layers are alternately arranged at regular intervals in a second direction that is perpendicular to the first direction in a plan view, The second base layer and the drift layer have a region where they are connected only by a path that does not pass through the first base layer. The semiconductor device according to claim 1 or 5.

8. the semiconductor substrate further includes a diffusion layer of a second conductivity type provided on the drift layer and under the gate oxide film, a plurality of the contact layers are arranged at regular intervals in a first direction in a plan view; the diffusion layers and the first base layers are alternately arranged at regular intervals in the first direction in a plan view, the diffusion layer and the region sandwiched between the contact layer and another contact layer are alternately arranged at regular intervals in a second direction that is a direction perpendicular to the first direction in a plan view, The second base layer and the drift layer have a region where they are connected only by a path that does not pass through the first base layer. The semiconductor device according to claim 1 or 5.

9. The semiconductor substrate is formed from a wide bandgap semiconductor. The semiconductor device according to claim 1 or 5.

10. forming a drift layer of a first conductivity type on a semiconductor substrate; forming a first base layer of a first conductivity type by ion-implanting a first impurity into the upper surface side of the drift layer; forming a first mask on an upper surface of the first base layer and ion-implanting a second impurity into the first base layer to form a second base layer of a second conductivity type on an upper surface of the drift layer, the second base layer being adjacent to the first base layer; forming a thin film on the top surface and sidewalls of the first mask and on the top surface of the second base layer; etching the thin film to form a second mask having the first mask; forming a first conductivity type source layer selectively provided on the upper surface side of the second base layer by ion-implanting a first impurity into the second base layer and the upper surface side of the second mask; removing the second mask; forming a second conductivity type contact layer selectively provided on the upper surface side of the second base layer by selectively ion-implanting the second impurity into the upper surface side of the source layer; forming a gate oxide film on the first base layer, the second base layer, the source layer, and the contact layer; forming a gate electrode on the gate oxide film; forming an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; forming a source electrode connected to the source layer through the first contact hole and connected to the contact layer through the second contact hole; forming a drain electrode on the lower surface side of the drift layer; Equipped with The first contact hole and the second contact hole are separated by the interlayer insulating film. A method for manufacturing a semiconductor device.

11. forming a drift layer of a first conductivity type on a semiconductor substrate; forming a first base layer of a first conductivity type by ion-implanting a first impurity into the upper surface side of the drift layer; forming a first mask on an upper surface of the first base layer and ion-implanting a second impurity into the first base layer to form a second base layer of a second conductivity type on an upper surface of the drift layer, the second base layer being adjacent to the first base layer; forming a thin film on the top surface and sidewalls of the first mask and on the top surface of the second base layer; etching the thin film to form a second mask having the first mask; forming a first conductivity type source layer selectively provided on the upper surface side of the second base layer by ion-implanting a first impurity into the second base layer and the upper surface side of the second mask; removing the second mask; forming a second conductivity type contact layer selectively provided on the upper surface side of the second base layer by selectively ion-implanting the second impurity into the upper surface side of the source layer; forming a gate oxide film on the first base layer, the second base layer, the source layer, and the contact layer; forming a gate electrode on the gate oxide film; forming an interlayer insulating film provided on the semiconductor substrate so as to cover the gate oxide film and the gate electrode, the interlayer insulating film having a plurality of first contact holes exposing portions of the source layer and a plurality of second contact holes exposing portions of the contact layer; forming a source electrode connected to the source layer through the first contact hole and connected to the contact layer through the second contact hole; forming a drain electrode on the lower surface side of the drift layer; Equipped with the openings of the first contact holes and the openings of the second contact holes are alternately arranged in a first direction in a plan view; The width of the opening of the first contact hole in the first direction is smaller than the width of the opening of the second contact hole in the first direction. A method for manufacturing a semiconductor device.

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