Active matrix substrate, liquid crystal display device, and manufacturing method of active matrix substrate

Abstract

To provide an active matrix substrate with improved contact structure between a pixel electrode and a TFT.SOLUTION: An active matrix substrate comprises: a substrate; a TFT disposed in each of a plurality of pixel regions; an insulation layer covering the TFT; a flattened layer covering the insulation layer; a pixel electrode provided on the flattened layer; and a connection electrode provided between the insulation layer and the flattened layer for electrically connecting the TFT to the pixel electrode. The TFT includes a gate electrode, a gate insulation layer electrically insulating the gate electrode, and an oxide semiconductor layer. The oxide semiconductor layer includes a channel region facing the gate electrode via the gate insulation layer, and a source region and a drain region which are located on both sides of the channel region. The insulation layer includes a contact hole in a position overlapping the drain region. The connection electrode is formed of transparent conductive materials and is connected to the drain region in the contact hole. The drain region has higher impurity density in a portion overlapping the contact hole than at least in a portion adjacent to the channel region.SELECTED DRAWING: Figure 7A

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to an active matrix substrate, a liquid crystal display device, and a method for manufacturing an active matrix substrate. [Background technology]

[0002] Currently, liquid crystal display devices equipped with active matrix substrates are widely used for various applications. Active matrix substrates are equipped with switching elements such as thin film transistors (TFTs) for each pixel electrode. The pixel electrodes and TFTs are insulated by a passivation layer (inorganic insulating layer) and a planarization layer (organic insulating layer). The pixel electrodes and the drain electrodes of the TFTs are electrically connected via contact holes provided in these layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-187714 Summary of the Invention [Problem to be solved by the invention]

[0004] As the resolution of liquid crystal display devices continues to increase year by year, planarization layers are sometimes formed thicker than conventional ones (e.g., 4 to 5 μm) to sufficiently planarize the surface on which pixel electrodes are mounted and to suppress the generation of load capacitance. Forming deep contact holes in a thick planarization layer increases the area occupied by the tapered portions of the contact holes, which is undesirable in terms of increasing resolution and aperture ratio. In response to this, Patent Document 1 discloses a configuration in which the bottom of the contact hole is raised by a pedestal, thereby making the contact hole shallower. However, the pedestal and the metal portion covering the pedestal leave room for improvement in terms of increasing aperture ratio.

[0005] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an active matrix substrate with an improved contact structure between pixel electrodes and TFTs. [Means for solving the problem]

[0006] This specification discloses an active matrix substrate, a liquid crystal display device, and a method for manufacturing an active matrix substrate, as described in the following items.

[0007] [Configuration 1] a display area including a plurality of pixel areas; A substrate; a thin film transistor (TFT) supported by the substrate and disposed in each of the plurality of pixel regions; an insulating layer covering the TFT; a planarization layer covering the insulating layer; a pixel electrode provided on the planarization layer; a connection electrode provided between the insulating layer and the planarization layer for electrically connecting the TFT and the pixel electrode; An active matrix substrate comprising: The TFT is A gate electrode; a gate insulating layer that electrically insulates the gate electrode; an oxide semiconductor layer including a channel region facing the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region located on both sides of the channel region; and the insulating layer has a contact hole at a position overlapping the drain region; the connection electrode is made of a transparent conductive material and is connected to the drain region through the contact hole; the drain region has a higher impurity concentration at least in a portion overlapping the contact hole than in a portion adjacent to the channel region; Active matrix substrate. [Configuration 2] The impurity is at least one of a Group 13 element and a Group 15 element. The active matrix substrate according to the above configuration 1. [Configuration 3] the connecting electrode includes at least one of indium tin oxide (ITO) and indium zinc oxide (IZO); the oxide semiconductor layer contains an In—Ga—Zn—O-based oxide semiconductor; 3. The active matrix substrate according to claim 1 or 2. [Configuration 4] when viewed from a normal direction of the substrate, at least a part of the planarization layer has a pixel contact hole at a position overlapping the gate electrode for connecting the pixel electrode and the connection electrode; 4. The active matrix substrate according to any one of the above configurations 1 to 3. [Configuration 5] When viewed from a normal direction of the substrate, at least a portion of a bottom surface of the pixel contact hole overlaps with a gate metal layer including the gate electrode. 5. The active matrix substrate according to the above configuration 4. [Configuration 6] 6. The active matrix substrate according to claim 4, wherein a part of the pixel electrode is in contact with the connection electrode at the pixel contact hole. [Configuration 7] another connection electrode formed of a transparent conductive material and electrically connecting the connection electrode and the pixel electrode, the other connection electrode being in contact with the connection electrode in the pixel contact hole; another planarization layer formed to fill the pixel contact hole and cover a part of the another connection electrode; Furthermore, the pixel electrode is in contact with a portion of the other connection electrode that is not covered by the other planarization layer, the pixel electrode includes a portion located on the other planarization layer; 7. The active matrix substrate according to any one of the above configurations 4 to 6. [Configuration 8] the other connection electrode and the pixel electrode are formed from the same transparent conductive material; 8. The active matrix substrate according to configuration 7. [Configuration 9] the other connection electrode and the pixel electrode are formed from at least one of indium tin oxide and indium zinc oxide; 9. The active matrix substrate according to the above configuration 7 or 8. [Configuration 10] The TFT is a lower gate electrode provided on the substrate; a lower gate insulating layer covering the lower gate electrode; the oxide semiconductor layer provided such that the channel region is disposed on the lower gate insulating layer; an upper gate insulating layer provided on the channel region of the oxide semiconductor layer; an upper gate electrode provided on the upper gate insulating layer and facing the channel region of the oxide semiconductor layer via the upper gate insulating layer; Equipped with 10. The active matrix substrate according to any one of the above configurations 1 to 9. [Configuration 11] when viewed from a normal direction of the substrate, the planarization layer has a pixel contact hole at a position at which at least a part of the pixel contact hole overlaps with the upper gate electrode, for electrically connecting the pixel electrode and the connection electrode; At least a part of a bottom surface of the pixel contact hole overlaps both the lower gate electrode and the upper gate electrode. 11. The active matrix substrate according to claim 10. [Configuration 12] an active matrix substrate according to any one of the above configurations 1 to 11; an opposing substrate provided opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate. [Configuration 13] 1. A method for manufacturing an active matrix substrate, comprising: forming a thin film transistor (TFT) on a substrate, wherein the TFT comprises: A gate electrode; a gate insulating layer that electrically insulates the gate electrode; an oxide semiconductor layer including a channel region facing the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region located on both sides of the channel region; having; forming an insulating layer on the TFT; providing a contact hole in the insulating layer that leads to the drain region; doping an impurity into a portion of the drain region that overlaps the contact hole through the contact hole; forming a connection electrode on the insulating layer at least at a position from the contact hole to the gate electrode, the connection electrode being for electrically connecting the TFT and the pixel electrode; forming a planarization layer on the insulating layer and the connecting electrode; A method for manufacturing an active matrix substrate, comprising: [Configuration 14] The TFT is a lower gate electrode provided on the substrate; a lower gate insulating layer covering the lower gate electrode; the oxide semiconductor layer provided such that the channel region is disposed on the lower gate insulating layer; an upper gate insulating layer provided on the channel region of the oxide semiconductor layer; an upper gate electrode provided on the upper gate insulating layer and facing the channel region of the oxide semiconductor layer via the upper gate insulating layer; Equipped with forming the connection electrode on the insulating layer at a position extending from the contact hole to overlap with the upper gate electrode; 14. A method for manufacturing an active matrix substrate according to the above configuration 13. [Configuration 15] forming a pixel contact hole in the planarization layer at a position overlapping the gate electrode or the upper gate electrode and the connection electrode, the pixel contact hole communicating with the connection electrode; forming a pixel electrode on the planarization layer at a position where at least a portion of the pixel electrode overlaps with the connection electrode through the pixel contact hole; 15. The method for manufacturing an active matrix substrate according to configuration 14, further comprising: [Configuration 16] forming a pixel contact hole in the planarization layer at a position overlapping the gate electrode or the upper gate electrode and the connection electrode, the pixel contact hole communicating with the connection electrode; forming another connection electrode on the planarization layer at a position where at least a portion of the connection electrode overlaps with the connection electrode through the pixel contact hole; forming another planarization layer to fill the pixel contact holes; forming a pixel electrode on at least one of the planarizing layer and the other planarizing layer at a position where at least a portion of the pixel electrode overlaps with the other connection electrode; 16. The method for manufacturing an active matrix substrate according to the above configuration 14 or 15, further comprising: [Effects of the Invention]

[0008] According to an embodiment of the present invention, it is possible to provide an active matrix substrate with an improved contact structure between a pixel electrode and a TFT. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram showing an example of a planar structure of an active matrix substrate 100 according to an embodiment. [Figure 2] FIG. 1 is a partial plan view schematically illustrating an active matrix substrate 100 according to an embodiment of the present invention. [Figure 3] 3 is a partial cross-sectional view schematically showing the active matrix substrate 100, taken along line AA in FIG. 2. FIG. [Figure 4]2. FIG. 3 is a partial cross-sectional view schematically showing an active matrix substrate 100 according to an embodiment of the present invention, taken along line BB in FIG. [Figure 5A] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 5B] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 5C] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 5D] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 5E] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 6A] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 6B] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 6C] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 6D] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 7A] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 7B] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 7C] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 7D] 1A to 1C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 100 according to an embodiment. [Figure 8A] 10A to 10C are cross-sectional views showing other manufacturing steps of the active matrix substrate 200. [Figure 8B]10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 200 according to another embodiment. [Figure 9A] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 9B] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 9C] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 9D] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 9E] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 10A] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 10B] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 10C] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 10D] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 10E] 10A to 10C are cross-sectional views illustrating a manufacturing process of an active matrix substrate 300 according to another embodiment. [Figure 11A] 10A to 10C are cross-sectional views illustrating a manufacturing process for an active matrix substrate 400 according to another embodiment. [Figure 11B] 10A to 10C are cross-sectional views illustrating a manufacturing process for an active matrix substrate 400 according to another embodiment. [Figure 12A] 10A to 10C are cross-sectional views illustrating a manufacturing process for an active matrix substrate 500 according to another embodiment. [Figure 12B] 10A to 10C are cross-sectional views illustrating a manufacturing process for an active matrix substrate 500 according to another embodiment. [Figure 12C]10A to 10C are cross-sectional views illustrating a manufacturing process for an active matrix substrate 500 according to another embodiment. [Figure 13] FIG. 1 is a cross-sectional view that schematically shows a liquid crystal display device 1000 that includes an active matrix substrate 100 (200, 300, 400, 500) according to an embodiment. [Figure 14] FIG. 1 is a cross-sectional view schematically showing an active matrix substrate 900 of a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0010] (Embodiment 1) An active matrix substrate, a liquid crystal display device, and a method for manufacturing an active matrix substrate according to an embodiment will be described below with reference to the accompanying drawings. While an active matrix substrate for use in a liquid crystal display device will be exemplified below as an embodiment of the active matrix substrate, the present technology is not limited thereto.

[0011] 1 is a schematic diagram showing an example of the planar structure of an active matrix substrate 100 according to one embodiment. Arrows X, Y, and Z in the figure correspond to the row direction, column direction, and normal direction of the substrate 1, respectively, of the active matrix substrate 100, which will be described later.

[0012] An overview of the active matrix substrate 100 will now be described. The active matrix substrate 100 has a display region DR and a non-display region (also called a "frame region") FR. The display region DR is an area that displays digital images and includes multiple pixel regions P. The pixel region P is an area that corresponds to one pixel, which is the smallest unit that makes up a digital image. The pixel region P is sometimes simply called a "pixel." The multiple pixel regions P are arranged in a matrix consisting of multiple rows and multiple columns. The non-display region FR is an area that does not contribute to display and is arranged around the display region DR.

[0013] The active matrix substrate 100 is configured by providing a large scale integrated circuit (LSI) that constitutes the above-mentioned plurality of pixels on a substrate 1. A plurality of gate lines GL extending in the row direction and a plurality of source lines SL extending in the column direction are provided in a portion of the substrate 1 that corresponds to the display region DR. Each pixel region P is, for example, a region surrounded by a pair of adjacent gate lines GL and a pair of adjacent source lines SL.

[0014] Peripheral circuits are arranged in a portion of the substrate 1 corresponding to the non-display region FR. Here, as the peripheral circuit, a gate driver GD that drives the gate lines GL is provided integrally (monolithically) with the substrate 1. Also, as the peripheral circuit, a source driver SD that drives the source lines SL is mounted on the substrate 1. Note that as a peripheral circuit, a source shared driving (SSD) circuit that drives the source bus lines (source lines SL) in a time-division manner may be further arranged, and the SSD circuit may be provided integrally with the substrate 1 like the gate driver GD.

[0015] Each pixel region P of the substrate 1 is provided with a thin-film transistor (TFT) 10 and a pixel electrode 18 electrically connected to the TFT 10. The TFT 10 disposed in each pixel region P is sometimes referred to as a "pixel TFT." The TFT 10 receives a gate signal (scanning signal) from a corresponding gate line GL and a source signal (display signal) from a corresponding source line SL. For simplicity, FIG. 1 illustrates one gate line GL for each pixel row. However, as will be described in detail later, multiple gate lines GL (e.g., lower gate lines and upper gate lines) may be provided for each pixel row, and each TFT 10 may receive a gate signal from these lower gate line and upper gate line. In other words, the TFT 10 may be, for example, a so-called double-gate thin-film transistor.

[0016] Next, the structure of the active matrix substrate 100 will be described in more detail with reference to FIGS. 2 to 4. FIG. 2 is a partial plan view schematically showing the active matrix substrate 100, illustrating a region where gate lines GL and source lines SL intersect. FIG. 3 is a partial cross-sectional view schematically showing the active matrix substrate 100, illustrating a cross-section along line AA in FIG. 2. FIG. 4 is a partial cross-sectional view schematically showing the active matrix substrate 100 according to one embodiment, illustrating a cross-section along line BB in FIG. 2.

[0017] As shown in Figure 3, etc., the active matrix substrate 100 comprises a substrate 1, a TFT 10 supported on the substrate 1, an insulating layer (e.g., a first interlayer insulating layer 8 and a second interlayer insulating layer 9) covering the TFT 10, a planarization layer 16 covering this insulating layer, a pixel electrode 18 provided on the planarization layer 16, and a connection electrode 14 provided between the insulating layer (e.g., the second interlayer insulating layer 9) and the planarization layer 16.

[0018] The substrate 1 has insulating properties. For example, the substrate 1 used in a liquid crystal display device is transparent and is typically a glass substrate or a transparent plastic substrate. In the present technology, "transparent" means being transparent to visible light (for example, having a transmittance of 80% or more, preferably 90% or more, more preferably 95% or more, and even more preferably 99% or more).

[0019] The TFT 10 is disposed in each pixel region P on the substrate 1. The TFT 10 includes a lower gate electrode 2, a lower gate insulating layer 3, an oxide semiconductor layer 4, an upper gate insulating layer 5, an upper gate electrode 6, and a source electrode .

[0020] The lower gate electrode 2 is provided on, for example, the substrate 1. The lower gate electrode 2 is electrically connected to a corresponding lower gate wiring GLA. In the illustrated example, a part of the lower gate wiring GLA (specifically, the part facing the oxide semiconductor layer 4) functions as the lower gate electrode 2. In this specification, the lower gate electrode 2 and wiring and / or electrodes formed in the same layer as the lower gate electrode 2 (by patterning the same conductive film) are collectively referred to as a "lower gate metal layer." Here, the lower gate metal layer includes the lower gate electrode 2 and the lower gate wiring GLA.

[0021] The lower gate insulating layer 3 covers the lower gate electrode 2. The lower gate insulating layer 3 provides insulation between the lower gate electrode 2 and the conductive layer (here, the oxide semiconductor layer 4) above it.

[0022] The oxide semiconductor layer 4 is provided on the lower gate insulating layer 3. The oxide semiconductor layer 4 includes a channel region 4c facing the lower gate electrode 2 via the lower gate insulating layer 3, and a source region 4s and a drain region 4d located on both sides of the channel region 4c. The source region 4s and the drain region 4d of the oxide semiconductor layer 4 are regions that have been made conductive by, for example, a resistance reduction treatment described below.

[0023] The upper gate insulating layer 5 is provided at least on the channel region 4c of the oxide semiconductor layer 4. The upper gate insulating layer 5 insulates the upper gate electrode 6 from the conductive layer (here, the oxide semiconductor layer 4) therebelow. Here, the upper gate insulating layer 5 is provided so as to cover the entire oxide semiconductor layer 4.

[0024] The upper gate electrode 6 is provided on the upper gate insulating layer 5 and faces the channel region 4c of the oxide semiconductor layer 4 via the upper gate insulating layer 5. The upper gate electrode 6 is electrically connected to the corresponding upper gate wiring GLB. In the illustrated example, a part of the upper gate wiring GLB (specifically, the part facing the oxide semiconductor layer 4) functions as the upper gate electrode 6. In this specification, the upper gate electrode 6 and wiring and / or electrodes formed in the same layer as the upper gate electrode 6 (by patterning the same conductive film) are collectively referred to as the "upper gate metal layer." Here, the upper gate metal layer includes the upper gate electrode 6 and the upper gate wiring GLB. The upper gate electrode 6 may be given the same potential as the lower gate electrode 2, or may be given a different potential, for example, for threshold control. When the upper gate electrode 6 and the lower gate electrode 2 are given the same potential, the upper gate wiring GLB and the lower gate wiring GLA may be electrically connected. When the upper gate electrode 6 and the lower gate electrode 2 are given the same potential, one of the upper gate electrode 6 and the lower gate electrode 2 may be an island electrode electrically connected to the other.

[0025] A first interlayer insulating layer 8 is provided so as to cover the upper gate electrode 6 and the oxide semiconductor layer 4. The source electrode 7 is provided on the first interlayer insulating layer 8. A source contact hole CH is formed in the first interlayer insulating layer 8 so as to expose a part of the source region 4s of the oxide semiconductor layer 4. S are formed. The source electrode 7 is in contact with the source region 4s through a source contact hole and is electrically connected to the source region 4s. The source electrode 7 is electrically connected to a corresponding source wiring SL. In the illustrated example, a part of the source wiring SL (specifically, the part facing the oxide semiconductor layer 4) functions as the source electrode 7. In this specification, the source electrode 7 and wiring and / or electrodes formed in the same layer as the source electrode 7 (by patterning the same conductive film) are collectively referred to as a "source metal layer." Here, the source metal layer includes the source electrode 7 and the source wiring SL.

[0026] A second interlayer insulating layer 9 is provided to cover the TFT 10, and a planarization layer 16 is formed on the second interlayer insulating layer 9. The planarization layer 16 is made of, for example, an organic insulating material. The planarization layer 16 in the present technology is typically a transparent organic insulating material. The planarization layer 16 is made of, for example, a photosensitive resin. A pixel electrode 18 is provided on the planarization layer 16. The pixel electrode 18 is electrically connected to the TFT 10.

[0027] The active matrix substrate 100 shown as an example is used in a FFS (Fringe Field Switching) mode liquid crystal display device, and further includes, although not shown here, a dielectric layer provided so as to cover the pixel electrodes 18, and a common electrode provided on the dielectric layer and facing the pixel electrodes 18. At least one slit is formed in the common electrode for each pixel region P.

[0028] The active matrix substrate 100 further includes a connection electrode 14 for electrically connecting the drain region 4d of the oxide semiconductor layer 4 and the pixel electrode 18. The connection electrode 14 is provided between the second interlayer insulating layer 9 and the planarizing layer 16. The connection electrode 14 is made of a transparent conductive material. A drain contact hole CH is formed in the first interlayer insulating layer 8 and the second interlayer insulating layer 9 so that a part of the drain region 4d of the oxide semiconductor layer 4 is exposed. D A part of the connection electrode 14 is formed through the drain contact hole CH D 4d, and is in contact with the drain region 4d.

[0029] The planarization layer 16 has a pixel contact hole CH formed so as to expose a part of the connection electrode 14. P A part of the pixel electrode 18 is formed through a pixel contact hole CH P When viewed from the normal direction of the substrate 1, the pixel contact hole CH P The bottom surface bf of the pixel contact hole CH is disposed so as to at least partially overlap both the lower gate metal layer and the upper gate metal layer.P The bottom surface bf of the pixel contact hole CH at least partially overlaps both the lower gate electrode 2 and the upper gate electrode 6. In the example shown in FIG. P The entire bottom surface bf of overlaps both the lower gate metal layer and the upper gate metal layer, more specifically, both the lower gate electrode 2 and the upper gate electrode 6.

[0030] With this configuration, the active matrix substrate 100 can improve the transmittance compared to, for example, the comparative active matrix substrate 900. This point will be described below.

[0031] FIG. 14 is a cross-sectional view schematically showing an active matrix substrate 900 of a comparative example. The active matrix substrate 900 of the comparative example includes a TFT 10 with a double gate structure. However, in the active matrix substrate 900 of the comparative example, the pixel contact hole CH P When viewed from the normal direction of the substrate 1, the pixel contact hole CH does not overlap with either the lower gate electrode 2 or the upper gate electrode 6, but overlaps with the drain region 4d of the oxide semiconductor layer 4. P When viewed from the normal direction of the substrate 1, the drain contact hole CH formed in the first interlayer insulating layer 8 and the second interlayer insulating layer 9 is D (more specifically, the drain contact hole CH D Pixel contact hole CH P A part of the pixel electrode 18 is disposed through the drain contact hole CH D , the pixel electrode 18 is in direct contact with the drain region 4d of the oxide semiconductor layer 4, thereby electrically connecting the pixel electrode 18 to the oxide semiconductor layer 4. Therefore, the active matrix substrate 900 of the comparative example does not include the connecting electrode 14.

[0032] In addition, in the active matrix substrate 900 of the comparative example, when viewed from the normal direction of the substrate 1, the pixel contact holes CH PThe TFT 10 is provided with a light-shielding layer 19 arranged to overlap the substrate 1. The light-shielding layer 19 is formed on the substrate 1 and is made of a metal film with low light transmittance, so a base coat layer 12 is required to cover the light-shielding layer 19. The TFT 10 is provided on the base coat layer 12.

[0033] In the active matrix substrate 900 of the comparative example, in order to reliably electrically connect the pixel electrode 18 and the oxide semiconductor layer 4, the drain contact hole CH D and pixel contact hole CH P However, if the positions of the two are too close, the drain contact hole CH D The photosensitive resin material constituting the planarization layer 16 is likely to remain at the bottom of the drain contact hole CH, which may result in poor electrical continuity. D The pixel contact hole CH P The opening diameter of the pixel contact hole CH must be large enough. P Therefore, it is necessary to set the exposure time when forming the pixel contact hole CH P is the pixel contact hole CH P The drain contact hole CH D It is difficult to reduce the size of the pixel contact hole CH with respect to the opening diameter of the pixel contact hole CH. P When used in a liquid crystal display device, this disturbs the alignment of liquid crystal molecules, which causes a decrease in the contrast ratio and display quality due to light leakage in the liquid crystal display device. Therefore, the pixel contact holes CH are formed by the light-shielding layer 19 of the active matrix substrate 900 and the black matrix provided on the counter substrate. P It is necessary to shield the vicinity from light, but in that case, the light from the backlight is blocked by the light-shielding layer 19 and the black matrix, resulting in a decrease in transmittance.

[0034] Furthermore, as already explained, Patent Document 1 discloses a configuration that can make shallow contact holes formed in a planarization layer (organic insulating film). In the configuration disclosed in Patent Document 1, the electrode (metal portion) that electrically connects the polysilicon semiconductor layer, which is the active layer of the TFT, to the pixel electrode is raised by a pedestal portion provided directly below it, thereby making it possible to make shallow contact holes formed in the planarization layer.

[0035] However, when a complex structure such as that disclosed in Patent Document 1 is actually formed within a pixel, there is a concern about light leakage. For example, a phenomenon in which the edges of island-shaped metal parts shine (a phenomenon known as streaks) may occur. To prevent light leakage due to such streaks, it is considered necessary to shield the vicinity of the metal parts (the vicinity of the pedestal) with a light-shielding layer on the active matrix substrate or a black matrix on the opposing substrate. Therefore, while the configuration disclosed in Patent Document 1 allows shallow contact holes to be formed, it is difficult to significantly improve transmittance (significantly improve aperture ratio).

[0036] In contrast, in the active matrix substrate 100 of this embodiment, when viewed from the normal direction of the substrate 1, the pixel contact holes CH P The bottom surface bf of the pixel contact hole CH at least partially overlaps both the lower gate electrode 2 and the upper gate electrode 6. This allows the thickness of the photosensitive resin material to be increased to the thickness of the pixel contact hole CH when the photosensitive resin material is exposed to light. P In the region where the pixel contact hole CH is formed, the pixel contact hole CH is reduced by the thickness of the lower gate electrode 2 and the upper gate electrode 6, and the exposure light is reflected by the lower gate electrode 2 and / or the upper gate electrode 6. Therefore, the pixel contact hole CH can be formed with a shorter exposure time and a smaller mask pattern. P Therefore, the pixel contact hole CH P The opening diameter of the pixel contact hole CH can be reduced. PSince the diameter of the opening can be reduced, the lower gate electrode 2 and the upper gate electrode 6 can sufficiently block light without forming a light-shielding layer, thereby improving transmittance. The active matrix substrate 100 of this embodiment does not require the formation of a separate structure such as the pedestal disclosed in Patent Document 1.

[0037] In the active matrix substrate 100 of this embodiment, the connection electrode 14 for electrically connecting the drain region 4d of the oxide semiconductor layer 4 to the pixel electrode 18 is made of a transparent conductive material. D The surrounding area can be made to contribute to the display, and the aperture ratio can be increased to further improve the transmittance.

[0038] According to the study by the present inventors, the contact resistance between the oxide semiconductor layer 4 and the connection electrode 14 made of a transparent conductive material (e.g., ITO or IZO) can be higher than when the connection electrode is made of a metal material. D The contact resistance between the connection electrode 14 (for example, ITO) and the oxide semiconductor layer 4 (for example, In—Ga—Zn—O-based oxide semiconductor) in the source contact hole CH S In some cases, the contact resistance may be higher by approximately one order of magnitude or more than the contact resistance between the oxide semiconductor layer 4 and the source electrode 7 (for example, a stacked film of Ti / Al / Ti) in the above case. This is for the following reason.

[0039] First, the oxide semiconductor layer 4 has a high ionic bond and is easily oxidized by adsorbing water vapor and oxygen molecules on its surface. D and source contact hole CH SWhen the first interlayer insulating layer 8 or the second interlayer insulating layer 9 is etched during the formation of the oxide semiconductor layer 4, the surface of the oxide semiconductor layer 4 exposed downward is oxidized (excessively stabilized). Even if the oxide semiconductor layer 4 has an oxidized surface, when it comes into contact with the source electrode 7 made of a metal material, the oxygen on the surface of the oxide semiconductor layer 4 moves to the source electrode 7 due to an oxidation-reduction reaction at the interface, and oxygen is reduced from the surface of the oxide semiconductor layer 4. Therefore, when the source contact hole CH S On the surface of the oxide semiconductor layer 4 exposed to the atmosphere, carriers increase and the contact resistance decreases.

[0040] In contrast, when a transparent conductive material (e.g., ITO) is used for the connection electrode 14, more oxygen is supplied to the oxide semiconductor layer 4 during the formation of the connection electrode 14. This reduces carriers (e.g., oxygen defects) that contribute to electrical conduction on the surface of the oxide semiconductor layer 4, further increasing the contact resistance.

[0041] In order to reduce the resistance at the contact portion with the oxide semiconductor layer 4, it is conceivable to increase the amount of impurities introduced in the resistance reduction treatment of the oxide semiconductor layer 4. However, simply increasing the amount of impurities doped into the oxide semiconductor layer 4 increases the overall mobility of the source region 4s and the drain region 4d. In this case, the transistor characteristics such as the threshold voltage of the TFT 10 change, which may cause a new problem in that desired characteristics cannot be obtained.

[0042] Therefore, in the present technology, the drain region 4d is formed by a drain contact hole CH D Overlapping part D H The drain contact hole CH is configured so that the impurity concentration is higher than at least the portion adjacent to the channel region 4c (see FIG. 7A). D Overlapping part D H The drain contact hole CH D This part D HThe impurity concentration does not necessarily have to be uniform, but it is sufficient that the impurity concentration is higher overall than the rest of the drain region 4d. D Overlapping part D H The impurity concentration M1 of the drain region 4d is, for example, a portion D C The impurity concentration M2 of the portion D adjacent to the channel region 4c is higher than that of the portion D C The part D of the drain region 4d C and the channel region 4c. However, as shown in FIG. 7A, this portion D C A part of the region between the channel region 4c and the region D, whose impurity concentration is the average impurity concentration of the region, is referred to as a part D adjacent to the channel region 4c. C can be considered representative of

[0043] As the impurity, various elements that can act as donors or acceptors in the target oxide semiconductor layer 4 can be considered. Examples include Group 13 elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In), and Group 15 elements such as phosphorus (P), arsenic (As), and antimony (Sb). Hydrogen (H) may also be used as the impurity.

[0044] Drain contact hole CH D Overlapping part D H The impurity concentration M1 of the region D adjacent to the channel region 4c is, for example, C The drain contact hole CH has an impurity concentration M1 that is slightly higher than the impurity concentration M2, thereby reducing the contact resistance with the connection electrode 14. D Overlapping part D H The impurity concentration M1 can be set to a level at which a desired contact can be achieved between the connection electrode 14 and the drain region 4d (and by extension, the source electrode 7). Although it depends on the etching conditions and the configuration of the oxide semiconductor layer 4, for example, in order to suitably reduce the contact resistance, the drain contact hole CHD Overlapping part D H The impurity concentration M1 of the portion D adjacent to the channel region 4c is C For example, the dose is about 10 13 ions / cm 2 ~10 16 ions / cm 2 , e.g. 10 13 ~10 15 ions / cm 2 Examples include increasing the degree.

[0045] As will be described later, when impurity doping is performed in the resistance reduction treatment of the oxide semiconductor layer 4, the portion D H The concentration of impurities M1 in the part D C The concentration M2 of the impurity in the oxide semiconductor layer 4 is higher by an amount corresponding to the dose. H When the same impurity ions are used in the resistance reduction treatment of the first embodiment, the amount of the impurity ions is H In part D C The dose is larger than that of the oxide semiconductor layer 4 by an amount corresponding to the dose. H When different impurity ions are used for the low resistance treatment of part D H In part D C In the process of reducing the resistance of the oxide semiconductor layer 4, if a method other than impurity doping (for example, plasma treatment) is used, the portion D H In part D C The drain contact hole CH contains impurity ions that are not contained in the drain contact hole CH in an amount corresponding to the dose amount. D Overlapping part D H and a portion D adjacent to the channel region 4c C The concentration of the impurity can be confirmed by, for example, structural analysis of the cross section of the relevant portion of the channel region 4c.

[0046] The method for checking the impurity concentration is not particularly limited. For example, D Overlapping part DH and a portion D adjacent to the channel region 4c C Various methods can be used to evaluate the relative concentration of impurities. One example is the measurement of the impurity concentration in the depth direction in a cross section perpendicular to the substrate by time-of-flight secondary ion mass spectrometry (TOF-SIMS). The concentration is expressed as an areal density (ions / cm 2 or atoms / cm 2 ) or the volume density (ions / cm 3 or atoms / cm 3 ) may be used. Another example is to use an energy dispersive X-ray spectroscopy (EDX) to perform qualitative and quantitative analysis of elements in a predetermined region of the surface (including a surface approximately parallel or perpendicular to the substrate, or a milled surface). In addition, the impurity concentration may be evaluated by cross-sectional structure analysis (e.g., dopant contrast analysis) using a focused ion beam (FIB) and a scanning electron microscope (SEM), or by an atomic force microscope (AFM) or scanning microwave microscopy (SMM).

[0047] (Manufacturing Method 1: Activation of Oxide Semiconductor Layer by Impurity Doping 1) Drain contact hole CH D Overlapping part D H A method for increasing the impurity concentration, that is, a method for manufacturing the active matrix substrate 100 of this embodiment, will be described below. 5A to 7D are cross-sectional views showing the manufacturing process of the active matrix substrate 100.

[0048] 5A, a lower gate electrode 2 and a lower gate wiring GLA (i.e., a lower gate metal layer) are formed on a substrate 1. For example, a conductive film is deposited by a sputtering method, and then the conductive film is patterned by a photolithography process, thereby forming the lower gate electrode 2 and the lower gate wiring GLA.

[0049] The substrate 1 can be, for example, a glass substrate, a silicon substrate, or a heat-resistant plastic substrate (resin substrate). Examples of materials that can be used for the lower gate metal layer include metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), and copper (Cu), or alloys thereof, or nitrides of these metals. The lower gate metal layer may be a laminated film made of multiple layers of these materials. Here, a film made by laminating a tantalum nitride (TaN) film and a W film in this order is used as the lower gate metal layer. The thickness of the lower gate metal layer is, for example, 100 nm or more and 500 nm or less.

[0050] Next, as shown in FIG. 5B, a lower gate insulating layer 3 is formed to cover the lower gate electrode 2 and the lower gate wiring GLA. For example, the lower gate insulating layer 3 can be formed by a CVD method. Examples of materials for the lower gate insulating layer 3 include silicon oxide (e.g., SiO), silicon nitride (SiN), silicon oxynitride (SiON; x>y), and silicon nitride oxide (SiNO; x>y). The lower gate insulating layer 3 may have a stacked structure. For example, a silicon nitride layer may be formed as a lower layer on the substrate 1 side to prevent diffusion of impurities from the substrate 1, and a silicon oxide layer may be formed as an upper layer thereon to ensure insulation. The thickness of the lower gate insulating layer 3 is, for example, 150 nm to 400 nm.

[0051] Next, as shown in FIG. 5C , an oxide semiconductor layer 4 is formed on the lower gate insulating layer 3. For example, an oxide semiconductor film is deposited by sputtering, and then the oxide semiconductor film is patterned by a photolithography process to form an island-shaped oxide semiconductor layer 4. Note that the source region 4s and the drain region 4d are not formed at this stage. The oxide semiconductor layer 4 is formed to face the lower gate electrode 2 with the lower gate insulating layer 3 interposed therebetween. Various oxide semiconductor materials can be considered as the constituent material of the oxide semiconductor layer 4. Here, an In-Ga-Zn-O-based semiconductor layer having a composition ratio of In:Ga:Zn=1:1:1 is formed as the oxide semiconductor layer 4. The thickness of the oxide semiconductor layer 4 is, for example, 10 nm to 200 nm.

[0052] Next, as shown in FIG. 5D, an upper gate insulating layer 5 is deposited to cover the oxide semiconductor layer 4. The upper gate insulating layer 5 is deposited by, for example, a CVD method. Then, the oxide semiconductor layer 4 is oxidized (e.g., baked or peroxidized). The upper gate insulating layer 5 may be, for example, an insulating layer similar to the lower gate insulating layer 3 (exemplified as the lower gate insulating layer 3). Here, a silicon oxide (e.g., SiO2) layer is formed as the upper gate insulating layer 5. When an oxide layer such as a silicon oxide layer is used as the upper gate insulating layer 5, the oxide layer can reduce oxygen vacancies occurring in the channel region 4c of the oxide semiconductor layer 4, thereby preventing the channel region from becoming low in resistance. The thickness of the upper gate insulating layer 5 is, for example, 50 nm to 150 nm.

[0053] Next, as shown in FIG. 5E, an upper gate electrode 6 and an upper gate wiring GLB (i.e., an upper gate metal layer) are formed on the upper gate insulating layer 5. For example, the upper gate electrode 6 and the upper gate wiring GLB can be formed by depositing a conductive film (upper gate metal film) by sputtering and then patterning the upper gate metal film by a photolithography process. The upper gate metal film may be a film containing a metal such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), or copper (Cu), or an alloy thereof, or a metal nitride thereof. Here, a film formed by stacking a Ti film, an Al film, and a Ti film in this order is used as the upper gate metal film. The thickness of the upper gate metal film is, for example, 100 nm or more and 400 nm or less.

[0054] 6A, a resistance reduction process is performed on the oxide semiconductor layer 4. Here, impurities are doped into the oxide semiconductor layer 4 from above the upper gate insulating layer 5 using the upper gate electrode 6 as a mask. By the impurity doping, regions of the oxide semiconductor layer 4 that do not overlap with the upper gate insulating layer 5 (regions that will become the source region 4s and drain region 4d) become low-resistance regions with lower resistivity than regions of the oxide semiconductor layer 4 that overlap with the upper gate insulating layer 5 (regions that will become the channel region 4c). The low-resistance regions may be conductive regions (e.g., sheet resistance: 200 Ω / □ or less).

[0055] As the impurity, for example, at least one of the above-mentioned group 13 elements and group 15 elements can be used. Here, for example, phosphorus (P) is used as the impurity. For example, the impurity such as phosphorus (P) is prepared as an ion source gas such as phosphine (PH3), ionized by applying plasma energy or the like, accelerated by applying an electromagnetic field, and then implanted into the substrate 1. As a result, the impurity is implanted into the region of the oxide semiconductor layer 4 that is not covered by the upper gate electrode 6, forming the source region 4s and the drain region 4d. The region of the oxide semiconductor layer 4 that is covered by the upper gate electrode 6 is not implanted with the impurity and becomes the channel region 4c. The channel region 4c is disposed between the source region 4s and the drain region 4d, separating them. Although not limited thereto, the implantation amount of the impurity for forming the source region 4s and the drain region 4d can be, for example, 10 13 ~10 15 ions / cm 2 For example, the degree of

[0056] Next, as shown in FIG. 6B, a first interlayer insulating layer 8 is formed to cover the upper gate insulating layer 5 and the upper gate electrode 6. The first interlayer insulating layer 8 can be formed, for example, by a CVD method. Examples of materials that can be used for the first interlayer insulating layer 8 include inorganic insulating materials such as silicon oxide (e.g., SiO), silicon nitride (SiN), silicon oxynitride (SiON; x>y), and silicon nitride oxide (SiNO; x>y). The first interlayer insulating layer 8 can be formed as a single layer film made of one material or as a laminated film made of two or more materials. The thickness of the first interlayer insulating layer 8 is, for example, 200 nm to 700 nm. Here, a silicon oxide layer is used as the first interlayer insulating layer 8.

[0057] Subsequently, a source contact hole CH is formed in the first interlayer insulating layer 8 so as to expose a part of the source region 4s of the oxide semiconductor layer 4. S (See Figure 4.) S can be formed by patterning the first interlayer insulating layer 8 by a photolithography process, for example.

[0058] Next, the source electrode 7 and source wiring SL (i.e., source metal layer) are formed on the first interlayer insulating layer 8 (see FIG. 4). For example, the source electrode 7 and source wiring SL can be formed by depositing a conductive film by sputtering and then patterning the conductive film by a photolithography process. Examples of materials for the source metal layer include metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), copper (Cu), chromium (Cr), and titanium (Ti), as well as alloys and nitrides of these metals. The first interlayer insulating layer 8 may be formed as a single layer film made of any of these materials, or as a laminated film made of two or more materials. Here, the source metal layer is formed by laminating a Ti film, an Al film, and a Ti film in this order. The thickness of the source metal layer is, for example, 200 nm to 700 nm.

[0059] Next, as shown in FIG. 6C, a second interlayer insulating layer 9 is formed to cover the TFT 10. For example, the second interlayer insulating layer 9 can be formed by a CVD method. Examples of materials for the second interlayer insulating layer 9 include inorganic insulating materials such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON; x>y), and silicon nitride oxide (SiNO; x>y). The second interlayer insulating layer 9 can be formed as a single layer film made of one material or as a laminated film made of two or more materials. The thickness of the second interlayer insulating layer 9 is, for example, 100 nm to 600 nm. Here, a silicon nitride layer is used as the second interlayer insulating layer 9.

[0060] Next, as shown in FIG. 6D, a drain contact hole CH is formed in the first interlayer insulating layer 8 and the second interlayer insulating layer 9 so that a part of the drain region 4d of the oxide semiconductor layer 4 is exposed. D Drain contact hole CH is formed. D The drain contact hole CH can be formed by patterning the first interlayer insulating layer 8 and the second interlayer insulating layer 9 by a photolithography process, for example.D The drain contact hole CH can be formed to have a size of, for example, 1.5 μm to 2.5 μm square. By etching the first interlayer insulating layer 8 and the second interlayer insulating layer 9 in this photolithography process, the drain contact hole CH D The exposed portion is, for example, oxidized at the surface.

[0061] Therefore, as shown in FIG. 7A, a drain contact hole CH D The substrate 1 on which the above-mentioned insulating interlayer 9 has been formed is doped with an impurity from above the second interlayer insulating layer 9. As the impurity, an impurity that acts as a donor or an acceptor can be used, as in the activation step of the oxide semiconductor layer 4. The impurity may be the same as or different from the impurity used in the activation step of the oxide semiconductor layer 4. The doping of the impurity can be performed in the same manner as in the activation step of the oxide semiconductor layer 4.

[0062] Here, the first interlayer insulating layer 8 and the second interlayer insulating layer 9 are sufficiently thick compared to, for example, the upper gate insulating layer 5. Therefore, the impurity ions implanted from above the second interlayer insulating layer 9 do not reach the portion of the oxide semiconductor layer 4 that is covered with the first interlayer insulating layer 8 and the second interlayer insulating layer 9. In addition, the impurity ions implanted from above the second interlayer insulating layer 9 do not reach the portion of the oxide semiconductor layer 4 that is covered with the first interlayer insulating layer 8 and the second interlayer insulating layer 9. D The exposed part D H As a result, the drain region 4d is doped with impurities. D Overlapping part D H This allows the impurity concentration to be selectively increased in the oxide semiconductor layer 4, and the drain contact hole CH D The oxidized part D H The contact resistance of the portion D is reduced. H The amount of impurity implanted to reduce the resistance is, for example, 10 13 ~10 15 ions / cm 2It is understood that a person skilled in the art who has read the present disclosure can determine the amount of impurities that is suitable for the contact through several trials.

[0063] Next, as shown in FIG. 7B, a connection electrode 14 is formed on the second interlayer insulating layer 9. For example, the connection electrode 14 can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the connection electrode 14 include indium tin oxide (ITO) and indium zinc oxide (IZO). In this example, indium tin oxide is used. The thickness of the connection electrode 14 is, for example, 30 nm or more and 100 nm or less.

[0064] Next, as shown in FIG. 7C, a planarization layer 16 is formed to cover the second interlayer insulating layer 9 and the connection electrodes 14. The planarization layer 16 can be formed, for example, by applying a photosensitive resin material onto the second interlayer insulating layer 9 and the connection electrodes 14. Examples of photosensitive resin materials include photosensitive acrylic resin, silicone resin, epoxy resin, and polyimide resin. Here, a photosensitive acrylic resin is used. The thickness t of the planarization layer 16 is, for example, about 2.5 μm to 5.0 μm.

[0065] As shown in FIG. 7D, the planarization layer 16 is exposed and developed to form the pixel contact holes CH P The portion corresponding to the pixel contact hole CH is removed to expose a part of the connection electrode 14. When the thickness of the lower gate electrode 2 and the upper gate electrode 6 is about 300 nm, P The depth d of the pixel contact hole CH is, for example, about 2.2 μm. P is formed, for example, into a 2.5 μm to 3.5 μm square (may be circular).

[0066] Next, as shown in FIG. 3, pixel electrodes 18 are formed on the planarization layer 16. For example, the pixel electrodes 18 can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the pixel electrodes 18 include indium tin oxide and indium zinc oxide. In this example, indium zinc oxide is used. The thickness of the pixel electrodes 18 is, for example, 30 nm or more and 100 nm or less.

[0067] Although not specifically shown, next, for example, a dielectric layer is formed to cover the pixel electrodes 18. For example, the dielectric layer can be formed by a CVD method. For example, an inorganic insulating layer similar to the first interlayer insulating layer 8 and the second interlayer insulating layer 9 can be used as the dielectric layer. Here, a silicon nitride layer is used as the dielectric layer. The thickness of the dielectric layer is, for example, 50 nm or more and 300 nm or less.

[0068] A common electrode is then formed on the dielectric layer. For example, the common electrode can be formed by depositing a transparent conductive film by sputtering and then patterning the transparent conductive film by a photolithography process. Examples of transparent conductive materials that can be used to form the common electrode include indium tin oxide and indium zinc oxide. In this example, indium zinc oxide is used. The thickness of the common electrode is, for example, 30 nm or more and 100 nm or less. In this manner, the active matrix substrate 100 can be manufactured.

[0069] If the pixel pitch is large enough to provide a sufficient gap between the source electrode 7 and the connection electrode 14, the connection electrode 14 may be provided in the same layer as the source electrode 7 (i.e., on the first interlayer insulating layer 8). In this case, the second interlayer insulating layer 9 can be omitted, simplifying the manufacturing process.

[0070] (Embodiment 2) (Manufacturing Method 2: Activation of Oxide Semiconductor Layer by Impurity Doping 2) Another method for manufacturing the active matrix substrate 200 according to the second embodiment will be described. FIGS. 8A and 8B are cross-sectional views showing another manufacturing process for the active matrix substrate 200. In the manufacturing method according to the second embodiment, after forming the connection electrode 14, the drain contact hole CH D Overlapping part D H 7A and 7B, the manufacturing method is the same as that of Embodiment 1. A redundant description of the steps and effects common to Embodiment 1 will be omitted.

[0071] In the manufacturing method of the second embodiment, the drain contact hole CH D After forming the connection electrode 14 (see FIG. 6D), the connection electrode 14 is formed as shown in FIG. 8A. The method for forming the connection electrode 14 is the same as in the first embodiment. The connection electrode 14 is formed by inserting the drain contact hole CH D In the drain region 4d, the drain contact hole CH D Overlapping part D H and come into contact with them.

[0072] Thereafter, as shown in FIG. 8B, impurities are doped from above the connection electrode 14 and the second interlayer insulating layer 9. The doping of impurities is the same as in the first embodiment. For example, since the second interlayer insulating layer 9, the first interlayer insulating layer 8, and the upper gate insulating layer 5 are sufficiently thick, the impurity ions implanted from above these insulating layers do not reach the oxide semiconductor layer 4. In contrast, the drain contact hole CH D In this example, the second interlayer insulating layer 9, the first interlayer insulating layer 8, and the upper gate insulating layer 5 are removed, and the connection electrode 14 is sufficiently thin compared to the first interlayer insulating layer 8 and the second interlayer insulating layer 9. Therefore, the impurity ions are not introduced into the drain contact hole CH where the insulating layers have been removed. D In the oxide semiconductor layer 4, a drain contact hole CH D Overlapping part D H is doped into

[0073] Even with this method, the drain contact hole CH D Overlapping part D H As a result, the impurity concentration can be selectively increased in the oxide semiconductor layer 4, D The oxidized part D H The contact resistance is reduced. The subsequent steps may be the same as those in Embodiment 1 (see FIGS. 7C to 7D, FIG. 3, etc.) In this way, the active matrix substrate 200 can be manufactured.

[0074] (Embodiment 3) (Manufacturing Method 3: Activation of Oxide Semiconductor Layer by Plasma Treatment 1) An active matrix substrate 300 according to embodiment 3 and a method for manufacturing the same will now be described. FIGS. 9A to 10E are cross-sectional views illustrating other manufacturing steps for the active matrix substrate 300. The manufacturing method of embodiment 3 differs from the manufacturing method of embodiment 1 in that the oxide semiconductor layer 4 is activated by plasma treatment. A redundant description of the processes and effects common to embodiment 1 will be omitted.

[0075] That is, the steps up to the formation of the upper gate insulating layer 5 are the same as those in the first embodiment (see FIGS. 5A to 5E). In the manufacturing method of Embodiment 3, the source region 4s and the drain region 4d of the oxide semiconductor layer 4 are then exposed as shown in FIG. 9A. For example, the source region 4s and the drain region 4d can be exposed by removing the portion of the upper gate insulating layer 5 that covers at least the source region 4s and the drain region 4d by patterning using a photolithography process. Note that in the step of forming the upper gate insulating layer 5 shown in FIG. 5E, the upper gate insulating layer 5 may be patterned together with the upper gate metal film. In this case, the step shown in FIG. 9A can be omitted.

[0076] Next, as shown in FIG. 9B, the exposed oxide semiconductor layer 4 is subjected to a resistance reduction process. Here, for example, plasma treatment is performed on the oxide semiconductor layer 4 using the upper gate electrode 6 as a mask. In the plasma treatment, the exposed oxide semiconductor layer 4 is exposed to an atmosphere generating, for example, argon (Ar) plasma, ammonia (NH3) plasma, hydrogen (H) plasma, or a mixture of these plasmas. This modifies the oxide semiconductor layer 4, increasing its carrier density. By this plasma treatment, the regions of the oxide semiconductor layer 4 that do not overlap with the upper gate insulating layer 5 and the upper gate electrode 6 (regions that will become the source region 4s and the drain region 4d) become low-resistivity regions with a lower resistivity than the regions of the oxide semiconductor layer 4 that overlap with the upper gate insulating layer 5 and the upper gate electrode 6 (regions that will become the channel region 4c). As a result, the source region 4s and the drain region 4d are formed.

[0077] Next, as shown in FIG. 9C, a first interlayer insulating layer 8 is formed to cover the exposed oxide semiconductor layer 4 and the upper gate electrode 6, and a source contact hole CH S 9E, a drain contact hole CH is formed in the first interlayer insulating layer 8 and the second interlayer insulating layer 9 so that a part of the drain region 4d of the oxide semiconductor layer 4 is exposed. D As a result, the drain contact hole CH D 9C to 9E can be performed in the same manner as the steps shown in FIGS. 6B to 6D of the first embodiment, although the upper gate insulating layer 5 is not included.

[0078] Then, as shown in FIG. 10A, a drain contact hole CH DThe substrate 1 on which the above-mentioned insulating layer 9 has been formed is doped with impurities from above the second interlayer insulating layer 9. Next, as shown in FIG. 10B, a connection electrode 14 is formed on the second interlayer insulating layer 9. Next, as shown in FIG. 10C, a planarization layer 16 is formed to cover the second interlayer insulating layer 9 and the connection electrode 14. Then, as shown in FIG. 10D, a pixel contact hole CH is formed in the planarization layer 16. P 10E, a pixel electrode 18 is formed on the planarization layer 16. The steps shown in FIGS. 10A to 10E can be performed in the same manner as the steps shown in FIGS. 7A to 7D and 3 of the first embodiment, although the upper gate insulating layer 5 is not provided. In this way, an active matrix substrate 300 can be fabricated.

[0079] (Embodiment 4) (Manufacturing Method 4: Activation of Oxide Semiconductor Layer by Plasma Treatment 2) Another method for manufacturing the active matrix substrate 400 according to the fourth embodiment will be described. Fig. 11A and Fig. 11B are cross-sectional views showing another manufacturing process for the active matrix substrate 400. In the manufacturing method according to the fourth embodiment, after forming the connection electrode 14, the drain contact hole CH D Overlapping part D H 11A and 11B, the manufacturing method of this embodiment differs from that of Embodiment 3 in that an impurity is doped into the semiconductor substrate. That is, the manufacturing method of this embodiment can be carried out in the same manner as in Embodiments 1 to 3. In the following, redundant explanations of the steps and effects common to Embodiments 1 to 3 will be omitted.

[0080] In the manufacturing method of the fourth embodiment, the drain contact hole CH D 9E), the connection electrode 14 is formed as shown in FIG. 11A. Then, as shown in FIG. 11B, impurities are doped from above the connection electrode 14 and the second interlayer insulating layer 9. For example, since the second interlayer insulating layer 9 and the first interlayer insulating layer 8 are sufficiently thick, impurity ions implanted from above these insulating layers do not reach the oxide semiconductor layer 4. In contrast, the drain contact hole CH DIn this case, the second interlayer insulating layer 9 and the first interlayer insulating layer 8 have been removed, and the connection electrode 14 is sufficiently thin compared to the first interlayer insulating layer 8 and the second interlayer insulating layer 9. Therefore, the impurity ions are not transferred to the drain contact hole CH where the insulating layers have been removed. D In the oxide semiconductor layer 4, a drain contact hole CH D Overlapping part D H is doped into

[0081] Even with this method, the drain contact hole CH D Overlapping part D H As a result, the impurity concentration can be selectively increased in the oxide semiconductor layer 4, D The oxidized part D H The contact resistance is reduced. Other steps may be the same as those in the first and third embodiments. In this way, the active matrix substrate 400 can be manufactured.

[0082] (Embodiment 5) An active matrix substrate 500 according to embodiment 5 and other manufacturing methods will be described. The active matrix substrate 500 differs from the active matrix substrate 300 of embodiment 3 in that it includes an additional connection electrode 15 (another connection electrode in the present technology) and an additional planarization layer 17 (another planarization layer in the present technology), as shown in FIG. 12C , for example. In the following description, the connection electrode 14 and the planarization layer 16 will be referred to as the "first connection electrode" and the "first planarization layer," respectively, and the additional connection electrode 15 and the additional planarization layer 17 will be referred to as the "second connection electrode" and the "second planarization layer," respectively. Note that, although not specifically described, the active matrix substrate 100 of embodiment 1 may also be provided with a connection electrode 15 and an additional planarization layer 17, for example.

[0083] The active matrix substrate 500 of the fifth embodiment can be produced by, for example, the following manufacturing method. FIGS. 12A to 12C are cross-sectional views showing the manufacturing process of the active matrix substrate 500 according to the fifth embodiment. Note that the pixel contact holes CH P The steps up to the formation of the active matrix substrate 500 may be the same as those in, for example, embodiment 3. Description of the configuration, manufacturing process, and effects of the active matrix substrate 500 that are common to the active matrix substrates of embodiments 1 to 4 will be omitted.

[0084] That is, as shown in FIG. 12A, the pixel contact hole CH P The pixel contact hole CH P The second connection electrode 15 is formed so as to cover the first connection electrode 14 and the pixel electrode 18. The second connection electrode 15 is formed from a transparent conductive material and electrically connects the first connection electrode 14 and the pixel electrode 18. The second connection electrode 15 is formed through the pixel contact hole CH P The first connection electrode 14 is in contact with the first connection electrode 14 at this point.

[0085] 12B, a second planarization layer 17 is formed on the second connection electrode 15. The second planarization layer 17 is formed in the pixel contact hole CH P The second planarization layer 17 is formed so as to fill in the gap between the second connection electrode 15 and the second connection electrode 15. The second planarization layer 17 is formed of, for example, a photosensitive resin material.

[0086] Then, as shown in FIG. 12C , the pixel electrode 18 is formed so as to overlap the second planarization layer 17. The pixel electrode 18 is in contact with at least a portion of the second connection electrode 15 that is not covered with the second planarization layer 17. The pixel electrode 18 includes a portion that is located on the second planarization layer 17. The second connection electrode 15 and the pixel electrode 18 are formed from the same transparent conductive material. Here, the second connection electrode 15 and the pixel electrode 18 are formed from indium tin oxide.

[0087] In the active matrix substrate 500 of the fifth embodiment, the pixel contact holes CH PThe second planarization layer 17 is formed so as to fill the pixel contact hole CH. P This suppresses the alignment disorder of the liquid crystal molecules caused by the above phenomenon, thereby enabling a further improvement in transmittance.

[0088] [About oxide semiconductors] The oxide semiconductor contained in the oxide semiconductor layer 4 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of crystalline oxide semiconductors include polycrystalline oxide semiconductors, microcrystalline oxide semiconductors, and crystalline oxide semiconductors whose c-axes are oriented approximately perpendicular to the layer surface.

[0089] The oxide semiconductor layer 4 may have a stacked structure of two or more layers. The oxide semiconductor layer 4 having a stacked structure may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer, or may include multiple crystalline oxide semiconductor layers with different crystal structures. Furthermore, the oxide semiconductor layer 4 having a stacked structure may include multiple amorphous oxide semiconductor layers. When the oxide semiconductor layer 4 has a stacked structure, the energy gaps of the layers may be different from each other.

[0090] The materials, structures, film formation methods, and configurations of oxide semiconductor layers having a stacked structure of the amorphous oxide semiconductor and the above-mentioned crystalline oxide semiconductors are described, for example, in JP 2014-007399 A. The entire disclosure of JP 2014-007399 A is incorporated herein by reference.

[0091] The oxide semiconductor layer 4 may contain at least one metal element selected from the group consisting of In, Ga, and Zn. In the above-described embodiment, the oxide semiconductor layer 4 contains, for example, an In—Ga—Zn—O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer 4 may be formed from an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.

[0092] The In-Ga-Zn-O based semiconductor may be amorphous or crystalline, and a crystalline In-Ga-Zn-O based semiconductor with its c-axis oriented generally perpendicular to the layer plane is preferred as the crystalline In-Ga-Zn-O based semiconductor.

[0093] The crystal structure of crystalline In-Ga-Zn-O-based semiconductors is disclosed, for example, in the aforementioned Japanese Patent Application Laid-Open Nos. 2014-007399, 2012-134475, and 2014-209727. The disclosures of Japanese Patent Application Laid-Open Nos. 2012-134475 and 2014-209727 are incorporated herein by reference in their entirety. TFTs having an In-Ga-Zn-O-based semiconductor layer have high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one-hundredth that of an a-Si TFT). Therefore, they are suitable for use as driver TFTs (e.g., TFTs included in a driver circuit provided on the same substrate as a display area, around a display area including multiple pixels) and pixel TFTs (TFTs provided in pixels).

[0094] The oxide semiconductor layer 4 may contain other oxide semiconductors instead of the In-Ga-Zn-O-based semiconductor. For example, it may contain an In-Sn-Zn-O-based semiconductor (e.g., In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer 4 may include an In-Al-Zn-O based semiconductor, an In-Al-Sn-Zn-O based semiconductor, a Zn-O based semiconductor, an In-Zn-O based semiconductor, a Zn-Ti-O based semiconductor, a Cd-Ge-O based semiconductor, a Cd-Pb-O based semiconductor, CdO (cadmium oxide), an Mg-Zn-O based semiconductor, an In-Ga-Sn-O based semiconductor, an In-Ga-O based semiconductor, a Zr-In-Zn-O based semiconductor, an Hf-In-Zn-O based semiconductor, an Al-Ga-Zn-O based semiconductor, a Ga-Zn-O based semiconductor, an In-Ga-Zn-Sn-O based semiconductor, or the like.

[0095] (Liquid crystal display device) The active matrix substrates 100, 200, 300, 400 and 500 according to the embodiments of the present invention can be suitably used in a liquid crystal display device. An example of a liquid crystal display device is shown in FIG.

[0096] The liquid crystal display device 1000 shown in Figure 13 includes an active matrix substrate 100 (or active matrix substrates 200, 300, 400, 500), a counter substrate 600 arranged opposite to the active matrix substrate 100, and a liquid crystal layer 30 arranged between the active matrix substrate 100 and the counter substrate 600.

[0097] The active matrix substrate 100 includes a TFT 10 (not shown) disposed in each pixel region P, a pixel electrode 18 electrically connected to the TFT 10, a dielectric layer (not shown) provided so as to cover the pixel electrode 18, and a common electrode (not shown) provided on the dielectric layer and facing the pixel electrode 18. At least one slit (not shown) is formed in the common electrode for each pixel region P.

[0098] An alignment film (not shown) is provided on the outermost surface of each of the active matrix substrate 100 and the counter substrate 600, facing the liquid crystal layer 30. The counter substrate 600 typically has a color filter layer and a black matrix (neither of which are shown).

[0099] The thickness (cell gap) of the liquid crystal layer 30 is determined by columnar spacers 50 provided on the liquid crystal layer 30 side of the counter substrate 600. A spacer receiving portion (not shown) may be provided on the active matrix substrate side.

[0100] Although the liquid crystal display device 1000 in the FFS mode, which is a type of lateral electric field mode, has been illustrated here, the active matrix substrate according to the embodiment of the present invention may be used in liquid crystal display devices of other display modes. In a liquid crystal display device in a vertical electric field mode such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, the common electrode is provided on the opposing substrate side. The active matrix substrate 100 according to the present technology is particularly suitable for use in high-resolution (e.g., 1000 ppi or more) liquid crystal display devices such as a liquid crystal display device 1000 for a head-mounted display. [Explanation of symbols]

[0101] 1...substrate, 2...lower gate electrode, 3...lower gate insulating layer, 4...oxide semiconductor layer, 4c...channel region, 4d...drain region, 4s...source region, 5...upper gate insulating layer, 6...upper gate electrode, 7...source electrode, 8...first interlayer insulating layer, 9...second interlayer insulating layer, 10...thin film transistor (TFT), 12...base coat layer, 14...first connection electrode, 15...second connection electrode, 16...planarization layer, 17...second planarization layer, 18...pixel electrode, 19...light-shielding layer, 30...liquid crystal layer, 50...columnar spacer, 100, 200, 300, 400, 500...active matrix substrate, 600...counter substrate, 1000...liquid crystal display device, CH D ...Drain contact hole, CH P ...pixel contact hole, bf...bottom surface, CH S …Source contact hole, D C…part, D H ...part, DR...display area, FR...non-display area, GD...gate driver, GL...gate wiring, GLA...lower gate wiring, GLB...upper gate wiring, SD...source driver, SL...source wiring

Claims

1. a display area including a plurality of pixel areas; A substrate; a thin film transistor (TFT) supported by the substrate and disposed in each of the plurality of pixel regions; an insulating layer covering the TFT; a planarization layer covering the insulating layer; a pixel electrode provided on the planarization layer; a connection electrode provided between the insulating layer and the planarization layer for electrically connecting the TFT and the pixel electrode; An active matrix substrate comprising: The TFT is A gate electrode; a gate insulating layer that electrically insulates the gate electrode; an oxide semiconductor layer including a channel region facing the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region located on both sides of the channel region; and the insulating layer has a contact hole at a position overlapping the drain region; the connection electrode is made of a transparent conductive material and is connected to the drain region through the contact hole; the drain region has a higher impurity concentration at least in a portion overlapping the contact hole than in a portion adjacent to the channel region; Active matrix substrate.

2. The impurity is at least one of a Group 13 element and a Group 15 element. The active matrix substrate according to claim 1 .

3. the connection electrode includes at least one of indium tin oxide (ITO) and indium zinc oxide (IZO); the oxide semiconductor layer contains an In—Ga—Zn—O-based oxide semiconductor; The active matrix substrate according to claim 1 .

4. when viewed from a normal direction of the substrate, at least a part of the planarization layer has a pixel contact hole at a position overlapping the gate electrode for connecting the pixel electrode and the connection electrode; The active matrix substrate according to claim 1 .

5. When viewed from a normal direction of the substrate, at least a portion of a bottom surface of the pixel contact hole overlaps with a gate metal layer including the gate electrode. The active matrix substrate according to claim 4 .

6. 5. The active matrix substrate according to claim 4, wherein a portion of the pixel electrode is in contact with the connection electrode in the pixel contact hole.

7. another connection electrode formed of a transparent conductive material and electrically connecting the connection electrode and the pixel electrode, the other connection electrode being in contact with the connection electrode in the pixel contact hole; another planarization layer formed to fill the pixel contact hole and cover a part of the another connection electrode; Furthermore, the pixel electrode is in contact with a portion of the other connection electrode that is not covered by the other planarization layer, the pixel electrode includes a portion located on the other planarization layer; The active matrix substrate according to claim 4 .

8. the other connection electrode and the pixel electrode are formed from the same transparent conductive material; The active matrix substrate according to claim 7 .

9. the other connection electrode and the pixel electrode are formed from at least one of indium tin oxide and indium zinc oxide; The active matrix substrate according to claim 8 .

10. The TFT is a lower gate electrode provided on the substrate; a lower gate insulating layer covering the lower gate electrode; the oxide semiconductor layer provided such that the channel region is disposed on the lower gate insulating layer; an upper gate insulating layer provided on the channel region of the oxide semiconductor layer; an upper gate electrode provided on the upper gate insulating layer and facing the channel region of the oxide semiconductor layer via the upper gate insulating layer; The active matrix substrate according to claim 1 , comprising:

11. when viewed from a normal direction of the substrate, the planarization layer has a pixel contact hole at a position at which at least a part of the pixel contact hole overlaps with the upper gate electrode, for electrically connecting the pixel electrode and the connection electrode; At least a part of a bottom surface of the pixel contact hole overlaps both the lower gate electrode and the upper gate electrode. The active matrix substrate according to claim 10 .

12. an active matrix substrate according to any one of claims 1 to 11; an opposing substrate provided opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate.

13. 1. A method for manufacturing an active matrix substrate, comprising: forming a thin film transistor (TFT) on a substrate, wherein the TFT comprises: A gate electrode; a gate insulating layer that electrically insulates the gate electrode; an oxide semiconductor layer including a channel region facing the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region located on both sides of the channel region; having forming an insulating layer on the TFT; providing a contact hole in the insulating layer that leads to the drain region; doping an impurity into a portion of the drain region that overlaps the contact hole through the contact hole; forming a connection electrode on the insulating layer at least at a position from the contact hole to the gate electrode, the connection electrode being for electrically connecting the TFT and the pixel electrode; forming a planarization layer on the insulating layer and the connection electrode; A method for manufacturing an active matrix substrate, comprising:

14. The TFT is a lower gate electrode provided on the substrate; a lower gate insulating layer covering the lower gate electrode; the oxide semiconductor layer provided such that the channel region is disposed on the lower gate insulating layer; an upper gate insulating layer provided on the channel region of the oxide semiconductor layer; an upper gate electrode provided on the upper gate insulating layer and facing the channel region of the oxide semiconductor layer via the upper gate insulating layer; Equipped with forming the connection electrode on the insulating layer at a position extending from the contact hole to overlap with the upper gate electrode; The method for manufacturing an active matrix substrate according to claim 13 .

15. forming a pixel contact hole in the planarization layer at a position overlapping the gate electrode or the upper gate electrode and the connection electrode, the pixel contact hole communicating with the connection electrode; forming a pixel electrode on the planarization layer at a position where at least a portion of the pixel electrode overlaps with the connection electrode through the pixel contact hole; The method for manufacturing an active matrix substrate according to claim 14 , further comprising:

16. forming a pixel contact hole in the planarization layer at a position overlapping the gate electrode or the upper gate electrode and the connection electrode, the pixel contact hole communicating with the connection electrode; forming another connection electrode on the planarization layer at a position where at least a portion of the connection electrode overlaps with the connection electrode through the pixel contact hole; forming another planarization layer to fill the pixel contact holes; forming a pixel electrode on at least one of the planarizing layer and the another planarizing layer at a position where at least a portion of the pixel electrode overlaps with the another connection electrode; The method for manufacturing an active matrix substrate according to claim 14 or 15, further comprising:

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