Method of manufacturing semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device, the method enabling a layer having been used for removing metal atoms from a semiconductor layer to be suitably removed.SOLUTION: According to one embodiment, a method of manufacturing semiconductor device includes a step of forming a semiconductor layer including a plurality of metal atoms. The method further includes a step of forming, on the semiconductor layer, a first layer other than a Si (silicon) layer as a layer including a main component element different from a main component element in the semiconductor layer. The method further includes a step of moving at least a part of the metal atoms in the semiconductor layer into or onto the first layer. The method further includes a step of moving the at least some of the metal atoms into or onto the first layer, then removing the first layer and the at least some of the metal atoms.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] When metal atoms contained in a semiconductor layer are removed into a layer called a getter layer, it is desirable to be able to conveniently remove the getter layer after removing the metal atoms. For example, it is desirable to be able to easily remove the getter layer and to be able to remove the getter layer while minimizing damage to the semiconductor layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-015868 [Patent Document 2] Japanese Patent Application Publication No. 2022-144977 [Non-patent literature]

[0004] [Non-Patent Document 1] H. Murata et al., "Direct synthesis of multilayer graphene on an insulator by Ni-induced layer exchange growth of amorphous carbon", Appl. Phys. Lett. 110, 033108 (2017) Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention relates to a method for manufacturing a semiconductor device that can suitably remove a layer used to remove metal atoms from a semiconductor layer. [Means for solving the problem]

[0006] According to one embodiment, a method for manufacturing a semiconductor device includes forming a semiconductor layer containing a plurality of metal atoms. The method further includes forming a first layer other than a Si (silicon) layer on the semiconductor layer as a layer containing a main component element different from that of the semiconductor layer. The method further includes migrating at least some of the metal atoms in the semiconductor layer to an interior or surface of the first layer. The method further includes removing the first layer and the at least some of the metal atoms after migrating at least some of the metal atoms to an interior or surface of the first layer. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] 1 is an enlarged cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 3] 4 is a cross-sectional view (1 / 2) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view (2 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 1 is a cross-sectional view (1 / 10) showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 1A and 1B are cross-sectional views (2 / 10) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 3 is a cross-sectional view (3 / 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 4 is a cross-sectional view (4 / 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 5 is a cross-sectional view (5 / 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 6 is a cross-sectional view (6 / 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 7 is a cross-sectional view (7 / 10) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 12]8 is a cross-sectional view (8 / 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 9 is a cross-sectional view (9 / 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 10 is a cross-sectional view (10 / 10) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 10 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 16] 10 is a cross-sectional view (2 / 2) showing a method for manufacturing a semiconductor device according to a modified example of the first embodiment. [Figure 17] 10 is a cross-sectional view (1 / 3) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 18] 10 is a cross-sectional view (2 / 3) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 19] 10 is a cross-sectional view (3 / 3) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 20] 10 is a cross-sectional view (1 / 7) showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 21] 10 is a cross-sectional view (2 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 22] 10 is a cross-sectional view (3 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 23] 10 is a cross-sectional view (4 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 24] 10 is a cross-sectional view (5 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. [Figure 25] 6 is a cross-sectional view (6 / 7) illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 26] 7 is a cross-sectional view (7 / 7) showing the method for manufacturing the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 26, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0009] (First embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment.

[0010] The semiconductor device of this embodiment includes, for example, a three-dimensional semiconductor memory. As will be described later, the semiconductor device of this embodiment is manufactured by bonding an array wafer including an array chip 1 and a circuit wafer including a circuit chip 2 together.

[0011] The array chip 1 includes a memory cell array 11 including a plurality of memory cells, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, an SiO2 film (silicon oxide film). The interlayer insulating film 13 is, for example, a stacked film including an SiO2 film and other insulating films.

[0012] The circuit chip 2 is provided below the array chip 1. The symbol S indicates the bonding surface between the array chip 1 and the circuit chip 2. The circuit chip 2 includes an interlayer insulating film 14 below the interlayer insulating film 13, and a substrate 15 below the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a laminated film including an SiO2 film and other insulating films. The substrate 15 is, for example, a semiconductor substrate such as a Si (silicon) substrate.

[0013] 1 shows an X direction and a Y direction that are parallel to the surface of the substrate 15 and perpendicular to each other, and a Z direction that is perpendicular to the surface of the substrate 15. The X direction, the Y direction, and the Z direction intersect with each other. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. The −Z direction may or may not coincide with the direction of gravity.

[0014] The array chip 1 includes a plurality of word lines WL as a plurality of electrode layers in a memory cell array 11. FIG. 1 shows a staircase structure 21 in the memory cell array 11 and a plurality of beam portions 22 provided in the staircase structure 21. Each word line WL is electrically connected to a word wiring layer 24 via a contact plug 23. Each columnar portion CL passing through the plurality of word lines WL is electrically connected to a bit line BL via a via plug 25 and is also electrically connected to a source line SL. The bit line BL is provided below the plurality of word lines WL, and the source line SL is provided above the plurality of word lines WL.

[0015] The circuit chip 2 includes a plurality of transistors 31. Each transistor 31 includes a gate insulating film 31a and a gate electrode 31b provided in this order on the substrate 15, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 15. The circuit chip 2 also includes a plurality of contact plugs 32 provided on the gate electrodes 31b, source diffusion layers, or drain diffusion layers of the plurality of transistors 31. The circuit chip 2 also includes a wiring layer 33, a wiring layer 34, and a wiring layer 35. The wiring layer 33 includes a plurality of wires and is provided on the plurality of contact plugs 32. The wiring layer 34 includes a plurality of wires and is provided on the wiring layer 33. The wiring layer 35 includes a plurality of wires and is provided on the wiring layer 34.

[0016] The circuit chip 2 further includes a plurality of via plugs 36 provided on the wiring layer 35, and a plurality of metal pads 37 provided on the plurality of via plugs 36. The metal pads 37 are, for example, a metal layer including a Cu (copper) layer. The circuit chip 2 functions as a control circuit (logic circuit) that controls the operation of the array chip 1. This control circuit is composed of transistors 31 and the like, and is electrically connected to the metal pads 37.

[0017] The array chip 1 includes a plurality of metal pads 41 provided on the plurality of metal pads 37, and a plurality of via plugs 42 provided on the plurality of metal pads 41. The metal pads 41 are, for example, a metal layer including a Cu layer. The array chip 1 also includes a wiring layer 43 and a wiring layer 44. The wiring layer 43 includes a plurality of wires and is provided on the plurality of via plugs 42. The wiring layer 44 includes a plurality of wires and is provided on the wiring layer 43. The bit lines BL are included in the wiring layer 44. The control circuit is electrically connected to the memory cell array 11 via the metal pads 41, 37, etc., and controls the operation of the memory cell array 11 via the metal pads 41, 37, etc.

[0018] The array chip 1 further includes a plurality of via plugs 45 provided on the wiring layer 44, and metal pads 46 provided on the plurality of via plugs 45 and on the insulating film 12. The array chip 1 also includes a passivation insulating film 47 provided on the metal pads 46 and on the insulating film 12. The metal pads 46 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) of the semiconductor device of this embodiment. The passivation insulating film 47 is, for example, a laminated film including an SiO2 film and an SiN film (silicon nitride film), and has an opening P that exposes the top surface of the metal pad 46. The metal pads 46 can be electrically connected to a mounting substrate or another device via a bonding wire, a solder ball, a metal bump, or the like through the opening P.

[0019] FIG. 2 is an enlarged cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0020] 2 shows the memory cell array 11 shown in FIG. 1. The memory cell array 11 includes a stacked film 51 including a plurality of electrode layers 51a and a plurality of insulating films 51b alternately stacked in the Z direction. The plurality of electrode layers 51a function as, for example, the above-mentioned word lines WL. Each electrode layer 51a is, for example, a metal layer including a W (tungsten) layer. Each insulating film 51b is, for example, a SiO2 film.

[0021] FIG. 2 further illustrates one of the multiple columnar portions CL illustrated in FIG. 1. Each columnar portion CL includes a memory insulating film 52, a channel semiconductor layer 53, and a core insulating film 54, which are provided in this order on the side surface of a stacked film 51. The memory insulating film 52 includes a block insulating film 52a, a charge storage layer 52b, and a tunnel insulating film 52c, which are provided in this order on the side surface of the stacked film 51. The block insulating film 52a is, for example, a SiO2 film. The charge storage layer 52b is, for example, an insulating film such as a SiN film. The charge storage layer 52b may be a semiconductor layer such as a polysilicon layer. The tunnel insulating film 52c is, for example, a SiO2 film. The channel semiconductor layer 53 is, for example, a polysilicon layer. The channel semiconductor layer 53 functions as the channel of the memory cell. The core insulating film 54 is, for example, a SiO2 film.

[0022] 3 and 4 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0023] 3 shows an array wafer W1 including a plurality of array chips 1 and a circuit wafer W2 including a plurality of circuit chips 2. The orientation of the array wafer W1 in FIG. 3 is opposite to the orientation of the array chip 1 in FIG. 1. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. FIG. 3 shows the array wafer W1 before its orientation is reversed for bonding, and FIG. 1 shows the array chip 1 after its orientation is reversed for bonding, bonding, and dicing.

[0024] 3, symbol S1 denotes the upper surface of the array wafer W1, and symbol S2 denotes the upper surface of the circuit wafer W2. The array wafer W1 includes a substrate 16 provided under an insulating film 12. The substrate 16 is, for example, a semiconductor substrate such as a Si substrate.

[0025] In this embodiment, first, as shown in FIG. 3, the memory cell array 11, insulating film 12, interlayer insulating film 13, metal pad 41, etc. are formed on the substrate 16 of the array wafer W1, and the interlayer insulating film 14, transistor 31, metal pad 37, etc. are formed on the substrate 15 of the circuit wafer W2. Next, as shown in FIG. 4, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that the surfaces S1 and S2 face each other. This bonds the interlayer insulating film 13 and the interlayer insulating film 14. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pad 41 and the metal pad 37. In this way, the substrate 16 and the substrate 15 are bonded together with the interlayer insulating films 13 and 14 interposed therebetween.

[0026] Thereafter, the substrate 16 is removed by CMP (Chemical Mechanical Polishing), the substrate 15 is thinned by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips (dicing). In this manner, the semiconductor device shown in FIG. 1 is manufactured. Note that the metal pads 46 and the passivation insulating film 47 are formed on the insulating film 12 after the substrate 16 is removed and the substrate 15 is thinned.

[0027] 1 shows the boundary surface between interlayer insulating film 13 and interlayer insulating film 14 and the boundary surface between metal pad 41 and metal pad 37, but these boundaries generally become invisible after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of metal pad 41 or the side surface of metal pad 37, or the positional deviation between the side surface of metal pad 41 and the side surface of metal pad 37.

[0028] 5 to 14 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment, each showing details of the process for forming the memory cell array 11 in FIG.

[0029] First, a laminated film 51 is formed above the substrate 16 of the array wafer W1, and an insulating film 61 is formed on the laminated film 51 (FIG. 5). The laminated film 51 is formed by alternately forming a plurality of insulating films 51b and a plurality of sacrificial layers 51a' on the substrate 16. Each sacrificial layer 51a' is, for example, a SiN film. The insulating film 61 is, for example, a SiO2 film.

[0030] Next, a plurality of memory holes H1 are formed in the insulating film 61 and the stacked film 51 by lithography and RIE (Reactive Ion Etching) (FIG. 6). Each memory hole H1 extends in the Z direction and has a circular shape in a plan view. In this embodiment, each memory hole H1 is formed to penetrate the insulating film 61 and the stacked film 51 in the Z direction.

[0031] Next, a memory insulating film 52, a channel semiconductor layer 53, a core insulating film 54, a cap semiconductor layer 62, and a getter layer 63 are formed in this order on the entire surface of the substrate 16 (FIG. 7). As a result, the memory insulating film 52, the channel semiconductor layer 53, and the core insulating film 54 are formed in this order on the side surfaces of the stacked film 51 and the insulating film 61 in each memory hole H1. In FIG. 7, the memory insulating film 52 and the channel semiconductor layer 53 are further formed in this order on the upper surface of the insulating film 61. FIG. 7 also shows a void V formed in the core insulating film 54.

[0032] 7, the memory insulating film 52, the channel semiconductor layer 53, and the core insulating film 54 are formed on the side surfaces of the stacked film 51 and the insulating film 61 and on the upper surface of the insulating film 61, and then the core insulating film 54 is removed from the upper surface of the insulating film 61. As a result, the upper surface of the channel semiconductor layer 53 is exposed from the core insulating film 54. Then, the cap semiconductor layer 62 and the getter layer 63 are formed in this order on the channel semiconductor layer 53 and the core insulating film 54. In FIG. 7, the lower surface of the cap semiconductor layer 62 is in contact with the upper surface of the channel semiconductor layer 53, and the lower surface of the getter layer 63 is in contact with the upper surface of the cap semiconductor layer 62.

[0033] The cap semiconductor layer 62 is, for example, a polysilicon layer, similar to the channel semiconductor layer 53. The channel semiconductor layer 53 and the cap semiconductor layer 62 are formed to contain metal atoms M in the process shown in FIG. 7. FIG. 7 schematically shows the metal atoms M contained in the channel semiconductor layer 53 and the cap semiconductor layer 62. The metal atoms M are, for example, Ni (nickel) atoms, Co (cobalt) atoms, Mn (manganese) atoms, Ti (titanium) atoms, Cr (chromium) atoms, Ru (ruthenium) atoms, Ir (iridium) atoms, Pd (palladium) atoms, Fe (iron) atoms, or Pt (platinum) atoms. The channel semiconductor layer 53 and the cap semiconductor layer 62 of this embodiment are undoped Si layers that do not contain either p-type impurity atoms or n-type impurity atoms. The channel semiconductor layer 53 and the cap semiconductor layer 62 are examples of semiconductor layers.

[0034] The channel semiconductor layer 53 and the cap semiconductor layer 62 of this embodiment are formed by crystallizing an amorphous silicon layer containing metal atoms M. As a result, the channel semiconductor layer 53 and the cap semiconductor layer 62 become polysilicon layers containing metal atoms M. According to this embodiment, by forming the channel semiconductor layer 53 and the cap semiconductor layer 62 to contain metal atoms M and then crystallizing the channel semiconductor layer 53 and the cap semiconductor layer 62, it is possible to increase the grain size of the crystal grains in the channel semiconductor layer 53 and the cap semiconductor layer 62. Annealing for crystallizing the channel semiconductor layer 53 and the cap semiconductor layer 62 may be performed at a low temperature to further increase the grain size of the crystal grains in the channel semiconductor layer 53 and the cap semiconductor layer 62.

[0035] In this embodiment, the channel semiconductor layer 53 and the cap semiconductor layer 62 are Si layers, and the getter layer 63 is a layer other than a Si layer. The getter layer 63 contains, for example, C (carbon), and in this embodiment, contains C as a main component element. Therefore, in the getter layer 63 of this embodiment, the composition ratio of C is higher than the composition ratio of any other element. The getter layer 63 is, for example, a C layer, which may further contain an impurity element. The impurity element is, for example, B (boron), P (phosphorus), As (arsenic), N (nitrogen), O (oxygen), or Si. The getter layer 63 is an example of a first layer. Each of the channel semiconductor layer 53 and the cap semiconductor layer 62 of this embodiment is a Si layer, and specifically, is either a layer containing only Si element (hereinafter referred to as "layer A") or a layer containing Si element as a main component element and elements other than Si element as impurity elements (hereinafter referred to as "layer B"). On the other hand, the getter layer 63 of this embodiment is a layer other than a Si layer, and specifically, is a layer other than layer A or layer B. The getter layer 63 of this embodiment contains a main component element different from the main component elements in the channel semiconductor layer 53 and the cap semiconductor layer 62.

[0036] The getter layer 63 may contain Ge (germanium) instead of C, and may contain, for example, Ge as a main component element and B, P, As, N, O, or Si as an impurity element. In this case, the getter layer 63 is, for example, a Ge layer.

[0037] The getter layer 63 is formed as an amorphous layer 63a in the process shown in Fig. 7. The amorphous layer 63a is, for example, an amorphous C layer. The amorphous layer 63a may be an amorphous Ge layer instead of an amorphous C layer.

[0038] The channel semiconductor layer 53 and the cap semiconductor layer 62 may contain only one type of metal atom M, or may contain two or more types of metal atoms M. The getter layer 63 may contain only one of C and Ge as a main component element, or may contain both C and Ge. The getter layer 63 may contain only one type of impurity element selected from B, P, As, N, O, and Si, or may contain two or more types of impurity element selected from B, P, As, N, O, and Si.

[0039] Next, the channel semiconductor layer 53, the cap semiconductor layer 62, the getter layer 63, and the like are annealed ( FIG. 8 ). This allows at least some of the metal atoms M in the channel semiconductor layer 53 and the cap semiconductor layer 62 to move near the getter layer 63 ( FIG. 8 ), and further allows these metal atoms M to move into or to the surface (upper surface) of the getter layer 63 ( FIG. 9 ). In FIG. 9 , the metal atoms M move to the surface of the getter layer 63, forming a metal layer 64 containing the metal atoms M. In this embodiment, the metal layer 64 is formed on the surface of the getter layer 63 during the annealing shown in FIGS. 8 and 9 . As a result, at least some of the metal atoms M in the channel semiconductor layer 53 and the cap semiconductor layer 62 are removed from the channel semiconductor layer 53 and the cap semiconductor layer 62, and the concentrations of the metal atoms M in the channel semiconductor layer 53 and the cap semiconductor layer 62 are reduced. This annealing is also called gettering annealing.

[0040] During the annealing shown in FIGS. 8 and 9, the getter layer 63 changes from an amorphous layer 63a to a crystallized layer 63b. The crystallized layer 63b is, for example, a polycrystalline C layer. An example of a polycrystalline C layer is a graphene layer. FIG. 9 shows multiple crystal grains G1 contained in the crystallized layer 63b. If the amorphous layer 63a is an amorphous Ge layer, the crystallized layer 63b becomes, for example, a polycrystalline Ge layer.

[0041] The annealing shown in Figures 8 and 9 is performed at, for example, 300°C to 1200°C. By increasing the annealing temperature to a certain extent, it is possible to cause, for example, the gettering shown in Figures 8 and 9. By decreasing the annealing temperature to a certain extent, it is possible to prevent, for example, the Si layer from melting. In this embodiment, the annealing is performed at, for example, 600°C to 1000°C.

[0042] 8 and 9 is performed in an atmosphere containing, for example, an inert gas. This makes it possible to prevent, for example, oxygen-based gases from adversely affecting layers in the array wafer W1 during the annealing. The annealing is performed in an atmosphere containing, for example, Ar (argon) gas, Ne (neon) gas, Xe (xenon) gas, N2 (nitrogen) gas, H2 (hydrogen) gas, or D2 (deuterium) gas.

[0043] In the gettering shown in FIGS. 8 and 9 , the following phenomenon may occur. For example, metal atoms M contained in the channel semiconductor layer 53 and the cap semiconductor layer 62 are sucked up into the getter layer 63, thereby removing the metal atoms M from the channel semiconductor layer 53 and the cap semiconductor layer 62. Furthermore, as shown in FIG. 8 , the metal atoms M contained in the channel semiconductor layer 53 and the cap semiconductor layer 62 form a region containing high concentrations of metal atoms M near the bottom surface of the getter layer 63, and this region vertically swaps with the getter layer 63. If this region is considered to be the metal layer 64, it can be considered that the metal layer 64 has moved from the bottom surface side to the top surface side of the getter layer 63, i.e., the position of the metal layer 64 has swapped with the position of the getter layer 63 ( FIG. 9 ). This is also called layer exchange. The layer exchange may also be expressed as the metal atoms M contained in the channel semiconductor layer 53 and the cap semiconductor layer 62 being sucked up to the surface (top surface) of the getter layer 63. Layer exchange occurs, for example, when the getter layer 63 is a C layer.

[0044] In this embodiment, the getter layer 63 is preferably formed on the cap semiconductor layer 62 so that no unnecessary film (e.g., an SiO2 film or an SiN film) is interposed between the cap semiconductor layer 62 and the getter layer 63. This makes it possible to prevent the unnecessary film from interfering with gettering. In this embodiment, the surface (upper surface) of the cap semiconductor layer 62 is treated with a chemical solution such as hydrofluoric acid, and then the getter layer 63 is formed on the cap semiconductor layer 62. This makes it possible to remove the unnecessary film from the surface of the cap semiconductor layer 62, thereby making it possible to prevent the unnecessary film from being interposed between the cap semiconductor layer 62 and the getter layer 63. An example of the unnecessary film is a native oxide film. Note that the step of treating the surface of the cap semiconductor layer 62 with the chemical solution and the step of forming the getter layer 63 are preferably performed in situ in the same chamber. This makes it possible to prevent the formation of a new unnecessary film on the surface of the cap semiconductor layer 62 between these steps.

[0045] Next, the metal layer 64 is removed (FIG. 10). The metal layer 64 is removed using a chemical solution such as SH (a mixture of sulfuric acid and hydrogen peroxide). According to the process shown in FIG. 10, the metal atoms M that migrated from the channel semiconductor layer 53 and the cap semiconductor layer 62 to the surface of the getter layer 63 and formed the metal layer 64 are removed.

[0046] Next, the getter layer 63 is removed (FIG. 11). The getter layer 63 is removed, for example, by oxidizing or ashing the getter layer 63. According to the process shown in FIG. 11, the metal atoms M that have migrated from the channel semiconductor layer 53 and the cap semiconductor layer 62 into the getter layer 63 and remain inside the getter layer 63 are removed.

[0047] According to this embodiment, by using a layer other than a Si layer for the getter layer 63, it is possible to preferably remove the getter layer 63. For example, if the channel semiconductor layer 53, the cap semiconductor layer 62, and the getter layer 63 were all Si layers, there was a risk that the cap semiconductor layer 62 and the channel semiconductor layer 53 would also be removed in a process of removing the getter layer 63. According to this embodiment, by using Si layers for the channel semiconductor layer 53 and the cap semiconductor layer 62 and a layer other than a Si layer for the getter layer 63, it is possible to easily remove the getter layer 63 while leaving the cap semiconductor layer 62 and the channel semiconductor layer 53. Furthermore, if the channel semiconductor layer 53, the cap semiconductor layer 62, and the getter layer 63 were all Si layers, there was a risk that the process of removing the getter layer 63 would damage the cap semiconductor layer 62 and the channel semiconductor layer 53. According to this embodiment, by using Si layers for the channel semiconductor layer 53 and the cap semiconductor layer 62 and a layer other than a Si layer for the getter layer 63, it is possible to suppress such damage (details will be described later).

[0048] The cap semiconductor layer 62 may or may not be removed in a subsequent process. That is, the cap semiconductor layer 62 may or may not remain in the finished semiconductor device. In this embodiment, an example in which the cap semiconductor layer 62 does not remain will be described. An example in which the cap semiconductor layer 62 remains will be described as a modified example of this embodiment.

[0049] Next, the cap semiconductor layer 62 is removed (FIG. 12). The cap semiconductor layer 62 is removed by, for example, CMP. In this embodiment, parts of the channel semiconductor layer 53, the memory insulating film 52, the insulating film 61, etc. are also removed by this CMP. FIG. 12 shows the columnar portions CL formed in each memory hole H1 (FIG. 6).

[0050] Next, slits (not shown) are formed in the laminated film 51 by lithography and RIE, and the sacrificial layer 51a' is removed by wet etching through the slits (FIG. 13). As a result, a plurality of cavities H2 are formed in the laminated film 51'.

[0051] Next, a plurality of electrode layers 51a are formed in the plurality of cavities H2 (FIG. 14). As a result, a stacked film 51 including a plurality of electrode layers 51a and a plurality of insulating films 51b alternately is formed above the substrate 61. In this manner, the memory cell array 11 shown in FIG. 3 is formed.

[0052] 15 and 16 are cross-sectional views showing a method for manufacturing a semiconductor device according to a modification of the first embodiment.

[0053] 5 to 11 are performed, but the process shown in FIG. 12 is not performed. Next, the sacrificial layer 51a' is removed (FIG. 15) in the same manner as in the process shown in FIG. 13, and the electrode layer 51a is formed (FIG. 16) in the same manner as in the process shown in FIG. 14. As a result, a stacked film 51 including a plurality of electrode layers 51a and a plurality of insulating films 51b is formed with the cap semiconductor layer 62 remaining. In this manner, the memory cell array 11 shown in FIG. 3 is formed.

[0054] The cap semiconductor layer 62 is used, for example, as a wiring layer. The cap semiconductor layer 62 may be thinned (i.e., partially removed) after the step shown in Fig. 11. For example, when the cap semiconductor layer 62 is used as a wiring layer, the cap semiconductor layer 62 may be thinned so that the thickness of the cap semiconductor layer 62 becomes a thickness suitable for use as a wiring layer.

[0055] 17 to 19 are cross-sectional views showing a method for manufacturing a semiconductor device as a comparative example of the first embodiment.

[0056] In this comparative example, the steps shown in FIGS. 5 to 7 are first performed. However, in the step shown in FIG. 7, a getter layer 71 is formed instead of the getter layer 63. FIG. 17 shows an array wafer W1 including a getter layer 71 instead of the getter layer 63. The getter layer 71 is, for example, an N-doped Si layer containing N (nitrogen) atoms. The getter layer 71 is formed as an amorphous layer 71a in FIG. 17. The amorphous layer 71a is, for example, an amorphous silicon layer.

[0057] Next, the channel semiconductor layer 53, the cap semiconductor layer 62, the getter layer 71, and the like are annealed (FIG. 18). This allows at least some of the metal atoms M in the channel semiconductor layer 53 and the cap semiconductor layer 62 to migrate into the getter layer 71 (FIG. 18). During this annealing, the getter layer 71 changes from an amorphous layer 71a to a crystallized layer 71b. The crystallized layer 71b is, for example, a polysilicon layer. FIG. 18 shows a plurality of crystal grains G2 contained in the crystallized layer 71b.

[0058] Next, the getter layer 71 is removed (FIG. 19). The getter layer 71 is removed using a chemical solution such as phosphoric acid. According to the process shown in FIG. 19, the metal atoms M that have migrated from the channel semiconductor layer 53 and the cap semiconductor layer 62 into the getter layer 71 are removed. The subsequent processes of this comparative example are performed in the same manner as in the first embodiment or its modified example.

[0059] The getter layer 71 in this comparative example is a Si layer, similar to the channel semiconductor layer 53 and the cap semiconductor layer 62. Therefore, it is difficult to selectively remove the getter layer 71 from among the channel semiconductor layer 53, the cap semiconductor layer 62, and the getter layer 71. The getter layer 71 in this comparative example is removed using a chemical solution such as phosphoric acid. During this process, the surface of the cap semiconductor layer 62 may be damaged by the chemical solution. FIG. 19 schematically illustrates the appearance of irregularities on the surface of the cap semiconductor layer 62 when the getter layer 71 is removed using the chemical solution. Such irregularities may occur, for example, near regions where metal atoms M were present at a high concentration. Damage to the cap semiconductor layer 62 or the channel semiconductor layer 53 may result in leakage current and reduced yields in the semiconductor device.

[0060] On the other hand, the getter layer 63 of this embodiment is a layer other than a Si layer. Therefore, this embodiment makes it possible to suppress such leakage current and yield reduction. Furthermore, this embodiment makes it possible to easily remove the getter layer 63, thereby reducing the number of manufacturing steps for the semiconductor device and improving the productivity of the semiconductor device, for example.

[0061] 9 are absorbed by the surface of the getter layer 63 to form a metal layer 64. Therefore, it is considered that the C layer (getter layer 63) has the same or higher ability to absorb the metal atoms M from the channel semiconductor layer 53 and the cap semiconductor layer 62 as the Si layer (getter layer 71).

[0062] As described above, in this embodiment, the getter layer 63 is a layer other than a Si layer, for example, a C layer or a Ge layer. Therefore, according to this embodiment, the getter layer 63 can be suitably removed.

[0063] (Second embodiment) 20 to 26 are cross-sectional views showing a method for manufacturing the semiconductor device of the second embodiment.

[0064] In this embodiment, the processes shown in FIGS. 5 to 7 are first performed. However, in the process shown in FIG. 7, the process of forming the core insulating film 54 and the cap semiconductor layer 62 is omitted. As a result, the memory insulating film 52, the channel semiconductor layer 53, and the getter layer 63 are formed in this order on the side surfaces of the stacked film 51 and the insulating film 61 in each memory hole H1 (FIG. 20). In FIG. 20, the memory insulating film 52, the channel semiconductor layer 53, and the getter layer 63 are further formed in this order on the upper surface of the insulating film 61. The getter layer 63 of this embodiment may include voids V in at least one of the memory holes H1, similar to the core insulating film 54 of the first embodiment.

[0065] The details of the getter layer 63 and the amorphous layer 63a of this embodiment are similar to those of the getter layer 63 and the amorphous layer 63a of the first embodiment. However, in this embodiment, the steps of forming the core insulating film 54 and the cap semiconductor layer 62 are omitted, so that the lower surface and side surfaces of the getter layer 63 are in contact with the upper surface and side surfaces of the channel semiconductor layer 53. Therefore, it is desirable that the getter layer 63 of this embodiment be formed on the channel semiconductor layer 53 so that no unnecessary film (for example, an SiO2 film or an SiN film) is interposed between the channel semiconductor layer 53 and the getter layer 63.

[0066] Next, the channel semiconductor layer 53, the getter layer 63, and the like are annealed (FIG. 21). This allows at least some of the metal atoms M in the channel semiconductor layer 53 to migrate into the getter layer 63 (FIG. 21), and further allows all or some of these metal atoms M to migrate to the surface (upper surface) of the getter layer 63 (FIG. 22). In FIG. 22, the metal atoms M migrate to the surface of the getter layer 63 and form a metal layer 64 containing the metal atoms M. In this embodiment, the metal layer 64 is formed on the surface of the getter layer 63 during the annealing shown in FIGS. 21 and 22. As a result, at least some of the metal atoms M in the channel semiconductor layer 53 are removed from the channel semiconductor layer 53, and the concentration of the metal atoms M in the channel semiconductor layer 53 decreases.

[0067] The getter layer 63 changes from an amorphous layer 63a to a crystallized layer 63b during the annealing shown in Figures 21 and 22. The details of the crystallized layer 63b in this embodiment are similar to those of the crystallized layer 63b in the first embodiment. The details of the annealing shown in Figures 21 and 22 are similar to those of the annealing shown in Figures 8 and 9.

[0068] Next, the metal layer 64 is removed (FIG. 23). The process shown in FIG. 23 is performed in the same manner as the process shown in FIG.

[0069] Next, the getter layer 63 is removed (FIG. 24). The process shown in FIG. 24 is performed in the same manner as the process shown in FIG.

[0070] According to this embodiment, by using a layer other than a Si layer for the getter layer 63, it is possible to preferably remove the getter layer 63. For example, if the channel semiconductor layer 53 and the getter layer 63 were both Si layers, there is a risk that the channel semiconductor layer 53 would also be removed during the process of removing the getter layer 63. According to this embodiment, by using a Si layer for the channel semiconductor layer 53 and a layer other than a Si layer for the getter layer 63, it is possible to easily remove the getter layer 63 while leaving the channel semiconductor layer 53. Furthermore, if the channel semiconductor layer 53 and the getter layer 63 were both Si layers, there is a risk that the process of removing the getter layer 63 would damage the channel semiconductor layer 53, as described in the first embodiment. For example, unevenness as shown in FIG. 19 may occur on the surface of the channel semiconductor layer 53. According to this embodiment, by using a Si layer for the channel semiconductor layer 53 and a layer other than a Si layer for the getter layer 63, it is possible to suppress such damage.

[0071] Next, a core insulating film 54 is formed over the entire surface of the substrate 16 (FIG. 25). As a result, the core insulating film 54 is formed in each memory hole H1 on the side surfaces of the stacked film 51 and insulating film 61 with the memory insulating film 52 and channel semiconductor layer 53 interposed therebetween. In FIG. 25, the core insulating film 54 is further formed on the upper surface of the insulating film 61 with the memory insulating film 52 and channel semiconductor layer 53 interposed therebetween. FIG. 25 further shows a void V formed in the core insulating film 54.

[0072] Next, the surface of the core insulating film 54 is planarized by CMP (FIG. 26). As a result, the core insulating film 54 outside the memory holes H1 is removed. In this embodiment, parts of the channel semiconductor layer 53, memory insulating film 52, insulating film 61, etc. are also removed by this CMP. FIG. 26 shows the columnar portions CL formed in each memory hole H1. The subsequent steps of this embodiment are performed in the same manner as in the first embodiment.

[0073] In this embodiment, a cap semiconductor layer 62 may be formed on the channel semiconductor layer 53 in any step after removing the getter layer 63. This cap semiconductor layer 62 may be used as, for example, a wiring layer.

[0074] As described above, in this embodiment, the getter layer 63 is a layer other than a Si layer, for example, a C layer or a Ge layer. Therefore, according to this embodiment, like the first embodiment, it is possible to preferably remove the getter layer 63.

[0075] Here, the first embodiment and the second embodiment are compared. According to the second embodiment, the getter layer 63 is disposed near the channel semiconductor layer 53, which makes it possible to easily remove the metal atoms M from the channel semiconductor layer 53. On the other hand, if voids V are formed in the getter layer 63 of the second embodiment, these voids V may hinder the movement of the metal atoms M within the getter layer 63. This is likely to be a problem when the aspect ratio of each memory hole H1 is high. According to the first embodiment, it is possible to avoid such problems caused by the voids V.

[0076] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the form of the method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0077] 1: Array chip, 2: Circuit chip, 11: memory cell array, 12: insulating film, 13: interlayer insulating film, 14: interlayer insulating film, 15: substrate, 16: substrate, 21: staircase structure portion, 22: beam portion, 23: contact plug, 24: word wiring layer, 25: via plug, 31: transistor, 31a: gate insulating film, 31b: gate electrode, 32: contact plug, 33: wiring layer, 34: wiring layer, 35: wiring layer, 36: via plug, 37: metal pad, 41: metal pad, 42: via plug, 43: wiring layer, 44: wiring layer, 45: via plug, 46: metal pad, 47: passivation insulating film, 51: laminated film, 51a: electrode layer, 51a': sacrificial layer, 51b: insulating film, 52: memory insulating film, 52a: block insulating film, 52b: charge storage layer, 52c: tunnel insulating film, 53: channel semiconductor layer, 54: core insulating film, 61: insulating film, 62: cap semiconductor layer, 63: getter layer, 63a: amorphous layer, 63b: crystallized layer, 64: metal layer, 71: getter layer, 71a: amorphous layer, 71b: crystallized layer

Claims

1. forming a semiconductor layer containing a plurality of metal atoms; forming a first layer other than a Si (silicon) layer on the semiconductor layer as a layer containing a main component element different from a main component element in the semiconductor layer; transferring at least some of the metal atoms in the semiconductor layer to the interior or surface of the first layer; After the at least some of the metal atoms have been transferred to the interior or surface of the first layer, the first layer and the at least some of the metal atoms are removed. A method for manufacturing a semiconductor device, comprising:

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the semiconductor layer is a Si layer.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein the semiconductor layer includes a channel semiconductor layer.

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first layer contains C (carbon) or Ge (germanium).

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the first layer further contains B (boron), P (phosphorus), As (arsenic), N (nitrogen), O (oxygen), or Si.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein said first layer contains C (carbon) or Ge (germanium) as said main component element.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the first layer further contains an impurity element selected from the group consisting of B (boron), P (phosphorus), As (arsenic), N (nitrogen), O (oxygen), and Si.

8. The first layer has SiO between the semiconductor layer and the first layer. ２ 2. The method for manufacturing a semiconductor device according to claim 1, wherein a silicon oxide film and a silicon nitride film are formed on said semiconductor layer so as not to intervene.

9. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the metal atom is a Ni (nickel) atom, a Co (cobalt) atom, a Mn (manganese) atom, a Ti (titanium) atom, a Cr (chromium) atom, a Ru (ruthenium) atom, an Ir (iridium) atom, a Pd (palladium) atom, an Fe (iron) atom, or a Pt (platinum) atom.

10. 2. The method for manufacturing a semiconductor device according to claim 1, wherein at least some of the metal atoms in the semiconductor layer are transferred to the interior or surface of the first layer by annealing the semiconductor layer.

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the annealing of the semiconductor layer is performed at a temperature of 300° C. to 1200° C.

12. The method for manufacturing a semiconductor device according to claim 10 , wherein the annealing of the semiconductor layer is performed in an atmosphere containing an inert gas.

13. The annealing of the semiconductor layer is performed using Ar (argon) gas, Ne (neon) gas, Xe (xenon) gas, N ２ (Nitrogen) gas, H ２ (hydrogen) gas, or D ２ The method for manufacturing a semiconductor device according to claim 10, wherein the method is carried out in an atmosphere containing (deuterium) gas.

14. The method of manufacturing a semiconductor device according to claim 10 , wherein the first layer changes from an amorphous layer to a crystallized layer during the annealing of the semiconductor layer.

15. The method for manufacturing a semiconductor device according to claim 10 , wherein a metal layer containing at least some of the metal atoms is formed on a surface of the first layer during the annealing of the semiconductor layer.

16. 16. The method for manufacturing a semiconductor device according to claim 15, wherein the first layer contains C (carbon) as the main component element.

17. The method for manufacturing a semiconductor device according to claim 15, wherein the first layer is removed after the metal layer is removed.

18. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the first layer is removed by oxidizing or ashing the first layer.

19. forming a semiconductor layer containing a plurality of metal atoms; forming a first layer containing C (carbon) or Ge (germanium) on the semiconductor layer; transferring at least some of the metal atoms in the semiconductor layer to the interior or surface of the first layer; After the at least some of the metal atoms have been transferred to the interior or surface of the first layer, the first layer and the at least some of the metal atoms are removed. A method for manufacturing a semiconductor device, comprising:

20. 20. The method for manufacturing a semiconductor device according to claim 18, wherein the first layer contains C or Ge as a main component element.

Images