Semiconductor device

Abstract

To provide a semiconductor device that suppresses inrush current during initial charging, shortens initial charging time, and suppresses drive voltage fluctuations.SOLUTION: A low-phase power supply VccL outputs a low-phase side drive voltage VL. A low-phase drive control circuit 1b receives the low-phase drive voltage VL and controls the drive of a low-phase switching element 2b. A bootstrap circuit 1c discharges the charge based on a charging current Ib flowing from the low-phase power supply VccL when the low-phase switching element 2b is turned on by the drive control of the low-phase drive control circuit 1b. An upper-phase drive control circuit 1a includes a charge current limiting circuit 1a1 that limits the charging current Ib flowing from the low-phase power supply VccL to the bootstrap circuit 1c according to the voltage level of a charge voltage Vchg, and performs the drive control of an upper-phase switching element 2a by receiving an upper-phase side drive voltage VH when the charge voltage Vchg is established.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In a semiconductor device including an IPM (Intelligent Power Module) incorporating a switching element that is a power semiconductor, a bootstrap circuit is used for a drive voltage for driving the gate of the switching element on the upper phase side.

[0003] As related art, for example, a power conversion device has been proposed that includes a charge / discharge resistor that suppresses inrush current when precharging of a smoothing capacitor starts and discharges charge when discharging starts (Patent Document 1). Also, a power supply control device has been proposed that limits current to prevent inrush current by using the on-resistance of a turned-on semiconductor switching element for a predetermined period immediately after power-on (Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-107045 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-44914 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device that suppresses inrush current during initial charging, shortens the initial charging time, and suppresses fluctuations in driving voltage. [Means for solving the problem]

[0006] To solve the above problems, a semiconductor device is provided that includes an upper-phase switching element, a lower-phase switching element connected in series to the upper-phase switching element, a lower-phase power supply that outputs a lower-phase drive voltage, a lower-phase drive control circuit that receives the lower-phase drive voltage and controls the drive of the lower-phase switching element, a bootstrap circuit that generates a charge voltage from electric charge stored by a charge current flowing from the lower-phase power supply when the lower-phase switching element is turned on by drive control of the low-phase drive control circuit, and an upper-phase drive control circuit that receives the charge voltage as the upper-phase drive voltage and controls the drive of the upper-phase switching element, the upper-phase drive control circuit including a charge current limiting circuit that limits the charge current flowing from the low-phase power supply to the bootstrap circuit in accordance with the voltage level of the charge voltage. [Effects of the Invention]

[0007] According to one aspect, it is possible to suppress inrush current during initial charging, shorten the initial charging time, and suppress fluctuations in driving voltage. [Brief explanation of the drawings]

[0008] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device. [Figure 2] FIG. 1 is a diagram illustrating an example of the overall configuration of a semiconductor device according to a reference example. [Figure 3] FIG. 10 is a diagram for explaining the operation of the bootstrap circuit during initial charging. [Figure 4] FIG. 10 is a diagram showing an example of a waveform of a charging current during initial charging. [Figure 5] FIG. 10 is a diagram showing an example of a waveform of a charging voltage during initial charging. [Figure 6] FIG. 10 is a diagram illustrating a state when the direction of the load current flowing during PWM operation is negative. [Figure 7] FIG. 10 is a diagram illustrating a state when the direction of the load current flowing during PWM operation is positive. [Figure 8] 10 is a diagram for explaining fluctuations in the upper phase drive voltage during PWM operation. FIG. [Figure 9]1 is a diagram showing an example of the overall configuration of a semiconductor device according to an embodiment of the present invention; [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of an LVIC and a bootstrap circuit on the upper phase side. [Figure 11] FIG. 10 is a diagram illustrating an example of the operation of the charging current limiting circuit at the start of initial charging. [Figure 12] 10 is a diagram showing an example of the operation of the charging current limiting circuit when the charging voltage during initial charging reaches or exceeds a predetermined level. FIG. [Figure 13] FIG. 10 is a diagram showing an example of a waveform of a charging current during initial charging. [Figure 14] FIG. 10 is a diagram showing an example of a waveform of a charging voltage during initial charging. [Figure 15] 10 is a diagram for explaining fluctuations in the upper phase drive voltage during PWM operation. FIG. [Figure 16] 10A and 10B are diagrams illustrating a modified example of the configuration of the semiconductor device according to the present embodiment. [Figure 17] FIG. 10 is a diagram illustrating an example of the operation of the charging current limiting circuit at the start of initial charging. [Figure 18] 10 is a diagram showing an example of the operation of the charging current limiting circuit when the charging voltage during initial charging reaches or exceeds a predetermined level. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the present embodiment will be described with reference to the drawings. In this specification and the drawings, elements having substantially the same configuration are designated by the same reference numerals, and redundant description may be omitted.

[0010] 1 is a diagram illustrating an example of a semiconductor device. The semiconductor device 1 includes an upper-phase switching element 2a, a lower-phase switching element 2b, an upper-phase drive control circuit 1a, a lower-phase drive control circuit 1b, a bootstrap circuit 1c, and a lower-phase power supply VccL. The upper-phase drive control circuit 1a includes a charging current limiting circuit 1a1.

[0011] The upper-phase switching element 2a and the lower-phase switching element 2b are connected in series. The high-potential main terminal of the upper-phase switching element 2a is connected to the positive terminal P, and the low-potential main terminal of the upper-phase switching element 2a is connected to the output terminal OUT, the reference potential terminal of the upper-phase drive control circuit 1a, the reference potential terminal of the bootstrap circuit 1c, and the high-potential main terminal of the lower-phase switching element 2b. The low-potential main terminal of the lower-phase switching element 2b is connected to the negative terminal N, the reference potential terminal of the lower-phase drive control circuit 1b, and the negative terminal of the lower-phase power supply VccL.

[0012] Here, the low-phase power supply VccL outputs a low-phase drive voltage VL. The low-phase drive control circuit 1b receives the low-phase drive voltage VL and controls the drive of the low-phase switching element 2b based on a switching drive signal input via the low-phase input terminal IN2.

[0013] In addition, when the lower-phase switching element 2b is turned on by the drive control of the lower-phase drive control circuit 1b, the charging current Ib flows in the following order: the positive terminal of the lower-phase power supply VccL, the bootstrap circuit 1c, the charging current limiting circuit 1a1, the bootstrap circuit 1c, the high-potential main terminal of the lower-phase switching element 2b, the low-potential main terminal, and the negative terminal of the lower-phase power supply VccL.

[0014] The bootstrap circuit 1c generates a charging voltage Vchg from the charge stored in the bootstrap circuit 1c based on the charging current Ib flowing from the low-phase power supply VccL. The charging current limiting circuit 1a1 limits the charging current Ib flowing from the low-phase power supply VccL to the bootstrap circuit 1c according to the voltage level of the charging voltage Vchg.

[0015] The upper-phase drive control circuit 1a receives the charging voltage Vchg discharged from the bootstrap circuit 1c as the upper-phase drive voltage VH, and controls the drive of the upper-phase switching element 2a.

[0016] In this way, the semiconductor device 1 has a configuration in which the charging current Ib flowing from the low-phase power supply VccL to the bootstrap circuit 1c is limited according to the voltage level of the charging voltage Vchg, thereby making it possible to suppress the generation of a large charging current (inrush current) during initial charging, as well as shortening the initial charging time and suppressing fluctuations in the upper-phase drive voltage.

[0017] Next, a semiconductor device according to a reference example will be described with reference to Fig. 2 to Fig. 8. Fig. 2 is a diagram showing an example of the overall configuration of a semiconductor device according to a reference example. The semiconductor device 100 includes a semiconductor module 110 and a power supply unit 120.

[0018] The semiconductor module 110 includes LVICs (Low Voltage ICs) 11U, 11V, 11W, and 12 and semiconductor chips 1U, 1V, 1W, 1X, 1Y, and 1Z, and has the function of an IPM.

[0019] The LVIC 11U and semiconductor chip 1U are arranged in the U phase on the upper phase (high side), the LVIC 11V and semiconductor chip 1V are arranged in the V phase on the upper phase, and the LVIC 11W and semiconductor chip 1W are arranged in the W phase on the upper phase.

[0020] The LVIC 12 is arranged on the lower phase (low side). The semiconductor chip 1X is arranged on the X phase of the lower phase side, the semiconductor chip 1Y is arranged on the Y phase of the lower phase side, and the semiconductor chip 1Z is arranged on the Z phase of the lower phase side.

[0021] In this way, the semiconductor device 100 has a configuration in which LVICs 11U, 11V, and 11W are arranged as gate drivers for driving the upper-phase semiconductor chips 1U, 1V, and 1W, respectively, and LVIC 12 is arranged as a gate driver for driving the lower-phase semiconductor chips 1X, 1Y, and 1Z.

[0022] The semiconductor chip 1U includes a U-phase switching element 13a and a free wheel diode (FWD) 13b connected in anti-parallel to the U-phase switching element 13a. The semiconductor chip 1V includes a V-phase switching element 14a and a free wheel diode (FWD) 14b connected in anti-parallel to the V-phase switching element 14a. The semiconductor chip 1W includes a W-phase switching element 15a and a free wheel diode (FWD) 15b connected in anti-parallel to the W-phase switching element 15a.

[0023] The semiconductor chip 1X includes an X-phase switching element 16a and an FWD 16b connected in anti-parallel to the X-phase switching element 16a. The semiconductor chip 1Y includes a Y-phase switching element 17a and an FWD 17b connected in anti-parallel to the Y-phase switching element 17a. The semiconductor chip 1Z includes a Z-phase switching element 18a and an FWD 18b connected in anti-parallel to the Z-phase switching element 18a.

[0024] U-phase switching element 13a, V-phase switching element 14a, W-phase switching element 15a, X-phase switching element 16a, Y-phase switching element 17a, and Z-phase switching element 18a are voltage-driven switching elements and are IGBTs (Insulated Gate Bipolar Transistors), or may be power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) instead of IGBTs.

[0025] Furthermore, FWDs 13b, 14b, 15b, 16b, 17b, and 18b are freewheeling diodes that circulate the load current. When U-phase switching element 13a, V-phase switching element 14a, W-phase switching element 15a, X-phase switching element 16a, Y-phase switching element 17a, and Z-phase switching element 18a are power MOSFETs, the FWDs may be realized by parasitic diodes.

[0026] The semiconductor module 110 has, as upper phase side terminals, terminal VccU (U-phase drive power supply terminal), terminal VccV (V-phase drive power supply terminal), terminal VccW (W-phase drive power supply terminal), terminal VinU (U-phase input terminal), terminal VinV (V-phase input terminal), terminal VinW (W-phase input terminal), terminal GNDU (U-phase GND terminal), terminal GNDV (V-phase GND terminal), and terminal GNDW (W-phase GND terminal).

[0027] The lower phase terminals include a terminal Vcc, a terminal VinX (X-phase input terminal), a terminal VinY (Y-phase input terminal), a terminal VinZ (Z-phase input terminal), and a terminal GND. The semiconductor module 110 also includes a positive terminal P, a negative terminal N, an output terminal U, an output terminal V, and an output terminal W.

[0028] The collectors of the U-phase switching element 13a, the V-phase switching element 14a, and the W-phase switching element 15a are connected to the positive terminal P. A node n1, at which the emitter of the U-phase switching element 13a and the collector of the X-phase switching element 16a are connected, is connected to the terminal GNDU, the reference potential end of the LVIC 11U, and the output terminal U.

[0029] A node n2, at which the emitter of the V-phase switching element 14a and the collector of the Y-phase switching element 17a are connected, is connected to the terminal GNDV, the reference potential end of the LVIC 11V, and the output terminal V.

[0030] A node n3, at which the emitter of the W-phase switching element 15a and the collector of the Z-phase switching element 18a are connected, is connected to the terminal GNDW, the reference potential end of the LVIC 11W, and the output terminal W.

[0031] A node n4, to which the emitter of the X-phase switching element 16a, the emitter of the Y-phase switching element 17a, and the emitter of the Z-phase switching element 18a are connected, is connected to the terminal GND, the reference potential end of the LVIC 12, and the negative terminal N.

[0032] On the other hand, the power supply unit 120 includes a lower-phase power supply VccL, bootstrap (BS) circuits 21U, 21V, and 21W, and a smoothing capacitor C0. The bootstrap circuit 21U is arranged in the U-phase on the upper phase side, the bootstrap circuit 21V is arranged in the V-phase on the upper phase side, and the bootstrap circuit 21W is arranged in the W-phase on the upper phase side. The lower-phase power supply VccL and smoothing capacitor C0 are arranged on the lower phase side.

[0033] The positive terminal of the low-phase power supply VccL is connected to the terminal Vcc, one end of the smoothing capacitor C0, and the first terminal p1 of each of the bootstrap circuits 21U, 21V, and 21W. The first terminal p1 is a terminal through which a charging current is input during initial charging. The negative terminal of the low-phase power supply VccL is connected to the other end of the smoothing capacitor C0 and the terminal GND.

[0034] The second terminal p2 of the bootstrap circuit 21U is connected to the terminal VccU, the second terminal p2 of the bootstrap circuit 21V is connected to the terminal VccV, and the second terminal p2 of the bootstrap circuit 21W is connected to the terminal VccW. The second terminal p2 is a terminal through which a charging current is input and a charging voltage is discharged.

[0035] The reference potential end gd of the bootstrap circuit 21U is connected to the terminal GNDU, the reference potential end gd of the bootstrap circuit 21V is connected to the terminal GNDV, and the reference potential end gd of the bootstrap circuit 21W is connected to the terminal GNDW.

[0036] The bootstrap circuit 21U generates a drive voltage (upper-phase drive voltage) for driving the gate of the U-phase switching element 13a based on the power supply voltage (lower-phase drive voltage) output from the lower-phase power supply VccL, and supplies the drive voltage to the LVIC 11U via a terminal VccU. The LVIC 11U receives a U-phase drive signal transmitted from a control unit (not shown), such as a microcomputer, via a terminal VinU, and drives (turns on / off) the U-phase switching element 13a based on the U-phase drive signal.

[0037] The bootstrap circuit 21V generates a drive voltage for driving the gate of the V-phase switching element 14a based on the power supply voltage output from the low-phase power supply VccL and supplies the drive voltage to the LVIC 11V via the terminal VccV. The LVIC 11V receives a V-phase drive signal transmitted from the control unit via the terminal VinV and drives the V-phase switching element 14a based on the V-phase drive signal.

[0038] Furthermore, the bootstrap circuit 21W generates a drive voltage for driving the gate of the W-phase switching element 15a based on the power supply voltage output from the low-phase power supply VccL and supplies the drive voltage to the LVIC 11W via the terminal VccW. The LVIC 11W receives a W-phase drive signal transmitted from the control unit via the terminal VinW and drives the W-phase switching element 15a based on the W-phase drive signal.

[0039] On the other hand, the LVIC 12 uses the power supply voltage of the low-phase power supply VccL as the drive voltage for driving the gates of the X-phase switching element 16a, the Y-phase switching element 17a, and the Z-phase switching element 18a. The LVIC 12 receives an X-phase drive signal transmitted from the control unit via the terminal VinX, and drives the X-phase switching element 16a based on the X-phase drive signal.

[0040] Similarly, the LVIC 12 receives a Y-phase drive signal transmitted from the control unit via a terminal VinY and drives the Y-phase switching element 17a based on the Y-phase drive signal, and also receives a Z-phase drive signal transmitted from the control unit via a terminal VinZ and drives the Z-phase switching element 18a based on the Z-phase drive signal.

[0041] In this way, the semiconductor device 100 uses bootstrap circuits 21U, 21V, and 21W as power supplies on the upper phase side, and each of the bootstrap circuits 21U, 21V, and 21W is configured with a diode, a capacitor, and a limiting resistor (the internal circuit configuration will be described later). Therefore, the configuration of the semiconductor device 100 can reduce the component mounting scale compared to a configuration in which a power supply is provided for each of the U phase, V phase, and W phase.

[0042] Next, the operation of the bootstrap circuit during initial charging of the semiconductor device 100 will be described with reference to Figures 3 to 5. Note that the bootstrap circuit has the same circuit configuration and operation for the U-phase, V-phase, and W-phase, so the following description will be focused on the U-phase.

[0043] 3 is a diagram for explaining the operation of the bootstrap circuit during initial charging. The bootstrap circuit 21U includes a diode Db, a capacitor Cb, and a limiting resistor Rb.

[0044] One end of limiting resistor Rb is connected to the positive terminal of low-phase power supply VccL, one end of smoothing capacitor C0, and terminal Vcc. The other end of limiting resistor Rb is connected to the anode of diode Db. The cathode of diode Db is connected to one end of capacitor Cb and terminal VccU. The other end of capacitor Cb is connected to terminal GNDU. In bootstrap circuit 21U configured as above, the following operation is performed during initial charging.

[0045] [Step S11] The LVIC 12 turns on the X-phase switching element 16a based on the X-phase drive signal input via the terminal VinX. [Step S12] When the X-phase switching element 16a is turned on, the other end of the capacitor Cb is connected to the negative terminal of the low-phase power supply VccL via the terminals GNDU and GND. As a result, a charging current Ib flows in the following order: the positive terminal of the low-phase power supply VccL, the limiting resistor Rb, the anode to cathode of the diode Db, the collector to emitter of the X-phase switching element 16a, and the negative terminal of the low-phase power supply VccL.

[0046] [Step S13] The charging current Ib flows, and the capacitor Cb is charged. [Step S14] The charge stored in capacitor Cb is discharged, and the resulting charging voltage is applied to the LVIC 11U via terminal VccU. The upper-phase drive voltage VH, established when the charging voltage is established, is used as the gate drive voltage for the LVIC 11U. The lower-phase drive voltage VL output from the lower-phase power supply VccL is supplied as the gate drive voltage for the LVIC 12.

[0047] 4 is a diagram showing an example of the waveform of the charging current during initial charging, where the vertical axis represents the charging current Ib and the horizontal axis represents time. [Section t1] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing to turn on the X-phase switching element 16a, it turns on the X-phase switching element 16a.

[0048] At this time, as described above, the charging current Ib flows to the capacitor Cb, but because the capacitor Cb is in an uncharged state and has no charge, a large current (inrush current Ibmax) flows through the capacitor Cb. However, because the bootstrap circuit 21U is provided with a limiting resistor Rb for suppressing the inrush current, the peak value of the inrush current Ibmax is suppressed so as not to exceed the rated current value Ir.

[0049] [Section t2] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing it to turn off the X-phase switching element 16a, it turns off the X-phase switching element 16a. At this time, the other end of the capacitor Cb is not electrically connected to the negative terminal of the low-phase power supply VccL, so that the charging current Ib does not flow.

[0050] [Section t3] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing it to turn on the X-phase switching element 16a, it turns on the X-phase switching element 16a. In this case, the charging current Ib flows to the capacitor Cb, but because the charge accumulated in the capacitor Cb during section t1 has accumulated, the peak value of the charging current Ib flowing to the capacitor Cb during section t3 is smaller than the peak value of the charging current Ib flowing to the capacitor Cb during section t1.

[0051] [Section t4] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing it to turn off the X-phase switching element 16a, it turns off the X-phase switching element 16a. At this time, the other end of the capacitor Cb is not electrically connected to the negative terminal of the low-phase power supply VccL, so that the charging current Ib does not flow.

[0052] The same operation is repeated until the capacitor Cb is fully charged. When the capacitor Cb is fully charged after a charging time tb1, the initial charging ends and the system enters the operational state.

[0053] In this way, in the initial charging operation, the X-phase switching element 16a (lower-phase IGBT) is turned on / off to charge the capacitor Cb (capacitor of the upper-phase bootstrap circuit) in the bootstrap circuit 21U.

[0054] In this case, when no charge has accumulated in the capacitor Cb, the charging current Ib flows into the capacitor Cb at a maximum current value of inrush current Ibmax, and as the capacitor Cb is charged, the value of the charging current Ib decreases.

[0055] Figure 5 shows an example of the waveform of the charging voltage during initial charging. The vertical axis represents the charging voltage Vchg, and the horizontal axis represents time. As the charging current Ib flows to the capacitor Cb, the capacitor Cb gradually accumulates charge, and the charging voltage Vchg discharged from the capacitor Cb also rises.

[0056] Then, the charging voltage Vchg reaches a certain voltage value (upper phase drive voltage VH) after the charging time tb1 from the start of charging of capacitor Cb until the charging is completed, and the initial charging state ends and the device transitions to an operating state.

[0057] As the charging current Ib increases, the charging speed of the capacitor Cb increases, and the charging time tb1 decreases; as the charging current Ib decreases, the charging speed decreases, and the charging time tb1 increases.

[0058] Next, the operation of the bootstrap circuit during PWM (Pulse Width Modulation) operation will be described with reference to Figures 6 to 8. When the initial charging is completed, the semiconductor device 100 transitions to an operating state and performs power control by PWM of the switching elements.

[0059] 6 is a diagram showing a state when the direction of the load current flowing during PWM operation is negative. A load 3a and a power supply Vccm are connected to the semiconductor module 110. The load 3a is an inductive load such as a motor, and includes an inductor La and a variable resistor RXa. One end of the inductor La is connected to the positive terminal P and the positive terminal of the power supply Vccm, and the other end of the inductor La is connected to one end of the variable resistor RXa. The other end of the variable resistor RXa is connected to the output terminal U. The negative terminal of the power supply Vccm is connected to the negative terminal N.

[0060] In this circuit configuration, when the X-phase switching element 16a is turned on, the charging current Ib flows in the direction as described above in Fig. 3. Furthermore, when the X-phase switching element 16a is turned on and the load current IL flowing from the load 3a becomes negative, the load current IL flows in the following order: load 3a, output terminal U, the collector to emitter of the X-phase switching element 16a, and negative terminal N.

[0061] In this manner, in the operation mode in which the load current IL flows in the negative direction (hereinafter referred to as mode m1), the upper phase drive voltage VH applied to the terminal VccU is calculated by the following equation (1). VH=VL-V FBD -Rb×Ib-V CE(sat) ···(1) In the parameters of equation (1), VL is the voltage of the lower phase power supply VccL (lower phase drive voltage), V FBD is the forward voltage of the diode Db, Rb is the resistance of the limiting resistor Rb, Ib is the current value of the charging current, V CE(sat) is the collector-emitter saturation voltage when a load current IL flows through the X-phase switching element 16a.

[0062] The direction from the negative terminal to the positive terminal of the low-phase power supply VccL is positive, and the low-phase drive voltage VL is positive. Therefore, when the charging current Ib flows in the direction of the arrow in the figure, the voltage (Rb × Ib) applied to the limiting resistor Rb is negative relative to the low-phase drive voltage VL, and the forward voltage V of the diode Db is FBD Furthermore, in mode m1, the load current IL flows from the collector to the emitter of the X-phase switching element 16a, so that V CE(sat) will be negative.

[0063] 7 is a diagram showing a state when the direction of the load current flowing during PWM operation is positive. A load 3b and a power supply Vccm are connected to the semiconductor module 110. The load 3b is an inductive load such as a motor, and includes an inductor Lb and a variable resistor RXb. One end of the inductor Lb is connected to the output terminal U, and the other end of the inductor Lb is connected to one end of the variable resistor RXb. The other end of the variable resistor RXb is connected to the negative terminal N and the negative terminal of the power supply Vccm. The positive terminal of the power supply Vccm is connected to the positive terminal P.

[0064] In such a circuit configuration, when the X-phase switching element 16a turns on, a charging current Ib flows in the direction as described above in FIG. 3. Also, when the X-phase switching element 16a turns on and the direction of the load current IL flowing from the load 3b becomes the positive direction, the load current IL flows in the order of the load 3b, the negative terminal N, from the anode to the cathode of FWD16b, the output terminal U, and the load 3b.

[0065] In the case of such an operation mode (hereinafter referred to as mode m2) where the direction of the load current IL becomes the positive direction, the upper-phase drive voltage VH applied to the terminal VccU is calculated by the following equation (2). VH = VL - V FBD -Rb×Ib + VF ···(2) Note that VF in Equation (2) is the forward voltage when the load current IL is flowing back through FWD16b. Also, in mode m2, since the load current IL flows from the anode to the cathode of FWD16b, VF becomes a positive value with respect to the lower-phase drive voltage VL.

[0066] Here, when the lower-phase drive voltage VL of the lower-phase power supply VccL is 15V, the upper-phase drive voltage VH in mode m1 becomes smaller than 15V (VH < 15V) from Equation (1). Also, when the lower-phase drive voltage VL is 15V and (V FBD +Rb×Ib) < VF, the upper-phase drive voltage VH in mode m2 becomes larger than 15V (VH > 15V) from Equation (2).

[0067] <​​​​​​[Section t12] This is the PWM operation in mode m1, where load current IL flows in the negative direction from load 3a to output terminal U. In this case, upper-phase drive voltage VH becomes larger in the negative direction than lower-phase drive voltage VL of the lower-phase power supply VccL by an amount corresponding to a fluctuation width w1. Thereafter, modes m1 and m2 are repeated in the same manner.

[0069] In this way, the upper phase drive voltage VH fluctuates depending on the operating mode, mode m1 or m2. Furthermore, from equations (1) and (2), it can be seen that the fluctuation width w1 of the upper phase drive voltage VH is highly dependent on the resistance value of the limiting resistor Rb, and the larger the resistance value of the limiting resistor Rb, the larger the fluctuation of the upper phase drive voltage VH, and the smaller the resistance value of the limiting resistor Rb, the smaller the fluctuation of the upper phase drive voltage VH.

[0070] As described above, the bootstrap circuit 21U includes a limiting resistor Rb, whose resistance is set so that the peak value of the inrush current during initial charging does not exceed the rated value. However, because the limiting resistor Rb has a fixed resistance, setting the limiting resistor Rb too high can result in a longer initial charging time and longer startup times. Furthermore, setting the limiting resistor Rb too high can result in larger fluctuations in the upper-phase drive voltage VH during PWM operation, resulting in unstable circuit operation.

[0071] On the other hand, if the resistance value of the limiting resistor Rb is reduced in order to shorten the charging time during initial charging and reduce the voltage fluctuation of the upper phase drive voltage VH, there is a possibility that the peak value of the inrush current will exceed the rated value.

[0072] In this way, in the semiconductor device 100 of the reference example, contradictory characteristics occur depending on the fixed resistance value set for the limiting resistor Rb, and the above-mentioned problems arise whether the resistance value is set large or small.

[0073] Although the above describes the problem with bootstrap circuit 21U arranged in the U phase on the upper phase side, the same problem occurs with bootstrap circuits 21V and 21W arranged in the V phase and W phase on the upper phase side, respectively.

[0074] Next, the semiconductor device of this embodiment will be described in detail. Fig. 9 is a diagram showing an example of the overall configuration of the semiconductor device of this embodiment. The semiconductor device 1-1 includes a semiconductor module 10-1 and a power supply unit 20. The semiconductor module 10-1 includes LVICs 11U-1, 11V-1, 11W-1, and 12 and semiconductor chips 1U, 1V, 1W, 1X, 1Y, and 1Z, and has an IPM function.

[0075] In addition, the semiconductor module 10-1 further has, as upper phase side terminals, a terminal VBSU (U-phase bootstrap input terminal), a terminal VBSV (V-phase bootstrap input terminal), and a terminal VBSW (W-phase bootstrap input terminal) in addition to the terminals described above in FIG. 2.

[0076] On the other hand, power supply unit 20 includes a lower-phase power supply VccL, bootstrap circuits 2U, 2V, and 2W, and a smoothing capacitor C0. Bootstrap circuit 2U is arranged in the U-phase on the upper phase side, bootstrap circuit 2V is arranged in the V-phase on the upper phase side, and bootstrap circuit 2W is arranged in the W-phase on the upper phase side. The lower-phase power supply VccL and smoothing capacitor C0 are arranged on the lower phase side.

[0077] The third terminal p3 of the bootstrap circuit 2U is connected to the terminal VBSU, the third terminal p3 of the bootstrap circuit 2V is connected to the terminal VBSV, and the third terminal p3 of the bootstrap circuit 2W is connected to the terminal VBSW. Note that other connections are the same as in Figure 2, so a description thereof will be omitted.

[0078] 10 shows an example of the configuration of the LVIC and bootstrap circuit on the upper phase side. Note that the circuit configuration and operation are the same for the U, V, and W phases, so the following explanation will focus on the LVIC 11U-1 and bootstrap circuit 2U located on the U phase side.

[0079] The LVIC 11U-1 in the semiconductor module 10-1 includes a charging current limiting unit 11a1 and an internal circuit 11b1. The charging current limiting unit 11a1 includes a comparator cmp1, a threshold voltage output source V0, a ​​switch sw0, a limiting resistor Rb1 (first limiting resistor), and a limiting resistor Rb2 (second limiting resistor). The internal circuit 11b1 includes circuits such as a gate driver that drives the U-phase switching element 13a using a drive signal received via a terminal VinU.

[0080] The bootstrap circuit 2U in the power supply unit 20 includes a diode Db and a capacitor Cb. In the semiconductor device 1-1, the bootstrap circuit 2U does not include a limiting resistor, and limiting resistors Rb1 and Rb2 are arranged inside the LVIC 11U-1.

[0081] Regarding the connection relationship of the components of the charging current limiting unit 11a1, the non-inverting input terminal (+) of the comparator cmp1 is connected to the terminal VccU, one end of the limiting resistor Rb1, one end of the limiting resistor Rb2, and the power supply voltage supply terminal of the internal circuit 11b1. The inverting input terminal (-) of the comparator cmp1 is connected to the positive terminal of the threshold voltage output source V0, and the negative terminal of the threshold voltage output source V0 is connected to GND.

[0082] The other end of the limiting resistor Rb1 is connected to the signal output terminal a2 of the switch sw0 and the terminal VBSU. The other end of the limiting resistor Rb2 is connected to the signal input terminal a1 of the switch sw0. The output terminal of the comparator cmp1 is connected to the switching control terminal a0 of the switch sw0.

[0083] Regarding the connection relationship of the components of the power supply unit 20, the anode of diode Db is connected to the positive terminal of the low-phase power supply VccL, one terminal of smoothing capacitor C0, and terminal Vcc. The cathode of diode Db is connected to terminal VBSU. One terminal of capacitor Cb is connected to terminal VccU, and the other terminal of capacitor Cb is connected to terminal GNDU. The negative terminal of the low-phase power supply VccL is connected to the other terminal of smoothing capacitor C0 and terminal GND.

[0084] Here, when an inrush current Ibmax flows through the limiting resistor Rb1 at the start of initial charging, the limiting resistor Rb1 has a resistance value that can limit the current so that the peak value of the inrush current Ibmax does not exceed the rated current value Ir (the resistance value of the limiting resistor Rb1 may be the same as the resistance value of the limiting resistor Rb shown in FIG. 3). Also, when the inrush current Ibmax flows through the parallel combined resistance of the limiting resistors Rb1 and Rb2, the limiting resistor Rb2 has a resistance value that can limit the current so that the peak value of the inrush current Ibmax does not exceed the rated current value Ir.

[0085] For example, suppose a resistance value of 50 Ω is sufficient to limit the inrush current Ibmax so that its peak value does not exceed the rated current value Ir. In this case, setting the limiting resistor Rb1 to 100 Ω will limit the inrush current Ibmax so that its peak value does not exceed the rated current value Ir. Furthermore, setting the limiting resistor Rb2 to 200 Ω will result in a combined parallel resistance of Rb1 and Rb2 of 67 Ω (>50 Ω). Therefore, even if the inrush current Ibmax flows through the combined parallel resistance of Rb1 and Rb2, the current can be limited so that its peak value does not exceed the rated current value Ir. Therefore, a resistance value of 200 Ω can be used for Rb2. On the other hand, setting the limiting resistor Rb2 to 80 Ω will result in a combined parallel resistance of Rb1 and Rb2 of 44 Ω, which is smaller than 50 Ω, making an 80 Ω limiting resistor Rb2 inappropriate. The combined parallel resistance value of the limiting resistors Rb1 and Rb2 is smaller than the resistance value of the limiting resistor Rb1.

[0086] FIG. 11 is a diagram showing an example of the operation of the charging current limiting circuit at the start of initial charging. [Step S21] The LVIC 12 turns on the X-phase switching element 16a based on the X-phase drive signal input via the terminal VinX.

[0087] [Step S22] When initial charging begins, no voltage of a predetermined level is applied to terminal VccU, and the voltage level of terminal VccU is lower than the threshold voltage Vth output by threshold voltage output source V0. Note that the voltage value of this predetermined level may be the same as the voltage value of threshold voltage Vth.

[0088] At this time, the comparator cmp1 outputs an L-level signal, and the switch sw0 receives this L-level signal and turns off. In this case, the terminal VccU is connected to the terminal VBSU via the limiting resistor Rb1.

[0089] [Step S23] One end of the capacitor Cb is electrically connected to the positive terminal of the low-phase power supply VccL via the terminal VccU, the limiting resistor Rb1, and the diode Db. When the X-phase switching element 16a is turned on, the other end of the capacitor Cb is electrically connected to the negative terminal of the low-phase power supply VccL via the terminals GNDU and GND, causing a charging current Ib to flow.

[0090] At this time, the charging current Ib flows in the following order: the positive terminal of the lower-phase power supply VccL, from the anode to the cathode of the diode Db, the limiting resistor Rb1, the terminal VccU, the capacitor Cb, from the collector to the emitter of the X-phase switching element 16a, and the negative terminal of the lower-phase power supply VccL.

[0091] [Step S24] As the charging current Ib flows, the capacitor Cb is charged. [Step S25] The charge stored in the capacitor Cb is discharged, and the charging voltage Vchg is discharged and output from the capacitor Cb toward the terminal VccU.

[0092] FIG. 12 is a diagram showing an example of the operation of the charging current limiting circuit when the charging voltage during initial charging reaches or exceeds a predetermined level. [Step S31] After a predetermined time has elapsed since the start of initial charging, the voltage level of the charging voltage Vchg rises, and a predetermined level of voltage is applied to the terminal VccU, exceeding the threshold voltage Vth. At this time, the comparator cmp1 outputs an H-level signal, and the switch sw0 receives this H-level signal and turns on. In this case, the terminal VccU is connected to the terminal VBSU via the parallel combined resistance of the limiting resistors Rb1 and Rb2.

[0093] [Step S32] Charging current Ib flows from the positive terminal of the low-phase power supply VccL to the anode and cathode of diode Db, and then, because switch sw0 is turned on, flows through the parallel combined resistance of limiting resistors Rb1 and Rb2. Furthermore, charging current Ib flows from terminal VccU, capacitor Cb, the collector to emitter of X-phase switching element 16a, and the negative terminal of the low-phase power supply VccL.

[0094] [Step S33] The capacitor Cb is charged by the charging current Ib. [Step S34] The capacitor Cb discharges the upper-phase drive voltage VH, which has been established when the charging voltage Vchg exceeds a predetermined level, and the upper-phase drive voltage VH is applied to the LVIC 11U-1 via the terminal VccU. The internal circuit 11b1 in the LVIC 11U-1 receives the upper-phase drive voltage VH and drives the gate of the U-phase switching element 13a.

[0095] 13 is a diagram showing an example of the waveform of the charging current during initial charging, where the vertical axis represents the charging current Ib and the horizontal axis represents time. (Time period T1) At the start of initial charging, the voltage level of the terminal VccU (the voltage level of the charging voltage Vchg) is less than the threshold voltage Vth, the switch sw0 is turned off, and the limiting resistor Rb1 is selected.

[0096] [Section t11] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing to turn on the X-phase switching element 16a, it turns on the X-phase switching element 16a.

[0097] At this time, capacitor Cb is in an uncharged state, meaning a large inrush current Ibmax flows through it. However, the inrush current Ibmax flows through limiting resistor Rb1, which has a high resistance value set so that the peak value of the inrush current Ibmax does not exceed the rated current value Ir. Therefore, at the start of initial charging, the inrush current Ibmax is suppressed so as not to exceed the rated current.

[0098] [Section t12] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing it to turn off the X-phase switching element 16a, it turns off the X-phase switching element 16a. At this time, the other end of the capacitor Cb is not conductive to the negative terminal of the low-phase power supply VccL, so that the charging current Ib does not flow.

[0099] [Section t13] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing it to turn on the X-phase switching element 16a, it turns on the X-phase switching element 16a. In this case, the charging current Ib flows to the capacitor Cb, but because the charge accumulated in the capacitor Cb during section t11 has accumulated, the peak value of the charging current Ib flowing to the capacitor Cb during section t13 is smaller than the peak value of the charging current Ib flowing to the capacitor Cb during section t11.

[0100] [Section t14] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing it to turn off the X-phase switching element 16a, it turns off the X-phase switching element 16a. At this time, the charging current Ib does not flow.

[0101] (Time period T2) A predetermined time has passed since the start of initial charging, and the voltage level of terminal VccU (the voltage level of charging voltage Vchg) becomes equal to or higher than the threshold voltage Vth, turning on switch sw0 and selecting the parallel combined resistance of limiting resistors Rb1 and Rb2.

[0102] [Section t21] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing to turn on the X-phase switching element 16a, it turns on the X-phase switching element 16a.

[0103] At this time, the charging current Ib flows through the parallel combined resistance of the limiting resistors Rb1 and Rb2. Because the resistance value of the parallel combined resistance of the limiting resistors Rb1 and Rb2 is smaller than the resistance value of the limiting resistor Rb1, an inrush current Ibmax flows through the capacitor Cb. However, even if the parallel combined resistance value of the limiting resistors Rb1 and Rb2 is lower than the resistance value of the limiting resistor Rb1, it is set so that the peak value of the inrush current Ibmax does not exceed the rated current value Ir. Therefore, even in section t21, the inrush current Ibmax is suppressed so as not to exceed the rated current value Ir.

[0104] [Section t22] When the LVIC 12 receives the X-phase drive signal via the terminal VinX instructing it to turn off the X-phase switching element 16a, it turns off the X-phase switching element 16a. At this time, the positive and negative terminals of the low-phase power supply VccL are not electrically connected, so no charging current Ib flows.

[0105] [Section t23] When the LVIC 12 receives the X-phase drive signal via terminal VinX instructing it to turn on the X-phase switching element 16a, it turns on the X-phase switching element 16a. A charging current Ib flows to capacitor Cb, but because capacitor Cb still has charge from the time it was charged before section t22, a charging current Ib smaller than the charging current flowing through capacitor Cb in section t21 flows through capacitor Cb. The same operation is repeated thereafter.

[0106] Here, during section t21 of time period T2, a charging current Ib is passed through the parallel combined resistance of limiting resistors Rb1 and Rb2, which has a resistance value smaller than the resistance value of limiting resistor Rb1, to charge capacitor Cb, and therefore the charging current Ib flowing into capacitor Cb increases.

[0107] Therefore, the time during which the charging current Ib flows in the semiconductor device 1-1 is shorter than the time during which the charging current Ib flows in the semiconductor device 100 due to the increase in the charging current Ib during the time period T2. In other words, the charging time tb2 of the semiconductor device 1-1 is shorter than the charging time tb1 of the semiconductor device 100.

[0108] 14 is a diagram showing an example of the waveform of the charging voltage during initial charging, where the vertical axis represents the charging voltage Vchg and the horizontal axis represents time. [Section t31] The charging voltage Vchg is less than the threshold voltage Vth, and the high-resistance limiting resistor Rb1 is selected. As the charging current Ib flows to the capacitor Cb, the capacitor Cb gradually accumulates charge, and the charging voltage Vchg discharged from the capacitor Cb also rises.

[0109] [Section t32] The charging voltage Vchg is equal to or greater than the threshold voltage Vth, and the parallel combined resistance of the low-resistance limiting resistors Rb1 and Rb2 is selected. Because the parallel combined resistance of the limiting resistors Rb1 and Rb2 increases the charging current Ib, the rise in the charging voltage Vchg of the semiconductor device 1-1 is greater than the rise in the charging voltage Vchg of the semiconductor device 100.

[0110] The time taken for the charging voltage Vchg to reach the upper phase drive voltage VH in the semiconductor device 1-1 is earlier than the time taken for the charging voltage Vchg to reach the upper phase drive voltage VH in the semiconductor device 100, because the charging current Ib increases and the rising level of the charging voltage Vchg becomes larger. In other words, the charging time tb2 of the semiconductor device 1-1 is shorter than the charging time tb1 of the semiconductor device 100. In this way, the initial charging of the semiconductor device 1-1 is completed earlier than the initial charging of the semiconductor device 100, as shown in FIGS. 13 and 14.

[0111] FIG. 15 is a diagram for explaining fluctuations in the upper phase drive voltage during PWM operation. [Section t41] This is PWM operation in mode m2, where a load current IL flows in the positive direction from the output terminal U to the load 3b. In this case, the upper-phase drive voltage VH is greater in the positive direction than the lower-phase drive voltage VL of the lower-phase power supply VccL by an amount corresponding to a fluctuation width w2.

[0112] However, during PWM operation when the upper phase drive voltage VH is established, the parallel combined resistance of the low resistance limiting resistors Rb1 and Rb2 is selected, so the fluctuation range w2 of the semiconductor device 1-1 is smaller than the fluctuation range w1 of the semiconductor device 100.

[0113] [Section t42] This is the PWM operation in mode m1, and load current IL flows in the negative direction from load 3a to output terminal U. In this case, the upper-phase drive voltage VH is greater in the negative direction than the lower-phase drive voltage VL of the lower-phase power supply VccL by a fluctuation width w2.

[0114] However, during PWM operation when the upper phase drive voltage VH is established, the parallel combined resistance of the low resistance limiting resistors Rb1 and Rb2 is selected, so the fluctuation range w2 of the semiconductor device 1-1 is smaller than the fluctuation range w1 of the semiconductor device 100.

[0115] In this way, during PWM operation when the upper phase drive voltage VH is established, the limiting resistors Rb1 and Rb2 are switched to a parallel connection, which reduces fluctuations in the upper phase drive voltage VH.

[0116] As described above, in the semiconductor device 1-1, when the charging voltage is less than the threshold voltage, the connection is switched to one limiting resistor to select a high resistance value and limit the charging current, and when the charging voltage is equal to or greater than the threshold voltage, the connection is switched to two limiting resistors in parallel to select a low resistance value and limit the charging current.

[0117] This makes it possible to reduce the initial charging time while suppressing the peak value of the inrush current at the start of initial charging, and also to suppress fluctuations in the upper phase drive voltage during PWM operation.

[0118] Next, a modified example of the semiconductor device of this embodiment will be described with reference to Figures 16 to 18. The semiconductor device of the modified example is configured so that when the charging voltage is below the threshold voltage, two limiting resistors are switched to a series connection to select a high resistance value, and when the charging voltage is equal to or higher than the threshold voltage, a single limiting resistor is switched to a connection to select a low resistance value. Note that the circuit configuration and operation are the same for the U-phase, V-phase, and W-phase, so only the U-phase side will be described.

[0119] 16 is a diagram showing a modified example of the configuration of the semiconductor device of this embodiment. The semiconductor device 1-2 includes a semiconductor module 10-2 and a power supply unit 20. The semiconductor module 10-2 includes an LVIC 11U-2. Other configurations within the semiconductor module 10-2 are the same as those in FIG. 10.

[0120] The LVIC 11U-2 includes a charging current limiting unit 11a2 and an internal circuit 11b1. The charging current limiting unit 11a2 includes a comparator cmp1, a threshold voltage output source V0, a ​​switch sw1 (first switch), a switch sw2 (second switch), a limiting resistor Rb11 (first limiting resistor), and a limiting resistor Rb12 (second limiting resistor).

[0121] Regarding the connection relationship of the components of the charging current limiting unit 11a2, the non-inverting input terminal (+) of the comparator cmp1 is connected to the terminal VccU, the signal input terminal a1 of the switch sw1, the signal input terminal a1 of the switch sw2, and the power supply voltage supply terminal of the internal circuit 11b1. The inverting input terminal (-) of the comparator cmp1 is connected to the positive terminal of the threshold voltage output source V0, and the negative terminal of the threshold voltage output source V0 is connected to GND.

[0122] The output terminal of the comparator cmp1 is connected to the switching control terminal a0 of the switch sw1 and the switching control terminal a0 of the switch sw2. One end of the limiting resistor Rb12 is connected to the signal output terminal a2 of the switch sw1. The other end of the limiting resistor Rb12 is connected to the signal output terminal a2 of the switch sw2 and one end of the limiting resistor Rb11. The other end of the limiting resistor Rb11 is connected to the terminal VBSU.

[0123] FIG. 17 is a diagram showing an example of the operation of the charging current limiting circuit at the start of initial charging. [Step S41] The LVIC 12 turns on the X-phase switching element 16a based on the X-phase drive signal input via the terminal VinX.

[0124] [Step S42] When initial charging begins, no voltage of the specified level is applied to terminal VccU, and the voltage level of terminal VccU is lower than the threshold voltage Vth output by threshold voltage output source V0. At this time, comparator cmp1 outputs an L-level signal. When switch sw1 receives this L-level signal, it turns on, and switch sw2 also turns off when it receives this L-level signal. In this case, terminal VccU is connected to terminal VBSU via the combined series resistance of limiting resistors Rb11 and Rb12.

[0125] [Step S43] One end of capacitor Cb is electrically connected to the positive terminal of the low-phase power supply VccL via terminal VccU, the combined series resistance of limiting resistors Rb11 and Rb12, and diode Db. When the X-phase switching element 16a is turned on, the other end of capacitor Cb is electrically connected to the negative terminal of the low-phase power supply VccL via terminals GNDU and GND, causing a charging current Ib to flow.

[0126] The charging current Ib flows in the following order: the positive terminal of the lower-phase power supply VccL, from the anode to the cathode of diode Db, the series combined resistance of limiting resistors Rb11 and Rb12, terminal VccU, capacitor Cb, from the collector to the emitter of X-phase switching element 16a, and the negative terminal of the lower-phase power supply VccL.

[0127] The series combined resistance of the limiting resistors Rb11 and Rb12 has a resistance value that limits the peak value of the inrush current so that it does not exceed the rated current value when the charging current Ib flows through the series combined resistance and an inrush current occurs when the switch sw1 is on and the switch sw2 is off.

[0128] [Step S44] As the charging current Ib flows, the capacitor Cb is charged. [Step S45] The charge stored in the capacitor Cb is discharged, and the charging voltage Vchg is discharged and output from the capacitor Cb toward the terminal VccU.

[0129] FIG. 18 is a diagram showing an example of the operation of the charging current limiting circuit when the charging voltage during initial charging reaches or exceeds a predetermined level. [Step S51] After a predetermined time has elapsed since the start of initial charging, the voltage level of the charging voltage Vchg rises, and a predetermined level of voltage is applied to the terminal VccU, exceeding the threshold voltage Vth. At this time, the comparator cmp1 outputs an H-level signal. The switch sw1 receives this H-level signal and turns off, and the switch sw2 receives this H-level signal and turns on. In this case, the terminal VccU is connected to the terminal VBSU via the limiting resistor Rb11.

[0130] [Step S52] Charging current Ib flows from the positive terminal of the low-phase power supply VccL to the anode and cathode of diode Db, and also flows through limiting resistor Rb11 because switch sw1 is off and switch sw2 is on. Furthermore, charging current Ib flows from terminal VccU, capacitor Cb, the collector to emitter of X-phase switching element 16a, and the negative terminal of the low-phase power supply VccL.

[0131] The limiting resistor Rb11 has a resistance value such that the peak value of the inrush current does not exceed the rated current value, even when the switch sw1 is turned off and the switch sw2 is turned on, causing a charging current Ib to flow through the limiting resistor Rb11 and generating an inrush current.

[0132] [Step S53] The capacitor Cb is charged by the charging current Ib. [Step S54] The upper-phase drive voltage VH, established when the charging voltage Vchg exceeds a predetermined level, is discharged from the capacitor Cb and applied to the LVIC 11U-2 via the terminal VccU. The internal circuit 11b1 in the LVIC 11U-2 receives the upper-phase drive voltage VH and drives the gate of the U-phase switching element 13a.

[0133] In this way, in semiconductor device 1-2, when the charging voltage is less than the threshold voltage, the connection is switched to a series combined resistance of two limiting resistors to select a high resistance value and limit the charging current, and when the charging voltage is equal to or greater than the threshold voltage, the connection is switched to a single limiting resistor to select a low resistance value and limit the charging current.

[0134] This makes it possible to reduce the initial charging time while suppressing the peak value of the inrush current at the start of initial charging, and also to suppress fluctuations in the upper phase drive voltage during PWM operation.

[0135] Although the embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the scope described in the above embodiments. Furthermore, various modifications and improvements can be made to the above embodiments. Furthermore, the technical scope of the present invention may include forms in which modifications or improvements have been made and their equivalents without departing from the spirit of the present invention. [Explanation of symbols]

[0136] 1. Semiconductor device 1a Upper phase drive control circuit 1a1 Charging current limiting circuit 1b Lower phase drive control circuit 1c Bootstrap Circuit 2a Upper phase switching element 2b Lower phase switching element VccL Lower phase power supply VL Lower phase drive voltage VH Upper phase drive voltage Ib charging current P positive terminal N negative terminal IN1 Upper phase input terminal IN2 Lower phase input terminal OUT output terminal

Claims

1. an upper phase switching element; a lower phase switching element connected in series to the upper phase switching element; a lower phase power supply that outputs a lower phase drive voltage; a lower phase drive control circuit that receives the lower phase drive voltage and controls the drive of the lower phase switching element; a bootstrap circuit that generates a charging voltage using electric charges stored by a charging current flowing from the low-phase power supply when the low-phase switching element is turned on by the drive control of the low-phase drive control circuit; an upper-phase drive control circuit including a charge current limiting circuit that limits the charge current flowing from the lower-phase power supply to the bootstrap circuit in accordance with the voltage level of the charge voltage, and that receives the charge voltage as an upper-phase drive voltage to drive and control the upper-phase switching element; A semiconductor device having:

2. 2. The semiconductor device according to claim 1, wherein said charging current limiting circuit limits said charging current to a high resistance value when said voltage level is below a predetermined level, and limits said charging current to a low resistance value when said voltage level is equal to or higher than said predetermined level.

3. the bootstrap circuit includes a diode and a capacitor; 3. The semiconductor device according to claim 2, wherein the capacitor is charged by the charging current that flows in this order through the lower-phase power supply, the forward direction of the diode, and the charging current limiting circuit, and the charging voltage is generated by the accumulated charge.

4. the charging current limiting circuit comprises a comparator that compares the charging voltage with a threshold voltage of the predetermined level and outputs a comparison result, a first limiting resistor, a second limiting resistor connected in parallel to the first limiting resistor, and a switch that switches in response to an output level of the comparator; The anode of the diode is connected to the positive terminal of the lower phase power supply, one end of the capacitor is connected to the non-inverting input terminal of the comparator, one end of the first limiting resistor, and one end of the second limiting resistor; the other end of the capacitor is connected to the negative terminal of the low-phase power supply when the low-phase switching element is turned on; The threshold voltage is applied to an inverting input terminal of the comparator, the other end of the first limiting resistor is connected to the signal output terminal of the switch and the cathode of the diode, and the other end of the second limiting resistor is connected to the signal input terminal of the switch; When a low potential level signal is output from the comparator, the switch is turned off, and the charging current is limited to the high resistance value of the selected first limiting resistor with the switch turned off; When a high potential level signal is output from the comparator, the switch is turned on, and the charging current is limited by the low resistance value of a parallel combined resistance of the first limiting resistor and the second limiting resistor selected when the switch is turned on.

4. The semiconductor device according to claim 3.

5. 5. The semiconductor device according to claim 4, wherein when the charging current flows and an inrush current occurs while the switch is off, the first limiting resistor has a resistance value that limits the peak value of the inrush current so that it does not exceed a rated current value.

6. 6. The semiconductor device according to claim 5, wherein the parallel combined resistance of the first limiting resistor and the second limiting resistor has a resistance value that limits the peak value of the inrush current so as not to exceed a rated current value when the charging current flows and the inrush current occurs when the switch is on.

7. the charging current limiting circuit comprises a comparator that compares the charging voltage with a threshold voltage of the predetermined level and outputs a comparison result, a first limiting resistor, a second limiting resistor connected in series to the first limiting resistor, a first switch that switches in response to an output level of the comparator, and a second switch that switches in response to the output level of the comparator; The anode of the diode is connected to the positive terminal of the lower phase power supply, one end of the capacitor is connected to the non-inverting input terminal of the comparator, the signal input terminal of the first switch, and the signal input terminal of the second switch; the other end of the capacitor is connected to the negative terminal of the low-phase power supply when the low-phase switching element is turned on; The threshold voltage is applied to an inverting input terminal of the comparator, one end of the second limiting resistor is connected to the signal output terminal of the first switch, and the other end of the second limiting resistor is connected to the signal output terminal of the second switch and one end of the first limiting resistor; the other end of the first limiting resistor is connected to the cathode of the diode; When a low potential level signal is output from the comparator, the first switch is turned on and the second switch is turned off, and the charging current is limited by the high resistance value of a series combined resistance of the selected first limiting resistor and the second limiting resistor; When a high potential level signal is output from the comparator, the first switch is turned off and the second switch is turned on, and the first switch is turned off and the second switch is turned on to limit the charging current at the low resistance value of the selected first limiting resistor.

4. The semiconductor device according to claim 3.

8. 8. The semiconductor device according to claim 7, wherein the series combined resistance of the first limiting resistor and the second limiting resistor has a resistance value that limits an inrush current so that a peak value of the inrush current does not exceed a rated current value when the charging current flows and an inrush current occurs when the first switch is on and the second switch is off.

9. 9. The semiconductor device according to claim 8, wherein, when the charging current flows and the inrush current occurs when the first switch is turned off and the second switch is turned on, the first limiting resistor has a resistance value that limits the peak value of the inrush current so that it does not exceed a rated current value.

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