Semiconductor device

Abstract

To improve a manufacturing yield of a semiconductor device.SOLUTION: A semiconductor chip CPH is mounted on a die pad DPH, and semiconductor chips CPL, CPC are mounted on a die pad DPH that is spaced apart from the die pad DPH in a Y direction. The semiconductor chip CPC incorporates a transformer and is adjacent to the semiconductor chip CPL in an X direction. In a plan view, a side SC3 of the semiconductor chip CPC faces a side SL2 of the semiconductor chip CPL, and a side SC1 of the semiconductor chip CPC on an opposite side of the side SC3 faces a side SH3 of the semiconductor chip CPH. A plurality of pads PL1 arranged along the side SL2 of the semiconductor chip CPL and a plurality of pads PC1 arranged along the side SC3 of the semiconductor chip CPC are electrically connected to each other via a plurality of wires. A plurality of pads PH1 arranged along the side SH3 of the semiconductor chip CPH and a plurality of pads PC3 arranged along the side SC1 of the semiconductor chip CPC are electrically connected to each other via a plurality of wires.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and can be suitably used in, for example, a semiconductor device having a plurality of semiconductor chips. [Background technology]

[0002] A semiconductor device in the form of a semiconductor package can be manufactured by mounting a semiconductor chip on a die pad, electrically connecting the pad electrodes of the semiconductor chip to the leads via wires, and sealing them with resin.

[0003] JP 2023-181601 A (Patent Document 1) describes a technology for transmitting a signal from one semiconductor chip to another semiconductor chip by inductively coupling two coils provided on the other semiconductor chip to each other, thereby transmitting an electrical signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2023-181601 Summary of the Invention [Problem to be solved by the invention]

[0005] It is desirable to reduce the size of semiconductor devices such as those disclosed in Patent Document 1. It is also desirable to improve the manufacturing yield.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] According to one embodiment, a semiconductor device includes a first chip mounting portion and a second chip mounting portion spaced apart from each other in a first direction, a first semiconductor chip mounted on the first chip mounting portion, a second semiconductor chip and a third semiconductor chip mounted on the second chip mounting portion, and a resin encapsulant encapsulating them. The first semiconductor chip and the third semiconductor chip are adjacent to each other in a second direction perpendicular to the first direction. The first semiconductor chip has a first side and a plurality of first chip pads arranged along the first side. The second semiconductor chip has a second side and a plurality of second chip pads arranged along the second side. The third semiconductor chip has a third side and a fourth side opposite the third side, two first conductor patterns magnetically or capacitively coupled to each other, a plurality of first pattern pads arranged along the third side, and a plurality of second pattern pads arranged along the fourth side. The plurality of first pattern pads are electrically connected to one of the two first conductor patterns, and the plurality of second pattern pads are electrically connected to the other of the two first conductor patterns. In a plan view, the third side of the third semiconductor chip faces the first side of the first semiconductor chip, and the fourth side of the third semiconductor chip faces the second side of the second semiconductor chip. The plurality of first chip pads and the plurality of first pattern pads are electrically connected to each other via a plurality of first wires, and the plurality of second chip pads and the plurality of second pattern pads are electrically connected to each other via a plurality of second wires. [Effects of the Invention]

[0008] According to one embodiment, it is possible to reduce the size of a semiconductor device. Alternatively, it is possible to improve the manufacturing yield of semiconductor devices. Alternatively, it is possible to reduce the size of a semiconductor device and improve the manufacturing yield of semiconductor devices. [Brief explanation of the drawings]

[0009] [Figure 1]1 is a circuit diagram showing an inverter circuit using the semiconductor device of the first embodiment. [Figure 2] 1 is a top view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan perspective view of a semiconductor device according to a first embodiment. [Figure 4] 1 is a plan perspective view of a semiconductor device according to a first embodiment. [Figure 5] 1 is a plan perspective view of a semiconductor device according to a first embodiment. [Figure 6] FIG. 2 is a bottom view of the semiconductor device of the first embodiment. [Figure 7] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 8] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 9] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 10] 1 is a cross-sectional view schematically showing three semiconductor chips in a semiconductor device according to a first embodiment. [Figure 11] 1 is a cross-sectional view schematically showing three semiconductor chips in a semiconductor device according to a first embodiment. [Figure 12] FIG. 1 is a plan perspective view of a semiconductor device of a first studied example. [Figure 13] FIG. 10 is a plan perspective view of a semiconductor device of a second studied example. [Figure 14] FIG. 10 is a plan perspective view of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a plan perspective view of a semiconductor device according to a second embodiment. [Figure 16] FIG. 11 is a circuit diagram showing an inverter circuit using the semiconductor device of the third embodiment. [Figure 17] FIG. 11 is a plan perspective view of a semiconductor device according to a third embodiment. [Figure 18] FIG. 11 is a plan perspective view of a semiconductor device according to a third embodiment. [Figure 19] FIG. 10 is a plan perspective view of a semiconductor device according to a fourth embodiment. [Figure 20] FIG. 10 is a plan perspective view of a semiconductor device according to a fourth embodiment. [Figure 21]FIG. 10 is a circuit diagram showing a DC-DC converter circuit using a semiconductor device according to a fifth embodiment. [Figure 22] FIG. 10 is a plan perspective view of a semiconductor device according to a fifth embodiment. [Figure 23] FIG. 10 is a plan perspective view of a semiconductor device according to a fifth embodiment. [Figure 24] FIG. 13 is a plan perspective view of a semiconductor device according to a sixth embodiment. [Figure 25] FIG. 13 is a plan perspective view of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following embodiments, the description will be divided into multiple sections or embodiments for convenience, as necessary. However, unless otherwise specified, they are not unrelated to one another, and one is a partial or complete modification, detail, supplementary explanation, etc., of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or clearly limited to a specific number in principle. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, unless otherwise specified or clearly considered essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of components, etc. are mentioned, it is intended to include those that are substantially similar to or similar to the shape, etc., unless otherwise specified or clearly considered not to be essential in principle. The same applies to the above numerical values ​​and ranges.

[0011] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0012] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to make the drawings easier to see, and hatching may be added even in plan views to make the drawings easier to see.

[0013] (Embodiment 1) <Circuit configuration> FIG. 1 is a circuit diagram showing an inverter circuit using a semiconductor device PKG of this embodiment. In FIG. 1, the portion surrounded by a dotted line and labeled CPH is formed in the semiconductor chip CPH, the portion surrounded by a dotted line and labeled CPL is formed in the semiconductor chip CPL, the portion surrounded by a dotted line and labeled CPC is formed in the semiconductor chip CPC, and the portion surrounded by a dashed line and labeled PKG is formed in the semiconductor device PKG. The inverter circuit shown in FIG. 1 uses two semiconductor devices PKG. To simplify the drawing, the circuit configuration of the semiconductor device PKG connected to the power transistor TS2 is omitted in FIG. 1, but the circuit configuration of the semiconductor device PKG connected to the power transistor TS2 is basically the same as the circuit configuration of the semiconductor device PKG connected to the power transistor TS1.

[0014] The semiconductor device PKG used in the inverter circuit shown in Fig. 1 includes three semiconductor chips CPC, CPL, and CPH. A transmitter circuit TX1 and a receiver circuit RX2 are formed in the semiconductor chip CPL. A receiver circuit RX1, a transmitter circuit TX2, and a drive circuit (control circuit) DR are formed in the semiconductor chip CPH. A transformer TR1 consisting of a plurality of (two in this case) coils L1a and L1b magnetically coupled to each other, and a transformer TR2 consisting of a plurality of (two in this case) coils L2a and L2b magnetically coupled to each other are formed in the semiconductor chip CPC. The inverter circuit shown in Fig. 1 also includes a control circuit CC, which is formed in another semiconductor chip provided outside the semiconductor package PKG.

[0015] The transmitter circuit TX1 and receiver circuit RX1 are circuits for transmitting signals from the control circuit CC to the driver circuit DR. The transmitter circuit TX1 converts the signal sent from the control circuit CC to the transmitter circuit TX1 and transmits it to the receiver circuit RX1 via the transformer TR1. The receiver circuit RX1 converts the signal received from the transmitter circuit TX1 via the transformer TR1 and transmits it to the driver circuit DR.

[0016] The transmitter circuit TX2 and receiver circuit RX2 are circuits for transmitting signals from the driver circuit DR to the control circuit CC. The transmitter circuit TX2 converts the signal sent from the driver circuit DR to the transmitter circuit TX2 and transmits it to the receiver circuit RX2 via a transformer TR2. The receiver circuit RX2 converts the signal received from the transmitter circuit TX2 via the transformer TR2 and transmits it to the control circuit CC.

[0017] 1 has power transistors TS1 and TS2. The power transistor TS1 is a transistor for a high-side switch (high potential side switch), and the power transistor TS2 is a transistor for a low-side switch (low potential side switch). The power transistors TS1 and TS2 are each formed in separate semiconductor chips provided outside the semiconductor package PKG.

[0018] In the following, a case where the power transistors TS1 and TS2 are power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) will be described. IGBTs (Insulated Gate Bipolar Transistors) can also be used as the power transistors TS1 and TS2. In that case, in the following description of the power transistors TS1 and TS2, "source" should be read as "emitter" and "drain" should be read as "collector."

[0019] In addition, in this application, the term "MOSFET" includes not only MISFETs (Metal Insulator Semiconductor Field Effect Transistors) that use an oxide film (silicon oxide film) as a gate insulating film, but also MISFETs that use an insulating film other than an oxide film as a gate insulating film.

[0020] The power transistors TS1 and TS2 are connected in series, and the source (S1) of the power transistor TS1 is connected to the drain (D2) of the power transistor TS2. A power supply potential (power supply voltage) V1 is supplied to the drain (D1) of the power transistor TS1 from a power supply (battery) BT1. A power supply potential (power supply voltage) V2 is supplied to the control circuit CC from a power supply (battery) BT2. The power supply potential V1 supplied to the drain (D1) of the power transistor TS1 is significantly higher than the power supply potential V2 (e.g., several volts to several tens of volts) supplied to the control circuit CC, and is, for example, 100 volts or more (several hundred volts). A reference potential lower than the power supply potential V1, such as a ground potential (GND), is supplied to the source (S2) of the power transistor TS2. The gate (G1) of the power transistor TS1 and the gate (G2) of the power transistor TS2 are each connected to a drive circuit DR.

[0021] In this embodiment, the same number of semiconductor devices PKGs as the number of power transistors TS1 and TS2 are used. In this case, a drive circuit DR provided in the semiconductor device PKG for the power transistor TS1 controls the voltage of the gate (G1) of the power transistor TS1, and a drive circuit DR provided in the semiconductor device PKG for the power transistor TS2 controls the voltage of the gate (G2) of the power transistor TS2. As another form, one semiconductor device PKG may be used for two power transistors TS1 and TS2, and in that case, a drive circuit DR provided in the common semiconductor device PKG controls the voltages of the gates (G1 and G2) of the two power transistors TS1 and TS2.

[0022] The operation of the power transistors TR1 and TR2 can be controlled by controlling the gate voltage supplied from the drive circuit DR to the gates (G1, G2) of each power transistor TS1 and TS2 in accordance with a signal (control signal) supplied from the control circuit CC to the drive circuit via the transmission circuit TX1, transformer TR1, and receiver circuit RX1.

[0023] A terminal T1 provided between the source (S1) of the power transistor TS1 and the drain (D2) of the power transistor TS2 is an output terminal of the inverter circuit. The terminal T1 is connected to a load LOD. The load LOD is, for example, a motor coil. The DC power supplied to the inverter circuit is converted into AC power by the inverter circuit and supplied to the load LOD.

[0024] A transformer TR1 is interposed between the transmitter circuit TX1 and the receiver circuit RX1, and a transformer TR2 is interposed between the transmitter circuit TX2 and the receiver circuit RX2. The control circuit CC can transmit a signal (control signal) to the driver circuit DR via the transmitter circuit TX1, transformer TR1, and receiver circuit RX1. The driver circuit DR can also transmit a signal to the control circuit CC via the transmitter circuit TX2, transformer TR2, and receiver circuit RX2. Coils L1a, L1b, L2a, and L2b can each be considered as inductors.

[0025] The transformer TR1 is formed by coils L1a and L1b formed within the semiconductor chip CPC. However, coils L1a and L1b are not connected by any conductor but are magnetically coupled to each other. Therefore, when current flows through coil L1a, an induced electromotive force is generated in coil L1b in response to changes in the current, resulting in an induced current. Coil L1a is the primary coil, and coil L1b is the secondary coil. By utilizing this, a signal is sent from the transmitter circuit TX1 to coil L1a (primary coil) of the transformer TR1, causing a current to flow. The receiver circuit RX1 then detects (receives) the induced current (or induced electromotive force) generated in coil L1b (secondary coil) of the transformer TR1. This allows the receiver circuit RX1 to receive a signal corresponding to the signal sent by the transmitter circuit TX1.

[0026] The transformer TR2 is formed by coils L2a and L2b formed within the semiconductor chip CPC. However, coils L2a and L2b are not connected by any conductor but are magnetically coupled. Therefore, when current flows through coil L2b, an induced electromotive force is generated in coil L2a in response to changes in the current, resulting in an induced current. Coil L2b is the primary coil, and coil L2a is the secondary coil. By utilizing this, the transmitter circuit TX2 sends a signal to coil L2b (primary coil) of the transformer TR2 to cause a current to flow. The receiver circuit RX2 then detects (receives) the induced current (or induced electromotive force) generated in coil L2a (secondary coil) of the transformer TR2. This allows the receiver circuit RX2 to receive a signal corresponding to the signal sent by the transmitter circuit TX2.

[0027] Signals can be transmitted between the semiconductor chip CPL and the semiconductor chip CPH via a path from the transmitting circuit TX1 via the transformer TR1 to the receiving circuit RX1, and a path from the transmitting circuit TX2 via the transformer TR2 to the receiving circuit RX2.

[0028] The semiconductor chip CPL and the semiconductor chip CPH have different voltage levels. For example, the semiconductor chip CPL is electrically connected to a low-voltage region having a circuit (e.g., a control circuit CC) that operates or is driven at a low voltage (e.g., several volts to several tens of volts) via a wire BW and a lead LD (specifically, a lead LD2) described later. The semiconductor chip CPH is electrically connected to a high-voltage region having a circuit (e.g., power transistors TS1 and TS2) that operates or is driven at a voltage higher than the low voltage (e.g., 100 V or higher) via a wire BW and a lead LD (specifically, a lead LD1) described later. However, because signals are transmitted between the semiconductor chips CPL and CPH via transformers TR1 and TR2, signals can be transmitted between circuits of different voltages.

[0029] Note that Figure 1 shows a case where the control circuit CC is built into a semiconductor chip other than the semiconductor chips CPC, CPH, and CPL, but in another embodiment, part or all of the control circuit CC can also be built into the semiconductor chip CPL.

[0030] <About the structure of semiconductor devices> FIG. 2 is a top view of the semiconductor device PKG of this embodiment, FIGS. 3, 4, and 5 are planar perspective views of the semiconductor device PKG, FIG. 6 is a bottom view (rear view) of the semiconductor device PKG, and FIGS. 7, 8, and 9 are cross-sectional views of the semiconductor device PKG. FIG. 3 shows a planar perspective view of the upper surface of the semiconductor device PKG when the sealing portion MR is seen through. FIG. 4 shows a planar perspective view of the upper surface of the semiconductor device PKG when the wires BW are further seen through (omitted) in FIG. 3. FIG. 5 shows a planar perspective view of the upper surface of the semiconductor device PKG when the semiconductor chips CPC, CPH, and CPL are further seen through (omitted) in FIG. 4. In FIGS. 3, 4, and 5, the outer periphery of the sealing portion MR is indicated by a dotted line. 2 and 3, a cross-sectional view of the semiconductor device PKG taken along line A1-A1 corresponds to Fig. 7, a cross-sectional view of the semiconductor device PKG taken along line A2-A2 corresponds to Fig. 8, and a cross-sectional view of the semiconductor device PKG taken along line A3-A3 corresponds to Fig. 9. Also, Figs. 2 to 6 show the X and Y directions. Here, the X and Y directions are directions that intersect with each other, and more specifically, are directions that are perpendicular to each other.

[0031] The semiconductor device (semiconductor package) PKG of this embodiment shown in Figures 2 to 9 is a semiconductor device in the form of a resin-sealed semiconductor package, and in this case is a semiconductor device in the form of an SOP (Small Outline Package). The configuration of the semiconductor device PKG will be described below with reference to Figures 2 to 9.

[0032] The semiconductor device PKG of this embodiment shown in Figures 2 to 9 has three semiconductor chips CPC, CPH, and CPL, a die pad DPL on which two semiconductor chips CPC and CPL are mounted, a die pad DPH on which one semiconductor chip CPH is mounted, a plurality of wires (bonding wires) BW, a plurality of leads LD, and a sealing part MR that seals these.

[0033] The sealing portion MR as a resin sealing body is made of a resin material such as a thermosetting resin material, and may contain a filler, etc. For example, the sealing portion MR may be formed using an epoxy resin containing a filler.

[0034] The sealing portion MR has an upper surface MRa which is one of the main surfaces, a lower surface (rear surface, bottom surface) MRb which is the main surface opposite to the upper surface MRa, and side surfaces MRc1, MRc2, MRc3, and MRc4 which intersect with the upper surface MRa and the lower surface MRb.

[0035] The side surfaces MRc1 and MRc3 are approximately parallel to the X direction, and the side surfaces MRc2 and MRc4 are approximately parallel to the Y direction. In the sealing portion MR, the side surfaces MRc1 and MRc3 are located opposite each other, the side surfaces MRc2 and MRc4 are located opposite each other, the side surface MRc1 intersects with the side surfaces MRc2 and MRc4, and the side surface MRc3 intersects with the side surfaces MRc2 and MRc4. The upper surface MRa and the lower surface MRb are each parallel to both the X direction and the Y direction. The planar shape of the sealing portion MR, i.e., the planar shapes of the upper surface MRa and the lower surface MRb of the sealing portion MR, is, for example, rectangular (oblong).

[0036] A portion of each of the leads LD of the semiconductor device PKG is sealed within the sealing portion MR, and another portion protrudes from the side surface of the sealing portion MR to the outside of the sealing portion MR. Hereinafter, the portion of the lead LD located within the sealing portion MR will be referred to as an inner lead portion, and the portion of the lead LD located outside the sealing portion MR will be referred to as an outer lead portion. A plating layer (not shown), such as a solder plating layer, may be formed on the outer lead portion of the lead LD.

[0037] The semiconductor device PKG of this embodiment has a structure in which a part of each lead LD (outer lead part) protrudes from the side surface of the sealing part MR, and the following description will be based on this structure, but is not limited to this structure. For example, it is also possible to adopt a structure in which each lead LD hardly protrudes from the side surface of the sealing part MR and a part of each lead LD is exposed at the lower surface MRb of the sealing part MR (SON (Small Outline Nonleaded Package) type structure).

[0038] The semiconductor device PKG has multiple leads LD arranged on the side MRc1 of the sealing portion MR and multiple leads LD arranged on the side MRc3 of the sealing portion MR. In the cases of FIGS. 2 to 9, no leads LD are arranged on the side MRc2, MRc4 of the sealing portion MR. Hereinafter, the leads LD arranged on the side MRc1 of the sealing portion MR will be referred to as leads LD1. Also, the leads LD arranged on the side MRc3 of the sealing portion MR will be referred to as leads LD2. The outer lead portion of each lead LD1 protrudes from the side MRc1 of the sealing portion MR to the outside of the sealing portion MR. Also, the outer lead portion of each lead LD2 protrudes from the side MRc3 of the sealing portion MR to the outside of the sealing portion MR. The outer lead portion of each lead LD is bent so that the lower surface near the end of the outer lead portion is positioned approximately flush with the lower surface MRb of the sealing portion MR. The outer lead portion of the lead LD functions as an external connection terminal portion (external terminal) of the semiconductor device PKG.

[0039] The die pad DPL is a chip mounting portion on which two semiconductor chips CPC and CPL are mounted, and the die pad DPH is a chip mounting portion on which a semiconductor chip CPH is mounted. The die pads DPH and DPL are spaced apart from each other in the Y direction, and a part of the sealing portion MR is interposed between the die pads DPH and DPL.

[0040] Of the die pads DPH, DPL, the die pad DPH is arranged closer to the side surface MRc1 of the sealing portion MR, and the die pad DPL is arranged closer to the side surface MRc3 of the sealing portion MR. That is, in the Y direction, the die pad DPH is arranged between the die pad DPL and the side surface MRc1 of the sealing portion MR, and the die pad DPL is arranged between the die pad DPH and the side surface MRc3 of the sealing portion MR. Each of the die pads DPH, DPL is sealed within the sealing portion MR and is not exposed from the sealing portion MR.

[0041] The die pads DPH, DPL and the leads LD are made of a conductor, preferably a metal material such as copper (Cu) or a copper alloy. The die pads DPH, DPL and the leads LD are preferably made of the same material. This facilitates the manufacture of a semiconductor device PKG using a lead frame.

[0042] The die pad DPH has an upper surface DPHa which is the main surface on which the semiconductor chip CPH is mounted, a lower surface (back surface) DPHb which is the main surface on the opposite side, and side surfaces DPHc1, DPHc2, DPHc3, and DPHc4 which intersect with the upper surface DPHa and the lower surface DPHb. In the die pad DPH, the side surface DPHc1 is located on the side surface MRc1 of the sealing portion MR, the side surface DPHc2 is located on the side surface MRc2 of the sealing portion MR, the side surface DPHc3 is located on the side surface MRc3 of the sealing portion MR, and the side surface DPHc4 is located on the side surface MRc4 of the sealing portion MR. In the die pad DPH, the side surfaces DPHc1 and DPHc3 are located opposite each other, and the side surfaces DPHc2 and DPHc4 are located opposite each other, with the side surface DPHc1 intersecting with the side surfaces DPHc2 and DPHc4, and the side surface DPHc3 intersecting with the side surfaces DPHc2 and DPHc4.

[0043] The die pad DPL has an upper surface DPLa which is the main surface on which the semiconductor chips CPC and CPL are mounted, a lower surface (back surface) DPLb which is the main surface opposite thereto, and side surfaces DPLc1, DPLc2, DPLc3, and DPLc4 which intersect with the upper surface DPLa and the lower surface DPLb. In the die pad DPL, the side surface DPLc1 is located on the side of the side surface MRc1 of the sealing portion MR, the side surface DPLc2 is located on the side of the side surface MRc2 of the sealing portion MR, the side surface DPLc3 is located on the side of the side surface MRc3 of the sealing portion MR, and the side surface DPLc4 is located on the side of the side surface MRc4 of the sealing portion MR. In the die pad DPL, the side surfaces DPLc1 and DPLc3 are located opposite each other, the side surfaces DPLc2 and DPLc4 are located opposite each other, the side surface DPLc1 intersects with the side surfaces DPLc2 and DPLc4, and the side surface DPLc3 intersects with the side surfaces DPLc2 and DPLc4. The side surface DPHc3 of the die pad DPH and the side surface DPLc1 of the die pad DPL face each other via a part of the sealing portion MR.

[0044] The side surfaces DPHc1 and DPHc3 of the die pad DPH and the side surfaces DPLc1 and DPLc3 of the die pad DPL are substantially parallel to the X direction, and the side surfaces DPHc2 and DPHc4 of the die pad DPH and the side surfaces DPLc2 and DPLc4 of the die pad DPL are substantially parallel to the Y direction. The upper surface DPHa and the lower surface DPHb of the die pad DPH and the upper surface DPLa and the lower surface DPLb of the die pad DPL are each substantially parallel to both the X direction and the Y direction. The planar shape of each of the die pads DPH and DPL is, for example, rectangular.

[0045] Of the multiple leads LD arranged on the side surface MRc1 of the encapsulating unit MR, the inner lead portion of lead LD1a is integrally connected to the side surface DPHc2 of the die pad DPH, and the inner lead portion of lead LD1b is integrally connected to the side surface DPHc4 of the die pad DPH. The leads LD1a and LD1b function as suspension leads that support the die pad DPH on the framework of the lead frame during manufacturing of the semiconductor device PKG. Furthermore, of the multiple leads LD arranged on the side surface MRc3 of the encapsulating unit MR, the inner lead portion of lead LD2a is integrally connected to the side surface DPLc2 of the die pad DPL, and the inner lead portion of lead LD2b is integrally connected to the side surface DPLc4 of the die pad DPL. The leads LD2a and LD2b function as suspension leads that support the die pad DPL on the framework of the lead frame during manufacturing of the semiconductor device PKG. On the side surface MRc1 of the sealing portion MR, a plurality of leads LD (LD1) are lined up in the X direction, with the leads LD1a and LD1b located at both ends of the arrangement. Also, on the side surface MRc3 of the sealing portion MR, a plurality of leads LD (LD2) are lined up in the X direction, with the leads LD2a and LD2b located at both ends of the arrangement.

[0046] Each of the three semiconductor chips CPC, CPH, and CPL has a front surface, which is one main surface, and a back surface, which is the main surface opposite to the front surface. The planar shape of each of the semiconductor chips CPC, CPH, and CPL is quadrangular, preferably rectangular. Therefore, in a planar view, the semiconductor chip CPC has four sides SC1, SC2, SC3, and SC4, the semiconductor chip CPH has four sides SH1, SH2, SH3, and SH4, and the semiconductor chip CPL has four sides SL1, SL2, SL3, and SL4. Each side of each of the semiconductor chips CPC, CPH, and CPL is a side that forms the periphery of the planar shape of the semiconductor chip and is formed by each side surface of the semiconductor chip. The planar dimensions (planar area) of the semiconductor chip CPH are larger than those of the semiconductor chip CPL and the semiconductor chip CPC. The length of the side SH3 of the semiconductor chip CPH is larger than the lengths of the sides SL1, SL2, SL3, and SL4 of the semiconductor chip CPL. The length of the side SH3 of the semiconductor chip CPH is greater than the lengths of the sides SC1, SC2, SC3, and SC4 of the semiconductor chip CPC.

[0047] The semiconductor chip CPH is mounted on the upper surface DPHa of the die pad DPH via a bonding material BDH, with the back surface of the semiconductor chip CPH facing the die pad DPH. The semiconductor chip CPC is mounted on the upper surface DPLa of the die pad DPL via a bonding material BDC, with the back surface of the semiconductor chip CPC facing the die pad DPL. The semiconductor chip CPL is mounted on the upper surface DPLa of the die pad DPL via a bonding material BDL, with the back surface of the semiconductor chip CPL facing the die pad DPL. That is, of the semiconductor chips CPC, CPH, and CPL, the semiconductor chip CPH is mounted on the die pad DPH, and the semiconductor chips CPC and CPL are mounted on the die pad DPL.

[0048] On the upper surface DPLa of the die pad DPL, the region where the semiconductor chip CPC is mounted and the region where the semiconductor chip CPL is mounted are spaced apart from each other (specifically, spaced apart in the X direction). That is, the semiconductor chip CPC and the semiconductor chip CPL are not stacked on each other, but are arranged side by side in the X direction on the upper surface DPLa of the die pad DPL at a distance from each other. That is, the semiconductor chip CPC and the semiconductor chip CPL arranged on the upper surface DPLa of the die pad DPL are adjacent to each other in the X direction.

[0049] In a plan view, the die pad DPL and the die pad DPH are adjacent to each other in the Y direction. Therefore, in a plan view, the semiconductor chip CPL and the semiconductor chip CPH are adjacent to each other in the Y direction. Also, in a plan view, the semiconductor chip CPC and the semiconductor chip CPH are adjacent to each other in the Y direction. In a plan view, the semiconductor chip CPC and the semiconductor chip CPL are included in the upper surface DPLa of the die pad DPL. Also, in a plan view, the semiconductor chip CPH is included in the upper surface DPHa of the die pad DPH. Note that a plan view corresponds to a case where the die pad DPL and the semiconductor chip CPL are viewed from a plane parallel to both the X direction and the Y direction.

[0050] The bonding materials BDC, BDH, and BDL can be conductive bonding materials such as silver paste. The back surface of the semiconductor chip CPH is bonded and fixed to the die pad DPH via the bonding material BDH, the back surface of the semiconductor chip CPC is bonded and fixed to the die pad DPL via the bonding material BDC, and the back surface of the semiconductor chip CPL is bonded and fixed to the die pad DPL via the bonding material BDL. The semiconductor chips CPC, CPH, and CPL are sealed within the sealing portion MR and are not exposed from the sealing portion MR.

[0051] An insulating bonding material can also be used as the bonding materials BDC, BDH, and BDL. However, when a conductive bonding material is used as the bonding materials BDC, BDH, and BDL, there is an advantage that the heat generated in the semiconductor chips CPC, CPH, and CPL can be easily conducted to the die pads DPH and DPL via the bonding materials BDC, BDH, and BDL.

[0052] Of the four sides SH1, SH2, SH3, and SH4 of the semiconductor chip CPH, sides SH1 and SH3 are located opposite each other, sides SH2 and SH4 are located opposite each other, side SH1 intersects with sides SH2 and SH4, and side SH3 intersects with sides SH2 and SH4. Sides SH1 and SH3 of the semiconductor chip CPH are approximately parallel to the X direction, and sides SH2 and SH4 of the semiconductor chip CPH are approximately parallel to the Y direction. The front and back surfaces of the semiconductor chip CPH are each approximately parallel to both the X and Y directions.

[0053] Of the sides SH1 and SH3 of the semiconductor chip CPH, the side SH1 of the semiconductor chip CPH is located closer to the side surface DPHc1 of the die pad DPH, and the side SH3 of the semiconductor chip CPH is located closer to the side surface DPHc3 of the die pad DPH. That is, in the Y direction, the side SH1 of the semiconductor chip CPH is located between the side surface DPHc1 of the die pad DPH and the side SH3 of the semiconductor chip CPH, and the side SH3 of the semiconductor chip CPH is located between the side surface DPHc3 of the die pad DPH and the side SH1 of the semiconductor chip CPH.

[0054] Of the four sides SL1, SL2, SL3, and SL4 of the semiconductor chip CPL, sides SL1 and SL3 are located opposite each other, sides SL2 and SL4 are located opposite each other, side SL1 intersects with sides SL2 and SL4, and side SL3 intersects with sides SL2 and SL4. Sides SL1 and SL3 of the semiconductor chip CPL are approximately parallel to the X direction, and sides SL2 and SL4 of the semiconductor chip CPL are approximately parallel to the Y direction. The front and back surfaces of the semiconductor chip CPL are each approximately parallel to both the X and Y directions.

[0055] Of the sides SL1 and SL3 of the semiconductor chip CPL, the side SL1 of the semiconductor chip CPL is located closer to the side surface DPLc1 of the die pad DPL, and the side SL3 of the semiconductor chip CPL is located closer to the side surface DPLc3 of the die pad DPL. That is, in the Y direction, the side SL1 of the semiconductor chip CPL is located between the side surface DPLc1 of the die pad DPL and the side SL3 of the semiconductor chip CPL, and the side SL3 of the semiconductor chip CPL is located between the side surface DPLc3 of the die pad DPL and the side SL1 of the semiconductor chip CPL.

[0056] Of the four sides SC1, SC2, SC3, and SC4 of the semiconductor chip CPC, sides SC1 and SC3 are located opposite each other, sides SC2 and SC4 are located opposite each other, side SC1 intersects with sides SC2 and SC4, and side SC3 intersects with sides SC2 and SC4. The front and back surfaces of the semiconductor chip CPC are each approximately parallel to both the X and Y directions.

[0057] Each of the sides SC1, SC2, SC3, and SC4 of the semiconductor chip CPC is inclined with respect to the X direction and also inclined with respect to the Y direction. That is, in a plan view, the semiconductor chip CPC is disposed at an incline. Therefore, each of the sides SC1, SC2, SC3, and SC4 of the semiconductor chip CPC is not parallel to either the X direction or the Y direction. The inclination angle of each of the sides SC1, SC2, SC3, and SC4 of the semiconductor chip CPC with respect to the X direction is preferably within a range of 40 to 50 degrees, and most preferably 45 degrees.

[0058] Of the corner formed by sides SC1 and SC2 of the semiconductor chip CPC, the corner formed by sides SC2 and SC3, the corner formed by sides SC3 and SC4, and the corner formed by sides SC4 and SC1, the corner formed by sides SC4 and SC1 is closest to the side DPLc1 of the die pad DPL, and the corner formed by sides SC2 and SC3 is closest to the side DPLc3 of the die pad DPL.

[0059] In a plan view, the distance (distance in the Y direction) between the semiconductor chip CPH and a corner formed by sides SC4 and SC1 among the four corners of the semiconductor chip CPC is smaller than the distance (distance in the Y direction) between the semiconductor chip CPH and other corners of the semiconductor chip CPC. Also, in a plan view, the distance (distance in the X direction) between the semiconductor chip CPL and a corner formed by sides SC3 and SC4 among the four corners of the semiconductor chip CPC is smaller than the distance (distance in the X direction) between the semiconductor chip CPL and other corners of the semiconductor chip CPC.

[0060] In a plan view, the side SC3 of the semiconductor chip CPC and the side SL2 of the semiconductor chip CPL face each other, and the side SC1 of the semiconductor chip CPC and the side SH3 of the semiconductor chip CPH face each other. Note that in a plan view, the side SC3 of the semiconductor chip CPC is inclined with respect to the side SL2 of the semiconductor chip CPL, and the side SC1 of the semiconductor chip CPC is inclined with respect to the side SH3 of the semiconductor chip CPH. Also, in a plan view, the side SL1 of the semiconductor chip CPL and the side SH3 of the semiconductor chip CPH face each other. Note that in a plan view, the side SL1 of the semiconductor chip CPL is parallel to the side SH3 of the semiconductor chip CPH. Also, in a plan view, the side SC4 of the semiconductor chip CPC and the side SH3 of the semiconductor chip CPH face each other. Note that in a plan view, the side SC4 of the semiconductor chip CPC is inclined with respect to the side SH3 of the semiconductor chip CPH.

[0061] A plurality of pads PH1, PH2, and PH3 are formed on the surface of the semiconductor chip CPH. A plurality of pads PL1, PL2, and PL3 are formed on the surface of the semiconductor chip CPL. A plurality of pads PC1, PC2, PC3, and PC4 are formed on the surface of the semiconductor chip CPC. Note that "bonding pads," "bonding pad electrodes," "pad electrodes," or "electrodes" will be simply referred to as "pads."

[0062] The pads PL1, PL2, PL3 of the semiconductor chip CPL are electrically connected to circuits (such as the above-mentioned transmitting circuit TX1 and receiving circuit RX2) formed in the semiconductor chip CPL through internal wiring of the semiconductor chip CPL.

[0063] Here, the pad PL1 of the semiconductor chip CPL is a pad electrically connected to the pad PC1 of the semiconductor chip CPC via a wire BW. The pad PL1 of the semiconductor chip CPL is electrically connected to the transmitting circuit TX1 in the semiconductor chip CPL via internal wiring of the semiconductor chip CPL. The pad PL2 of the semiconductor chip CPL is a pad electrically connected to the pad PC2 of the semiconductor chip CPC via a wire BW. The pad PL2 of the semiconductor chip CPL is electrically connected to the receiving circuit RX2 in the semiconductor chip CPL via internal wiring of the semiconductor chip CPL. The pad PL3 of the semiconductor chip CPL is a pad electrically connected to the lead LD2 via a wire BW. On the surface of the semiconductor chip CPL, a plurality of pads PL1 and PL2 are arranged along a side SL2 of the semiconductor chip CPL, and a plurality of pads PL3 are arranged along a side SL3 of the semiconductor chip CPL.

[0064] The pads PH1, PH2, PH3 of the semiconductor chip CPH are electrically connected to circuits (such as the above-mentioned receiving circuit RX1, transmitting circuit TX2, and driving circuit DR) formed within the semiconductor chip CPH through internal wiring of the semiconductor chip CPH.

[0065] Here, the pad PH1 of the semiconductor chip CPH is a pad electrically connected to the pad PC3 of the semiconductor chip CPC via a wire BW. The pad PH1 of the semiconductor chip CPH is electrically connected to the receiving circuit RX1 in the semiconductor chip CPH via the internal wiring of the semiconductor chip CPH. The pad PH2 of the semiconductor chip CPH is a pad electrically connected to the pad PC4 of the semiconductor chip CPC via a wire BW. The pad PH2 of the semiconductor chip CPH is electrically connected to the transmitting circuit TX2 in the semiconductor chip CPH via the internal wiring of the semiconductor chip CPH. The pad PH3 of the semiconductor chip CPH is a pad electrically connected to the lead LD1 via a wire BW. On the surface of the semiconductor chip CPH, a plurality of pads PH1 and PH2 are arranged along the side SH3 of the semiconductor chip CPH, and a plurality of pads PH3 are arranged along the side SH1 of the semiconductor chip CPH.

[0066] The pad PC1 of the semiconductor chip CPC is a pad electrically connected to the coil L1a formed in the semiconductor chip CPC. The pad PC2 of the semiconductor chip CPC is a pad electrically connected to the coil L2a formed in the semiconductor chip CPC. The pad PC3 of the semiconductor chip CPC is a pad electrically connected to the coil L1b formed in the semiconductor chip CPC. The pad PC4 of the semiconductor chip CPC is a pad electrically connected to the coil L2b formed in the semiconductor chip CPC. On the surface of the semiconductor chip CPC, the pads PC1 and PC2 are arranged along a side SC3 of the semiconductor chip CPC, and the pads PC3 and PC4 are arranged along a side SC1 of the semiconductor chip CPC.

[0067] A plurality of pads PL1 of the semiconductor chip CPL and a plurality of pads PC1 of the semiconductor chip CPC are electrically connected to each other via wires BW. That is, one end of the wire BW is connected to each of the pads PL1 of the semiconductor chip CPL, and the other end of the wire BW is connected to the pad PC1 of the semiconductor chip CPC. Also, a plurality of pads PL2 of the semiconductor chip CPL and a plurality of pads PC2 of the semiconductor chip CPC are electrically connected to each other via wires BW. That is, one end of the wire BW is connected to each of the pads PL2 of the semiconductor chip CPL, and the other end of the wire BW is connected to the pad PC2 of the semiconductor chip CPC.

[0068] A plurality of pads PH1 of the semiconductor chip CPH and a plurality of pads PC3 of the semiconductor chip CPC are electrically connected to each other via wires BW. That is, one end of the wire BW is connected to each of the pads PH1 of the semiconductor chip CPH, and the other end of the wire BW is connected to the pad PC3 of the semiconductor chip CPC. Also, a plurality of pads PH2 of the semiconductor chip CPH and a plurality of pads PC4 of the semiconductor chip CPC are electrically connected to each other via wires BW. That is, one end of the wire BW is connected to each of the pads PH2 of the semiconductor chip CPH, and the other end of the wire BW is connected to the pad PC4 of the semiconductor chip CPC.

[0069] Furthermore, the pads PL3 of the semiconductor chip CPL and the leads LD2 are electrically connected to each other via wires BW, i.e., one end of the wire BW is connected to each of the pads PL3 of the semiconductor chip CPL, and the other end of the wire BW is connected to the inner lead portion of the lead LD2.

[0070] Furthermore, the pads PH3 of the semiconductor chip CPH and the leads LD1 are electrically connected to each other via wires BW, i.e., one end of the wire BW is connected to each of the pads PH3 of the semiconductor chip CPH, and the other end of the wire BW is connected to the inner lead portion of the lead LD1.

[0071] The wire (bonding wire) BW is a conductive wire. Specifically, the wire BW is made of metal, and gold (Au) wire, copper (Cu) wire, or aluminum (Al) wire can be suitably used. The wire BW is sealed within the sealing portion MR and is not exposed from the sealing portion MR. In each lead LD, the connection point of the wire BW is an inner lead portion located within the sealing portion MR.

[0072] When the semiconductor device PKG is in use, the semiconductor chip CPL in the semiconductor device PKG is electrically connected to a circuit external to the semiconductor device PKG (specifically, the control circuit CC) via a wire BW (specifically, the wire BW electrically connecting the pad PL3 and the lead LD2), the lead LD2, etc. Also, when the semiconductor device PKG is in use, the semiconductor chip CPH in the semiconductor device PKG is electrically connected to a circuit external to the semiconductor device PKG (specifically, an inverter circuit constituted by power transistors TS1 and TS2) via a wire BW (specifically, the wire BW electrically connecting the pad PH3 and the lead LD1), the lead LD1, etc. The drive circuit DR formed in the semiconductor chip CPH is electrically connected to the receiving circuit RX1 and the transmitting circuit TX2 formed in the semiconductor chip CPH via internal wiring of the semiconductor chip CPH, etc. Moreover, when the semiconductor device PKG is used, the drive circuit DR formed in the semiconductor chip CPH is electrically connected to a circuit (specifically, an inverter circuit constituted by power transistors TS1 and TS2) outside the semiconductor device PKG via a wire BW (specifically, a wire BW electrically connecting the pad PH3 and the lead LD1) and the lead LD1, etc. A power supply potential V1 supplied to the inverter circuit constituted by the power transistors TS1 and TS2 is higher than a power supply potential V2 supplied to the control circuit CC.

[0073] <About the manufacturing process of semiconductor devices> Next, a manufacturing process (assembly process) of the semiconductor device PKG of this embodiment will be briefly described.

[0074] To manufacture the semiconductor device PKG, a lead frame integrally having die pads DPH, DPL and a plurality of leads LD, and semiconductor chips CPC, CPH, CPL are prepared.

[0075] Next, the semiconductor chip CPH is mounted on the upper surface DPHa of the die pad DPH of the lead frame via the bonding material BDH, the semiconductor chip CPC is mounted on the upper surface DPLa of the die pad DPL via the bonding material BDC, and the semiconductor chip CPL is mounted on the upper surface DPLa of the die pad DPL via the bonding material BDL. At this time, the semiconductor chips CPC, CPH, and CPL are mounted with their back surfaces facing the die pad. Thereafter, the bonding materials BDC, BDH, and BDL are hardened by heat treatment or the like.

[0076] Next, a wire bonding process is performed. In the wire bonding process, pad PL1 of the semiconductor chip CPL and pad PC1 of the semiconductor chip CPC, and pad PL2 of the semiconductor chip CPL and pad PC2 of the semiconductor chip CPC are electrically connected via wires BW, respectively. Also, pad PH1 of the semiconductor chip CPH and pad PC3 of the semiconductor chip CPC, and pad PH2 of the semiconductor chip CPH and pad PC4 of the semiconductor chip CPC are electrically connected via wires BW, respectively. Also, pad PH3 of the semiconductor chip CPH and lead LD1, and pad PL3 of the semiconductor chip CPL and lead LD2 are electrically connected via wires BW, respectively.

[0077] Next, resin sealing is performed in a molding process (resin molding process) to form a sealing portion MR that seals the die pads DPH, DPL, the semiconductor chips CPC, CPH, CPL, the wires BW, and the inner lead portions of the leads LD.

[0078] Next, a plating layer (not shown) is formed as needed on the outer lead portion of the lead LD exposed from the sealing portion MR. After that, outside the sealing portion MR, the lead LD is cut at a predetermined position and separated from the frame of the lead frame.

[0079] Next, the outer lead portion of the lead LD protruding from the sealing portion MR is bent (lead processing, lead forming).

[0080] In this manner, the semiconductor device PKG shown in FIGS. 2 to 9 is manufactured.

[0081] <About semiconductor chips> 10 and 11 are cross-sectional views schematically showing the semiconductor chips CPC, CPH, and CPL in the semiconductor device PKG. Fig. 10 corresponds to a cross-sectional view passing through pads PL1, PC1, PC3, and PH1, and Fig. 11 corresponds to a cross-sectional view passing through pads PL2, PC2, PC4, and PH2. In Fig. 10 and 11, the die pads DPH and DPL, the semiconductor chips CPC, CPH, and CPL, and the wires BW are shown, but the sealing portion MR is not shown.

[0082] As shown in Figures 10 and 11, the semiconductor chip CPC has a semiconductor substrate SB1, a multilayer wiring structure MW1 formed thereon, and a protective film PA1 formed thereon. The multilayer wiring structure MW1 includes multiple interlayer insulating films and multiple wiring layers. The protective film PA1 is a protective film located in the uppermost layer of the semiconductor chip CPC. Wires BW are connected to pads PC1, PC2, PC3, and PC4 exposed from openings in the protective film PA1, respectively.

[0083] The semiconductor chip CPC also includes coils L1a, L1b, L2a, and L2b, which are formed by wiring layers that make up the multilayer wiring structure MW1. Coils L1a and L1b are shown in Figure 10, and coils L2a and L2b are shown in Figure 11. Figures 10 and 11 also schematically show wirings WR1 and WR2 within the semiconductor chip CPC.

[0084] Of the coils L1a and L1b constituting the transformer TR1, the coil L1a is electrically connected to the pad PL1 of the semiconductor chip CPL via the pad PC1 of the semiconductor chip CPC and the wire BW, and the coil L1b is electrically connected to the pad PH1 of the semiconductor chip CPH via the pad PC3 of the semiconductor chip CPC and the wire BW (see FIG. 10).Furthermore, of the coils L2a and L2b constituting the transformer TR2, the coil L2a is electrically connected to the pad PL2 of the semiconductor chip CPL via the pad PC2 of the semiconductor chip CPC and the wire BW, and the coil L2b is electrically connected to the pad PH2 of the semiconductor chip CPH via the pad PC4 of the semiconductor chip CPC and the wire BW (see FIG. 11).

[0085] In the semiconductor chip CPC, the coils L1a and L1b are formed so as to overlap each other in a planar view, and the coils L2a and L2b are formed so as to overlap each other in a planar view. In FIGS. 10 and 11, in the semiconductor chip CPC, the coil L1a is formed below the coil L1b, and the coil L2a is formed below the coil L2b. The pad PC3 is connected to the coil L1b, the pad PC4 is connected to the coil L2b, the pad PC1 is connected to the coil L1a via the wiring WR1, and the pad PC2 is connected to the coil L2a via the wiring WR2. Alternatively, in the semiconductor chip CPC, the coil L1b may be formed below the coil L1a, and the coil L2b may be formed below the coil L2a. Each of the coils L1a, L1b, L2a, and L2b is formed by a spiral conductor pattern (wiring pattern).

[0086] No semiconductor element (i.e., transistor such as the above-mentioned MOSFET) is formed in the semiconductor chip CPC. In other words, no semiconductor element (i.e., transistor such as the above-mentioned MOSFET) is formed on the semiconductor substrate SB1 constituting the semiconductor chip CPC.

[0087] The semiconductor chip CPL has a semiconductor substrate SB2, a multilayer wiring structure MW2 formed thereon, and a protective film PA2 formed thereon. The multilayer wiring structure MW2 includes multiple interlayer insulating films and multiple wiring layers. The protective film PA2 is a protective film located in the uppermost layer of the semiconductor chip CPL. A plurality of semiconductor elements (not shown), such as transistors, are formed on the semiconductor substrate SB2 that constitutes the semiconductor chip CPL. Wires BW are connected to pads PL1, PL2, and PL3 exposed from openings in the protective film PA2, respectively.

[0088] The semiconductor chip CPH has a semiconductor substrate SB3, a multilayer wiring structure MW3 formed thereon, and a protective film PA3 formed thereon. The multilayer wiring structure MW3 includes multiple interlayer insulating films and multiple wiring layers. The protective film PA3 is a protective film located in the uppermost layer of the semiconductor chip CPH. A plurality of semiconductor elements (not shown), such as transistors, are formed on the semiconductor substrate SB3 that constitutes the semiconductor chip CPH. Wires BW are connected to pads PH1, PH2, and PH3 exposed from openings in the protective film PA3, respectively.

[0089] <About the process of the review> FIG. 12 is a plan perspective view of a semiconductor device PKG101 of a first study example studied by the present inventors, and corresponds to FIG. 3 above.

[0090] 12 has a die pad DPH101 and a die pad DPL101 instead of the die pads DPH and DPL described above. A semiconductor chip CPH101 corresponding to the semiconductor chip CPH and a semiconductor chip CPC101 corresponding to the semiconductor chip CPC are mounted on the die pad DPH101, and a semiconductor chip CPL101 corresponding to the semiconductor chip CPL is mounted on the die pad DPL101.

[0091] In the case of the semiconductor device PKG101 of the first studied example, three semiconductor chips CPL101, CPC101, and CPH101 are aligned in a row in the Y direction as shown in Fig. 12. In this case, the inventors have found through their studies that the following problem may occur.

[0092] First, as described above, a semiconductor chip operated at a low voltage has a transmitting circuit and a receiving circuit formed therein, while a semiconductor chip operated at a high voltage has not only a transmitting circuit and a receiving circuit but also a driving circuit formed therein. Therefore, it is difficult to make the planar dimensions (planar area) of the high-voltage semiconductor chips CPH, CPH101 smaller than those of the low-voltage semiconductor chips CPL, CPL101. In other words, the planar dimensions (planar area) of the low-voltage semiconductor chips CPL, CPL101 can be made smaller than those of the high-voltage semiconductor chips CPH, CPH101. Furthermore, in recent years, with the increasing functionality of semiconductor devices and the increase in current flowing in the circuits (such as inverter circuits) used, the planar dimensions of the high-voltage semiconductor chips CPH, CPH101 have tended to increase compared to those of the low-voltage semiconductor chips CPL, CPL101.

[0093] Furthermore, as mentioned above, the semiconductor chip on which the multiple transformers are formed does not have a transmitting circuit, a receiving circuit, or a driving circuit formed therein, so the planar dimensions (planar area) of the semiconductor chips CPC and CPC101 can be made smaller than those of the high-voltage semiconductor chips CPH and CPH101.

[0094] When three semiconductor chips CPL101, CPC101, and CPH101 are arranged in a row in the Y direction, as in the semiconductor device PKG101 of the first studied example, the dimension of the semiconductor device PKG101 in the Y direction increases. This results in an increase in the size of the semiconductor device PKG101. In order to reduce the dimension of the semiconductor device PKG101 in the Y direction, it is effective to reduce the dimension of each semiconductor chip CPL101, CPC101, and CPH101 in the Y direction. However, reducing the dimension of each semiconductor chip CPL101, CPC101, and CPH101 in the Y direction requires increasing the dimension of each semiconductor chip CPL101, CPC101, and CPH101 in the X direction, which increases the aspect ratio (ratio of the length of the long side to the length of the short side) of each semiconductor chip CPL101, CPC101, and CPH101. When the aspect ratio of a semiconductor chip increases, cracks tend to occur in the semiconductor chip, for example, when cutting a semiconductor wafer to obtain the semiconductor chip, when transporting the semiconductor chip, etc. This reduces the manufacturing yield of the semiconductor chip and the manufacturing yield of the semiconductor device incorporating the semiconductor chip.

[0095] 12, the planar dimensions of the semiconductor chip CPL101 and the semiconductor chip CPC101 are smaller than the planar dimensions of the semiconductor chip CPH101. Therefore, if the X-direction dimensions of these three semiconductor chips CPL101, CPC101, and CPH101 are made the same, the aspect ratios of the semiconductor chip CPL101 and the semiconductor chip CPC101 will be significantly larger than the aspect ratio of the semiconductor chip CPH101. For this reason, the above-mentioned crack problem is of particular concern for the semiconductor chips CPL101 and CPC101, which have large aspect ratios.

[0096] <Main features and effects> One of the main features of the semiconductor device PKG of this embodiment is that, as shown in FIG. 4 , a semiconductor chip CPH is mounted (disposed) on a die pad DPH, and a semiconductor chip CPC and a semiconductor chip CPL are mounted (disposed) on a die pad DPL located adjacent to the die pad DPH in the Y direction so as to be adjacent to each other in the X direction perpendicular to the Y direction. As described above, the lengths of the sides SL1, SL2, SL3, and SL4 of the semiconductor chip CPL are shorter than the length of the side SH3 of the semiconductor chip CPH. Furthermore, the lengths of the sides SC1, SC2, SC3, and SC4 of the semiconductor chip CPC are also shorter than the length of the side SH3 of the semiconductor chip CPH. Therefore, by adopting the above-described layout, the dimension of the semiconductor device PKG of this embodiment in the Y direction can be reduced without increasing the aspect ratios of the semiconductor chips CPC and CPL. That is, the semiconductor device PKG can be miniaturized. Furthermore, since the semiconductor device PKG can be miniaturized without increasing the aspect ratio of each of the semiconductor chips CPC and CPL, the risk of cracks occurring in each of the semiconductor chips CPL and CPC, for example, when obtaining semiconductor chips by cutting a semiconductor wafer or when transporting the semiconductor chips, can be reduced. This makes it possible to improve the manufacturing yield of the semiconductor chips CPL and CPC and the manufacturing yield of the semiconductor device PKG. As a result, the manufacturing cost of the semiconductor device PKG can be reduced.

[0097] Another main feature of the semiconductor device PKG of this embodiment is that, on the surface of the semiconductor chip CPL, a plurality of pads PL1 and PL2 are arranged along the side SL2 of the semiconductor chip CPL; on the surface of the semiconductor chip CPH, a plurality of pads PH1 and PH2 are arranged along the side SH3; on the surface of the semiconductor chip CPH, a plurality of pads PC1 and PC2 are arranged along the side SC3 of the semiconductor chip CPC, and a plurality of pads PC3 and PC4 are arranged along the side SC1 of the semiconductor chip CPC. In the semiconductor chip CPC, the sides SC1 and SC3 are located opposite each other. In plan view, the semiconductor chip CPL and the semiconductor chip CPC are arranged along the side SH3 of the semiconductor chip CPH so that the side SC3 of the semiconductor chip CPC faces the side SL2 of the semiconductor chip CPL and the side SC1 of the semiconductor chip CPC faces the side SH3 of the semiconductor chip CPH. This can improve the manufacturing yield of the semiconductor device PKG. Furthermore, the performance of the semiconductor device PKG can be improved.

[0098] 13 is a plan perspective view of a semiconductor device PKG201 of a second study example studied by the present inventors. Fig. 13 corresponds to Fig. 4 above, and does not show the wires BW.

[0099] 13, the semiconductor device PKG201 of the second studied example has a semiconductor chip CPH mounted on a die pad DPH, and the semiconductor chip CPL and the semiconductor chip CPC201 arranged adjacent to each other in the X direction on the die pad DPL. Here, the semiconductor chip CPC201 of the second studied example has a structure similar to that of the semiconductor chip CPC of the present embodiment, but the orientation of the semiconductor chip CPC201 is different from that of the semiconductor chip CPC of the present embodiment. Therefore, like the semiconductor chip CPC, the semiconductor chip CPC201 has built-in transformers TR1 and TR2 and four sides SC1, SC2, SC3, and SC4 and a plurality of pads PC1, PC2, PC3, and PC4. The positions of the pads PC1, PC2, PC3, and PC4 on the semiconductor chip CPC201 are the same as the positions of the pads PC1, PC2, PC3, and PC4 on the semiconductor chip CPC. Therefore, on the surface of the semiconductor chip CPC201, the pads PC3 and PC4 are arranged along the side SC1 of the semiconductor chip CPC201, and the pads PC1 and PC2 are arranged along the side SC3 of the semiconductor chip CPC201.

[0100] 13, the semiconductor chip CPC201 is arranged such that, in a plan view, SC1 and SC3 of the semiconductor chip CPC201 are parallel to the Y direction and SC2 and SC4 of the semiconductor chip CPC201 are parallel to the X direction. Therefore, in a plan view, the side SC3 of the semiconductor chip CPC201 and the side SL2 of the semiconductor chip CPL face each other, and therefore the multiple pads PC1 and PC2 arranged along the side SC3 on the surface of the semiconductor chip CPC201 can be connected to the multiple pads PL1 and PL2 of the semiconductor chip CPL via multiple wires.

[0101] However, in the case of the semiconductor device PKG201 of the second study example shown in FIG. 13 , in a plan view, the side SC1 of the semiconductor chip CPC201 does not face the side SH3 of the semiconductor chip CPH, but the side SC4 of the semiconductor chip CPC201 faces the side SH3 of the semiconductor chip CPH. Therefore, it is difficult to connect the pads PC3 and PC4 arranged along the side SC1 on the surface of the semiconductor chip CPC201 to the pads PH1 and PH2 of the semiconductor chip CPH via multiple wires. If the pads PC3 and PC4 of the semiconductor chip CPC201 and the pads PH1 and PH2 of the semiconductor chip CPH are connected via multiple wires, there is a concern that the multiple wires may short-circuit. Therefore, even if the semiconductor device PKG201 is manufactured, the manufacturing yield will be low.

[0102] In contrast, in the case of the semiconductor device PKG of this embodiment, in a plan view, the side SC3 of the semiconductor chip CPC faces the side SL2 of the semiconductor chip CPL, and the side SC1 of the semiconductor chip CPC faces the side SH3 of the semiconductor chip CPH. Because the side SC3 of the semiconductor chip CPC and the side SL2 of the semiconductor chip CPL face each other in a plan view, the pads PC1 and PC2 arranged along the side SC3 on the surface of the semiconductor chip CPC can be easily and accurately connected to the pads PL1 and PL2 of the semiconductor chip CPL via the wires BW. This makes it possible to accurately prevent short-circuiting between the wires BW when the pads PC1 and PC2 of the semiconductor chip CPC and the pads PL1 and PL2 of the semiconductor chip CPL are connected via the wires BW. Furthermore, since the side SC1 of the semiconductor chip CPC and the side SH3 of the semiconductor chip CPH face each other in a plan view, the pads PC3 and PC4 arranged along the side SC1 on the surface of the semiconductor chip CPC can be easily and accurately connected to the pads PH1 and PH2 of the semiconductor chip CPH via the wires BW. This effectively prevents short-circuiting between the wires BW when the pads PC3 and PC4 of the semiconductor chip CPC and the pads PH1 and PH2 of the semiconductor chip CPH are connected via the wires BW. As a result, the manufacturing yield of the semiconductor device PKG can be improved. Therefore, the manufacturing cost of the semiconductor device PKG can be reduced.

[0103] Here, in a plan view, the fact that the side SC3 of the semiconductor chip CPC faces the side SL2 of the semiconductor chip CPL and the side SC1 of the semiconductor chip CPC faces the side SH3 of the semiconductor chip CPH means that the side SC3 of the semiconductor chip CPC is inclined with respect to the side SL2 of the semiconductor chip CPL and the side SC1 of the semiconductor chip CPC is inclined with respect to the side SH3 of the semiconductor chip CPH. This is because, when the side SC3 of the semiconductor chip CPC is parallel to or perpendicular to the side SL2 of the semiconductor chip CPL and the side SC1 of the semiconductor chip CPC is parallel to or perpendicular to the side SH3 of the semiconductor chip CPH, it is not possible for the side SC3 of the semiconductor chip CPC to face the side SL2 of the semiconductor chip CPL and the side SC1 of the semiconductor chip CPC to face the side SH3 of the semiconductor chip CPH at the same time.

[0104] The inclination angle B1 of the side SC3 of the semiconductor chip CPC with respect to the side SL2 of the semiconductor chip CPL (i.e., the inclination angle of the side SC3 of the semiconductor chip CPC with respect to the Y direction) is preferably within a range of 40 to 50 degrees, and most preferably 45 degrees. Also, the inclination angle B2 of the side SC1 of the semiconductor chip CPC with respect to the side SH3 of the semiconductor chip CPH (i.e., the inclination angle of the side SC1 of the semiconductor chip CPC with respect to the X direction) is preferably within a range of 40 to 50 degrees, and most preferably 45 degrees. This makes it easier to easily and accurately connect the multiple pads PC1, PC2 of the semiconductor chip CPC to the multiple pads PL1, PL2 of the semiconductor chip CPL via the multiple wires BW, and to easily and accurately connect the multiple pads PC3, PC4 of the semiconductor chip CPC to the multiple pads PH1, PH2 of the semiconductor chip CPH via the multiple wires BW.

[0105] Furthermore, in this embodiment, the semiconductor chip CPC is mounted on the die pad DPL, not on the die pad DPH. Compared to the die pad DPH on which the semiconductor chip CPH is mounted, the die pad DPL on which the semiconductor chip CPL is mounted is less susceptible to voltage fluctuations. This is because the semiconductor chip CPL is electrically connected to the low-voltage region via wires BW and leads LD2, etc., and the semiconductor chip CPH is electrically connected to the high-voltage region via wires BW and leads LD1, etc. Therefore, compared to when the semiconductor chip CPC is mounted on the die pad DPH, when the semiconductor chip CPC is mounted on the die pad DPL, voltage fluctuations in the die pad DPL are less likely to occur, thereby suppressing noise from occurring in signals transmitted via the transformers TR1 and TR2 in the semiconductor chip CPC. As a result, the performance of the semiconductor device PKG can be improved.

[0106] In this embodiment, two transformers TR1 and TR2 are built in the semiconductor chip CPC. As a modified example, there may be a case where only one transformer is built in the semiconductor chip CPC. For example, in the semiconductor device PKG, if the semiconductor chip CPC does not have the transformer TR2 built in but has the transformer TR1 built in, the semiconductor chip CPC has pads PC1 and PC3 but does not have pads PC2 and PC4, the semiconductor chip CPL has pads PL1 and PL3 but does not have the pad PL2, and the semiconductor chip CPH has pads PH1 and PH3 but does not have the pad PH2.

[0107] In this embodiment, the semiconductor chip CPC is illustrated with two pads electrically connected to each of the coils L1a, L1b, L2a, and L2b. Alternatively, the semiconductor chip CPC may have three or more pads electrically connected to each of the coils L1a, L1b, L2a, and L2b. For example, if each coil is a differential type, the number of pads electrically connected to that coil is three. In this case, the number of pads PC1, PC2, PC3, and PC4 is three. The number of pads PL1 is the same as the number of pads PC1, the number of pads PL2 is the same as the number of pads PC2, the number of pads PH1 is the same as the number of pads PC3, and the number of pads PH2 is the same as the number of pads PC4. This also applies to the following second to sixth embodiments.

[0108] (Embodiment 2) 14 and 15 are planar perspective views of the semiconductor device PKG (hereinafter referred to as the semiconductor device PKG1) of the present embodiment 2. Fig. 14 corresponds to Fig. 3 above, and Fig. 15 corresponds to Fig. 4 above.

[0109] 14 and 15, the structure of the semiconductor device PKG1 of the present second embodiment will be described, focusing on the differences from the semiconductor device PKG of the above-described first embodiment. Repetitive description of the points that the semiconductor device PKG1 of the present second embodiment has in common with the semiconductor device PKG of the above-described first embodiment will be omitted.

[0110] 14 and 15, the semiconductor device PKG1 of the second embodiment has two semiconductor chips CPC1 and CPC2 instead of the semiconductor chip CPC. The semiconductor chips CPC1 and CPC2 are sealed with a sealing portion MR. Of the transformers TR1 and TR2, the transformer TR1 (coils L1a and L1b) is formed in the semiconductor chip CPC1, and the transformer TR2 (coils L2a and L2b) is formed in the semiconductor chip CPC2. Therefore, of the pads PC1, PC2, PC3, and PC4, the pads PC1 and PC3 are formed on the semiconductor chip CPC1, and the pads PC2 and PC4 are formed on the semiconductor chip CPC2.

[0111] In the semiconductor device PKG1 of this second embodiment, three semiconductor chips CPL, CPC1, and CP2 are mounted on the die pad DPL via bonding material, and one semiconductor chip CPH is mounted on the die pad DPH via bonding material.

[0112] Each of the semiconductor chips CPC1 and CPC2 has a front surface, which is one of the main surfaces, and a back surface, which is the main surface opposite to the front surface. The planar shape of each of the semiconductor chips CPC1 and CPC2 is quadrangular, preferably rectangular. Therefore, in a planar view, the semiconductor chip CPC1 has four sides SC1a, SC2a, SC3a, and SC4a, and the semiconductor chip CPC2 has four sides SC1b, SC2b, SC3b, and SC4b.

[0113] Of the four sides SC1a, SC2a, SC3a, and SC4a of the semiconductor chip CPC1, sides SC1a and SC3a are located opposite each other, sides SC2a and SC4a are located opposite each other, side SC1a intersects with sides SC2a and SC4a, and side SC3a intersects with sides SC2a and SC4a. Furthermore, of the four sides SC1b, SC2b, SC3b, and SC4b of the semiconductor chip CPC2, sides SC1b and SC3b are located opposite each other, sides SC2b and SC4b are located opposite each other, side SC1b intersects with sides SC2b and SC4b, and side SC3b intersects with sides SC2b and SC4b. The front and back surfaces of the semiconductor chips CPC1 and CPC2 are each substantially parallel to both the X and Y directions.

[0114] In a plan view, the semiconductor chip CPC1 is adjacent to the semiconductor chip CPL in the X direction, the semiconductor chip CPC2 is adjacent to the semiconductor chip CPL in the X direction, and the semiconductor chip CPL is arranged between the semiconductor chip CPC1 and the semiconductor chip CPC2 in the X direction. Therefore, the semiconductor chip CPC1, the semiconductor chip CPL, and the semiconductor chip CPC2 are arranged along the side SH3 of the semiconductor chip CPH. Each of the semiconductor chips CPC1, CPC2, and CPL is adjacent to the semiconductor chip CPH in the Y direction.

[0115] In the second embodiment, in a plan view, the side SC3a of the semiconductor chip CPC1 and the side SL2 of the semiconductor chip CPL face each other, and the side SC1a of the semiconductor chip CPC1 and the side SH3 of the semiconductor chip CPH face each other. Note that, in a plan view, the side SC3a of the semiconductor chip CPC1 is inclined with respect to the side SL2 of the semiconductor chip CPL, and the side SC1a of the semiconductor chip CPC1 is inclined with respect to the side SH3 of the semiconductor chip CPH. Also, in a plan view, the side SC2b of the semiconductor chip CPC2 and the side SL4 of the semiconductor chip CPL face each other, and the side SC4b of the semiconductor chip CPC2 and the side SH3 of the semiconductor chip CPH face each other. Note that, in a plan view, the side SC2b of the semiconductor chip CPC2 is inclined with respect to the side SL4 of the semiconductor chip CPL, and the side SC4b of the semiconductor chip CPC2 is inclined with respect to the side SH3 of the semiconductor chip CPH.

[0116] Each of the sides SC1a, SC2a, SC3a, SC4a, SC1b, SC2b, SC3b, and SC4b of the semiconductor chips CPC1 and CPC2 is inclined with respect to the X direction and with respect to the Y direction. Therefore, each of the sides SC1a, SC2a, SC3a, SC4a, SC1b, SC2b, SC3b, and SC4b of the semiconductor chips CPC1 and CPC2 is not parallel to either the X direction or the Y direction. The inclination angle with respect to the X direction of each of the sides SC1a, SC2a, SC3a, SC4a, SC1b, SC2b, SC3b, and SC4b of the semiconductor chips CPC1 and CPC2 is preferably within a range of 40 to 50 degrees, and most preferably 45 degrees.

[0117] In the second embodiment, on the surface of the semiconductor chip CPL, a plurality of pads PL1 are arranged along a side SL2 of the semiconductor chip CPL, a plurality of pads PL2 are arranged along a side SL4 of the semiconductor chip CPL, and a plurality of pads PL3 are arranged along the side SL3 of the semiconductor chip CPL. Also, on the surface of the semiconductor chip CPH, a plurality of pads PH1 are arranged along a side SH3 of the semiconductor chip CPH, a plurality of pads PH2 are arranged along the side SH3 of the semiconductor chip CPH, and a plurality of pads PH3 are arranged along the side SH1 of the semiconductor chip CPH. Note that the plurality of pads PH1 are arranged near the side SH2 of the semiconductor chip CPH, and the plurality of pads PH2 are arranged near the side SH4 of the semiconductor chip CPH. Also, on the surface of the semiconductor chip CPC1, a plurality of pads PC1 are arranged along a side SC3a of the semiconductor chip CPC1, and a plurality of pads PC3 are arranged along the side SC1a of the semiconductor chip CPC1. Moreover, on the surface of the semiconductor chip CPC2, the multiple pads PC2 are arranged along a side SC2b of the semiconductor chip CPC2, and the multiple pads PC4 are arranged along a side SC4b of the semiconductor chip CPC2. In a plan view, the distance (distance in the Y direction) between the semiconductor chip CPH and a corner formed by sides SC4a and SC1a, among the four corners of the semiconductor chip CPC1, is shorter than the distance (distance in the Y direction) between the semiconductor chip CPH and the other corners of the semiconductor chip CPC1. In a plan view, the distance (distance in the Y direction) between the semiconductor chip CPH and a corner formed by sides SC4b and SC1b, among the four corners of the semiconductor chip CPC2, is shorter than the distance (distance in the Y direction) between the semiconductor chip CPH and the other corners of the semiconductor chip CPC2.

[0118] Next, the effects of the semiconductor device PKG1 of the second embodiment will be described.

[0119] In the semiconductor device PKG1 of the second embodiment, the semiconductor chip CPH is disposed on the die pad DPH, and the semiconductor chips CPC1, CPC2, and CPL are disposed on the die pad DPL located adjacent to the die pad DPH in the Y direction. The semiconductor chips CPC1 and CPL are adjacent to each other in the X direction, the semiconductor chip CPC2 and CPL are adjacent to each other in the X direction, and the semiconductor chip CPL is located between the semiconductor chips CPC1 and CPC2 in the X direction. This allows the dimension of the semiconductor device PKG in the Y direction to be reduced without increasing the aspect ratios of the semiconductor chips CPC1, CPC2, and CPL. This allows the semiconductor device PKG1 to be miniaturized. Furthermore, since the aspect ratios of the semiconductor chips CPC1, CPC2, and CPL can be reduced, the risk of cracks occurring in the semiconductor chips CPL, CPC1, and CPC2 can be reduced, for example, when a semiconductor wafer is cut to obtain semiconductor chips or when the semiconductor chips are transported. This makes it possible to improve the manufacturing yield of the semiconductor chips CPL, CPC1, CPC2 and the manufacturing yield of the semiconductor device PKG1.

[0120] In the semiconductor device PKG1 of the second embodiment, the side SC1a of the semiconductor chip CPC1 and the side SH3 of the semiconductor chip CPH face each other in a plan view. Therefore, the pads PC3 arranged along the side SC1a on the surface of the semiconductor chip CPC1 can be easily and accurately connected to the pads PH1 of the semiconductor chip CPH via the wires BW. Furthermore, the side SC3a of the semiconductor chip CPC1 and the side SL2 of the semiconductor chip CPL face each other in a plan view. Therefore, the pads PC1 arranged along the side SC3a on the surface of the semiconductor chip CPC1 can be easily and accurately connected to the pads PL1 of the semiconductor chip CPL via the wires BW. Furthermore, the side SC4b of the semiconductor chip CPC2 and the side SH3 of the semiconductor chip CPH face each other in a plan view. Therefore, the pads PC4 arranged along the side SC4b on the surface of the semiconductor chip CPC2 can be easily and accurately connected to the pads PH2 of the semiconductor chip CPH via the wires BW. In addition, in a plan view, the side SC2b of the semiconductor chip CPC2 and the side SL4 of the semiconductor chip CPL face each other. Therefore, the pads PC2 arranged along the side SC2b on the surface of the semiconductor chip CPC2 can be easily and accurately connected to the pads PL2 of the semiconductor chip CPL via the wires BW. Since it is possible to accurately prevent adjacent wires BW from shorting each other, it is possible to improve the manufacturing yield of the semiconductor device PKG1.

[0121] Furthermore, in the semiconductor device PKG1 of the second embodiment, the semiconductor chips CPC1 and CPC2 are mounted on the die pad DPL, not on the die pad DPH. Therefore, compared to when the semiconductor chips CPC1 and CPC2 are mounted on the die pad DPH, when the semiconductor chips CPC1 and CPC2 are mounted on the die pad DPL, voltage fluctuations on the die pad DPL are less likely to occur, which makes it possible to suppress noise from occurring in signals transmitted via the transformers TR1 and TR2 in the semiconductor chips CPC1 and CPC2. As a result, the performance of the semiconductor device PKG1 can be improved.

[0122] Furthermore, in the second embodiment, the transformer TR1 (coils L1a and L1b) is formed within the semiconductor chip CPC1, and the transformer TR2 (coils L2a and L2b) is formed within the semiconductor chip CPC2. This reduces coupling noise between the transformers TR1 and TR2. That is, signals transmitted via the transformer TR1 and signals transmitted via the transformer TR2 are electromagnetically separated and prevented from interfering with each other. This further improves the performance of the semiconductor device PKG1.

[0123] On the other hand, in the case of the first embodiment, the transformer TR1 (coils L1a, L1b) and the transformer TR2 (coils L2a, L2b) are formed in the semiconductor chip CPC, so that the number of semiconductor chips included in the semiconductor device PKG can be reduced, and therefore the manufacturing cost of the semiconductor device PKG can be reduced.

[0124] (Embodiment 3) 16 is a circuit diagram showing an inverter circuit using the semiconductor device PKG of the present third embodiment (hereinafter referred to as the semiconductor device PKG2), and corresponds to FIG. 1 above. FIGS. 17 and 18 are planar perspective views of the semiconductor device PKG2 of the present third embodiment. FIG. 17 corresponds to FIG. 3 above, and FIG. 18 corresponds to FIG. 4 above.

[0125] 16 to 18, the structure of the semiconductor device PKG2 of the present embodiment 3 will be described, focusing on the differences from the semiconductor device PKG of the above-described embodiment 1. Repetitive description of the points that the semiconductor device PKG2 of the present embodiment 3 has in common with the semiconductor device PKG of the above-described embodiment 1 will be omitted.

[0126] In the third embodiment, as shown in Fig. 16, not only transformers TR1 and TR2 but also a transformer TR3 consisting of coils L3a and L3b magnetically coupled to each other is formed within the semiconductor chip CPC. Therefore, as shown in Fig. 17 and Fig. 18, the semiconductor chip CPC has pads PC1, PC2, PC3, and PC4, as well as a plurality of pads PC5 electrically connected to the coil L3a and a plurality of pads PC6 electrically connected to the coil L3b. On the surface of the semiconductor chip CPC, the plurality of pads PC1, PC2, and PC5 are arranged along a side SC3 of the semiconductor chip CPC, and the plurality of pads PC3, PC4, and PC6 are arranged along a side SC1 of the semiconductor chip CPC.

[0127] In the third embodiment, as shown in FIG. 16, not only the transmitter circuit TX1 and receiver circuit RX2 but also the transmitter / receiver circuit TRX1 are formed within the semiconductor chip CPL. Furthermore, not only the receiver circuit RX1, transmitter circuit TX2, and driver circuit DR but also the transmitter / receiver circuit TRX2 are formed within the semiconductor chip CPH. The transmitter / receiver circuit TRX1 functions as both a transmitter circuit and a receiver circuit. Similarly, the transmitter / receiver circuit TRX2 functions as both a transmitter circuit and a receiver circuit. Therefore, the transmitter / receiver circuit TRX2 can receive a signal transmitted from the transmitter / receiver circuit TRX1 via the transformer TR3, and the transmitter / receiver circuit TRX1 can receive a signal transmitted from the transmitter / receiver circuit TRX2 via the transformer TR3.

[0128] 17 and 18, the semiconductor chip CPL has pads PL1, PL2, and PL3, as well as a plurality of pads PL4 electrically connected to the transceiver circuit TRX1. On the surface of the semiconductor chip CPL, the plurality of pads PL1, PL2, and PL4 are arranged along a side SL2 of the semiconductor chip CPL, and the plurality of pads PL3 are arranged along a side SL3 of the semiconductor chip CPL. The plurality of pads PL4 of the semiconductor chip CPL are electrically connected to a plurality of pads PC5 of the semiconductor chip CPC via a plurality of wires BW. Furthermore, the semiconductor chip CPH has pads PH1, PH2, and PH3, as well as a plurality of pads PH4 electrically connected to the transceiver circuit TRX2. On the surface of the semiconductor chip CPH, the plurality of pads PH1, PH2, and PH4 are arranged along a side SH3 of the semiconductor chip CPH, and the plurality of pads PH3 are arranged along a side SH1 of the semiconductor chip CPH. The pads PH4 of the semiconductor chip CPH are electrically connected to the pads PC6 of the semiconductor chip CPC via the wires BW, respectively.

[0129] In the semiconductor device PKG2 of the third embodiment, the three semiconductor chips CPL, CPC, and CPH are arranged in the same manner as in the semiconductor device PKG of the first embodiment. Therefore, in the third embodiment, substantially the same effects as those of the first embodiment can be obtained. That is, in addition to the effects described in the first embodiment, the pads PC6 arranged along the side SC1 on the surface of the semiconductor chip CPC can be easily and accurately connected to the pads PH4 of the semiconductor chip CPH via the wires BW. Furthermore, the pads PC5 arranged along the side SC3 on the surface of the semiconductor chip CPC can be easily and accurately connected to the pads PL4 of the semiconductor chip CPL via the wires BW. Since it is possible to accurately prevent adjacent wires BW from shorting each other, the manufacturing yield of the semiconductor device PKG2 can be improved.

[0130] As a modification of the third embodiment, the number of transformers formed in the semiconductor chip CPC can be four or more.

[0131] (Fourth embodiment) 19 and 20 are planar perspective views of the semiconductor device PKG (hereinafter referred to as semiconductor device PKG3) of the present embodiment 4. Fig. 19 corresponds to Fig. 3 above, and Fig. 20 corresponds to Fig. 4 above.

[0132] 19 and 20, the structure of the semiconductor device PKG3 of the present embodiment 4 will be described, focusing on the differences from the semiconductor device PKG1 of the above-described embodiment 2. Repetitive description of the points that the semiconductor device PKG3 of the present embodiment 4 has in common with the semiconductor device PKG1 of the above-described embodiment 2 will be omitted.

[0133] A circuit diagram of an inverter circuit using the semiconductor device PKG3 of the fourth embodiment is substantially the same as the circuit diagram of Fig. 16 except that two semiconductor chips CPC1 and CPC2 are used instead of the semiconductor chip CPC. Therefore, in the fourth embodiment, of the transformers TR1, TR2, and TR3 shown in the circuit diagram of Fig. 16, the transformer TR1 (coils L1a and L1b) and the transformer TR3 (coils L3a and L3b) are formed in the semiconductor chip CPC1, and the transformer TR2 (coils L2a and L2b) is formed in the semiconductor chip CPC2. Also, in the fourth embodiment, as shown in Fig. 16, not only the transmitter circuit TX1 and the receiver circuit RX2 but also the transmitter / receiver circuit TRX1 are formed in the semiconductor chip CPL, and not only the receiver circuit RX1, the transmitter circuit TX2, and the driver circuit DR but also the transmitter / receiver circuit TRX2 are formed in the semiconductor chip CPH.

[0134] Reflecting this, in this embodiment 4, pads PC1, PC3, PC5, and PC6 are formed on the semiconductor chip CPC1, pads PC2 and PC4 are formed on the semiconductor chip CPC2, pads PL1, PL2, PL3, and PL4 are formed on the semiconductor chip CPL, and pads PH1, PH2, PH3, and PH4 are formed on the semiconductor chip CPH.

[0135] On the surface of the semiconductor chip CPC1, the pads PC1 and PC5 are arranged along a side SC3a of the semiconductor chip CPC1, and the pads PC3 and PC6 are arranged along a side SC1a of the semiconductor chip CPC1. On the surface of the semiconductor chip CPC2, the pads PC2 are arranged along a side SC2b of the semiconductor chip CPC2, and the pads PC4 are arranged along a side SC4b of the semiconductor chip CPC2. On the surface of the semiconductor chip CPL, the pads PL1 and PL4 are arranged along a side SL2 of the semiconductor chip CPL, the pads PL2 are arranged along a side SL4 of the semiconductor chip CPL, and the pads PL3 are arranged along the side SL3 of the semiconductor chip CPL. The pads PL4 of the semiconductor chip CPL are electrically connected to the pads PC5 of the semiconductor chip CPC1 via the wires BW, respectively. On the surface of the semiconductor chip CPH, a plurality of pads PH1 and PH4 are arranged along a side SH3 of the semiconductor chip CPH near the side SH2, a plurality of pads PH2 are arranged along the side SH3 of the semiconductor chip CPH near the side SH4, and a plurality of pads PH3 are arranged along the side SH1 of the semiconductor chip CPH. The plurality of pads PH4 of the semiconductor chip CPH are electrically connected to a plurality of pads PC6 of the semiconductor chip CPC1 via a plurality of wires BW, respectively.

[0136] In the semiconductor device PKG3 of the fourth embodiment, the arrangement of the four semiconductor chips CPL, CPC1, CPC2, and CPH is the same as that of the semiconductor device PKG1 of the second embodiment. Therefore, in the fourth embodiment, substantially the same effects as those of the second embodiment can be obtained. That is, in addition to the effects described in the second embodiment, the pads PC6 arranged along the side SC1a on the surface of the semiconductor chip CPC1 can be easily and accurately connected to the pads PH4 of the semiconductor chip CPH via the wires BW. Furthermore, the pads PC5 arranged along the side SC3a on the surface of the semiconductor chip CPC1 can be easily and accurately connected to the pads PL4 of the semiconductor chip CPL via the wires BW. Since it is possible to accurately prevent adjacent wires BW from shorting each other, the manufacturing yield of the semiconductor device PKG3 can be improved.

[0137] As a modification of the fourth embodiment, the number of transformers formed in the semiconductor chip CPC2 may be two or more. Also, the number of transformers formed in the semiconductor chip CPC1 may be three or more.

[0138] (Embodiment 5) Fig. 21 is a circuit diagram showing a DC-DC converter circuit using the semiconductor device PKG of the present fifth embodiment (hereinafter referred to as semiconductor device PKG4), and corresponds to Fig. 1 above. Figs. 22 and 23 are planar perspective views of the semiconductor device PKG4 of the present fifth embodiment. Fig. 22 corresponds to Fig. 3 above, and Fig. 23 corresponds to Fig. 4 above.

[0139] 21 to 23, the structure of the semiconductor device PKG4 of the present embodiment 3 will be described, focusing on the differences from the semiconductor device PKG of the above-described embodiment 1. Repetitive description of the points that the semiconductor device PKG4 of the present embodiment 5 has in common with the semiconductor device PKG of the above-described embodiment 1 will be omitted.

[0140] 22 and 23, the semiconductor device PKG4 of the fifth embodiment has two semiconductor chips CPH1 and CPH2 instead of the semiconductor chip CPH, and has two die pads DPH1 and DPH2 instead of the die pad DPH. The die pads DPH1, DPH2, and DPL are spaced apart from one another. The semiconductor chip CPH1 is mounted on the die pad DPH1 via a bonding material, and the semiconductor chip CPH2 is mounted on the die pad DPH2 via a bonding material. The semiconductor chips CPH1 and CPH2 and the die pads DPH1 and DPH2 are sealed with a sealing portion MR. Parts of the sealing portion MR are interposed between the die pads DPH1 and DPH2, between the die pads DPH1 and DPL, and between the die pads DPH2 and DPL.

[0141] In the fifth embodiment, as shown in FIG. 21 , a receiving circuit RX1 and a driving circuit DR are formed in a semiconductor chip CPH1, and a receiving circuit RX2 and a driving circuit DR are formed in a semiconductor chip CPH2. The semiconductor chip CPH1 has a plurality of pads PH1 and PH3, and the semiconductor chip CPH2 has a plurality of pads PH2 and PH3. The plurality of pads PH1 of the semiconductor chip CPH1 are electrically connected to the receiving circuit RX1 in the semiconductor chip CPH1. The plurality of pads PH2 of the semiconductor chip CPH2 are electrically connected to the receiving circuit RX2 in the semiconductor chip CPH2. The semiconductor chip CPL has a plurality of pads PL1, PL2, and PL3, and the plurality of pads PL1 are electrically connected to the transmitting circuit TX1, and the plurality of pads PL2 are electrically connected to the transmitting circuit TX2. The configuration of the semiconductor chip CPC in the fifth embodiment is the same as that in the first embodiment.

[0142] In the fifth embodiment, as shown in FIG. 21 , one semiconductor device PKG4 is used for two power transistors TS1 and TS2. The semiconductor chip CPH1 of the semiconductor device PKG4 is connected to the power transistor TS2 used as a low-side switch, and the semiconductor chip CPH2 of the semiconductor device PKG4 is connected to the power transistor TS1 used as a high-side switch. The control circuit CC controls the gate voltage supplied to the gate G2 of the power transistor TS2 from the drive circuit DR in the semiconductor chip CPH1 in response to a signal supplied from the control circuit CC to the drive circuit DR in the semiconductor chip CPH1 via the transmitter circuit TX1 in the semiconductor chip CPL, the transformer TR1 in the semiconductor chip CPC, and the receiver circuit RX1 in the semiconductor chip CPH1. The control circuit CC also controls the gate voltage supplied to the gate G1 of the power transistor TS1 from the drive circuit DR in the semiconductor chip CPH2 in response to a signal supplied from the control circuit CC to the drive circuit DR in the semiconductor chip CPH2 via the transmitter circuit TX2 in the semiconductor chip CPL, the transformer TR2 in the semiconductor chip CPC, and the receiver circuit RX2 in the semiconductor chip CPH2.

[0143] Each of the semiconductor chips CPH1 and CPH2 has a front surface, which is one main surface, and a back surface, which is the main surface opposite the front surface. The planar shape of each of the semiconductor chips CPH1 and CPH2 is quadrangular, preferably rectangular. Therefore, in a planar view, the semiconductor chip CPH1 has four sides SH1a, SH2a, SH3a, and SH4a, and the semiconductor chip CPH2 has four sides SH1b, SH2b, SH3b, and SH4b.

[0144] Of the four sides SH1a, SH2a, SH3a, and SH4a of the semiconductor chip CPH1, sides SH1a and SH3a are located opposite each other, sides SH2a and SH4a are located opposite each other, side SH1a intersects with sides SH2a and SH4a, and side SH3a intersects with sides SH2a and SH4a. Furthermore, of the four sides SH1b, SH2b, SH3b, and SH4b of the semiconductor chip CPH2, sides SH1b and SH3b are located opposite each other, sides SH2b and SH4b are located opposite each other, side SH1b intersects with sides SH2b and SH4b, and side SH3b intersects with sides SH2b and SH4b. The sides SH1a and SH3a of the semiconductor chip CPH1 and the sides SH1b and SH3b of the semiconductor chip CPH2 are each parallel to the X direction. The sides SH2a and SH4a of the semiconductor chip CPH1 and the sides SH2b and SH4b of the semiconductor chip CPH2 are parallel to the Y direction.

[0145] The die pad DPH1 and the die pad DPH2 are adjacent to each other in the X direction. The die pad DPH1 and the die pad DPL are adjacent to each other in the Y direction. The die pad DPH2 and the die pad DPL are adjacent to each other in the Y direction. The semiconductor chip CPH1 and the semiconductor chip CPH2 are adjacent to each other in the X direction. A side SH4a of the semiconductor chip CPH1 and a side SH2b of the semiconductor chip CPH2 face each other. The semiconductor chip CPL and the semiconductor chip CPC are adjacent to each other in the X direction. The semiconductor chip CPH1 and the semiconductor chip CPC are adjacent to each other in the Y direction. The semiconductor chip CPL and the semiconductor chip CPH2 are adjacent to each other in the Y direction. A side SL1 of the semiconductor chip CPL and a side SH3b of the semiconductor chip CPH2 face each other.

[0146] In addition, in the fifth embodiment, in a plan view, the side SC3 of the semiconductor chip CPC faces the side SL2 of the semiconductor chip CPL, and the side SC1 of the semiconductor chip CPC faces the side SH3a of the semiconductor chip CPH1. This is because the semiconductor chip CPC is disposed at an incline in a plan view. That is, each of the sides SC1, SC2, SC3, and SC4 of the semiconductor chip CPC is inclined with respect to the X direction and with respect to the Y direction. Therefore, the side SC3 of the semiconductor chip CPC is inclined with respect to the side SL2 of the semiconductor chip CPL, and the side SC1 of the semiconductor chip CPC is inclined with respect to the side SH3a of the semiconductor chip CPH1. The inclination angle of each of the sides SC1, SC2, SC3, and SC4 of the semiconductor chip CPC with respect to the X direction is preferably within a range of 40 degrees to 50 degrees, and most preferably 45 degrees.

[0147] On the surface of the semiconductor chip CPH1, the pads PH1 are arranged along a side SH3a of the semiconductor chip CPH1, and the pads PH3 are arranged along a side SH1a of the semiconductor chip CPH1. On the surface of the semiconductor chip CPH2, the pads PH2 are arranged along a side SH3b of the semiconductor chip CPH2, and the pads PH3 are arranged along a side SH1b of the semiconductor chip CPH2. The directions of the sides SL1, SL2, SL3, and SL4 of the semiconductor chip CPL, the directions of the sides SC1, SC2, SC3, and SC4 of the semiconductor chip CPC, the arrangement of the pads PL1, PL2, and PL3 on the semiconductor chip CPL, and the arrangement of the pads PC1, PC2, PC3, and PC4 on the semiconductor chip CPC are the same in the fifth embodiment as in the first embodiment. Furthermore, when viewed in a plane, the distance (distance in the Y direction) between the corner formed by sides SC4 and SC1 of the four corners of the semiconductor chip CPC and the semiconductor chip CPH1 is smaller than the distance (distance in the Y direction) between the other corners of the semiconductor chip CPC and the semiconductor chip CPH1.

[0148] Next, the effects of the semiconductor device PKG4 of the fifth embodiment will be described.

[0149] In the semiconductor device PKG4 of the fifth embodiment, the semiconductor chip CPH1 is arranged on the die pad DPH1, the semiconductor chip CPH2 is arranged on the die pad DPH2 located adjacent to the die pad DPH1 in the X direction, and the semiconductor chip CPL and the semiconductor chip CPC are arranged on the die pad DPL located adjacent to the die pads DPH1 and DPH2 in the Y direction. The semiconductor chips CPH1 and CPH2 are adjacent to each other in the X direction, the semiconductor chips CPC and CPL are adjacent to each other in the X direction, and the semiconductor chips CPC and CPH1 are adjacent to each other in the Y direction. This allows the dimension of the semiconductor device PKG4 of the present embodiment in the Y direction to be reduced without increasing the aspect ratios of the semiconductor chips CPH1, CPH2, CPC, and CPL. This allows the semiconductor device PKG4 to be miniaturized. Furthermore, since the aspect ratio of each of the semiconductor chips CPH1, CPH2, CPC, and CPL can be suppressed, it is possible to suppress the risk of cracks occurring in the semiconductor chips CPH1, CPH2, CPC, and CPL, for example, when cutting a semiconductor wafer to obtain semiconductor chips, when transporting the semiconductor chips, etc. This makes it possible to improve the manufacturing yield of the semiconductor chips CPH1, CPH2, CPC, and CPL and the manufacturing yield of the semiconductor device PKG4.

[0150] In the semiconductor device PKG4 of the fifth embodiment, the side SC3 of the semiconductor chip CPC and the side SL2 of the semiconductor chip CPL face each other in a plan view. Therefore, the pads PC1 and PC2 arranged along the side SC3 on the surface of the semiconductor chip CPC can be easily and accurately connected to the pads PL1 and PL2 of the semiconductor chip CPL via the wires BW. Furthermore, the side SC1 of the semiconductor chip CPC and the side SH3a of the semiconductor chip CPH1 face each other in a plan view. Therefore, the pads PC3 arranged along the side SC1 on the surface of the semiconductor chip CPC can be easily and accurately connected to the pads PH1 of the semiconductor chip CPH1 via the wires BW. Furthermore, the pads PC4 arranged along the side SC1 on the surface of the semiconductor chip CPC can be easily and accurately connected to the pads PH2 of the semiconductor chip CPH2 via the wires BW. Since adjacent wires BW can be accurately prevented from short-circuiting, the manufacturing yield of the semiconductor device PKG4 can be improved.

[0151] In addition, in the present fifth embodiment, the number of transformers formed in the semiconductor chip CPC is two. As a modification of the present fifth embodiment, the number of transformers formed in the semiconductor chip CPC can be three or more.

[0152] (Sixth embodiment) 24 and 25 are planar perspective views of the semiconductor device PKG (hereinafter referred to as semiconductor device PKG5) according to the sixth embodiment. Fig. 24 corresponds to Fig. 3 above, and Fig. 25 corresponds to Fig. 4 above.

[0153] 24 and 25, the structure of the semiconductor device PKG5 of the present sixth embodiment will be described, focusing on the differences from the semiconductor device PKG4 of the above-described fifth embodiment. Repetitive description of the points that the semiconductor device PKG5 of the present sixth embodiment has in common with the semiconductor device PKG4 of the above-described fifth embodiment will be omitted.

[0154] A circuit diagram of a DC-DC converter circuit using the semiconductor device PKG5 of the sixth embodiment is almost the same as the circuit diagram of Fig. 21, except that two semiconductor chips CPC1 and CPC2 are used instead of the semiconductor chip CPC. Therefore, in the fourth embodiment, of the transformers TR1 and TR2 shown in the circuit diagram of Fig. 21, the transformer TR1 (coils L1a and L1b) is formed in the semiconductor chip CPC1, and the transformer TR2 (coils L2a and L2b) is formed in the semiconductor chip CPC2.

[0155] As shown in FIGS. 24 and 25, the semiconductor device PKG5 of the sixth embodiment has two semiconductor chips CPC1 and CPC2 instead of the semiconductor chip CPC. The semiconductor chips CPC1 and CPC2 are sealed with a sealing portion MR. Of the transformers TR1 and TR2 shown in the circuit diagram of FIG. 21, the transformer TR1 (coils L1a and L1b) is formed in the semiconductor chip CPC1, and the transformer TR2 (coils L2a and L2b) is formed in the semiconductor chip CPC2. Therefore, of the pads PC1, PC2, PC3, and PC4, the pads PC1 and PC3 are formed on the semiconductor chip CPC1, and the pads PC2 and PC4 are formed on the semiconductor chip CPC2. The configurations of the semiconductor chips CPC1 and CPC2 in the sixth embodiment are the same as those in the second embodiment. The arrangements of the semiconductor chips CPC1, CPC2, and CPL in the sixth embodiment are the same as those in the second embodiment.

[0156] In the semiconductor device PKG5 of this embodiment 6, three semiconductor chips CPL, CPC1, and CP2 are mounted on the die pad DPL via bonding material, one semiconductor chip CPH1 is mounted on the die pad DPH1 via bonding material, and one semiconductor chip CPH2 is mounted on the die pad DPH2 via bonding material.

[0157] The directions of the sides SL1, SL2, SL3, and SL4 of the semiconductor chip CPL, the directions of the sides SH1a, SH2a, SH3a, and SH4a of the semiconductor chip CPH1, and the directions of the sides SH1b, SH2b, SH3b, and SH4b of the semiconductor chip CPH2 in the sixth embodiment are the same as those in the second embodiment. The directions of the sides SC1a, SC2a, SC3a, and SC4a of the semiconductor chip CPC1, the directions of the sides SC1b, SC2b, SC3b, and SC4b of the semiconductor chip CPC2, the arrangement of the pads PC1 and PC3 on the semiconductor chip CPC1, the arrangement of the pads PC2 and PC4 on the semiconductor chip CPC2, and the arrangement of the pads PL1, PL2, and PL3 on the semiconductor chip CPL in the sixth embodiment are the same as those in the second embodiment. Moreover, on the surface of the semiconductor chip CPH1, the pads PH1 are arranged along the side SH3a of the semiconductor chip CPH1 near the side SH2a, and the pads PH3 are arranged along the side SH1a of the semiconductor chip CPH1. Moreover, on the surface of the semiconductor chip CPH2, the pads PH2 are arranged along the side SH3b of the semiconductor chip CPH2 near the side SH4a, and the pads PH3 are arranged along the side SH1b of the semiconductor chip CPH2.

[0158] In a plan view, the distance (distance in the Y direction) between the semiconductor chip CPH1 and the corner formed by the sides SC4a and SC1a, among the four corners of the semiconductor chip CPC1, is shorter than the distance (distance in the Y direction) between the semiconductor chip CPH1 and the other corners of the semiconductor chip CPC1. Also, in a plan view, the distance (distance in the Y direction) between the semiconductor chip CPH2 and the corner formed by the sides SC4b and SC1b, among the four corners of the semiconductor chip CPC2, is shorter than the distance (distance in the Y direction) between the semiconductor chip CPH2 and the other corners of the semiconductor chip CP2C.

[0159] In the semiconductor device PKG5 of the sixth embodiment, the side SC1a of the semiconductor chip CPC1 and the side SH3a of the semiconductor chip CPH1 face each other in a plan view. Therefore, the pads PC3 arranged along the side SC1a on the surface of the semiconductor chip CPC1 can be easily and accurately connected to the pads PH1 of the semiconductor chip CPH1 via the wires BW. Furthermore, the side SC3a of the semiconductor chip CPC1 and the side SL2 of the semiconductor chip CPL face each other in a plan view. Therefore, the pads PC1 arranged along the side SC3a on the surface of the semiconductor chip CPC1 can be easily and accurately connected to the pads PL1 of the semiconductor chip CPL via the wires BW. Furthermore, the side SC4b of the semiconductor chip CPC2 and the side SH3b of the semiconductor chip CPH2 face each other in a plan view. Therefore, the pads PC4 arranged along the side SC4b on the surface of the semiconductor chip CPC2 can be easily and accurately connected to the pads PH2 of the semiconductor chip CPH2 via the wires BW. In addition, in a plan view, the side SC2b of the semiconductor chip CPC2 and the side SL4 of the semiconductor chip CPL face each other. Therefore, the pads PC2 arranged along the side SC2b on the surface of the semiconductor chip CPC2 can be easily and accurately connected to the pads PL2 of the semiconductor chip CPL via the wires BW. Since it is possible to accurately prevent adjacent wires BW from shorting each other, it is possible to improve the manufacturing yield of the semiconductor device PKG5.

[0160] In the sixth embodiment, in addition to being able to obtain substantially the same effects as those of the fifth embodiment, the transformer TR1 (coils L1a and L1b) is formed in the semiconductor chip CPC1, and the transformer TR2 (coils L2a and L2b) is formed in the semiconductor chip CPC2, so that the coupling noise of the transformers TR1 and TR2 can be reduced, thereby further improving the performance of the semiconductor device PKG5.

[0161] On the other hand, in the case of the fifth embodiment, the transformer TR1 (coils L1a, L1b) and the transformer TR2 (coils L2a, L2b) are formed in the semiconductor chip CPC, so that the number of semiconductor chips included in the semiconductor device PKG4 can be reduced, thereby reducing the manufacturing cost of the semiconductor device PKG4.

[0162] As a modification of the sixth embodiment, the number of transformers formed in the semiconductor chip CPC1 may be two or more. Also, the number of transformers formed in the semiconductor chip CPC2 may be two or more.

[0163] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0164] In the first to sixth embodiments, one or more transformers are formed in each of the semiconductor chips CPC, CPC1, and CPC2. However, a capacitive element (capacitor) may be used instead of the transformer. A capacitive element is formed of two capacitively coupled electrodes (specifically, an upper electrode and a lower electrode facing each other). Even when a capacitive element is used instead of a transformer, a signal can be transmitted from the transmitting circuit to the receiving circuit via the capacitive element. When a capacitive element is used instead of a transformer, in the first to sixth embodiments, the transformer TR1 may be read as the capacitive element TR1, the transformer TR2 may be read as the capacitive element TR2, the transformer TR3 may be read as the capacitive element TR3, and the coils L1a, L1b, L2a, L2b, L3a, and L3b may be read as the electrodes L1a, L1b, L2a, L2b, L3a, and L3b, respectively. In this case, however, electrodes L1a and L1b are capacitively coupled to each other, electrodes L2a and L2b are capacitively coupled to each other, and electrodes L3a and L3b are capacitively coupled to each other. Coils L1a, L1b, L2a, L2b, L3a, and L3b are each formed by a spiral conductor pattern, and electrodes L1a, L1b, L2a, L2b, L3a, and L3b are each formed by a flat conductor pattern. The transformer is formed by two (a pair of) conductor patterns magnetically coupled to each other, and the capacitive element is formed by two (a pair of) conductor patterns capacitively coupled to each other. [Explanation of symbols]

[0165] BDC,BDH,BDL Bonding material BT1,BT2 power supply BW Wire CC control circuit CPC, CPC1, CPC2, CPC101, CPL, CPL101, CPH, CPH1, CPH2, CPH101 semiconductor chips DPH, DPH1, DPH2, DPH101, DPL, DPL101 die pad DPHa,DPLa top surface DPHb, DPLb bottom surface DPHc1, DPHc2, DPHc3, DPHc4 Side DPLc1, DPLc2, DPLc3, DPLc4 Side DR drive circuit L1a,L1b,L2a,L2b,L3a,L3b Coil LD, LD1, LD2 leads LOD load MR sealing part MRa top surface MRb bottom side MRc1,MRc2,MRc3,MRc4 Side MW1,MW2,MW3 Multilayer wiring structure PA1,PA2,PA3 Protective film PC1, PC2, PC3, PC4, PC5, PC6 Pads PH1, PH2, PH3, PH4 pads PL1, PL2, PL3, PL4 pads PKG,PKG1,PKG2,PKG3,PKG4,PKG5,PKG101 semiconductor device RX1,RX2 receiving circuit SB1, SB2, SB3 semiconductor substrate SC1,SC1a,SC1b,SC2,SC2a,SC2b,SC3,SC3a,SC3b,SC4,SC4a,SC4b,SL1,SL2,SL3,SL4,SH1,SH1a,SH1b,SH2,SH2a,SH2b,SH3,SH3a,SH3b,SH4,SH4a,SH4b TS1, TS2 power transistors TRX1, TRX2 transmitter / receiver circuit TX1,TX2 transmitter circuit WR1, WR2 wiring

Claims

1. a first chip mounting portion; a second chip mounting portion spaced apart from the first chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion, the first semiconductor chip including a first side, a first circuit, and a plurality of first chip pads arranged along the first side and electrically connected to the first circuit; a second semiconductor chip mounted on the second chip mounting portion, the second semiconductor chip including a second side, a second circuit, and a plurality of second chip pads arranged along the second side and electrically connected to the second circuit; a third semiconductor chip mounted on the first chip mounting portion, the third semiconductor chip comprising: a third side, a fourth side opposite to the third side, two first conductor patterns magnetically or capacitively coupled to each other; a plurality of first pattern pads arranged along the third side and electrically connected to one of the two first conductor patterns; and a plurality of second pattern pads arranged along the fourth side and electrically connected to the other of the two first conductor patterns; a plurality of first wires electrically connecting the plurality of first chip pads and the plurality of first pattern pads, respectively; a plurality of second wires electrically connecting the plurality of second chip pads and the plurality of second pattern pads, respectively; a resin encapsulant that encapsulates the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion, the second chip mounting portion, the plurality of first wires, and the plurality of second wires; Including, the first chip mounting portion and the second chip mounting portion are adjacent to each other in a first direction, the planar shape of the first semiconductor chip is a rectangle having the first side, the second semiconductor chip has a planar shape that is a rectangle having the second side, the planar shape of the third semiconductor chip is a rectangle having the third side and the fourth side, the length of the second side is greater than the lengths of the first side, the third side, and the fourth side; the first semiconductor chip and the third semiconductor chip are adjacent to each other in a second direction perpendicular to the first direction, A semiconductor device, wherein, in a planar view, the first semiconductor chip and the third semiconductor chip are arranged along the second side of the second semiconductor chip so that the third side of the third semiconductor chip faces the first side of the first semiconductor chip and so that the fourth side of the third semiconductor chip faces the second side of the second semiconductor chip.

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein, in a planar view, the third side of the third semiconductor chip is inclined with respect to the first side of the first semiconductor chip, and the fourth side of the third semiconductor chip is inclined with respect to the second side of the second semiconductor chip.

3. 2. The semiconductor device according to claim 1, each of the first circuit and the second circuit is a transmitting circuit or a receiving circuit; The semiconductor device, wherein the two first conductor patterns form a transformer or a capacitive element.

4. 4. The semiconductor device according to claim 3, The semiconductor device, wherein the second semiconductor chip further includes a drive circuit.

5. 2. The semiconductor device according to claim 1, the first semiconductor chip further includes a third circuit and a plurality of third chip pads arranged along the first side and electrically connected to the third circuit; the second semiconductor chip further includes a fourth circuit and a plurality of fourth chip pads arranged along the second side and electrically connected to the fourth circuit; the third semiconductor chip further includes two second conductor patterns magnetically or capacitively coupled to each other, a plurality of third pattern pads arranged along the third side and electrically connected to one of the two second conductor patterns, and a plurality of fourth pattern pads arranged along the fourth side and electrically connected to the other of the two second conductor patterns; the third chip pads are electrically connected to the third pattern pads via third wires, respectively; the plurality of fourth chip pads are electrically connected to the plurality of fourth pattern pads via a plurality of fourth wires, respectively; a semiconductor device, wherein the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion, the second chip mounting portion, the plurality of first wires, the plurality of second wires, the plurality of third wires, and the plurality of fourth wires are sealed with the resin sealing body.

6. 6. The semiconductor device according to claim 5, the first semiconductor chip further includes a fifth circuit and a plurality of fifth chip pads arranged along the first edge and electrically connected to the fifth circuit; the second semiconductor chip further includes a sixth circuit and a plurality of sixth chip pads arranged along the second side and electrically connected to the sixth circuit; the third semiconductor chip further includes two third conductor patterns magnetically or capacitively coupled to each other, a plurality of fifth pattern pads arranged along the third side and electrically connected to one of the two third conductor patterns, and a plurality of sixth pattern pads arranged along the fourth side and electrically connected to the other of the two third conductor patterns; the fifth chip pads are electrically connected to the fifth pattern pads via fifth wires, respectively; the sixth chip pads are electrically connected to the sixth pattern pads via sixth wires, respectively; the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion, the second chip mounting portion, the plurality of first wires, the plurality of second wires, the plurality of third wires, the plurality of fourth wires, the plurality of fifth wires, and the plurality of sixth wires are sealed with the resin sealing body.

7. 2. The semiconductor device according to claim 1, a fourth semiconductor chip mounted on the first chip mounting portion, the fourth semiconductor chip comprising: a fifth side, a sixth side opposite to the fifth side, two second conductor patterns magnetically or capacitively coupled to each other, a plurality of third pattern pads arranged along the fifth side and electrically connected to one of the two second conductor patterns, and a plurality of fourth pattern pads arranged along the sixth side and electrically connected to the other of the two second conductor patterns; Further comprising: the first semiconductor chip further includes a seventh side opposite to the first side, a third circuit, and a plurality of third chip pads arranged along the seventh side and electrically connected to the third circuit; the second semiconductor chip further includes a fourth circuit and a plurality of fourth chip pads arranged along the second side and electrically connected to the fourth circuit; the fourth semiconductor chip has a planar shape that is a rectangle having the fifth side and the sixth side, the first semiconductor chip and the fourth semiconductor chip are adjacent to each other in the second direction, the first semiconductor chip is located between the third semiconductor chip and the fourth semiconductor chip in the second direction, the third chip pads are electrically connected to the third pattern pads via third wires, respectively; the plurality of fourth chip pads are electrically connected to the plurality of fourth pattern pads via a plurality of fourth wires, respectively; the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the first chip mounting portion, the second chip mounting portion, the plurality of first wires, the plurality of second wires, the plurality of third wires, and the plurality of fourth wires are sealed with the resin sealing body, A semiconductor device, wherein, in a planar view, the first semiconductor chip, the third semiconductor chip, and the fourth semiconductor chip are arranged along the second side of the second semiconductor chip so that the third side of the third semiconductor chip faces the first side of the first semiconductor chip, the fourth side of the third semiconductor chip faces the second side of the second semiconductor chip, the fifth side of the fourth semiconductor chip faces the seventh side of the first semiconductor chip, and the sixth side of the fourth semiconductor chip faces the second side of the second semiconductor chip.

8. 8. The semiconductor device according to claim 7, A semiconductor device, wherein, in a planar view, the third side of the third semiconductor chip is inclined with respect to the first side of the first semiconductor chip, the fourth side of the third semiconductor chip is inclined with respect to the second side of the second semiconductor chip, the fifth side of the fourth semiconductor chip is inclined with respect to the seventh side of the first semiconductor chip, and the sixth side of the fourth semiconductor chip is inclined with respect to the second side of the second semiconductor chip.

9. 9. The semiconductor device according to claim 8, each of the first circuit, the second circuit, the third circuit, and the fourth circuit is a transmitting circuit or a receiving circuit; The semiconductor device, wherein the two first conductor patterns and the two second conductor patterns each form a transformer or a capacitive element.

10. 8. The semiconductor device according to claim 7, the first semiconductor chip further includes a fifth circuit and a plurality of fifth chip pads arranged along the first edge and electrically connected to the fifth circuit; the second semiconductor chip further includes a sixth circuit and a plurality of sixth chip pads arranged along the second side and electrically connected to the sixth circuit; the third semiconductor chip further includes two third conductor patterns magnetically or capacitively coupled to each other, a plurality of fifth pattern pads arranged along the third side and electrically connected to one of the two third conductor patterns, and a plurality of sixth pattern pads arranged along the fourth side and electrically connected to the other of the two third conductor patterns; the fifth chip pads are electrically connected to the fifth pattern pads via fifth wires, respectively; the sixth chip pads are electrically connected to the sixth pattern pads via sixth wires, respectively; the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the first chip mounting portion, the second chip mounting portion, the plurality of first wires, the plurality of second wires, the plurality of third wires, the plurality of fourth wires, the plurality of fifth wires, and the plurality of sixth wires are sealed with the resin sealing body.

11. a first chip mounting portion; a second chip mounting portion spaced apart from the first chip mounting portion; a third chip mounting portion spaced apart from the first chip mounting portion and the second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion, the first semiconductor chip including a first side, a first circuit, and a plurality of first chip pads arranged along the first side and electrically connected to the first circuit; a second semiconductor chip mounted on the second chip mounting portion, the second semiconductor chip including a second side, a second circuit, and a plurality of second chip pads arranged along the second side and electrically connected to the second circuit; a third semiconductor chip mounted on the third chip mounting portion, the third semiconductor chip including a third side, a third circuit, and a plurality of third chip pads arranged along the third side and electrically connected to the third circuit; a fourth semiconductor chip mounted on the first chip mounting portion, the fourth semiconductor chip comprising: a fourth side, a fifth side opposite to the fourth side, two first conductor patterns magnetically or capacitively coupled to each other, a plurality of first pattern pads arranged along the fourth side and electrically connected to one of the two first conductor patterns, and a plurality of second pattern pads arranged along the fifth side and electrically connected to the other of the two first conductor patterns; a plurality of first wires electrically connecting the plurality of first chip pads and the plurality of first pattern pads, respectively; a plurality of second wires electrically connecting the plurality of second chip pads and the plurality of second pattern pads, respectively; a resin encapsulant that encapsulates the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the first chip mounting portion, the second chip mounting portion, the plurality of first wires, and the plurality of second wires; Including, the first chip mounting portion and the second chip mounting portion are adjacent to each other in a first direction, the first chip mounting portion and the third chip mounting portion are adjacent to each other in the first direction, the second chip mounting portion and the third chip mounting portion are adjacent to each other in a second direction perpendicular to the first direction, the planar shape of the first semiconductor chip is a rectangle having the first side, the second semiconductor chip has a planar shape that is a rectangle having the second side, the planar shape of the third semiconductor chip is a rectangle having the third side, the fourth semiconductor chip has a planar shape that is a rectangle having the fourth side and the fifth side; the first semiconductor chip and the fourth semiconductor chip are adjacent to each other in the second direction, A semiconductor device, wherein, in a planar view, the first semiconductor chip and the fourth semiconductor chip are arranged along the second side of the second semiconductor chip so that the fourth side of the fourth semiconductor chip faces the first side of the first semiconductor chip and so that the fifth side of the fourth semiconductor chip faces the second side of the second semiconductor chip.

12. 12. The semiconductor device according to claim 11, the first semiconductor chip further includes a fourth circuit and a plurality of fourth chip pads arranged along the first side and electrically connected to the fourth circuit; the fourth semiconductor chip further includes two second conductor patterns magnetically or capacitively coupled to each other, a plurality of third pattern pads arranged along the fourth side and electrically connected to one of the two second conductor patterns, and a plurality of fourth pattern pads arranged along the fifth side and electrically connected to the other of the two second conductor patterns; the plurality of fourth chip pads are electrically connected to the plurality of third pattern pads via a plurality of third wires, respectively; the third chip pads are electrically connected to the fourth pattern pads via fourth wires, respectively; the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the first chip mounting portion, the second chip mounting portion, the plurality of first wires, the plurality of second wires, the plurality of third wires, and the plurality of fourth wires are sealed with the resin sealing body.

13. The semiconductor device according to claim 11 further comprises: a fifth semiconductor chip mounted on the first chip mounting portion, the fifth semiconductor chip comprising: a sixth side; a seventh side opposite to the sixth side; two second conductor patterns magnetically or capacitively coupled to each other; a plurality of third pattern pads arranged along the sixth side and electrically connected to one of the two second conductor patterns; and a plurality of fourth pattern pads arranged along the seventh side and electrically connected to the other of the two second conductor patterns; Further comprising: the first semiconductor chip further includes an eighth side opposite to the first side, a fourth circuit, and a plurality of fourth chip pads arranged along the eighth side and electrically connected to the fourth circuit; the fifth semiconductor chip has a planar shape that is a rectangle having the sixth side and the seventh side, the first semiconductor chip and the fifth semiconductor chip are adjacent to each other in the second direction, the first semiconductor chip is located between the fourth semiconductor chip and the fifth semiconductor chip in the second direction, the plurality of fourth chip pads are electrically connected to the plurality of third pattern pads via a plurality of third wires, respectively; the third chip pads are electrically connected to the fourth pattern pads via fourth wires, respectively; the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the fourth semiconductor chip, the fifth semiconductor chip, the first chip mounting portion, the second chip mounting portion, the plurality of first wires, the plurality of second wires, the plurality of third wires, and the plurality of fourth wires are sealed with the resin sealing body, a semiconductor device in which, in a planar view, the first semiconductor chip, the fourth semiconductor chip, and the fifth semiconductor chip are arranged along the second side of the second semiconductor chip and the third side of the third semiconductor chip, respectively, so that the fourth side of the fourth semiconductor chip faces the first side of the first semiconductor chip, the fifth side of the fourth semiconductor chip faces the second side of the second semiconductor chip, the sixth side of the fifth semiconductor chip faces the eighth side of the first semiconductor chip, and the seventh side of the fifth semiconductor chip faces the third side of the third semiconductor chip.

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