Semiconductor device

Abstract

To replace a transistor by another transistor with a different breakdown voltage.SOLUTION: In a semiconductor device, a target transistor (10b) and a drive circuit (20b) are accommodated in a housing. A control signal input terminal (Tb_G) to receive a control signal (Scnt) from outside of the semiconductor device is provided on the housing. The drive circuit generates a rectified voltage (Vr) by rectifying the control signal, generates a drive voltage (Vdrv) by stepping down the rectified voltage, and turns on or off the target transistor by controlling a voltage between the gate electrode and the source electrode of the target transistor according to the control signal based on the drive voltage.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices that function as switching devices are mounted in various devices such as switching power supplies (see Patent Document 1 below). This type of semiconductor device is configured by housing a transistor having a drain electrode, a source electrode, and a gate electrode in a housing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-061818

[0004] [overview] When there is a demand to replace a semiconductor device (switching device) mounted in a certain system with a different type of semiconductor device, it is often difficult to simply replace it due to differences in withstand voltage and the like.

[0005] A semiconductor device according to one embodiment of the present disclosure comprises a target transistor having a drain electrode, a source electrode, and a gate electrode, a drive circuit, a housing that houses the target transistor and the drive circuit, and a plurality of external terminals exposed from the housing, wherein the plurality of external terminals include a drain terminal connected to the drain electrode, a source terminal connected to the source electrode, and a control signal input terminal configured to receive a control signal from outside the semiconductor device, wherein the control signal is a rectangular wave signal that alternates between a first level that instructs the target transistor to be on and a second level that instructs the target transistor to be off, and the drive circuit comprises: a rectified voltage generation circuit configured to rectify the control signal to generate a rectified voltage; a linear regulator configured to generate a drive voltage by stepping down the rectified voltage; and a driver configured to turn the target transistor on or off by controlling the voltage between the gate electrode and the source electrode in accordance with the control signal based on the drive voltage. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic overall configuration diagram of a switching system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing the relationship between the waveform of a control signal and the state of a target transistor according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is an external view of a semiconductor device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a transparent plan view of a semiconductor device according to a first example of an embodiment of the present disclosure. [Figure 5] FIG. 5 is a configuration diagram of a switching system according to a first example belonging to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram for explaining the configuration of the first reference method. [Figure 7] FIG. 7 is a diagram for explaining the configuration of the second reference method. [Figure 8]FIG. 8 is an external plan view of a semiconductor device according to a second example of the embodiment of the present disclosure. [Figure 9] FIG. 9 is a transparent plan view of a semiconductor device according to a second example of the embodiment of the present disclosure. [Figure 10] FIG. 10 is a configuration diagram of a switching system according to a second example of the embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram showing the internal configuration of a rectified voltage generating circuit and its peripheral configuration according to a second example belonging to the embodiment of the present disclosure. [Figure 12] FIG. 12 is a waveform diagram of a control signal, a rectified voltage, and a driving voltage according to a second example of the embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram illustrating an example of a circuit of a linear regulator according to a second example of the embodiment of the present disclosure. [Figure 14] FIG. 14 is a diagram illustrating another circuit example of a linear regulator according to a second example of the embodiment of the present disclosure. [Figure 15] FIG. 15 is a diagram illustrating yet another circuit example of a linear regulator according to a second example of the embodiment of the present disclosure. [Figure 16] FIG. 16 is a diagram illustrating yet another circuit example of a linear regulator according to a second example belonging to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram illustrating yet another circuit example of a linear regulator according to a second example of the embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram illustrating yet another circuit example of a linear regulator according to a second example belonging to an embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram illustrating yet another circuit example of a linear regulator according to a second example belonging to an embodiment of the present disclosure. [Figure 20] FIG. 20 is a diagram illustrating yet another circuit example of a linear regulator according to a second example belonging to an embodiment of the present disclosure. [Figure 21]FIG. 21 is a diagram illustrating yet another circuit example of a linear regulator according to a second example belonging to an embodiment of the present disclosure. [Figure 22] FIG. 22 is a diagram illustrating yet another circuit example of a linear regulator according to a second example belonging to an embodiment of the present disclosure. [Figure 23] FIG. 23 is a diagram illustrating yet another circuit example of a linear regulator according to a second example belonging to an embodiment of the present disclosure. [Figure 24] FIG. 24 is a transparent plan view of a semiconductor device according to a third example of the embodiment of the present disclosure. [Figure 25] FIG. 25 is a transparent plan view of a semiconductor device according to a fourth example of the embodiment of the present disclosure. [Figure 26] FIG. 26 is an external plan view of a semiconductor device according to a fourth example of the embodiment of the present disclosure. [Figure 27] FIG. 27 is an external plan view of a semiconductor device according to a fifth example of the embodiments of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductor may be formed using a conductor such as metal. The 0V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. Level refers to the level (height) of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0009] For any transistor configured as a FET (field-effect transistor), such as a MOSFET or a HEMT, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." Also, unless otherwise specified, the back gate of any MOSFET can be considered shorted to the source. HEMT is an abbreviation for "High Electron Mobility Transistor." For any transistor, the period during which the transistor is in the on state is referred to as the on period, and the period during which the transistor is in the off state is referred to as the off period. Hereinafter, the on and off states of any transistor may be simply referred to as on and off.

[0010] Unless otherwise specified, the connection between a plurality of parts that form a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection.

[0011] When any two voltages to be compared are voltage v1 and voltage v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0012] FIG. 1 shows a schematic overall configuration diagram of a switching system SYS (in other words, a switching circuit) according to an embodiment of the present disclosure. The switching system SYS includes a semiconductor device 1, a target circuit 2, and a control signal supply circuit 3. In the following description, the external wiring refers to the wiring provided outside the semiconductor device 1, and the internal wiring refers to the wiring provided inside the semiconductor device 1.

[0013] The semiconductor device 1 is a switching device having a target transistor 10. The target transistor 10 is a switching element (switching transistor) formed of a semiconductor. The target transistor 10 has a drain, a source, and a gate. The target transistor 10 is an N-channel type MOSFET or HEMT. The drain and source of the target transistor 10 are connected to the target circuit 2. More specifically, the drain of the target transistor 10 is connected to the external wiring WR1 and connected to the first end of the target circuit 2 through the external wiring WR1, and the source of the target transistor 10 is connected to the external wiring WR2 and connected to the second end of the target circuit 2 through the external wiring WR2.

[0014] The target circuit 2 includes at least a circuit that supplies a voltage between the drain and source of the target transistor 10 and a circuit that supplies a drain current to the target transistor 10, and may also include various other circuits. In any case, during an on-period of the target transistor 10, the drain current of the target transistor 10 flows through a current loop LP that passes through the target circuit 2, the external wiring WR1, the channel of the target transistor 10 (the channel between the drain and source), and the external wiring WR2. The drain current of the target transistor 10 may flow from the drain to the source of the target transistor 10, or may flow in the opposite direction. During an off-period of the target transistor 10, the current loop LP is cut off, and no drain current is generated in the target transistor 10. Although the external wiring WR2 may have a potential other than ground, here the external wiring WR2 is connected to ground and therefore has ground potential.

[0015] The control signal supply circuit 3 is connected to ground and operates based on a power supply voltage having a predetermined positive DC voltage value with respect to the ground potential. The control signal supply circuit 3 supplies a control signal Scnt to the semiconductor device 1. The control signal supply circuit 3 and the semiconductor device 1 are connected to each other via an external wiring WR3. The control signal supply circuit 3 outputs the control signal Scnt to the external wiring WR3, thereby inputting the control signal Scnt to the semiconductor device 1. The control signal Scnt is a rectangular wave signal that alternates between high and low levels. Figure 2 shows the relationship between the waveform of the control signal Scnt and the state of the target transistor 10. The high level of the control signal Scnt is level LV1, and the low level of the control signal Scnt is level LV2. Therefore, the level of the control signal Scnt alternates between levels LV1 and LV2. The low level LV2 is equal to the potential of the external wiring WR2 (and therefore essentially equal to the potential of the source of the target transistor 10). The high level LV1 is higher than the low level LV2 by a voltage V12. In other words, the potential difference between levels LV1 and LV2 is equal to the voltage V12. The high level LV1 may be equal to the level of the power supply voltage of the control signal supply circuit 3.

[0016] The high level LV1 is a level that instructs the target transistor 10 to be in the ON state, and the low level LV2 is a level that instructs the target transistor 10 to be in the OFF state. Therefore, in the switching system SYS, the target transistor 10 is set to the ON state during a period in which the control signal Scnt has the high level LV1, and the target transistor 10 is set to the OFF state during a period in which the control signal Scnt has the low level LV2. To achieve this, in the semiconductor device 1, the gate voltage of the target transistor 10 is controlled based on the control signal Scnt.

[0017] FIG. 3 shows a schematic external view of the semiconductor device 1. The semiconductor device 1 is an electronic component including one or more semiconductor chips, a housing CS that houses the one or more semiconductor chips, and a plurality of external terminals that are exposed to the outside of the semiconductor device 1 from the housing CS. The semiconductor device 1 is formed by encapsulating the semiconductor chips in a housing CS made of resin. Note that the number of external terminals of the semiconductor device 1 and the type of housing CS of the semiconductor device 1 shown in FIG. 3 are merely examples and can be designed as desired. However, it is assumed here that the semiconductor device 1 is provided with external terminals T_D, T_PS, T_KS, and T_G as a plurality of external terminals, as shown in FIG. 3.

[0018] The structure of the semiconductor device 1 in FIG. 3 will be briefly described assuming mutually orthogonal X-, Y-, and Z-axes. In the exemplary configuration of FIG. 3, the housing CS has a front and back surface facing each other. The front and back surfaces are parallel to the X- and Y-axes, respectively. The direction from the negative side to the positive side of the Z-axis coincides with the direction from the back surface to the front surface. FIG. 3 is a plan view of the semiconductor device 1 as viewed from the back surface. A resin back surface 810 forming the back surface of the housing CS has a roughly rectangular outer shape. A resin through-hole 812 is provided in the housing CS, penetrating from the back surface to the front surface. A recess 813 provided in the housing CS corresponds to a depression extending from the back surface to the front surface. When viewed in a direction parallel to the Z-axis, the resin through-hole 812 and the recess 813 have circular shapes with the same center, and the radius of the resin through-hole 812 is smaller than the radius of the recess 813. A back surface terminal 814 is provided in the resin back surface 810 at a position surrounding the resin through-hole 812 and the recess 813. The back surface terminal 814 forms a metal surface exposed from the resin forming the housing CS. Connecting the rear terminals 814 to a heat dissipation member via an electrical insulating sheet or the like can promote the dissipation of heat generated by the semiconductor element 1. The housing CS has resin end faces 821 and 822 facing each other. The resin end faces 821 and 822 are surfaces parallel to the X-axis and Z-axis, and the resin end face 822 is located on the positive side of the Y-axis as viewed from the resin end face 821. The housing CS is provided with end face protrusions 823 and 824. The end face protrusions 823 and 824 each protrude from the resin end face 822 toward the positive side of the Y-axis, and although not clear from FIG. 3 , they have a roughly rectangular parallelepiped shape (however, their shapes are arbitrary). The end face protrusions 823 and 824 are spaced apart from each other in the X-axis direction, and the end face protrusion 823 is located on the positive side of the X-axis as viewed from the end face protrusion 824.

[0019] The external terminals T_D, T_PS, T_KS, and T_G are metal terminals exposed from the housing CS and are arranged in a row along the X-axis direction. The external terminals T_D, T_PS, T_KS, and T_G are arranged at positions spaced apart from one another. The external terminals T_PS and T_KS are provided between the external terminals T_D and T_G. The external terminals T_D, T_PS, T_KS, and T_G are arranged in this order from the external terminal T_D toward the external terminal T_G. Therefore, the external terminal T_PS is provided between the external terminals T_D and T_KS, and the external terminal T_KS is provided between the external terminals T_PS and T_G. In the configuration example of FIG. 3 , the external terminal T_D protrudes from the end surface protrusion 823 toward the positive side of the Y-axis, and the external terminals T_PS, T_KS, and T_G protrude from the end surface protrusion 824 toward the positive side of the Y-axis.

[0020] Several embodiments based on the above content are described below. Note that if there are any matters in each of the embodiments described below that contradict the matters described above, the description of each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the embodiments described below can also be applied to any other embodiment (i.e., any two or more of the embodiments can be combined).

[0021] <<First Example>> A first embodiment will be described. The semiconductor device 1 according to the first embodiment is a semiconductor device 1a. FIG. 4 shows a transparent plan view of the semiconductor device 1a. In FIG. 4, the outline of a semiconductor chip provided in the semiconductor device 1a is illustrated in a dashed rectangular frame, and the internal wiring of the semiconductor device 1a is illustrated by solid line segments. Note that FIG. 4 only shows the internal wiring schematically, and the actual number of internal wirings is arbitrary. FIG. 5 shows a circuit diagram of a switching system SYS according to the first embodiment. The semiconductor device 1a has a housing CSa as a housing CS, and external terminals Ta_D, Ta_PS, Ta_KS, and Ta_G as external terminals T_D, T_PS, T_KS, and T_G. The positional relationship of the external terminals Ta_D, Ta_PS, Ta_KS, and Ta_G is the same as the positional relationship of the external terminals T_D, T_PS, T_KS, and T_G in FIG. 3. 3, and the matters described above regarding the housing CS (the explanations regarding the resin through-hole 812 and the resin end surface 822, etc.) also apply to the housing CSa. The external terminals Ta_D, Ta_PS, Ta_KS, and Ta_G are a drain terminal, a power source terminal, a Kelvin source terminal, and a gate terminal, respectively. The Kelvin source terminal is sometimes called a driver source terminal.

[0022] The semiconductor chip CPa is accommodated in the housing CSa. The semiconductor chip CPa is arranged between the housing 812 and the recess 813 and the resin end surface 822 in the Y-axis direction. The semiconductor chip CPa is formed of a predetermined reference semiconductor material. The reference semiconductor material is, for example, Si (silicon) or SiC (silicon carbide). A target transistor 10 is formed in the semiconductor chip CPa. The target transistor 10 formed in the semiconductor chip CPa is a target transistor 10a. In other words, the target transistor 10a is formed of the reference semiconductor material. Note that forming the semiconductor chip CPa or the target transistor 10a from the reference semiconductor material means that the semiconductor chip CPa or the target transistor 10a is formed using the reference semiconductor material as a base material, and more specifically, impurities are added to the reference semiconductor material in the semiconductor chip CPa or the target transistor 10a.

[0023] Two N-type semiconductor regions separated from each other are formed in the semiconductor chip CPa, one of which is the source region of the target transistor 10a and the other is the drain region of the target transistor 10a. A source electrode is formed on the source region, and a drain electrode is formed on the drain region. The source region and source electrode in the semiconductor chip CPa form the source of the target transistor 10a, and the drain region and drain electrode in the semiconductor chip CPa form the drain of the target transistor 10a. A P-type semiconductor region is provided between the source region and drain region in the semiconductor chip CPa, and a gate electrode is formed on the P-type semiconductor region via a gate oxide film. The gate of the target transistor 10a is formed by the gate electrode in the semiconductor chip CPa. The drain electrode, source electrode, and gate electrode in the semiconductor chip CPa are the drain electrode, source electrode, and gate electrode of the target transistor 10a, respectively.

[0024] The external terminal Ta_D is connected to a first end of the target circuit 2 through an external wiring WR1, while the external terminal Ta_PS is connected to a second end of the target circuit 2 through an external wiring WR2. The external terminal Ta_G is connected to a control signal supply circuit 3 through an external wiring WR3, while the external terminal Ta_KS is connected to the control signal supply circuit 3 through an external wiring WR4. The control signal supply circuit 3 outputs a control signal Scnt to the external wiring WR3 based on the potential of the external wiring WR4 (and therefore the potential of the external terminal Ta_KS). Therefore, the low level LV2 corresponds to the potential of the external wiring WR4, and the high level LV1 is higher than the potential of the external wiring WR4 (than the potential of the source electrode of the target transistor 10a) by a voltage V12. Note that the external wiring WR4 is connected to ground independently of the external wiring WR2.

[0025] The drain electrode of the target transistor 10a is connected to an external terminal Ta_D through a first internal wiring within the casing CSa. The source electrode of the target transistor 10a is connected to an external terminal Ta_PS through a second internal wiring within the casing CSa and is also connected to an external terminal Ta_KS through a third internal wiring within the casing CSa. The gate electrode of the target transistor 10a is connected to an external terminal Ta_G through a fourth internal wiring within the casing CSa. The internal wirings connect the necessary parts using well-known wire bonding.

[0026] The external terminal Ta_PS includes an inductance component. The inductance component included in the external terminal Ta_PS is specifically referred to as the package inductance component La. For convenience, the package inductance component La is shown in FIG. 5. The source electrode of the target transistor 10a is connected to the external wiring WR2 via the external terminal Ta_PS, which includes the package inductance component La. The current in the above-mentioned current loop LP (FIG. 1) flows through the external terminal Ta_D and the external terminal Ta_PS. When the drain current of the target transistor 10a changes as the target transistor 10a is switched, an electromotive force is generated in the package inductance component La.

[0027] If a control signal Scnt is supplied between the external terminals Ta_PS and Ta_G, the switching of the target transistor 10a will stop due to the influence of the above-mentioned electromotive force. In the first embodiment, the source electrode of the target transistor 10a is connected to the external terminal Ta_KS without passing through the external terminal Ta_PS. Although an inductance component due to the external terminal Ta_KS exists between the source electrode of the target transistor 10a and the external terminal Ta_KS, the current flowing through the external terminal Ta_KS is much smaller than the current flowing through the external terminal Ta_PS, and therefore the electromotive force due to the inductance component of the external terminal Ta_KS can be ignored. The use of the external terminal Ta_KS can improve the switching speed of the target transistor 10a.

[0028] The breakdown voltage between the gate electrode and source electrode of the target transistor 10a is greater than the voltage V12. By setting the voltage V12 to a voltage smaller than the breakdown voltage and increasing the voltage V12 as much as possible, it is possible to reduce the on-resistance of the target transistor 10a and improve the switching speed.

[0029] However, forming a switching transistor from GaN (gallium nitride) can increase switching speed, miniaturize components, and improve system efficiency. However, simply replacing the target transistor 10a in the switching system SYS of FIG. 5 with a GaN switching transistor is difficult because the driving methods for Si or SiC switching transistors and GaN switching transistors are different. If the target transistor 10a in FIG. 5 were replaced with a GaN switching transistor and a control signal Scnt for Si or SiC were supplied between the gate and source of the GaN switching transistor, a voltage exceeding the breakdown voltage could be applied between the gate and source of the GaN switching transistor.

[0030] For this reason, when replacing a Si or SiC switching transistor with a GaN switching transistor, the following first or second reference method is considered.

[0031] 6, in the first reference method, a linear regulator discrete component 912 and a driver discrete component 913 are prepared in addition to a GaN switching transistor discrete component 911. The control signal Scnt is then converted into a GaN drive signal using the discrete components 912 and 913 to drive the GaN switching transistor. However, the first reference method increases the number of components, and replacing Si or SiC with GaN requires significant pattern changes to the substrate on which each component is mounted (which is why designers find it difficult to adopt the first reference method).

[0032] In the second reference method, as shown in FIG. 7 , a semiconductor chip 922 on which a GaN switching transistor is formed and a semiconductor chip 923 on which a driver integrated circuit for driving the GaN switching transistor are formed are enclosed in a common housing to form a single semiconductor device 921. The second reference method prevents the increase in the number of components seen in the first reference method. However, a power supply voltage for driving the driver integrated circuit must be separately supplied to the semiconductor device 921, and external terminals for receiving the power supply voltage must be provided separately on the semiconductor device 921. In addition, special measures are required, such as providing several external terminals on the semiconductor device 921 to ensure proper operation of the driver integrated circuit. As a result, even with the second reference method, significant pattern changes to the substrate are required when replacing Si or SiC with GaN (which makes it difficult for designers to adopt the second reference method).

[0033] <<Second Example>> A second embodiment will be described. The semiconductor device 1 according to the second embodiment is a semiconductor device 1b. FIG. 8 shows a schematic external view of the semiconductor device 1b. FIG. 9 shows a transparent plan view of the semiconductor device 1b. In FIG. 9, the outline of a semiconductor chip provided in the semiconductor device 1b is illustrated in a dashed rectangular frame, and the internal wiring of the semiconductor device 1b is illustrated in solid lines. Note that FIG. 9 only shows the internal wiring diagrammatically, and the actual number of internal wirings is arbitrary. FIG. 10 shows a circuit diagram of a switching system SYS according to the second embodiment. The semiconductor device 1b has a housing CSb as the housing CS, and external terminals Tb_D, Tb_PS, Tb_KS, and Tb_G as the external terminals T_D, T_PS, T_KS, and Tb_G. The external terminals Tb_D, Tb_PS, Tb_KS, and Tb_G are a drain terminal, a power source terminal, a Kelvin source terminal, and a control signal input terminal, respectively. The Kelvin source terminal is sometimes referred to as a driver source terminal.

[0034] The housing CSb in the semiconductor device 1b is the same as the housing CS described with reference to Fig. 3, and the matters described above regarding the housing CS (the explanations regarding the tree through-hole 812 and the resin end surface 822, etc.) also apply to the housing CSb. The positional relationship between the external terminals Tb_D, Tb_PS, Tb_KS, and Tb_G in the semiconductor device 1b is the same as the positional relationship between the external terminals T_D, T_PS, T_KS, and T_G in Fig. 3. Therefore, the positional relationship between the external terminals Tb_D, Tb_PS, Tb_KS, and Tb_G in the semiconductor device 1b is the same as the positional relationship between the external terminals Ta_D, Ta_PS, Ta_KS, and Ta_G in the semiconductor device 1a (see Figs. 4 and 9). The shapes of the external terminals Tb_D, Tb_PS, Tb_KS, and Tb_G in the semiconductor device 1b are the same as those of the external terminals Ta_D, Ta_PS, Ta_KS, and Ta_G in the semiconductor device 1a, respectively, and the sizes of the external terminals Tb_D, Tb_PS, Tb_KS, and Tb_G in the semiconductor device 1b are the same as those of the external terminals Ta_D, Ta_PS, Ta_KS, and Ta_G in the semiconductor device 1a, respectively. Furthermore, the shape and size of the housing CSb in the semiconductor device 1b are the same as those of the housing CSa in the semiconductor device 1a (see FIGS. 4 and 9). Therefore, in the switching system SYS of FIG. 5, the semiconductor device 1a can be replaced with the semiconductor device 1b without any need to change the pattern of the board, etc. The shape and size of the housing CSb may be slightly different from those of the housing CSa.

[0035] The semiconductor chips CPb1 and CPb2 are housed separately in the housing CSb. The semiconductor chips CPb1 and CPb2 are arranged in the Y-axis direction between the housing 812 and the recess 813 and the resin end surface 822. The semiconductor chip CPb1 is arranged on the positive side of the X-axis as viewed from the semiconductor chip CPb2. The semiconductor chip CPb1 is made of a first semiconductor material. The first semiconductor material is GaN (gallium nitride). The target transistor 10 is formed in the semiconductor chip CPb1. The target transistor 10 formed in the semiconductor chip CPb1 is the target transistor 10b. That is, the target transistor 10b is formed of the first semiconductor material.

[0036] The semiconductor chip CPb2 is made of a second semiconductor material. The driving circuit 20b is formed in the semiconductor chip CPb2. The second semiconductor material is Si (silicon).

[0037] A source electrode, a drain electrode, and a gate electrode that function as the source, drain, and gate of the target transistor 10b are formed on the semiconductor chip CPb1. The target transistor 10b is a HEMT.

[0038] The external terminal Tb_D is connected to the external wiring WR1 and is connected to a first end of the target circuit 2 through the external wiring WR1. The external terminal Tb_PS is connected to the external wiring WR2 and is connected to a second end of the target circuit 2 through the external wiring WR2. The external terminal Tb_G is connected to the control signal supply circuit 3 through the external wiring WR3, while the external terminal Tb_KS is connected to the control signal supply circuit 3 through the external wiring WR4. The control signal supply circuit 3 outputs a control signal Scnt to the external wiring WR3 based on the potential of the external wiring WR4 (and therefore the potential of the external terminal Tb_KS). Therefore, the low level LV2 corresponds to the potential of the external wiring WR4, and the high level LV1 is higher than the potential of the external wiring WR4 (than the potential of the source electrode of the target transistor 10b) by a voltage V12. Note that the external wiring WR4 is connected to ground independently of the external wiring WR2. Here, an example is given in which the external wiring WR4 and WR2 are connected to ground, but the connection destination of the external wiring WR4 and WR2 is not limited to ground, and the target transistor 10b may also be used as the high-side transistor (upper arm) of a half-bridge circuit, for example.

[0039] The location of the drain electrode on the semiconductor chip CPb1 is connected to the external terminal Tb_D through internal wiring Wb_D (drain wiring) within the casing CSb. That is, the drain electrode of the target transistor 10b is connected to the external terminal Tb_D through internal wiring Wb_D (drain wiring). The location of the source electrode on the semiconductor chip CPb1 is connected to the external terminal Tb_PS through internal wiring Wb_PS (power source wiring) within the casing CSb. That is, the source electrode of the target transistor 10b is connected to the external terminal Tb_PS through internal wiring Wb_PS (power source wiring).

[0040] The location of the source electrode on the semiconductor chip CPb1 is connected to the external terminal Tb_KS through the internal wiring Wb_KS1 (first Kelvin source wiring) within the housing CSb. That is, the source electrode of the target transistor 10b is connected to the external terminal Tb_KS through the internal wiring Wb_KS1 (Kelvin source wiring). Separately, the semiconductor chip CPb2 is connected to the external terminal Tb_KS through the internal wiring Wb_KS2 (second Kelvin source wiring) within the housing CSb. This provides the potential of the external terminal Tb_KS (and therefore the source potential of the target transistor 10b) to the semiconductor chip CPb2 and the drive circuit 20b. As described above, the low level LV2 corresponds to the potential of the external wiring WR4. Since the external wiring WR4 is connected to the external terminals Tb_KS and Tb_PS and the source electrode of the target transistor 10b, the potentials of the external terminals Tb_KS and Tb_PS and the source electrode of the target transistor 10b are also equal to the low level LV2 (the voltage drop or electromotive force generated in the wiring or terminal is assumed to be sufficiently small and can be ignored).

[0041] The semiconductor chip CPb2 is connected to an external terminal Tb_G through internal wiring Wb_IN (input wiring) within the housing CSb, thereby inputting a control signal Scnt to the drive circuit 20b. The semiconductor chip CPb2 is also connected to the semiconductor chip CPb1 through internal wiring Wb_G (gate wiring) within the housing CSb. One end of the internal wiring Wb_G is connected to the gate electrode of the target transistor 10b on the semiconductor chip CPb1, and the drive circuit 20b controls the gate potential of the target transistor 10b by controlling the potential of the internal wiring Wb_G. The internal wiring connects the necessary parts using well-known wire bonding.

[0042] The external terminal Tb_PS includes an inductance component. The inductance component included in the external terminal Tb_PS is specifically referred to as a package inductance component Lb (not shown). Therefore, the source electrode of the target transistor 10b is connected to the external wiring WR2 via the external terminal Tb_PS, which includes the package inductance component Lb. The current in the above-mentioned current loop LP (FIG. 1) flows through the external terminal Tb_D and the external terminal Tb_PS. When the drain current of the target transistor 10b changes as the target transistor 10b switches, an electromotive force is generated in the package inductance component Lb.

[0043] In the second embodiment, the source electrode of the target transistor 10b is connected to the external terminal Tb_KS without passing through the external terminal Tb_PS. Although an inductance component due to the external terminal Tb_KS exists between the source electrode of the target transistor 10b and the external terminal Tb_KS, the current flowing through the external terminal Tb_KS is much smaller than the current flowing through the external terminal Tb_PS, so the electromotive force due to the inductance component of the external terminal Tb_KS can be ignored. The use of the external terminal Tb_KS can improve the switching speed of the target transistor 10b.

[0044] The gate breakdown voltage of a transistor formed from GaN is relatively smaller, or tends to be smaller, than the gate breakdown voltage of a transistor formed from Si or SiC. Therefore, when considering replacing the semiconductor device 1a with the semiconductor device 1b in the switching system SYS of FIG. 5, the voltage V12 is larger, or can be larger, than the breakdown voltage between the gate electrode and source electrode of the target transistor 10b. In other words, the potential difference between levels LV1 and LV2 is larger, or can be larger, than the breakdown voltage between the gate electrode and source electrode of the target transistor 10b. In consideration of this, a drive circuit 20b for driving the gate of the GaN target transistor 10b is provided in the semiconductor device 1b.

[0045] The drive circuit 20b includes a rectified voltage generation circuit 21b, a linear regulator 22b, and a driver 23b. The rectified voltage generation circuit 21b generates a rectified voltage Vr by rectifying the control signal Scnt based on the potential of the internal wiring Wb_KS2 (hence the potential of the external terminal Tb_KS and the potential of the source electrode of the target transistor 10b). The rectified voltage Vr is a pulsating voltage (pulsating voltage), as described below (see FIG. 12). The linear regulator 22b generates a drive voltage Vdrv, which is a DC voltage, by stepping down the rectified voltage Vr. The drive voltage Vdrv is a DC voltage with a potential higher than a low level LV2 (ground potential here). The absolute value of the potential difference between the low level LV2 and the drive voltage Vdrv is greater than the gate threshold voltage of the target transistor 10b. Therefore, when the drive voltage Vdrv is supplied to the gate electrode of the target transistor 10b, the target transistor 10b is turned on. On the other hand, when a voltage having a low level LV2 is supplied to the gate electrode of the target transistor 10b, the target transistor 10b is turned off.

[0046] The driver 23b receives the drive voltage Vdrv and the control signal Scnt through the external terminal Tb_G. The driver 23b is also connected to the gate electrode of the target transistor 10b through the internal wiring Wb_G and to the external terminal Tb_KS through the internal wiring Wb_KS2. The driver 23b controls the voltage of the gate electrode of the target transistor 10b based on the drive voltage Vdrv and the control signal Scnt, with the potential of the external terminal Tb_KS as a reference, thereby turning the target transistor 10b on or off. In other words, the driver 23b controls the voltage between the gate electrode and source electrode of the target transistor 10b based on the drive voltage Vdrv and the control signal Scnt, thereby turning the target transistor 10b on or off. The driver 23b supplies the drive voltage Vdrv to the gate electrode of the target transistor 10b during the high-level period of the control signal Scnt, thereby turning the target transistor 10b on. During the low-level period of the control signal Scnt, the driver 23b supplies a voltage having the potential of the internal wiring Wb_KS2 (and therefore the potential of the external terminal Tb_KS and the potential of the source electrode of the target transistor 10b) to the gate electrode of the target transistor 10b, thereby setting the target transistor 10b to an off state. Here, it is assumed that the external wirings WR2 and WR4 are connected to ground, so the voltage between the gate electrode and source electrode of the target transistor 10b is equal to the drive voltage Vdrv during the high-level period of the control signal Scnt and equal to 0 V during the low-level period of the control signal Scnt. Note that the high-level period of the control signal Scnt refers to the period during which the control signal Scnt is at high level LV1, and the low-level period of the control signal Scnt refers to the period during which the control signal Scnt is at low level LV2.

[0047] The drive voltage Vdrv has a level suitable for driving the gate of the target transistor 10b made of GaN. The linear regulator 22b generates the drive voltage Vdrv from the rectified voltage Vr so that the drive voltage Vdrv has a predetermined target level LV3 (see FIG. 12). The target level LV3 is lower than the high level LV1 and higher than the low level LV2. However, the potential difference between the target level LV3 and the low level LV2 is greater than the gate threshold voltage of the target transistor 10b and smaller than the breakdown voltage between the gate electrode and source electrode of the target transistor 10b. Therefore, the target transistor 10b can be driven safely.

[0048] FIG. 11 shows the internal configuration of the rectified voltage generating circuit 21b and its peripheral configuration. FIG. 12 shows the waveforms of the control signal Scnt, the rectified voltage Vr, and the drive voltage Vdrv. The rectified voltage generating circuit 21b includes a rectifier diode 211 and a capacitor 212. The anode of the rectifier diode 211 is connected to the external terminal Tb_G via the internal wiring Wb_IN. The cathode of the rectifier diode 211 and a first end of the capacitor 212 are commonly connected to a node 213 within the semiconductor chip CPb2. The second end of the capacitor 212 is connected to a reference node NDref. The reference node NDref is connected to the external terminal Tb_KS via the internal wiring Wb_KS2 and therefore has the potential of the source electrode of the target transistor 10b (and therefore the potential of the external terminal Tb_KS and the potential of the external wiring WR4). The voltage at the node 213 is the rectified voltage Vr.

[0049] The control signal supply circuit 3 has a terminal 3a connected to an external wiring WR3 and a terminal 3b connected to an external wiring WR4, and sets the potential of the terminal 3b to a low level LV2 and a potential higher than the potential of the terminal 3b by a voltage V12 to a high level LV1.

[0050] During the high-level period of the control signal Scnt, the control signal supply circuit 3 supplies a charging current to the capacitor 212 through the rectifier diode 211. The charging current flows in a current loop from the terminal 3a via the external terminal Tb_G, the rectifier diode 211, the capacitor 212, and the external terminal Tb_KS to the terminal 3b, and then returns to the terminal 3a within the control signal supply circuit 3. During the low-level period of the control signal Scnt, the charging current is not generated. The forward voltage of the rectifier diode 211 is represented by the symbol "Vf." Then, during the high-level period of the control signal Scnt, the rectified voltage Vr has a potential lower than the high level LV1 by the forward voltage Vf, and during the low-level period of the control signal Scnt, the rectified voltage Vr gradually decreases in accordance with the power consumption of the linear regulator 22b.

[0051] The initial level of the control signal Scnt is a low level LV2. After the level of the control signal Scnt first rises to a high level LV1, the rectified voltage Vr rises to a predetermined voltage V LIM The semiconductor device 1b and the control signal supply circuit 3 are designed so that the voltage V does not fall below the predetermined voltage V. LIM has a level higher than the target level LV3, and the linear regulator 22b controls the rectified voltage Vr to be a predetermined voltage V LIM When this is the case or more, the level of the drive voltage Vdrv can be maintained at the target level LV3.

[0052] FIG. 13 shows a linear regulator 1100 as an example of the linear regulator 22b. The linear regulator 1100 includes an output transistor 1101, a transistor 1102, a Zener diode 1103, a resistor 1104, and a capacitor 1105. The transistors 1101 and 1102 are N-channel MOSFETs. The drain of the output transistor 1101 and a first terminal of the resistor 1104 are connected to a node 213 to which the rectified voltage Vr is applied. The second terminal of the resistor 1104 is connected to the gate of the output transistor 1101 and the drain and gate of the transistor 1102. The source of the transistor 1102 is connected to the cathode of the Zener diode 1103. The source of the output transistor 1101 and a first terminal of the capacitor 1105 are connected to an output node 1106. The second terminal of the capacitor 1105 and the anode of the Zener diode 1103 are connected to a reference node NDref. In the linear regulator 1100, the voltage at the output node 1106 is the drive voltage Vdrv, and the drive voltage Vdrv at the output node 1106 is supplied to the driver 23b.

[0053] In linear regulator 1100, the sum of the Zener voltage of Zener diode 1103 and the gate threshold voltage of transistor 1102 is applied as reference voltage Vref0 to the gate of output transistor 1101. Output transistor 1101 generates a voltage lower than reference voltage Vref0 by its own gate threshold voltage as drive voltage Vdrv at output node 1106. In linear regulator 1100, components 1102 to 1104 control the potential of the gate of output transistor 1101 so that drive voltage Vdrv has a target level LV3.

[0054] The linear regulator 22b may be any linear regulator as long as it can generate the drive voltage Vdrv having the target level LV3 by stepping down the rectified voltage Vr.

[0055] For example, the linear regulator 1110 in FIG. 14 can be used as the linear regulator 22b. The linear regulator 1110 includes an output transistor 1111, an operational amplifier 1112, resistors 1113 and 1114, and a reference voltage source 1115. The output transistor 1111 is a P-channel MOSFET. In the linear regulator 1110, the source of the output transistor 1111 is connected to a node 213 to which the rectified voltage Vr is applied, the drain of the output transistor 1111 is connected to an output node 1116, and the gate of the output transistor 1111 is connected to the output terminal of the operational amplifier 1112. In the linear regulator 1110, a first terminal of the resistor 1113 is connected to the output node 1116, and a second terminal of the resistor 1113 is connected to a first terminal of a resistor 1114. A second terminal of the resistor 1114 is connected to a reference node NDref. In the linear regulator 1110, the voltage at the output node 1116 is the drive voltage Vdrv, and the drive voltage Vdrv at the output node 1116 is supplied to the driver 23b. In the linear regulator 1110, a feedback voltage Vfb1, which is a divided voltage of the drive voltage Vdrv, is generated at a connection node between resistors 1113 and 1114. In the linear regulator 1110, the connection node between resistors 1113 and 1114 is connected to the non-inverting input terminal of an operational amplifier 1112, and the feedback voltage Vfb1 is applied to the non-inverting input terminal of the operational amplifier 1112. In the linear regulator 1110, a reference voltage source 1115 is connected to a reference node NDref and generates a predetermined reference voltage Vref1 higher than the potential of the reference node NDref. In the linear regulator 1110, the reference voltage Vref1 from the reference voltage source 1115 is supplied to the inverting input terminal of the operational amplifier 1112. The operational amplifier 1112 and the reference voltage source 1115 are driven using the rectified voltage Vr as a power supply voltage with the potential of the reference node NDref as a reference.

[0056] In the linear regulator 1110, when "Vfb1 > Vref1" holds, the operational amplifier 1112 raises the potential of the gate of the output transistor 1111 to decrease the drain current of the output transistor 1111 (the current flowing from node 213 through the output transistor 1111 towards the output node 1116). When "Vfb1 < Vref1" holds, the operational amplifier 1112 lowers the potential of the gate of the output transistor 1111 to increase the drain current of the output transistor 1111. As a result, in the linear regulator 1110, the potential of the gate of the output transistor 1111 is controlled by the operational amplifier 1112 so that the feedback voltage Vfb1 and the reference voltage Vref1 match. The drive voltage Vdrv when "Vfb1 = Vref1" has the target level LV3.

[0057] For example, the linear regulator 1120 in FIG. 15 may be used as the linear regulator 22b. By replacing the output transistor 1111 in the linear regulator 1110 of FIG. 14 with the output transistor 1121 which is a PNP bipolar transistor, the linear regulator 1110 is transformed into the linear regulator 1120. Along with this replacement, in the linear regulator 1120, the emitter of the output transistor 1121 is connected to the node 213 to which the rectified voltage Vr is applied, the collector of the output transistor 1121 is connected to the output node 1116, and the base of the output transistor 1121 is connected to the output terminal of the operational amplifier 1112. In other respects, the configuration of the linear regulator 1120 is the same as that of the linear regulator 1110.

[0058] In the linear regulator 1120, when "Vfb1 > Vref1" holds, the operational amplifier 1112 increases the potential of the base of the output transistor 1121 to decrease the collector current of the output transistor 1121 (the current flowing from node 213 through the output transistor 1121 towards the output node 1116), and when "Vfb1 < Vref1" holds, it decreases the potential of the base of the output transistor 1121 to increase the collector current of the output transistor 1121. As a result, in the linear regulator 1120, the potential of the base of the output transistor 1121 is controlled by the operational amplifier 1112 so that the feedback voltage Vfb1 and the reference voltage Vref1 match. The drive voltage Vdrv when "Vfb1 = Vref1" has the target level LV3.

[0059] Also, for example, the linear regulator 1130 in FIG. 16 may be used as the linear regulator 22b. By replacing the output transistor 1111 in the linear regulator 1110 of FIG. 14 with an output transistor 1131 which is an N-channel type MOSFET, the linear regulator 1110 is transformed into the linear regulator 1130. Along with this replacement, in the linear regulator 1130, the drain of the output transistor 1131 is connected to the node 213 to which the rectified voltage Vr is applied, the source of the output transistor 1131 is connected to the output node 1116, and the gate of the output transistor 1131 is connected to the output terminal of the operational amplifier 1112. Further, along with this replacement, in the linear regulator 1130, the connection node between the resistors 1113 and 1114 is connected to the inverting input terminal of the operational amplifier 1112 so that the feedback voltage Vfb1 is applied to the inverting input terminal of the operational amplifier 1112, and the reference voltage Vref1 from the reference voltage source 1115 is supplied to the non-inverting input terminal of the operational amplifier 1112. In other respects, the configuration of the linear regulator 1130 is the same as that of the linear regulator 1110.

[0060] In the linear regulator 1130, when "Vfb1 > Vref1" holds, the operational amplifier 1112 reduces the potential of the gate of the output transistor 1131, thereby decreasing the drain current of the output transistor 1131 (the current flowing from node 213 through the output transistor 1131 towards the output node 1116). When "Vfb1 < Vref1" holds, the operational amplifier 1112 increases the potential of the gate of the output transistor 1131, thereby increasing the drain current of the output transistor 1131. As a result, in the linear regulator 1130, the potential of the gate of the output transistor 1131 is controlled by the operational amplifier 1112 so that the feedback voltage Vfb1 and the reference voltage Vref1 match. The drive voltage Vdrv when "Vfb1 = Vref1" has the target level LV3.

[0061] Also, for example, the linear regulator 1140 in FIG. 17 may be used as the linear regulator 22b. By replacing the output transistor 1111 in the linear regulator 1110 of FIG. 14 with an output transistor 1141 which is an NPN bipolar transistor, the linear regulator 1110 is transformed into the linear regulator 1140. Along with this replacement, in the linear regulator 1140, the collector of the output transistor 1141 is connected to the node 213 to which the rectified voltage Vr is applied, the emitter of the output transistor 1141 is connected to the output node 1116, and the base of the output transistor 1141 is connected to the output terminal of the operational amplifier 1112. Further, along with this replacement, in the linear regulator 1140, the connection node between the resistors 1113 and 1114 is connected to the inverting input terminal of the operational amplifier 1112, so that the feedback voltage Vfb1 is applied to the inverting input terminal of the operational amplifier 1112, and the reference voltage Vref1 from the reference voltage source 1115 is supplied to the non-inverting input terminal of the operational amplifier 1112. In other respects, the configuration of the linear regulator 1140 is the same as that of the linear regulator 1110.

[0062] In the linear regulator 1140, when "Vfb1 > Vref1" holds, the operational amplifier 1112 reduces the base potential of the output transistor 1141 to decrease the emitter current of the output transistor 1141 (the current flowing from node 213 through the output transistor 1141 to the output node 1116), and when "Vfb1 < Vref1" holds, the operational amplifier 1112 increases the base potential of the output transistor 1141 to increase the emitter current of the output transistor 1141. As a result, in the linear regulator 1140, the base potential of the output transistor 1141 is controlled by the operational amplifier 1112 so that the feedback voltage Vfb1 and the reference voltage Vref1 match. The drive voltage Vdrv when "Vfb1 = Vref1" has the target level LV3.

[0063] As shown in Figures 18 to 21, the reference voltage Vref1 may be generated by a voltage generation circuit 1117 including a resistor 1117_1 and a Zener diode 1117_2. That is, the linear regulators 1110 to 1140 shown in Figures 14 to 17 may be modified to linear regulators 1110a to 1140a shown in Figures 18 to 21, respectively. By replacing the reference voltage source 1115 in the linear regulators 1110, 1120, 1130, and 1140 with the voltage generation circuit 1117, the linear regulators 1110a, 1120a, 1130a, and 1140a are obtained, respectively. Except for the replacement of the reference voltage source 1115 with the voltage generation circuit 1117, the configurations and operations of the linear regulators 1110a to 1140a are similar to those of the linear regulators 1110 to 1140, respectively. However, upon this replacement, in the linear regulators 1110a to 1140a, a first end of a resistor 1117_1 is connected to a node 213 to which the rectified voltage Vr is applied, a second end of the resistor 1117_1 is connected to a cathode of a Zener diode 1117_2, and an anode of the Zener diode 1117_2 is connected to a reference node NDref, so that a reference voltage Vref1 corresponding to the Zener voltage of the Zener diode 1117_2 is applied to the cathode of the Zener diode 1117_2. In the linear regulators 1110a and 1120a, the reference voltage Vref1 from the voltage generation circuit 1117 is supplied to the inverting input terminal of the operational amplifier 1112, and in the linear regulators 1130a and 1140a, the reference voltage Vref1 from the voltage generation circuit 1117 is supplied to the non-inverting input terminal of the operational amplifier 1112. The voltage generating circuit 1117 can also be considered to be one form of the reference voltage source 1115 .

[0064] Alternatively, for example, the linear regulator 1150 in FIG. 22 may be used as the linear regulator 22b. The linear regulator 1150 includes an operational amplifier 1152, resistors 1153 and 1154, and a reference voltage source 1155. In the linear regulator 1150, the output terminal of the operational amplifier 1152 and a first terminal of the resistor 1153 are connected to an output node 1156, and the second terminal of the resistor 1153 is connected to a first terminal of the resistor 1154. The second terminal of the resistor 1154 is connected to the reference node NDref (and therefore to ground). In the linear regulator 1150, the voltage at the output node 1156 is the drive voltage Vdrv, and the drive voltage Vdrv at the output node 1156 is supplied to the driver 23b. In the linear regulator 1150, a feedback voltage Vfb2, which is a divided voltage of the drive voltage Vdrv, is generated at the connection node between the resistors 1153 and 1154. In the linear regulator 1150, the connection node between resistors 1153 and 1154 is connected to the inverting input terminal of the operational amplifier 1152, and a feedback voltage Vfb2 is applied to the inverting input terminal of the operational amplifier 1152. In the linear regulator 1150, a reference voltage source 1155 is connected to a reference node NDref, and generates a predetermined reference voltage Vref2 higher than the potential of the reference node NDref, and supplies this to the non-inverting input terminal of the operational amplifier 1152. The operational amplifier 1152 and the reference voltage source 1155 are driven using the rectified voltage Vr as a power supply voltage, with the potential of the reference node NDref as the reference.

[0065] In the linear regulator 1150, a drive voltage Vdrv is output from the output terminal of an operational amplifier 1152. The operational amplifier 1152 directly controls the potential of an output node 1156 (i.e., the level of the drive voltage Vdrv) so that the feedback voltage Vfb2 and the reference voltage Vref2 match. When "Vfb2=Vref2", the drive voltage Vdrv has a target level LV3.

[0066] As shown in FIG. 23, the reference voltage Vref2 may be generated by a voltage generation circuit 1157 including a resistor 1157_1 and a Zener diode 1157_2. That is, the linear regulator 1150 in FIG. 22 may be modified into a linear regulator 1150a in FIG. 23. The linear regulator 1150a is obtained by replacing the reference voltage source 1115 in the linear regulator 1150 with the voltage generation circuit 1157. Except for the fact that the reference voltage source 1115 is replaced with the voltage generation circuit 1157, the configuration and operation of the linear regulator 1150a are similar to those of the linear regulator 1150. However, in this replacement, in the linear regulator 1150a, a first terminal of a resistor 1157_1 is connected to a node 213 to which the rectified voltage Vr is applied, a second terminal of the resistor 1157_1 is connected to a cathode of a Zener diode 1157_2, and an anode of the Zener diode 1157_2 is connected to a reference node NDref. As a result, a reference voltage Vref2 corresponding to the Zener voltage of the Zener diode 1157_2 is applied to the cathode of the Zener diode 1157_2. In the linear regulator 1150a, the reference voltage Vref2 from a voltage generation circuit 1157 is supplied to the non-inverting input terminal of the operational amplifier 1112. The voltage generation circuit 1157 can also be considered as one form of the reference voltage source 1155.

[0067] <<Third Example>> A third embodiment will now be described. In the first embodiment, the type of the casing CS of the semiconductor device 1 and the total number of external terminals can be modified in various ways. For example, the semiconductor device 1a in FIG. 4 can be modified into the semiconductor device 1c in FIG.

[0068] Fig. 24 is a transparent plan view of semiconductor device 1c. In Fig. 24, the outline of the semiconductor chip provided in semiconductor device 1c is illustrated in a dashed rectangular frame, and the internal wiring of semiconductor device 1c is illustrated in solid line segments. Note that Fig. 24 illustrates the internal wiring schematically, and the actual number of internal wirings is arbitrary. Semiconductor device 1c has a housing CSc as its housing CS.

[0069] The semiconductor device 1c has external terminals Ta_KS and Ta_G as the external terminals T_KS and T_G. The semiconductor device 1c has external terminals Ta_D1 to Ta_D3, and the external terminals Ta_D1 to Ta_D3 form the external terminal Ta_D. Although not clear from FIG. 24, the external terminals Ta_D1 to Ta_D3 are coupled to one another by a metal body provided on the back surface of the casing CSc, and the external terminals Ta_D1 to Ta_D3 form an integrated metal terminal (Ta_D). The semiconductor device 1c has external terminals Ta_PS1 to Ta_PS6, and the external terminals Ta_PS1 to Ta_PS6 form the external terminal Ta_PS. Although not clear from FIG. 24, the external terminals Ta_PS1 to Ta_PS6 are coupled to one another by a metal body provided on the back surface of the casing CSc, and the external terminals Ta_PS1 to Ta_PS6 form an integrated metal terminal (Ta_PS). The external terminals Ta_D, Ta_PS, Ta_KS, and Ta_G are a drain terminal, a power source terminal, a Kelvin source terminal, and a gate terminal, respectively. The Kelvin source terminal is sometimes called a driver source terminal.

[0070] In the semiconductor device 1c, a semiconductor chip CPa is housed in a housing CSc. The semiconductor device 1c according to the third embodiment differs from the semiconductor device 1a according to the first embodiment only in the shape of the housing CS and the total number of external terminals. The configuration of the semiconductor chip CPa is the same between the semiconductor devices 1a and 1c, and the connection relationship between the target transistor 10a in the semiconductor chip CPa and the external terminals Ta_D, Ta_PS, Ta_KS, and Ta_G is also the same between the semiconductor devices 1a and 1c. Therefore, for matters not shown in the third embodiment, the description of the first embodiment also applies to the third embodiment. In this application, the symbols "1a" and "CSa" in the description of the first embodiment are replaced with the symbols "1c" and "CSc," respectively, in the third embodiment.

[0071] <<Fourth Example>> A fourth embodiment will now be described. In the second embodiment, the type of the casing CS of the semiconductor device 1 and the total number of external terminals can be modified in various ways. For example, the semiconductor device 1b in FIG. 9 can be modified into the semiconductor device 1d in FIG. 25 in accordance with the semiconductor device 1c in FIG. 24.

[0072] Fig. 25 is a transparent plan view of semiconductor device 1d. In Fig. 25, the outline of the semiconductor chip provided in semiconductor device 1d is illustrated by a dashed rectangular frame, and the internal wiring of semiconductor device 1d is illustrated by solid line segments. Note that Fig. 25 illustrates the internal wiring schematically, and the actual number of internal wirings is arbitrary. Semiconductor device 1d has a housing CSd as its housing CS.

[0073] The semiconductor device 1d has external terminals Tb_KS and Tb_G as the external terminals T_KS and T_G. The semiconductor device 1d has external terminals Tb_D1 to Tb_D3, and the external terminals Tb_D1 to Tb_D3 form the external terminal Tb_D. Although not clear from FIG. 25, the external terminals Tb_D1 to Tb_D3 are connected to one another by a metal body provided on the back surface of the casing CSd, and the external terminals Tb_D1 to Tb_D3 form an integrated metal terminal (Tb_D). The semiconductor device 1d has external terminals Tb_PS1 to Tb_PS6, and the external terminals Tb_PS1 to Tb_PS6 form the external terminal Tb_PS. Although not clear from FIG. 25, the external terminals Tb_PS1 to Tb_PS6 are connected to one another by a metal body provided on the back surface of the casing CSd, and the external terminals Tb_PS1 to Tb_PS6 form an integrated metal terminal (Tb_PS). The external terminals Tb_D, Tb_PS, Tb_KS, and Tb_G are a drain terminal, a power source terminal, a Kelvin source terminal, and a control signal input terminal, respectively. The Kelvin source terminal is sometimes called a driver source terminal.

[0074] In the semiconductor device 1d, semiconductor chips CPb1 and CPb2 are housed in a housing CSd. The semiconductor device 1d according to the fourth embodiment differs from the semiconductor device 1b according to the second embodiment only in the shape of the housing CS and the total number of external terminals. The configurations of the semiconductor chips CPb1 and CPb2 are the same as those of the semiconductor devices 1b and 1d. The connection relationship between the target transistor 10b in the semiconductor chip CPb1 and the external terminals Tb_D, Tb_PS, and Tb_KS is the same as that of the semiconductor devices 1b and 1d. The connection relationship between the drive circuit 20b in the semiconductor chip CPb2 and the external terminals Tb_KS and Tb_G and the target transistor 10b is the same as that of the semiconductor devices 1b and 1d. The configuration and operation of the drive circuit 20b are the same as those described in the second embodiment. Therefore, for matters not described in the fourth embodiment, the description of the second embodiment also applies to the fourth embodiment. In this application, the symbols "1b" and "CSb" in the description of the second embodiment are to be read as symbols "1d" and "CSd", respectively, in the fourth embodiment.

[0075] The positional relationship between the external terminals Tb_D1 to Tb_D3, Tb_PS1 to Tb_PS6, Tb_KS and Tb_G in the semiconductor device 1d is the same as the positional relationship between the external terminals Ta_D1 to Ta_D3, Ta_PS1 to Ta_PS6, Ta_KS and Ta_G in the semiconductor device 1c (see FIGS. 24 and 25). The shapes of the external terminals Tb_D1 to Tb_D3, Tb_PS1 to Tb_PS6, Tb_KS, and Tb_G in the semiconductor device 1d are the same as the shapes of the external terminals Ta_D1 to Ta_D3, Ta_PS1 to Ta_PS6, Ta_KS, and Ta_G in the semiconductor device 1c, respectively, and the sizes of the external terminals Tb_D1 to Tb_D3, Tb_PS1 to Tb_PS6, Tb_KS, and Tb_G in the semiconductor device 1d are also the same as the sizes of the external terminals Ta_D1 to Ta_D3, Ta_PS1 to Ta_PS6, Ta_KS, and Ta_G in the semiconductor device 1c, respectively. Furthermore, the shape and size of the casing CSd in the semiconductor device 1d are the same as the shape and size of the casing CSc in the semiconductor device 1c (see FIGS. 24 and 25). Therefore, in the switching system SYS (see FIG. 1), the semiconductor device 1c can be replaced with the semiconductor device 1d without any need to change the pattern of the substrate, etc. The shape and size of the housing CSd may be slightly different from the shape and size of the housing CSc.

[0076] In addition, the shape of the casing CS in the semiconductor device 1 and the total number and arrangement positions of the external terminals can be designed arbitrarily. For example, the semiconductor device 1b in FIG. 9 may be modified into the semiconductor device 1f in FIG. 26. FIG. 26 is a transparent plan view of the semiconductor device 1f. In FIG. 26, the outer shape of the semiconductor chip provided in the semiconductor device 1f is illustrated in a dashed rectangular frame, and the internal wiring of the semiconductor device 1f is illustrated in solid line segments. Note that the internal wiring is illustrated schematically in FIG. 26, and the actual number of internal wirings, etc., is arbitrary. The semiconductor device 1f has a casing CSf as its casing CS.

[0077] The semiconductor device 1f has external terminals Tb_KS and Tb_G as the external terminals T_KS and T_G. The semiconductor device 1f has external terminals Tb_D11 to Tb_D14, and the external terminals Tb_D11 to Tb_D14 form the external terminal Tb_D. The external terminals Tb_D11 to Tb_D14 may be coupled to each other by a metal body provided on the back surface of the housing CSf, and the external terminals Tb_D11 to Tb_D14 may form an integrated metal terminal (Tb_D). The semiconductor device 1f has external terminals Tb_PS11 and Tb_PS12, and the external terminals Tb_PS11 and Tb_PS12 may form an integrated metal terminal (Tb_PS). The external terminals Tb_PS11 and Tb_PS12 may be coupled to each other by a metal body provided on the back surface of the housing CSf, and the external terminals Tb_PS11 and Tb_PS12 may form an integrated metal terminal (Tb_PS). The external terminals Tb_D, Tb_PS, Tb_KS, and Tb_G are a drain terminal, a power source terminal, a Kelvin source terminal, and a control signal input terminal, respectively. The Kelvin source terminal is sometimes called a driver source terminal.

[0078] In the semiconductor device 1f, semiconductor chips CPb1 and CPb2 are housed in a housing CSf. The semiconductor device 1f differs from the semiconductor device 1b of the second embodiment only in the shape of the housing CS and the total number of external terminals, and the configurations of the semiconductor chips CPb1 and CPb2 are the same between the semiconductor devices 1b and 1f. The connection relationship between the target transistor 10b in the semiconductor chip CPb1 and the external terminals Tb_D, Tb_PS, and Tb_KS is the same between the semiconductor devices 1b and 1f. The connection relationship between the drive circuit 20b in the semiconductor chip CPb2 and the external terminals Tb_KS and Tb_G, as well as the target transistor 10b, is the same between the semiconductor devices 1b and 1f. The configuration and operation of the drive circuit 20b are the same as those described in the second embodiment.

[0079] <<Fifth Example>> A fifth embodiment will be described. Two types of casings are given as the casing CS of the semiconductor device 1. Semiconductor device 1b is described as a semiconductor device that can replace semiconductor device 1a having casing CSa (see FIGS. 4 and 9), and semiconductor device 1d is described as a semiconductor device 1 that can replace semiconductor device 1c having casing CSc (see FIGS. 24 and 25). However, as already mentioned, the type of casing CS of semiconductor device 1 and the total number of external terminals can be varied in various ways. When a semiconductor device having target transistor 10a is distributed as a reference semiconductor device (see FIG. 5), by forming a semiconductor device having target transistor 10b and driver circuit 20b to match the external terminal configuration and shape of the reference semiconductor device (see FIG. 10), the reference semiconductor device can be replaced with the latter semiconductor device (a semiconductor device having target transistor 10b and driver circuit 20b) without any need to change the substrate pattern, etc.

[0080] A system including both semiconductor devices 1a and 1b may be configured. That is, for example, a system including the switching system SYS of Fig. 5 and the switching system SYS of Fig. 10 may be configured. Similarly, a system including both semiconductor devices 1c and 1d may be configured.

[0081] In some cases, the semiconductor device 1 does not have a Kelvin source terminal. FIG. 27 shows an example of the external appearance of the semiconductor device 1 that does not have the external terminal T_KS, which is a Kelvin source terminal. When the semiconductor device 1 does not have the external terminal T_KS, the portions described as being connected to the external terminal T_KS are connected to the external terminal T_PS, which is a power source terminal, instead of the external terminal T_KS. Therefore, when the semiconductor device 1a according to the first embodiment does not have the external terminal Ta_KS (Kelvin source terminal) (see FIGS. 4 and 5, etc.), the portions described as being connected to the external terminal Ta_KS in the first embodiment may be interpreted as being connected to the external terminal Ta_PS instead of the external terminal Ta_KS. The same applies to the third embodiment. When the semiconductor device 1b according to the second embodiment does not have the external terminal Tb_KS (Kelvin source terminal) (see FIGS. 9 and 10, etc.), the portions described as being connected to the external terminal Tb_KS in the second embodiment may be interpreted as being connected to the external terminal Tb_PS instead of the external terminal Tb_KS. The same applies to the fourth embodiment.

[0082] As described above, it is assumed that the target transistor 10b is formed of a first semiconductor material, and that the first semiconductor material is GaN (gallium nitride). However, the first semiconductor material may be a semiconductor material other than GaN (e.g., Si or SiC). When it is desired to replace an existing target transistor 10 formed of a certain semiconductor material with a target transistor 10 formed of a different semiconductor material, and when the breakdown voltage between the gate electrode and source electrode of the latter target transistor 10 is lower than the breakdown voltage between the gate electrode and source electrode of the former target transistor 10 due to the difference in semiconductor material, the configurations shown in the second and fourth embodiments can be employed.

[0083] The technology according to the present disclosure can be applied to any application requiring a switching element. For example, the semiconductor device 1 can be applied to a switching transistor in a switching power supply. The technology according to the present disclosure (the semiconductor device 1, the switching system SYS) can be applied to any AC / DC adapter, as well as to power supplies in data centers, servers, or base stations, and can also be applied to on-board chargers or automotive DC / DC converters. The technology according to the present disclosure (the semiconductor device 1, the switching system SYS) can also be applied to motor drivers, LED drivers, etc.

[0084] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0085] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0086] A semiconductor device according to one aspect of the present disclosure is a semiconductor device (1b, 1d) including a target transistor (10b) having a drain electrode, a source electrode, and a gate electrode, a drive circuit (20b), a housing (CSb, CSd) that houses the target transistor and the drive circuit, and a plurality of external terminals exposed from the housing, wherein the plurality of external terminals include a drain terminal (Tb_D) connected to the drain electrode, source terminals (Tb_PS, Tb_KS) connected to the source electrode, and a control signal input terminal (Tb_G) configured to receive a control signal (Scnt) from outside the semiconductor device, and the control signal is transmitted to the target transistor. The control signal is a rectangular wave signal that alternates between a first level (LV1) that instructs a transistor to be turned on and a second level (LV2) that instructs the transistor to be turned off, and the drive circuit has a configuration (first configuration) that includes: a rectified voltage generation circuit (21b) configured to generate a rectified voltage (Vr) by rectifying the control signal; a linear regulator (22b) configured to generate a drive voltage (Vdrv) by stepping down the rectified voltage; and a driver (23b) configured to turn the target transistor on or off by controlling the voltage between the gate electrode and the source electrode in accordance with the control signal based on the drive voltage.

[0087] This allows the target transistor to be driven by converting an externally supplied control signal into a signal suitable for the target transistor. By using the semiconductor device according to the first configuration, an existing transistor formed of a certain semiconductor material can be easily replaced with a target transistor formed of another semiconductor material without requiring changes to the pattern of the substrate on which each component is mounted.

[0088] In the semiconductor device according to the first configuration, the linear regulator may generate the drive voltage having a target level (LV3) lower than the first level and higher than the second level by stepping down the rectified voltage, the potential of the source terminal has the second level, and the potential difference between the target level and the second level may be greater than the gate threshold voltage of the target transistor and smaller than the breakdown voltage between the gate electrode and the source electrode (second configuration).

[0089] This allows the target transistor to be driven safely regardless of the level of the control signal.

[0090] In the semiconductor device according to the second configuration (see Figures 13 to 21), the linear regulator may have an output transistor (1101, 1111, 1121, 1131, 1141) inserted between the node (213) to which the rectified voltage is applied and the node to which the driving voltage is applied, and may be configured (third configuration) to control the potential of the gate or base of the output transistor so that the driving voltage has the target level.

[0091] In the semiconductor device according to the second configuration (see Figures 22 and 23), the linear regulator may have an operational amplifier (1152) configured to output the drive voltage, and the operational amplifier may be configured (fourth configuration) to adjust the level of the drive voltage to the target level by adjusting the drive voltage so that a predetermined reference voltage (Vref2) matches a feedback voltage (Vfb2) corresponding to the drive voltage.

[0092] In the semiconductor device according to any one of the first to fourth configurations, the rectified voltage generating circuit may be configured (fifth configuration) to include a rectifier diode (211) having an anode connected to the control signal input terminal and a cathode connected to a node to which the rectified voltage is applied, and a capacitor (212) provided between the node (213) to which the rectified voltage is applied and a reference node (NDref) having the potential of the source electrode.

[0093] In the semiconductor device according to any of the first to fifth configurations, the driver may be configured (sixth configuration) to set the target transistor to an on state by supplying the drive voltage to the gate electrode of the target transistor during a period in which the control signal has the first level, and to set the target transistor to an off state by supplying a voltage having the potential of the source electrode to the gate electrode of the target transistor during a period in which the control signal has the second level.

[0094] In the semiconductor device according to any one of the first to sixth configurations, the potential difference between the first level and the second level may be larger than the breakdown voltage between the gate electrode and the source electrode (seventh configuration).

[0095] If the potential difference between the first level and the second level is greater than the breakdown voltage between the gate electrode and the source electrode, problems will arise if a control signal is supplied directly to the gate of the target transistor, but by using the semiconductor device disclosed herein, the target transistor can be driven safely.

[0096] In the semiconductor device according to any of the first to seventh configurations, the source terminal may include a power source terminal (Tb_PS) including a package inductance component and a Kelvin source terminal (Tb_KS), the source electrode of the target transistor is individually connected to the power source terminal and the Kelvin source terminal, the driver is connected to the gate electrode of the target transistor and the Kelvin source terminal, and controls the voltage of the gate electrode of the target transistor based on the potential of the Kelvin source terminal in accordance with the control signal based on the drive voltage (eighth configuration).

[0097] In the semiconductor device according to the eighth configuration, a first semiconductor chip (CPb1) on which the target transistor is formed and a second semiconductor chip (CPb2) on which the drive circuit is formed may be housed in the housing, the first semiconductor chip is connected to the drain terminal through drain wiring (Wb_D) inside the housing, thereby connecting the drain electrode to the drain terminal, the first semiconductor chip is connected to the power source terminal through power source wiring (Wb_PS) inside the housing, thereby connecting the source electrode to the power source terminal, the second semiconductor chip is connected to the control signal input terminal through input wiring (Wb_IN) inside the housing, thereby inputting the control signal to the drive circuit, and the first semiconductor chip and the second semiconductor chip may be individually connected to the Kelvin source terminal through Kelvin source wiring (Wb_KS1, Wb_KS2) inside the housing (ninth configuration).

[0098] In the semiconductor device according to any one of the first to ninth configurations, the target transistor may be formed from GaN (tenth configuration). [Explanation of symbols]

[0099] SYS Switching System 1, 1a, 1b, 1c, 1d, 1f Semiconductor device 2 Target circuit 3 Control signal supply circuit 10, 10a, 10b Target transistor WR1~WR4 external wiring Scnt control signal CS, CSa, CSb, CSc, CSd, CSf Housing T_D, T_PS, T_KS, T_G external terminals Ta_D, Ta_PS, Ta_KS, Ta_G external terminals Tb_D, Tb_PS, Tb_KS, Tb_G external terminals CPa, CPb1, CPb2 semiconductor chips Wb_D, Wb_PS, Wb_KS1, Wb_KS2, Wb_G, Wb_IN internal wiring 20b Drive circuit 21b Rectified voltage generation circuit 22b Linear Regulator 23b driver Vr Rectified voltage Vdrv drive voltage 211 Rectifier diode 212 Capacitor 213 nodes NDref Reference Node 1100, 1110, 1120, 1130, 1140, 1150, 1110a, 1120a, 1130a, 1140a, 1150a linear regulator 1101, 1111, 1121, 1131, 1141 output transistors 1112 1152 operational amplifier Vref0~Vref2 reference voltage Vfb1, Vfb2 feedback voltage Ta_D1~Ta_D3, Tb_D1~Tb_D3, Tb_D11~Tb_D14 external terminals Ta_PS1~Ta_PS6, Tb_PS1~Tb_PS6, Tb_PS11, Tb_PS12 External terminals 810 Resin back 812 Resin through hole 813 recess 814 rear terminal 822 Resin end face 823, 824 Resin protrusions 911~913, 921 Discrete parts 922, 923 Semiconductor chips

Claims

1. a target transistor having a drain electrode, a source electrode, and a gate electrode; A drive circuit; a housing that houses the target transistor and the drive circuit; a plurality of external terminals exposed from the housing, the plurality of external terminals include a drain terminal connected to the drain electrode, a source terminal connected to the source electrode, and a control signal input terminal configured to receive a control signal from outside the semiconductor device; the control signal is a square wave signal that alternates between a first level that instructs the target transistor to be on and a second level that instructs the target transistor to be off, The drive circuit includes a rectified voltage generation circuit configured to generate a rectified voltage by rectifying the control signal, a linear regulator configured to generate a drive voltage by stepping down the rectified voltage, and a driver configured to turn on or off the target transistor by controlling a voltage between the gate electrode and the source electrode in accordance with the control signal based on the drive voltage. , semiconductor device.

2. the linear regulator generates the drive voltage having a target level lower than the first level and higher than the second level by stepping down the rectified voltage; the potential of the source terminal has the second level; The potential difference between the target level and the second level is greater than the gate threshold voltage of the target transistor and less than the breakdown voltage between the gate electrode and the source electrode. The semiconductor device according to claim 1 .

3. The linear regulator has an output transistor inserted between a node to which the rectified voltage is applied and a node to which the drive voltage is applied, and controls the potential of the gate or base of the output transistor so that the drive voltage has the target level. The semiconductor device according to claim 2 .

4. the linear regulator includes an operational amplifier configured to output the drive voltage; The operational amplifier adjusts the drive voltage so that a predetermined reference voltage and a feedback voltage corresponding to the drive voltage coincide with each other, thereby adjusting the level of the drive voltage to the target level. The semiconductor device according to claim 2 .

5. The rectified voltage generating circuit includes a rectifier diode having an anode connected to the control signal input terminal and a cathode connected to a node to which the rectified voltage is applied, and a capacitor provided between the node to which the rectified voltage is applied and a reference node having the potential of the source electrode.

5. The semiconductor device according to claim 1.

6. The driver sets the target transistor to an ON state by supplying the drive voltage to the gate electrode of the target transistor during a period when the control signal has the first level, and sets the target transistor to an OFF state by supplying a voltage having a potential of the source electrode to the gate electrode of the target transistor during a period when the control signal has the second level.

5. The semiconductor device according to claim 1.

7. The potential difference between the first level and the second level is greater than the breakdown voltage between the gate electrode and the source electrode.

5. The semiconductor device according to claim 1.

8. the source terminals include a power source terminal including a package inductance component and a Kelvin source terminal; the source electrode of the target transistor is connected to the power source terminal and the Kelvin source terminal, respectively; The driver is connected to the gate electrode and the Kelvin source terminal of the target transistor, and controls the voltage of the gate electrode of the target transistor based on the drive voltage and the control signal, with the potential of the Kelvin source terminal as a reference.

5. The semiconductor device according to claim 1.

9. a first semiconductor chip on which the target transistor is formed and a second semiconductor chip on which the drive circuit is formed are housed in the housing; the first semiconductor chip is connected to the drain terminal through a drain wiring inside the housing, thereby connecting the drain electrode to the drain terminal; the first semiconductor chip is connected to the power source terminal through a power source wiring inside the housing, thereby connecting the source electrode to the power source terminal; the second semiconductor chip is connected to the control signal input terminal through an input wiring inside the housing, so that the control signal is input to the drive circuit; The first semiconductor chip and the second semiconductor chip are individually connected to the Kelvin source terminal through Kelvin source wiring within the housing. The semiconductor device according to claim 8 .

10. The target transistor is formed of GaN 5. The semiconductor device according to claim 1.

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