SPAD element and manufacturing method of the SPAD element

Abstract

To provide a SPAD element which can prevent deterioration of noise characteristics due to leakage current or the like, reduce noise by miniaturization of a cathode, and reduce power consumption.SOLUTION: A SPAD element includes a trench for separating a SPAD element formed on a substrate from other SPAD elements, a semiconductor film of a first conductivity type formed on a side wall of the trench, a first insulating film formed inside the trench and covering the semiconductor film, an anode electrode layer of the first conductivity type in contact with the semiconductor film, a first semiconductor layer of a second conductivity type provided on a first surface side which is a light incident surface than the anode electrode layer, a conductor layer that is in contact with the first semiconductor layer and is provided on a second surface side that is a surface opposite to the first surface, a cathode electrode layer in which the side wall of the conductor layer is covered with a second insulating film, and a second semiconductor layer that is in contact with the first semiconductor layer and has a first conductivity type.SELECTED DRAWING: Figure 4A

Description

[Technical Field]

[0001] The present invention relates to a SPAD element and a method for manufacturing a SPAD element. [Background technology]

[0002] In recent years, attention has been focused on SPADs (Single Photon Avalanche Diodes), which amplify the electric charge generated by the photoelectric conversion of incident light through avalanche amplification and output it as an electrical signal. SPADs are capable of detecting individual light particles, have extremely high time resolution, and are attracting attention as a photon counting sensor that counts incident photons one by one for each pixel, enabling a high dynamic range and noise-free readout.

[0003] To generate avalanche amplification, a high reverse bias voltage must be applied to the PN junction. However, as pixels become smaller and the distance between the PN junction and the power contact becomes shorter, a strong electric field is formed between them, which can cause leakage current or tunnel current. Such currents are amplified in the strong electric field region even in the dark when there is no light, and can be detected as false signals, resulting in noise.

[0004] Patent Document 1 below discloses the following solid-state imaging device. The device includes a first surface of a semiconductor substrate having a plurality of photoelectric conversion elements, a lattice-shaped first trench, and a second trench provided along the bottom of the first trench. Each photoelectric conversion element includes a photoelectric conversion region that photoelectrically converts incident light and generates electric charges within an element region defined by the first and second trenches. Each photoelectric conversion element includes a first semiconductor region that surrounds the photoelectric conversion region within the element region, a first contact that contacts the first semiconductor region at the bottom of the first trench, and a first electrode that contacts the first contact within the first trench. Each photoelectric conversion element includes a second semiconductor region that is provided in a region that contacts the first semiconductor region within the element region and has the same first conductivity type as the first semiconductor region. Each photoelectric conversion element also includes a third semiconductor region that is provided in a region that contacts the second semiconductor region within the element region, between the second semiconductor region and the first surface, and has a second conductivity type opposite to the first conductivity type. Each photoelectric conversion element includes a second contact provided on the first surface so as to contact the third semiconductor region, and a second electrode in contact with the second contact, The height of the first contact from the first surface is different from the height of the third semiconductor region from the first surface. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2020 / 203222 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the above prior art has the following problems: 1) There is a possibility that noise characteristics will deteriorate due to leakage currents from the anode electrode, etc., inside the trench; 2) There is a limit to how much the cathode electrode can be miniaturized, which increases the volume of the high electric field region, making it difficult to reduce noise; 3) Furthermore, it is not possible to reduce power consumption by reducing the capacitance of the cathode electrode.

[0007] The present invention has been made to solve the above problems by providing a SPAD element and a method for manufacturing the SPAD element that can prevent deterioration of noise characteristics due to leakage current, reduce noise by reducing the volume of the high electric field region, and reduce power consumption. [Means for solving the problem]

[0008] a first insulating film formed inside the trench and covering the semiconductor film; an anode electrode layer of the first conductive type in contact with the semiconductor film; a first semiconductor layer of a second conductive type provided closer to a first surface, which is a light incident surface, than the anode electrode layer; a conductor layer in contact with the first semiconductor layer and provided on a second surface, which is a surface opposite to the first surface, the sidewall of which is covered with a second insulating film; and a second semiconductor layer of the first conductive type in contact with the first semiconductor layer. [Effects of the Invention]

[0009] It is possible to prevent deterioration of noise characteristics due to leakage current and the like, reduce noise by miniaturizing the cathode electrode, and reduce power consumption by reducing the capacitance of the cathode electrode. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of an image sensor. [Figure 2] FIG. 1 is a circuit diagram showing an example of a schematic configuration of a SPAD pixel. [Figure 3] FIG. 2 is a diagram showing a stacked structure of a pixel array. [Figure 4A] FIG. 2 is a cross-sectional view showing the structure of a SPAD element. [Figure 4B] FIG. 4B is a cross-sectional view of the AA plane in FIG. 4A. [Figure 5] FIG. 2 is an explanatory diagram showing the potential of a photoelectric conversion region and the like. [Figure 6]10A to 10C are explanatory diagrams for explaining a method of manufacturing a SPAD element. [Figure 7] 7 is a flowchart showing main steps of a method for manufacturing a SPAD element corresponding to FIG. 6. [Figure 8] FIG. 2 is a cross-sectional view showing the structure of a SPAD element. [Figure 9] 10A to 10C are explanatory diagrams for explaining a method of manufacturing a SPAD element. [Figure 10] 10 is a flowchart showing the main steps of a method for manufacturing a SPAD element corresponding to FIG. 9. [Figure 11] 10A to 10C are explanatory diagrams for explaining a method of manufacturing a SPAD element. [Figure 12] 12 is a flowchart showing the main steps of a method for manufacturing a SPAD element corresponding to FIG. 11. [Figure 13] 1 is a flowchart showing the main steps of a method for manufacturing a SPAD element. [Figure 14A] FIG. 2 is a cross-sectional view showing the structure of a SPAD element. [Figure 14B] 14B is a cross-sectional view of the AA plane in FIG. 14A. [Figure 14C] FIG. 10 is a cross-sectional view showing another structure of the second insulating film. [Figure 15A] FIG. 2 is a cross-sectional view showing the structure of a SPAD element. [Figure 15B] 15B is a cross-sectional view of the AA plane in FIG. 15A. [Figure 15C] FIG. 10 is a cross-sectional view showing another structure of the second insulating film. [Figure 16] FIG. 2 is a cross-sectional view showing the structure of a SPAD element. [Figure 17] FIG. 2 is a cross-sectional view showing the structure of a SPAD element. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, a SPAD device and a method for manufacturing a SPAD device according to an embodiment will be described in detail with reference to the drawings. The described embodiments are merely exemplary, and various modifications are possible from such embodiments. Hereinafter, the same reference numerals in the drawings refer to the same components, and the size of each component in the drawings is expressed in proportions different from the actual size for the sake of clarity and convenience of explanation.

[0012] Hereinafter, the expressions "upper" or "above" include not only what is directly above / below / left / right in contact, but also what is above / below / left / right without contact.

[0013] Terms such as "first" and "second" are used to describe various components, but are used only to distinguish one component from another, and are not intended to limit the materials or structures of the components.

[0014] An element expressed in the singular includes a plurality of elements unless the context clearly dictates otherwise. Furthermore, when a part "comprises" a certain element, this does not mean that other elements are excluded, but that other elements may also be included, unless otherwise specified to the contrary.

[0015] In addition, terms such as "unit" and "module" used in the specification refer to a unit that processes one or more functions or operations, and may be realized by hardware or software, or a combination of hardware and software.

[0016] (First embodiment) <Image sensor 1> FIG. 1 is a block diagram showing a schematic configuration of an image sensor 1. The image sensor 1 is, for example, a back-illuminated image sensor 1. The image sensor 1 may also be a front-illuminated image sensor 1. In a back-illuminated image sensor 1, the surface opposite to the element-forming surface of a semiconductor substrate 510 (see FIG. 4A) is the light incident surface. In a front-illuminated image sensor 1, the element-forming surface is the light incident surface. For ease of explanation, the following description will be given taking as an example a case where the image sensor 1 is a back-illuminated image sensor 1. The semiconductor substrate 510 constitutes a substrate.

[0017] The image sensor 1 includes a pixel array 10, a control circuit 20, a drive circuit 30, and an output circuit 40.

[0018] The pixel array 10 includes a plurality of SPAD pixels 11 arranged in a matrix. Each SPAD pixel 11 is connected to a pixel drive line 50 for each column and to an output signal line 60 for each row. The pixel drive lines 50 are connected to output terminals of a drive circuit 30 corresponding to each column. The output signal lines 60 are connected to input terminals of an output circuit 40 corresponding to each row.

[0019] The drive circuit 30 includes a shift register, an address decoder, etc., and drives all of the SPAD pixels 11 in the pixel array 10 simultaneously or column by column. The drive circuit 30 also includes a circuit that applies a quench voltage VQ, which will be described later, to each SPAD pixel 11. When driving each SPAD pixel 11 column by column, the drive circuit 30 may also include a circuit that applies a selection signal voltage VSEL to each SPAD pixel 11 in a selected column. In this case, each SPAD pixel 11 is selected by the selection signal voltage VSEL, a power supply voltage is applied only to the selected SPAD pixel 11, and a detection signal VOUT is output from that SPAD pixel 11.

[0020] The detection signals VOUT output from the respective SPAD pixels 11 are input to the output circuit 40 through the respective output signal lines 60. The output circuit 40 outputs the detection signals VOUT input from the respective SPAD pixels 11 as image signals.

[0021] The control circuit 20 includes a timing generator or the like that generates various timing signals, and controls the drive circuit 30 and the output circuit 40 based on the various timing signals generated by the timing generator.

[0022] <SPAD pixel 11> FIG. 2 is a circuit diagram showing a schematic configuration example of the SPAD pixel 11.

[0023] The SPAD pixel 11 includes a SPAD element 100, a quench resistor 200, and an inverter 300. As will be described later, the SPAD element 100 may be formed on a pixel chip 500 (see FIG. 3), and the quench resistor 200 and the inverter 300 may be formed on a logic chip 600. The pixel chip 500 and the logic chip 600 are aligned and joined for each SPAD pixel 11, thereby forming each SPAD pixel 11. In FIG. 2, a connection point where the SPAD element 100 and the quench resistor 200 are connected by the joining of the pixel chip 500 and the logic chip 600 is shown as node N1. Also, the boundary between the pixel chip 500 and the logic chip 600 is shown by a dashed line.

[0024] The SPAD element 100 is a light-receiving element, and when photons are incident in a state where a reverse bias voltage equal to or higher than the breakdown voltage is applied between the anode and the cathode, an avalanche current is generated. An anode voltage VA is applied to the anode of the SPAD element 100, and a cathode voltage VC is applied to the cathode via the quench resistor 200. The anode voltage VA is set, for example, to -15V to -30V. The cathode voltage VC is set, for example, to 3V. The SPAD element 100 operates in Geiger mode when a reverse bias voltage equal to or higher than the breakdown voltage is applied, and can detect one photon.

[0025] The quench resistor 200 is configured by, for example, a PMOS (Metal Oxide Semiconductor) transistor. The quench resistor 200 operates as a quench resistor when a quench voltage VQ supplied from the drive circuit 30 is applied to the gate of the quench resistor 200. The quench resistor 200 also has a recharge function that returns the voltage supplied to the SPAD element 100 to VC by passing a current equivalent to the voltage drop caused by the quench operation.

[0026] The current flowing through the SPAD element 100 is converted into a voltage by the quench resistor 200 and output to the inverter 300 .

[0027] The inverter 300 is configured by connecting a PMOS transistor 300P and an NMOS transistor 300N in series. The source of the PMOS transistor 300P is connected to the power supply VHV for driving the digital circuit, and the drain is connected to the drain of the NMOS transistor 300N. The drain of the NMOS transistor 300N is connected to the drain of the PMOS transistor 300P, and the source of the NMOS transistor 300N is grounded. The gates of the PMOS transistor 300P and the NMOS transistor 300N are connected to each other, and their connection point serves as the input of the inverter 300. The connection point of the drain of the PMOS transistor 300P and the drain of the NMOS transistor 300N serves as the output of the inverter 300. The input of the inverter 300 is connected to a node N1, which is the connection point between the SPAD element 100 and the quench resistor 200.

[0028] The inverter 300 converts the input voltage into a digital signal and outputs it as a detection signal VOUT. Note that a buffer for impedance conversion may be provided at the output of the inverter 300, so that an impedance-converted detection signal VOUT may be output from each SPAD pixel 11.

[0029] The detection signal VOUT is input to the output circuit 40. The output circuit 40 outputs the detection signal VOUT to a processor (not shown) via, for example, a TDC (Time to Digital Converter) (not shown). The detection signal VOUT is subjected to various processes by the processor.

[0030] <Operation of SPAD pixel 11> When photons are incident on the SPAD element 100 in a state where a reverse bias voltage VSPAD greater than or equal to breakdown is applied to the SPAD element 100 via the quench resistor 200, an avalanche current is generated in the SPAD element 100. The reverse bias voltage VSPAD is the sum of the absolute value of the anode voltage VA and the absolute value of the cathode voltage VC. When the avalanche current flows through the quench resistor 200, the voltage of the node N1 drops. When the voltage of the node N1 becomes lower than the threshold voltage of the PMOS transistor 300P of the inverter 300, the PMOS transistor 300P conducts, and the power supply VHV is output from the inverter 300 as a detection signal of a high level.

[0031] After that, when the voltage of the node N1 continues to drop, the voltage applied to the SPAD element 100 becomes smaller than the breakdown voltage. As a result, the avalanche current stops flowing, and the voltage of the node N1 rises. When the voltage of the node N1 becomes higher than the threshold voltage of the NMOS transistor 300N of the inverter 300, the NMOS transistor 300N conducts, and the ground voltage is output from the inverter 300 as a detection signal of a low level.

[0032] <Stacked structure of pixel array 10> FIG. 3 is a diagram showing the stacked structure of the pixel array 10.

[0033] The SPAD pixels 11 form a pixel array 10 by being arranged in an array. The SPAD elements 100 form an element array 70 by the SPAD pixels 11 being arranged in an array. The pixel array 10 has a structure in which a pixel chip 500 and a logic chip 600 are stacked. The pixel chip 500 is a semiconductor chip on which the SPAD elements 100 are formed in an array. The logic chip 600 is a semiconductor chip on which a quench resistor 200 and an inverter 300 are formed at positions corresponding to each SPAD element 100. A control circuit 20, a drive circuit 30, and an output circuit 40 may be further formed on the logic chip 600. A buffer as described above for impedance-converting the detection signal VOUT may be formed on the logic chip 600.

[0034] The pixel chip 500 and the logic chip 600 can be joined by electronic force, for example, by flattening and contacting their respective bonding surfaces. Specifically, the pixel chip 500 and the logic chip 600 can be joined by metal bonding between metal pads formed on their respective surfaces (bonding surfaces).

[0035] <Structure of SPAD Element 100> FIG. 4A is a cross-sectional view showing the structure of the SPAD element 100. FIG. 4B is a plan view of the A-A plane in FIG. 4A. In FIG. 4A, two adjacent SPAD elements 100 are shown in order to clearly show the configuration of the trench 103 provided between adjacent SPAD elements 100.

[0036] The surface where the light indicated by the thick arrow in FIG. 4A is incident is also referred to as the light incident surface of the semiconductor substrate 510. The light incident surface constitutes the first surface. The surface of the semiconductor substrate 510 opposite to the light incident surface constitutes the second surface.

[0037] A plurality of SPAD elements 100 are formed in the semiconductor substrate 510 constituting the pixel chip 500. The semiconductor substrate 510 is, for example, a single crystal silicon substrate.

[0038] Each SPAD element 100 includes a trench 103 for isolating it from other SPAD elements 100. The trenches 103 of the multiple SPAD elements 100 formed in the semiconductor substrate 510 can be connected to each other to form a lattice shape when viewed in plan from the light incident surface.

[0039] The photoelectric conversion region 109 is a region that converts incident light into electricity to generate electron-hole pairs. As will be described later, the photoelectric conversion region 109 is designed to have a potential such that electrons generated by photoelectric conversion are gathered in the avalanche region 110.

[0040] The semiconductor film 102 has a first conductivity type. The first conductivity type may be, for example, P-type. The semiconductor film 102 is formed on the sidewall of the trench 103. The semiconductor film 102 is formed by implanting, for example, boron (B) as an impurity. The semiconductor film 102 is in contact with the anode electrode layer 105. When a reverse bias voltage VSPAD is applied between the anode electrode layer 105 and the cathode electrode layer 106, the semiconductor film 102 forms an electric field for guiding electrons generated in the photoelectric conversion region 109 to the avalanche region 110.

[0041] The anode electrode layer 105 is formed to be in contact with the semiconductor film 102. The anode electrode layer 105 has a first conductivity type, which may be, for example, a P-type.

[0042] The anode electrode layer 105 can be in contact with the surface (second surface) opposite the light incident surface.

[0043] A first insulating film 101 is formed inside the trench 103 to cover the semiconductor film 102. The first insulating film 101 can be formed, for example, by depositing silicon dioxide (SiO2) on the semiconductor film 102 by CVD (Chemical Vapor Deposition).

[0044] The cathode electrode layer 106 includes a first semiconductor layer 106a and a conductor layer 106b. The first semiconductor layer 106a is in contact with the conductor layer 106b. The sidewall of the conductor layer 106b is covered with a second insulating film 108. The first semiconductor layer 106a and the conductor layer 106b may have a second conductivity type. The second conductivity type may be, for example, N-type.

[0045] For simplicity of explanation, the following description will be given taking as an example a case where the first conductivity type is P type and the second conductivity type is N type.

[0046] In this specification, the conductor layer 106b includes at least one of single crystal silicon, polysilicon, and a metal.

[0047] The second insulating film 108 may be a silicon oxide film (a film made of silicon dioxide (SiO2)).

[0048] The width of the first semiconductor layer 106a may be equal to or greater than the width of the conductor layer 106b and equal to or less than the width of the combination of the conductor layer 106b and the second insulating film 108.

[0049] The second semiconductor layer 107 is in contact with the first semiconductor layer 106a. The second semiconductor layer 107 may be a P-type semiconductor layer. The P-type second semiconductor layer 107 and the N-type first semiconductor layer are joined together to form a PN junction of the SPAD element 100.

[0050] The anode electrode layer 105 is formed at a position in contact with the surface (second surface) opposite to the light incident surface, and the first semiconductor layer 106a of the cathode electrode layer 106 is formed via the conductor layer 106b whose sidewalls are covered with the second insulating film 108, thereby increasing the distance between the anode and the cathode in the SPAD element 100. That is, by employing a structure in which the first semiconductor layer 106a of the cathode electrode layer 106 is embedded inside the photoelectric conversion region 109, the distance between the anode electrode layer 105 and the portion of the cathode electrode layer 106 that is not covered with the second insulating film 108 (i.e., the first semiconductor layer 106a) can be increased. This reduces the magnitude of the electric field between the anode and the cathode in the SPAD element 100, making it possible to prevent deterioration of noise characteristics due to leakage current, etc.

[0051] Fig. 5 is an explanatory diagram showing the potential of the photoelectric conversion region 109, etc. Fig. 5 shows the potential along line A-A' and the potential along line B-B' in a cross-sectional view showing the structure of the SPAD element 100. In the example of Fig. 5, the cathode voltage VC applied to the cathode electrode layer 106 is 3 V, and the anode voltage VA applied to the anode electrode layer 105 is -15 V.

[0052] In the cross-sectional view of FIG. 5, a region marked with the symbol "P+" indicates a region having a higher acceptor (impurity) concentration (denoted by the symbol "P") than the acceptor (impurity) concentration of the second semiconductor layer 107. A region marked with the symbol "N+" indicates a region having a higher donor (impurity) concentration (denoted by the symbol "N") than the donor (impurity) concentration of the first semiconductor layer 106a. A region marked with the symbol "N-" indicates a region having a lower donor concentration than the donor concentration of the first semiconductor layer 106a.

[0053] The potential along line A-A' in the center of the photoelectric conversion region 109 is designed to allow electrons generated by photoelectric conversion to gather in the avalanche region 110 without any obstacles. At the potential along line B-B' at the edge of the photoelectric conversion region 109, a barrier is formed to direct the electrons generated by photoelectric conversion toward the avalanche region 110 (to prevent the electrons from escaping to the cathode electrode layer 106 without passing through the avalanche region 110). The barrier can be formed by providing a P-type third semiconductor layer 113. The P-type third semiconductor layer 113 will be described in detail in the second embodiment below. The height of the barrier can be, for example, 1 to 2 V. This allows the potential to be designed so that electrons generated by photoelectric conversion gather in the avalanche region 110.

[0054] A P-type trench electrode layer 104 may be formed inside the trench 103 in contact with the first insulating film 101. In this case, an anode voltage VA may be applied to the trench electrode layer 104 together with the anode electrode layer 105. Alternatively, a voltage lower than that of the anode electrode may be applied to the trench electrode layer 104.

[0055] An anti-reflection film 111 is formed on the light incident surface of the semiconductor substrate 510 to prevent reflection of incident light.

[0056] Color filters (not shown) and on-chip lenses (not shown) corresponding to each SPAD element 100 may be formed on the anti-reflection film 111. The color filters may be any of a color filter that selectively transmits light of a red (R) wavelength component, a color filter that selectively transmits light of a green (G) wavelength component, and a color filter that selectively transmits light of a blue (B) wavelength component, corresponding to each SPAD element 100. Each color filter may be formed to form a Bayer array.

[0057] On the surface of the semiconductor substrate 510 opposite to the light incident surface, a wiring layer (not shown) is formed. The wiring layer is composed of a stacked insulating film and wiring. Wiring of a plurality of layers can be stacked via an insulating film. In that case, wirings of the same node adjacent via the insulating film are connected to each other by vias formed in the insulating film. The wiring may include an anode wiring for supplying the anode voltage VA to the SPAD element 100 and a cathode wiring for supplying the cathode voltage VC to the SPAD element 100. The anode wiring can be connected to the anode electrode layer 105 and the in-trench electrode layer 104. The cathode wiring is connected to the cathode electrode layer 106. The wiring includes connection pads. The connection pads are exposed on the surface of the wiring layer.

[0058] The connection pads can be joined by metal bonding to the connection pads exposed on the surface of the logic chip 600. Thereby, the pixel chip 500 and the logic chip 600 can be joined.

[0059] The logic chip 600 can be composed of a substrate and a wiring layer. In this case, elements constituting a logic circuit including the quenching resistor 200 and transistors constituting the inverter 300 are formed on the substrate. Also, wirings for constituting a logic circuit including wirings connecting the quenching resistor 200 and the inverter 300 and wirings including connection pads are formed in the wiring layer.

[0060] <Method for manufacturing the SPAD element 100> A method for manufacturing the SPAD element 100 will be described.

[0061] FIG. 6 is an explanatory diagram for explaining the method for manufacturing the SPAD element 100.

[0062] (1) Trenches 103 are formed to separate and isolate a plurality of SPAD elements formed in a semiconductor substrate 510, a semiconductor film 102 is formed on the sidewall of the formed trench 103, and a first insulating film 101 is formed inside the trench 103 to cover the formed semiconductor film 102. Furthermore, an intra-trench electrode layer 104 that contacts the first insulating film 101 can be formed inside the trench 103.

[0063] The trench 103 can be formed as follows: a layer of hard mask material is formed on the semiconductor substrate 510, and the hard mask material is etched by plasma etching using a mask in which openings corresponding to the positions of the trenches 103 are formed. The trench 103 is then formed by plasma etching the semiconductor substrate 510 using the hard mask material in which openings corresponding to the positions of the trenches 103 are formed by etching as a mask.

[0064] The semiconductor film 102 can be formed as follows: An acceptor impurity is implanted by plasma doping, and the acceptor is activated by heat treatment, thereby forming a P-type semiconductor film 102 on the sidewall of the trench 103. For example, boron (B) is used as the acceptor. Alternatively, the P-type semiconductor layer 101 may be formed by depositing a material containing boron (for example, a glass material) inside the trench and diffusing the boron in the material into the semiconductor substrate 510 in a solid phase by heat treatment.

[0065] The first insulating film 101 can be formed by depositing silicon dioxide (SiO2) on the semiconductor film 102 by CVD.

[0066] The intra-trench electrode layer 104 can be formed in the trench 103 by depositing polysilicon or metal by CVD.

[0067] (2) A first internal trench 112 is formed within the region defined by the trench 103. The first internal trench 112 can be formed as follows: A layer 700 of hard mask material is formed on the semiconductor substrate 510, and the layer 700 of hard mask material is etched by plasma etching using a mask having openings formed therein corresponding to the positions of the first internal trenches 112. Then, the semiconductor substrate 510 is etched by plasma etching using the layer 700 of hard mask material having openings formed therein corresponding to the positions of the first internal trenches 112 as a mask, thereby forming the first internal trenches 112.

[0068] (3) A second insulating film 108 is formed to cover the sidewalls of the first internal trench 112. The second insulating film 108 can be formed by depositing silicon dioxide (SiO2) on the semiconductor substrate 510 by ALD (Atomic Layer Deposition). An ISSG (In-Situ Stream Generator) can be used to control the film thickness of the second insulating film 108 deposited on the sidewalls of the first internal trench 112, etc.

[0069] (4) An acceptor impurity is implanted through the second insulating film 108 formed at the bottom of the first internal trench 112, and the acceptor is activated by heat treatment to form a P-type second semiconductor layer 107. For example, boron (B) is used as the acceptor. Then, a donor impurity is implanted through the second insulating film 108 formed at the bottom of the first internal trench 112, and the donor is activated by heat treatment to form an N-type first semiconductor layer 106a in contact with the second semiconductor layer 107. For example, phosphorus (P) or arsenic (As) is used as the donor. Note that the heat treatment may be performed once after implanting the acceptor for forming the second semiconductor layer 107 and the donor for forming the first semiconductor layer 106a.

[0070] (5) The second insulating film 108 formed on the bottom of the first internal trench 112 is removed by etching. The second insulating film 108 formed on the bottom of the first internal trench 112 can be removed by dry etching.

[0071] (6) An N-type material is deposited on the semiconductor substrate 510 by CVD or the like to fill the first internal trench 112 with the N-type material, thereby forming a conductor layer 106b in contact with the first semiconductor layer 106a. For example, polysilicon doped with a donor impurity may be used as the N-type material filling the first internal trench 112. For example, phosphorus (P) or arsenic (As) may be used as the donor.

[0072] (7) The N-type material deposited on the semiconductor substrate 510 is removed, leaving behind the inside of the first internal trench 112, and the layer of hard mask material 700 is also removed. The N-type material and the layer of hard mask material 700 can be removed by dry etching.

[0073] Thereafter, acceptors, which are impurities, are implanted into the semiconductor substrate 510 to form a P-type anode electrode layer 105 in contact with the semiconductor film 102 .

[0074] FIG. 7 is a flowchart showing the main steps of a method for manufacturing the SPAD element 100 corresponding to FIG.

[0075] A lattice-shaped trench 103 is formed to separate a plurality of SPAD elements 100 formed on a semiconductor substrate 510 from one another (S101).

[0076] Next, a P-type semiconductor film 102 is formed on the sidewall of the trench 103 (S102).

[0077] Next, a first insulating film 101 that covers the semiconductor film 102 is formed inside the trench 103 (S103).

[0078] Next, a first inner trench 112 is formed in the region bounded by the trench (S104).

[0079] Next, the second insulating film 108 is formed to cover the first inner trench 112 (S105).

[0080] Next, by sequentially implanting acceptor and donor, which are impurities, through the second insulating film 108 formed at the bottom of the first internal trench 112, a P-type second semiconductor layer 107 and a first semiconductor layer 106a in contact with the second semiconductor layer 107 are formed (S106).

[0081] Next, the second insulating film 108 formed at the bottom of the first internal trench 112 is removed by etching (S107).

[0082] Next, the first internal trench 112 is filled with an N-type material to form a conductor layer 106b in contact with the first semiconductor layer 106a (S108).

[0083] Next, by implanting acceptor, which is an impurity, into the semiconductor substrate 510, a P-type anode electrode layer 105 in contact with the semiconductor film 102 is formed (S109).

[0084] (Second Embodiment) The second embodiment will be described. The difference between this embodiment and the first embodiment is as follows. In this embodiment, the SPAD element 100 further includes a P-type third semiconductor layer 113 that connects the opposing semiconductor films 102 to each other and overlaps with the second semiconductor layer 107. Since other points are the same as those of the first embodiment, redundant descriptions are omitted.

[0085] <Structure of SPAD Element 100> FIG. 8 is a cross-sectional view showing the structure of the SPAD element 100. The SPAD element 100 includes a P-type third semiconductor layer 113 that connects the opposing semiconductor films 102 to each other and overlaps with the second semiconductor layer 107.

[0086] <Manufacturing Method of SPAD Element 100> The manufacturing method of the SPAD element 100 will be described.

[0087] FIG. 9 is an explanatory diagram for explaining the manufacturing method of the SPAD element 100.

[0088] (1) Trenches 103 are formed to separate and isolate a plurality of SPAD elements formed in a semiconductor substrate 510, a semiconductor film 102 is formed on the sidewall of the formed trench 103, and a first insulating film 101 is formed inside the trench 103 to cover the formed semiconductor film 102. Furthermore, an intra-trench electrode layer 104 that contacts the first insulating film 101 can be formed inside the trench 103.

[0089] (2) An acceptor impurity is implanted into the semiconductor substrate 510 and activated by heat treatment to form a P-type third semiconductor layer 113 that connects the opposing semiconductor films 102 within the region separated by the trench 103. For example, boron (B) is used as the acceptor.

[0090] (3) A first inner trench 112 is formed within the region bounded by the trench 103.

[0091] (4) The second insulating film 108 is formed to cover the sidewall of the first inner trench 112 .

[0092] (5) A P-type second semiconductor layer 107 is formed in a portion of the third semiconductor layer 113 by injecting a donor impurity through the second insulating film 108 formed at the bottom of the first internal trench 112 and activating the donor by heat treatment. For example, phosphorus (P) or arsenic (As) is used as the donor. As shown in FIG. 9 , the amount of donor injected into a portion of the third semiconductor layer 113 is relatively small to form the second semiconductor layer 107. By relatively lowering the donor concentration in the portion of the third semiconductor layer 113, it is possible to form a second semiconductor layer 107 with a relatively low hole density while maintaining the P-type conductivity of the third semiconductor layer 113. This allows for a potential distribution in which electrons generated by photoelectric conversion are likely to gather in the second semiconductor layer 107.

[0093] Furthermore, a donor impurity is injected through the second insulating film 108 formed at the bottom of the first internal trench 112 and activated by heat treatment to form an N-type first semiconductor layer 106a in contact with the second semiconductor layer 107. For example, phosphorus (P) or arsenic (As) is used as the donor.

[0094] The heat treatment for forming the second semiconductor layer 107 and the first semiconductor layer 106a may be performed in one step after implanting the donors for forming the second semiconductor layer 107 and the donors for forming the first semiconductor layer 106a.

[0095] (6) The second insulating film formed on the bottom of the first internal trench 112 is removed by etching.

[0096] (7) An N-type material is deposited on the semiconductor substrate 510 by CVD or the like to fill the first inner trench 112 with the N-type material, forming a conductor layer 106b in contact with the first semiconductor layer 106a.

[0097] (8) The N-type material deposited on the semiconductor substrate 510 is removed, leaving behind the first internal trenches 112, and the layer of hard mask material 700 is removed.

[0098] Thereafter, acceptors, which are impurities, are implanted into the semiconductor substrate 510 to form a P-type anode electrode layer 105 in contact with the semiconductor film 102 .

[0099] FIG. 10 is a flowchart showing the main steps of a method for manufacturing the SPAD element 100 corresponding to FIG.

[0100] A lattice-shaped trench 103 is formed to separate the plurality of SPAD elements 100 formed on the semiconductor substrate 510 from one another (S201).

[0101] Next, a P-type semiconductor film 102 is formed on the sidewall of the trench 103 (S202).

[0102] Next, the first insulating film 101 that covers the semiconductor film 102 is formed inside the trench 103 (S203).

[0103] Next, by implanting an acceptor impurity, a P-type third semiconductor layer 113 that connects the opposing semiconductor films 102 together is formed in the region separated by the trenches 103 (S204).

[0104] Next, a first inner trench 112 is formed in the region defined by the trench 103 (S205).

[0105] Next, the second insulating film 108 is formed to cover the sidewalls of the first inner trench 112 (S206).

[0106] Next, a donor impurity is injected through the second insulating film 108 formed at the bottom of the first internal trench 112, thereby forming a P-type second semiconductor layer 107 in a part of the third semiconductor layer 113 (S207).

[0107] Next, donors, which are impurities, are injected through the second insulating film 108 formed at the bottom of the first internal trench 112, thereby forming an N-type first semiconductor layer 106a in contact with the second semiconductor layer 107 (S208).

[0108] Next, the second insulating film 108 formed on the bottom of the first internal trench 112 is removed by etching (S209).

[0109] Next, the first inner trench 112 is filled with an N-type material to form a conductor layer 106b in contact with the first semiconductor layer 106a (S210).

[0110] Next, acceptors, which are impurities, are implanted into the semiconductor substrate 510 to form the P-type anode electrode layer 105 in contact with the semiconductor film 102 (S211).

[0111] (Third embodiment) A description will be given of the third embodiment. The differences between this embodiment and the second embodiment are as follows. In the second embodiment, the second insulating film 108 is formed by depositing silicon dioxide (SiO2) on the sidewalls of the first internal trench 112. The second semiconductor layer 107 and the first semiconductor layer 106a are formed by implanting donors through the second insulating film 108 formed at the bottom of the second insulating film 108. Further, the conductor layer 106b is formed by filling the trench with an N-type material. On the other hand, in this embodiment, two trenches are formed, and the second insulating film 108 is formed by filling the two trenches with silicon dioxide (SiO2). Further, the second semiconductor layer 107, the first semiconductor layer 106a, and the conductor layer 106b are formed by implanting donors between the two trenches. Since other points of this embodiment are the same as those of the second embodiment, duplicate explanations are omitted or simplified.

[0112] <Method for manufacturing SPAD element 100> A description will be given of the method for manufacturing the SPAD element 100.

[0113] FIG. 11 is an explanatory diagram for explaining the method for manufacturing the SPAD element 100.

[0114] (1) Trenches 103 for separating a plurality of SPAD elements formed on a semiconductor substrate 510 from each other are formed by partitioning each of them, a semiconductor film 102 is formed on the sidewalls of the formed trenches 103, and a first insulating film 101 covering the formed semiconductor film 102 is formed inside the trenches 103. Further, a trench internal electrode layer 104 contacting the first insulating film 101 can be formed inside the trenches 103.

[0115] (2) An acceptor, which is an impurity, is implanted into the semiconductor substrate 510 and activated by heat treatment to form a P-type third semiconductor layer 113 that connects the opposing semiconductor films 102 to each other within the region partitioned by the trenches 103. As the acceptor, for example, boron (B) is used.

[0116] (3) Silicon dioxide (SiO2) is deposited on the semiconductor substrate 510 as a fourth insulating film 702, and silicon nitride (SiN) 701 is deposited on the fourth insulating film 702. The silicon dioxide (SiO2) of the fourth insulating film 702 and the silicon nitride (SiN) 701 are deposited by, for example, CVD. A resist 703 is formed on the silicon nitride (SiN), and the resist 703 is patterned by etching. Specifically, the resist 703 is patterned to form openings corresponding to the positions of the two second internal trenches 114.

[0117] (4) Using the patterned resist 703 as a mask, the fourth insulating film 702 and the silicon nitride (SiN) 701 are patterned by etching. Specifically, portions of the fourth insulating film 702 and the silicon nitride (SiN) 701 corresponding to the openings in the resist 703 are removed by plasma etching, thereby patterning the silicon dioxide (SiO2) and silicon nitride (SiN) 701 that constitute the fourth insulating film 702. As a result, openings corresponding to the positions of the two second internal trenches 114 are formed in the fourth insulating film 702 and the silicon nitride (SiN) 701.

[0118] (5) Using the patterned fourth insulating film 702 and silicon nitride (SiN) 701 as a mask, the semiconductor substrate 510 is etched by plasma etching to form two second inner trenches 114. The two second inner trenches 114 are formed to a depth such that the bottoms of the second inner trenches 114 do not contact the third semiconductor layer 113.

[0119] (6) An insulating material is deposited on the semiconductor substrate 510 to fill the two second internal trenches 114 with the insulating material to form the second insulating film 108. For example, silicon dioxide (SiO2) is used as the insulating material. The insulating material is deposited on the semiconductor substrate 510 by, for example, CVD.

[0120] (7) The silicon nitride (SiN) 701 layer on the semiconductor substrate 510 is removed, and the deposited insulating material is thinned. Specifically, for example, the silicon nitride (SiN) 701 layer is removed using hot phosphoric acid, and the insulating material is thinned by CMP (Chemical Mechanical Polishing).

[0121] (8) A P-type second semiconductor layer 107 is formed in a portion of the third semiconductor layer 113 by injecting a donor impurity through the fourth insulating film 702 between the two second internal trenches 114 and activating the donor by heat treatment. For example, phosphorus (P) or arsenic (As) is used as the donor. The amount of donor injected into a portion of the third semiconductor layer 113 is relatively small to form the second semiconductor layer 107. By relatively lowering the donor concentration in the portion of the third semiconductor layer 113, it is possible to form a second semiconductor layer 107 with a relatively low hole density while maintaining the P-type conductivity of the third semiconductor layer 113. This allows for a potential distribution in which electrons generated by photoelectric conversion are likely to gather in the second semiconductor layer 107.

[0122] Furthermore, a donor impurity is implanted through the fourth insulating film 702 between the two second internal trenches 114 and activated by heat treatment to form an N-type first semiconductor layer 106a in contact with the second semiconductor layer 107. As the donor, for example, phosphorus (P) or arsenic (As) is used. Because the bottoms of the two second internal trenches 114 are not in contact with the third semiconductor layer 113, the first semiconductor layer 106a is formed such that at least a portion thereof is not covered with the second insulating film 108.

[0123] Furthermore, a donor impurity is implanted through the fourth insulating film 702 between the two second internal trenches 114 and activated by heat treatment to form an N-type semiconductor layer as the conductor layer 106b in contact with the first semiconductor layer 106a. For example, phosphorus (P) or arsenic (As) is used as the donor.

[0124] FIG. 12 is a flowchart showing the main steps of a method for manufacturing the SPAD element 100 corresponding to FIG.

[0125] A lattice-shaped trench 103 is formed to separate the plurality of SPAD elements 100 formed on the semiconductor substrate 510 from one another (S301).

[0126] Next, a P-type semiconductor film 102 is formed on the sidewall of the trench 103 (S302).

[0127] Next, the first insulating film 101 that covers the semiconductor film 102 is formed inside the trench 103 (S303).

[0128] Next, by implanting donors as impurities, a P-type third semiconductor layer 113 that connects the opposing semiconductor films 102 together is formed in the region separated by the trenches 103 (S304).

[0129] Next, a fourth insulating film 702 is formed on the semiconductor substrate 510 (S305).

[0130] Next, two second inner trenches 114 are formed in the region separated by the trenches 103, penetrating the fourth insulating film 702 (S306).

[0131] Next, donors, which are impurities, are implanted through the fourth insulating film 702 between the two second internal trenches 114, thereby forming the second semiconductor layer 107 in a part of the third semiconductor layer 113 (S307).

[0132] Next, donors, which are impurities, are implanted through the fourth insulating film 702 between the two second internal trenches 114 to form the first semiconductor layer 106a in contact with the second semiconductor layer 107 (S308).

[0133] Next, donors, which are impurities, are implanted through the fourth insulating film 702 between the two second internal trenches 114 to form a conductor layer 106b in contact with the first semiconductor layer 106a (S309).

[0134] Next, a P-type anode electrode layer 105 in contact with the semiconductor film 102 is formed by implanting an acceptor, which is an impurity, into the semiconductor substrate 510 (S310).

[0135] Next, the fourth insulating film 702 is removed (S311).

[0136] (Fourth Embodiment) The fourth embodiment will be described. The differences between this embodiment and the third embodiment are as follows. In the third embodiment, a second semiconductor layer 107 is formed in a part of the third semiconductor layer 113 by implanting a donor, which is an impurity, through the fourth insulating film 702 between the two second internal trenches 114. On the other hand, in this embodiment, the third semiconductor layer 113 is not formed, and the second semiconductor layer 107 is formed by implanting an acceptor, which is an impurity, through the fourth insulating film 702 between the two second internal trenches 114. Other points are the same as those in the third embodiment, and thus the overlapping description will be omitted.

[0137] <Manufacturing Method of SPAD Element 100> FIG. 13 is a flowchart showing the main steps of the manufacturing method of the SPAD element 100.

[0138] Steps S401 to S405, S407 to S410 are the same as steps S301 to S303, S305, S306, S308 to S311 in FIG. 12, and thus the description thereof will be omitted. In this embodiment, the step corresponding to step S304 in FIG. 12 is not executed.

[0139] In step S406, the second semiconductor layer 107 is formed by implanting an acceptor, which is an impurity, through the fourth insulating film 702 between the two second internal trenches 114.

[0140] (Fifth Embodiment) The fifth embodiment will be described. The difference between this embodiment and the first embodiment is as follows. In the first embodiment, the second insulating film 108 and the anode electrode layer 105 are separated. On the other hand, in this embodiment, the second insulating film 108 is formed to a range where it is close to or in contact with the anode electrode layer 105. In other respects, since this embodiment is the same as the first embodiment, duplicate explanations will be omitted.

[0141] <Structure of SPAD element 100> FIG. 14A is a cross-sectional view showing the structure of the SPAD element 100. FIG. 14B is a plan view of the A-A plane in FIG. 14A.

[0142] As shown in FIGS. 14A and 14B, the second insulating film 108 is formed to a range where it is close to the anode electrode layer 105. As an example, the second insulating film 108 is formed in a circular shape as viewed in the A-A plane. Thereby, the effect of reducing the capacitance of the cathode electrode by the second insulating film 108 can be increased, further reducing power consumption can be realized, and the potential of the anode electrode can be stably supplied to the semiconductor film 102.

[0143] FIG. 14C is a plan view of the A-A plane in FIG. 14A with another structure of the second insulating film 108.

[0144] As shown in FIG. 14C, the second insulating film 108 is formed in a structure that matches the shape of the trench 103. With this structure, the distance between the anode electrode and the cathode electrode can be maximized, and a fine pixel can be realized.

[0145] (Sixth embodiment) The sixth embodiment will be described. The difference between this embodiment and the first embodiment is as follows. In this embodiment, it further includes a third insulating film 115 that contacts the anode electrode layer 105 and is separated from the second insulating film 108. In other respects, since this embodiment is the same as the first embodiment, duplicate explanations will be omitted.

[0146] <Structure of SPAD element 100> Fig. 15A is a cross-sectional view showing the structure of the SPAD element 100. Fig. 15B is a plan view of the AA plane in Fig. 15A.

[0147] 15A and 15B, the SPAD element 100 includes, in addition to the second insulating film 108, a third insulating film 115 that is in contact with the anode electrode layer 105 and spaced apart from the second insulating film 108. The presence of the third insulating film 115 increases the distance between the anode and cathode in the SPAD element 100. That is, the distance that contributes to the electric field (electric field intensity) between the anode electrode layer 105 and the portion of the cathode electrode layer 106 that is not covered with the second insulating film 108 (i.e., the first semiconductor layer 106a) can be increased. This reduces the magnitude of the electric field between the anode and cathode in the SPAD element 100, thereby preventing deterioration of noise characteristics due to leakage current, etc.

[0148] The third insulating film 115 can be formed simultaneously with the second insulating film 108 by the same method as the method for forming the second insulating film 108 shown in FIG.

[0149] FIG. 15C shows another structure of the second insulating film 108, and is a plan view of the AA plane in FIG. 15A.

[0150] As shown in FIG. 15C, by making the cross section of the second insulating film 108 circular, the formation of corners that may cause electric field concentration is suppressed, thereby preventing the occurrence of new sources of leakage current, etc.

[0151] (Variation) The third insulating film 115 may be provided anywhere between the anode electrode layer 105 and the second insulating film .

[0152] (Seventh embodiment) The seventh embodiment will be described. The difference between this embodiment and the second embodiment is as follows. In this embodiment, a fourth N-type semiconductor layer 116 having an impurity concentration lower than that of the first semiconductor layer 106a is further included in a region on the opposite side of the light incident surface from the first semiconductor layer 106a. Since other aspects of this embodiment are the same as those of the second embodiment, duplicate explanations will be omitted.

[0153] <Structure of SPAD element 100> FIG. 16 is a cross-sectional view showing the structure of the SPAD element 100.

[0154] As shown in FIG. 16, the SPAD element 100 includes a fourth N-type semiconductor layer 116 having a donor concentration lower than that of the first N-type semiconductor layer 106a in a region on the opposite side of the light incident surface from the first semiconductor layer 106a. Thereby, a potential distribution in which avalanche does not occur in a region other than the avalanche region 110 can be achieved within the SPAD element 100.

[0155] (Eighth embodiment) The eighth embodiment will be described. The difference between this embodiment and the second embodiment is as follows. In this embodiment, a fifth P-type semiconductor layer 117 having an impurity concentration lower than that of the second semiconductor layer 107 is further included in a region on the opposite side of the light incident surface from the first semiconductor layer 106a. Since other aspects of this embodiment are the same as those of the second embodiment, duplicate explanations will be omitted.

[0156] <Structure of SPAD element 100> FIG. XVII is a cross-sectional view showing the structure of the SPAD element 100.

[0157] As shown in FIG. 17, the SPAD element 100 includes a fifth P-type semiconductor layer 117 having an acceptor concentration lower than that of the second P-type semiconductor layer 107 in a region on the opposite side of the light incident surface from the second semiconductor layer 107. Thereby, a potential distribution in which avalanche does not occur in a region other than the avalanche region 110 can be achieved within the SPAD element 100.

[0158] The embodiment has the following advantages.

[0159] The SPAD element is configured to include a semiconductor film of a first conductivity type formed on the sidewall of a trench for separating the SPAD element from other SPAD elements formed on the substrate, a first insulating film formed inside the trench and covering the semiconductor layer, an anode electrode layer of the first conductivity type in contact with the semiconductor film, a first semiconductor layer provided on the first surface side of the substrate, a conductor layer in contact with the first semiconductor layer and provided on the second surface side, the sidewall of the conductor layer being covered with a second insulating film, a cathode electrode layer of a second conductivity type in contact with the first semiconductor layer, and a second semiconductor layer of the first conductivity type in contact with the first semiconductor layer. This prevents deterioration of noise characteristics due to leakage current, etc., reduces noise due to parasitic resistance, etc. by miniaturizing the cathode electrode, and reduces power consumption by reducing the capacitance of the cathode electrode.

[0160] In addition, the anode electrode layer is formed so as to contact the second surface, which makes it easy to increase the distance between the anode and cathode in the SPAD element and effectively reduces the magnitude of the electric field, thereby effectively preventing deterioration of noise characteristics due to leakage current, etc.

[0161] The conductor layer contains at least one of single crystal silicon, polysilicon, and metal, which allows the structure of the conductor layer covered with the second insulating film to be easily formed while ensuring reliability.

[0162] The width of the first semiconductor layer is set to be equal to or greater than the width of the conductor layer and equal to or less than the width of the composite of the conductor layer and the second insulating film. This facilitates miniaturization of the cathode electrode while ensuring reliability. Furthermore, by reducing defects that may occur in the cathode electrode, deterioration of noise characteristics due to leakage current and the like can be further suppressed.

[0163] The SPAD element also includes a third semiconductor layer of the first conductivity type that connects the opposing semiconductor films and overlaps the second semiconductor layer, thereby improving the sensitivity of the SPAD element.

[0164] In addition, the region closer to the second surface than the first semiconductor layer includes a fourth semiconductor layer of the second conductivity type having a lower impurity concentration than the first semiconductor layer, or a fifth semiconductor layer of the first conductivity type having a lower impurity concentration than the second semiconductor layer, thereby making it easier to achieve a potential distribution within the SPAD element that does not cause unnecessary avalanches.

[0165] Furthermore, the second insulating film is formed of a silicon oxide film, which makes it possible to easily form a structure of a conductor layer covered with the second insulating film while ensuring reliability.

[0166] Furthermore, the second insulating film is made thicker up to the area where it contacts the anode electrode layer, which allows the capacitance of the cathode electrode to be further reduced.

[0167] The SPAD element further includes a third insulating film that is in contact with the anode electrode layer or is provided between the anode electrode layer and the second insulating film and is spaced apart from the second insulating film. This reduces the magnitude of the electric field between the anode and cathode in the SPAD element, thereby preventing deterioration of noise characteristics due to leakage current, etc.

[0168] The above-described embodiments are merely examples, and those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the disclosed embodiments should be considered from an illustrative perspective, not a restrictive one. The scope of the invention is defined in the claims, and all structures within the scope of the claims should be construed as being within the scope of the invention. [Explanation of symbols]

[0169] 1 image sensor, 10 pixel array, 11 SPAD pixels, 20 control circuit, 30 drive circuit, 40 output circuit, 50 pixel drive lines, 60 output signal line, 70 element array, 100 SPAD elements, 101 first insulating film, 102 semiconductor film, 103 trench, 104 trench electrode layer, 105 anode electrode layer, 106 cathode electrode layer, 106a first semiconductor layer, 106b conductor layer, 107 second semiconductor layer, 108 second insulating film, 109 Photoelectric conversion region, 110 avalanche region, 111 Anti-reflective coating, 112 First Internal Trench, 113 third semiconductor layer, 114 Second internal trench, 115 third insulating film, 116 fourth semiconductor layer, 117 fifth semiconductor layer, 200 quench resistance, 300 inverter, 500 pixel chip, 510 semiconductor substrate, 600 logic chips, 621 wiring, 621a connection pad, 700 hard mask material, 701 nitride film, 702 fourth insulating film, 703 Resist.

Claims

1. a trench for isolating a SPAD element formed on the substrate from other SPAD elements; a semiconductor film of a first conductivity type formed on a sidewall of the trench; a first insulating film formed inside the trench and covering the semiconductor film; an anode electrode layer of the first conductivity type in contact with the semiconductor film; a cathode electrode layer including a first semiconductor layer of a second conductivity type provided closer to a first surface, which is a light incident surface, than the anode electrode layer, and a conductor layer in contact with the first semiconductor layer and provided on a second surface, which is a surface opposite to the first surface, the sidewall of the conductor layer being covered with a second insulating film; a second semiconductor layer of the first conductivity type in contact with the first semiconductor layer; A SPAD element having:

2. The SPAD device according to claim 1 , wherein the anode electrode layer is in contact with the second surface.

3. The SPAD device according to claim 1 , wherein the conductor layer includes at least one of single crystal silicon, polysilicon, and metal.

4. The SPAD element according to claim 1 , wherein the width of the first semiconductor layer is equal to or greater than the width of the conductor layer and is equal to or less than the width of a combination of the conductor layer and the second insulating film.

5. The SPAD element according to claim 1 , further comprising a third semiconductor layer of the first conductivity type that connects the opposing semiconductor films together and overlaps the second semiconductor layer.

6. 2. The SPAD element according to claim 1, further comprising: a fourth semiconductor layer of the second conductivity type having a lower impurity concentration than the first semiconductor layer in a region closer to the second surface than the first semiconductor layer; or a fifth semiconductor layer of the first conductivity type having a lower impurity concentration than the second semiconductor layer in a region closer to the second surface than the first semiconductor layer.

7. The SPAD element according to claim 1 , wherein the second insulating film is a silicon oxide film.

8. The SPAD device according to claim 1 , wherein the second insulating film is formed up to a range in contact with the anode electrode layer.

9. The SPAD element according to claim 1 , further comprising a third insulating film spaced apart from the second insulating film, the third insulating film being in contact with the anode electrode layer or being provided between the anode electrode layer and the second insulating film.

10. forming trenches for separating and isolating a plurality of SPAD elements formed on a substrate, forming a semiconductor film of a first conductivity type on a sidewall of the formed trenches, and forming a first insulating film inside the trenches to cover the formed semiconductor film; (b) forming a first interior trench within the area bounded by the trench; forming a second insulating film covering a sidewall of the first inner trench; (d) forming a second semiconductor layer of the first conductivity type and a first semiconductor layer of the second conductivity type in contact with the second semiconductor layer by injecting impurities through the second insulating film formed at the bottom of the first inner trench; (e) removing the second insulating film formed on the bottom of the first inner trench by etching; (f) filling the first interior trench with a material of the second conductivity type to form a conductor layer in contact with the first semiconductor layer; (g) forming an anode electrode layer of the first conductivity type in contact with the semiconductor film by implanting impurities into the substrate; A method for manufacturing a SPAD element having the above structure.

11. forming trenches for separating and isolating a plurality of SPAD elements formed on a substrate, forming a semiconductor film of a first conductivity type on a sidewall of the formed trenches, and forming a first insulating film inside the trenches to cover the formed semiconductor film; (h) forming a third semiconductor layer of the first conductivity type in the region partitioned by the trench by injecting impurities into the substrate, the third semiconductor layer connecting the opposing semiconductor films; (b) forming a first interior trench within the area bounded by the trench; forming a second insulating film covering a sidewall of the first inner trench; (d1) forming a second semiconductor layer of the first conductivity type in a portion of the third semiconductor layer by injecting impurities through the second insulating film formed at the bottom of the first inner trench; (d2) forming a first semiconductor layer of a second conductivity type in contact with the second semiconductor layer by injecting impurities through the second insulating film formed at the bottom of the first inner trench; (e) removing the second insulating film formed on the bottom of the first inner trench by etching; (f) filling the first interior trench with a material of the second conductivity type to form a conductor layer in contact with the first semiconductor layer; (g) forming an anode electrode layer of the first conductivity type in contact with the semiconductor film by implanting impurities into the substrate; A method for manufacturing a SPAD element having the above structure.

12. A step (A) of forming trenches for separating a plurality of SPAD elements formed on a substrate from one another, forming a semiconductor film of a first conductivity type on a sidewall of the formed trenches, and forming a first insulating film inside the trenches to cover the formed semiconductor film; (B) forming a fourth insulating film on the substrate by depositing an insulating material on the substrate; (B) forming two second inner trenches penetrating the fourth insulating film within the region separated by the trenches; (C) depositing an insulating material on the substrate to fill the two second interior trenches with the insulating material to form a second insulating film; Step (D) of injecting impurities through the fourth insulating film between the two second inner trenches to form a second semiconductor layer of the first conductivity type, a first semiconductor layer of the second conductivity type in contact with the second semiconductor layer, and a conductor layer of the second conductivity type in contact with the first semiconductor layer, the sidewall of which is covered with the second insulating film; (E) forming an anode electrode layer of the first conductivity type in contact with the semiconductor film by injecting impurities into the substrate through the fourth insulating film; A method for manufacturing a SPAD element having the above structure.

13. A step (A) of forming trenches for separating a plurality of SPAD elements formed on a substrate from one another, forming a semiconductor film of a first conductivity type on a sidewall of the formed trenches, and forming a first insulating film inside the trenches to cover the formed semiconductor film; (F) forming a third semiconductor layer of the first conductivity type in the region separated by the trench by injecting impurities into the substrate, the third semiconductor layer connecting the opposing semiconductor films; (B) forming a fourth insulating film on the substrate by depositing an insulating material on the substrate; (B) forming two second inner trenches penetrating the fourth insulating film within the region separated by the trenches; (C) depositing an insulating material on the substrate to fill the two second interior trenches with the insulating material to form a second insulating film; (D1) forming a second semiconductor layer of the first conductivity type in a portion of the third semiconductor layer by injecting impurities through the fourth insulating film between the two second inner trenches; A step (D2) of forming a first semiconductor layer of a second conductivity type in contact with the second semiconductor layer by injecting impurities through the fourth insulating film between the two second inner trenches, and a conductor layer of the second conductivity type in contact with the first semiconductor layer, the conductor layer having a sidewall covered with the second insulating film; (E) forming an anode electrode layer of the first conductivity type in contact with the semiconductor film by injecting impurities into the substrate through the fourth insulating film; A method for manufacturing a SPAD element having the above structure.

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