SOI wafer and method for manufacturing SOI wafer

Abstract

To provide an SOI wafer that has a highly slip-resistant region on the support substrate side and has the same quality as low-oxygen concentration wafers used in IGBTs on the surface side, which is to become the functional layer.SOLUTION: An SOI wafer includes a support substrate made of silicon single crystal, a silicon oxide film provided on the support substrate, and a functional layer made of silicon single crystal and located on the silicon oxide film, and the support substrate is heavily doped with phosphorus or boron, the oxygen concentration of the functional layer is 4.0×1017 atoms / cm3 or less, the thickness of the support substrate is more than 10 μm, and the thickness of the functional layer is more than 325 μm.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an SOI wafer and a method for manufacturing an SOI wafer. [Background technology]

[0002] In recent years, thyristors, bipolar transistors, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), insulated gate bipolar transistors (IGBTs), and other switching devices for power applications have been actively developed. Among these, IGBTs combine the high speed of MOSFETs with the low saturation voltage characteristics of bipolar transistors, and are attracting attention for applications requiring large capacity, high voltage resistance, and high-speed switching, such as power supplies for the drive motors of hybrid and electric vehicles.

[0003] Silicon wafers with low oxygen concentration are used as substrates for manufacturing IGBTs. The reason for using low oxygen concentration wafers is that high oxygen concentration can cause oxygen precipitates, which can reduce yields, and oxygen donors can easily affect substrate resistance. For wafers with a diameter of 200 mm or less, FZ (Floating Zone) wafers with a low oxygen concentration are used, and even for wafers with a diameter of 300 mm, the oxygen concentration is 4 x 10 17 atoms / cm 3 The following low oxygen concentration wafers are used:

[0004] The wafers used for these IGBTs are prone to slip due to their low oxygen content. While there are various causes of slip in low-oxygen silicon wafers, the most common cause is scratches introduced by the pins or heat treatment boat that support the wafer coming into contact with the wafer during heat treatment in the device process. Slip can cause current leakage and misalignment problems in the photolithography process, significantly impacting device yield. However, as mentioned above, the oxygen concentration cannot be increased in silicon wafers for IGBTs because oxygen precipitates reduce yield.

[0005] To reduce scratches introduced during heat treatment, it is necessary to improve the pins and heat treatment boat that come into contact with the wafer, as well as the heat treatment conditions, but this is not easy.In order to reduce the occurrence of slip during the heat treatment process, research is being conducted to improve the slip resistance (the difficulty of scratches turning into slip) of the wafers used.

[0006] Patent Document 1 discloses a silicon wafer suitable for IGBT applications that can suppress the occurrence of slip. Patent Document 1 describes a silicon wafer in which the oxygen concentration profile in the thickness direction of the silicon wafer is 1.5×10 lower than the oxygen concentration of the silicon wafer (ASTM F121, 1979). 17 atoms / cm 3 or more exists only in the surface layer of the back surface, and the average oxygen concentration in the region from the outermost surface of the back surface of the silicon wafer to 10 μm in the thickness direction is 4.0 × 10 17 atoms / cm 3 Over 15.0 x 10 17 atoms / cm 3 The following silicon wafer is disclosed: [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2023-90559 Summary of the Invention [Problem to be solved by the invention]

[0008] To date, silicon wafers suitable for IGBT applications have been developed using various techniques, as described in Patent Document 1. However, in recent IGBT manufacturing processes, most of the backside of the wafer is ground away, leaving a final device fabrication area of ​​approximately 100 μm on the frontside. The present inventors focused on this fact and came up with the idea of ​​using an SOI wafer structure for IGBT applications to enhance the slip resistance of the support substrate, and attempted to realize this idea. Therefore, the present invention aims to provide an SOI wafer and a method for manufacturing the same, which has a highly slip-resistant region on the support substrate side and a front side, which serves as a functional layer, with quality equivalent to that of low-oxygen-concentration wafers used in IGBTs. [Means for solving the problem]

[0009] The present inventors conducted extensive research to solve the above-mentioned problems. Through experiments, the inventors discovered that in an SOI wafer having a support substrate, a silicon oxide film, and a functional layer made of single-crystal silicon, slip resistance can be improved by controlling the dopant concentration of the support substrate. The inventors discovered that if the functional layer is sufficiently thick, the functional layer can satisfy the characteristics required of an IGBT and solve the above-mentioned problems, leading to the completion of the present invention. Specifically, the gist of the present invention is as follows:

[0010] (1) a support substrate made of single crystal silicon; a silicon oxide film provided on the support substrate; a functional layer located on the silicon oxide film and made of single crystal silicon, the support substrate is heavily doped with phosphorus or boron; The oxygen concentration of the functional layer is 4.0×10 17 atoms / cm3 is as follows: The thickness of the support substrate is greater than 10 μm, An SOI wafer, wherein the functional layer has a thickness of more than 325 μm.

[0011] (2) The support substrate is doped with phosphorus, and the phosphorus concentration is 1.2×10 19 atoms / cm 3 Over 7.4 x 10 19 atoms / cm 3 The SOI wafer according to (1) above, which is:

[0012] (3) The support substrate is doped with boron and has a boron concentration of 1.8×10 18 atoms / cm 3 Over 2.0 x 10 19 atoms / cm 3 The SOI wafer according to (1) above, which is:

[0013] (4) The SOI wafer according to any one of (1) to (3) above, wherein the thickness of the functional layer is greater than the thickness of the support substrate.

[0014] (5) The SOI wafer according to any one of (1) to (4) above, wherein the thickness of the functional layer is at least twice as thick as the thickness of the support substrate.

[0015] (6) The SOI wafer according to any one of (1) to (5) above, wherein the thickness of the support substrate is less than 400 μm.

[0016] (7) The SOI wafer according to any one of (1) to (6) above, wherein the thickness of the support substrate is 20 μm or more.

[0017] (8) The SOI wafer according to any one of (1) to (6) above, wherein the functional layer has a thickness of 500 μm or more.

[0018] (9) The SOI wafer according to any one of (1) to (8) above, wherein the support substrate further has an oxide film on the surface opposite to the functional layer side.

[0019] (10) an oxide film forming step of forming a silicon oxide film on the surface of the support substrate silicon wafer; a bonding step of bonding the support substrate silicon wafer and the functional layer silicon wafer together via the silicon oxide film; a grinding step after the bonding step, The grinding step includes: a first grinding step of grinding the silicon wafer for support substrate to form a support substrate having a thickness of more than 10 μm; a second grinding step of grinding the functional layer silicon wafer to form a functional layer with a thickness of more than 325 μm; the silicon wafer for the support substrate is doped with phosphorus or boron at a high concentration; The oxygen concentration of the silicon wafer for the functional layer is 4.0 × 10 17 atoms / cm 3 The following is a method for manufacturing an SOI wafer.

[0020] (11) The method for producing an SOI wafer according to (10) above, further comprising, after the grinding step, an oxide film forming step of forming an oxide film on the surface of the support substrate opposite to the functional layer side. [Effects of the Invention]

[0021] According to the present invention, it is possible to provide an SOI wafer having a highly slip-resistant region on the support substrate side and having a surface side that becomes a functional layer and has quality equivalent to that of low-oxygen concentration wafers used in IGBTs, and a method for manufacturing the same. Furthermore, by providing an SOI wafer with a highly slip-resistant region on the support substrate side and with a surface layer that is equivalent in quality to low-oxygen-concentration wafers used in IGBTs, the yield of IGBT manufacturing can be improved. Improving yields increases the efficiency of semiconductor manufacturing, enabling the production of higher-quality products, promoting technological innovation and contributing to the sustainable development of the industry. Improving yields also contributes to the efficient use of resources by reducing material waste in the semiconductor manufacturing process. Furthermore, improving yields reduces energy waste in the semiconductor manufacturing process, thereby contributing to the reduction of greenhouse gas emissions. In other words, the present invention can contribute to, for example, the Sustainable Development Goals (SDGs) "Goal 9: Industry, Innovation, and Infrastructure," "Goal 12: Ensure Sustainable Consumption and Production," and "Goal 13: Climate Action." [Brief explanation of the drawings]

[0022] [Figure 1] This is an XRT image of a low-oxygen-concentration silicon wafer obtained in a preliminary experiment. [Figure 2] 1 shows XRT images of each silicon wafer in a preliminary experiment. [Figure 3] 1 is a schematic cross-sectional view of an SOI wafer according to one embodiment of the present invention. [Figure 4] 1 is a diagram of a method for manufacturing an SOI wafer according to one embodiment of the present invention. [Figure 5] FIG. 10 is a schematic cross-sectional view of an SOI wafer according to a modified example of the present invention. [Figure 6] 1 is an XRT image showing the evaluation criteria for slip resistance in an example. DETAILED DESCRIPTION OF THE INVENTION

[0023] Prior to describing the embodiments, a preliminary experiment that led to the conception of the present invention will be described.

[0024] (Preliminary experiment) A commercially available low-oxygen-concentration silicon wafer (oxygen concentration: 4.0 × 10) with a diameter of 300 mm is used for IGBTs. 17 atoms / cm 3 (See below) was prepared. To simulate the IGBT manufacturing process, this silicon wafer was placed in a vertical furnace and subjected to heat treatment at 1100°C. To investigate the slip length caused by contact scratches with the boat supporting this silicon wafer, the slip length on the backside of the silicon wafer after heat treatment was measured using XRT images (X-ray topography). The results are shown in Figure 1.

[0025] Next, (A) the boron concentration is 1.3 × 10 15 atoms / cm 3 , p-wafer with a substrate resistivity of 10 Ω·cm and (B) boron concentration of 1.1×10 19 atoms / cm 3 , p++ wafer with substrate resistivity of 0.008 Ω·cm and (C) phosphorus concentration of 2.7 × 10 19 atoms / cm 3 We prepared n+++ wafers with a substrate resistance of 0.0025 Ω·cm. Each of these wafers (A), (B), and (C) was subjected to heat treatment using an RTA furnace (Rapid Thermal Anneal). The heat treatment conditions were 1250°C, 30 seconds, and a nitrogen atmosphere. Figure 2 shows the XRT images of each wafer after heat treatment.

[0026] As shown in Figure 2, in the (A) p- wafer, slip occurred at the contact point with the quartz pins supporting the wafer, whereas in the (B) p++ wafer and (C) n+++ wafer, no slip occurred. Therefore, it was confirmed that the (B) p++ wafer and (C) n+++ wafer have extremely high resistance to slip caused by scratches. Through the above experiments, the inventors have clarified that the slip resistance of wafers in the IGBT manufacturing process varies depending on the type and concentration of impurities doped into the wafer.

[0027] Here, scratches that serve as slip initiation sites are primarily introduced during heat treatment. This is because materials harder than silicon wafers, such as quartz and SiC, are used as support members. The depth of scratches introduced during heat treatment varies depending on the heat treatment conditions and transport method. However, according to a known paper (ECS Journal of Solid State Science and Technology, 2020 9 055012), the damage depth of scratches is at most approximately 20 μm. Therefore, a highly slip-resistant region is reliable if it has a thickness of 20 μm or more from the backside, which is the damage depth of the scratches, and in reality, even a thinner thickness is practical. In the IGBT manufacturing process, the backside of the wafer is ultimately ground, and only approximately 100 μm of the front side of the silicon wafer is actually used. For SOI wafers using the bonding method, p++ or n+++ wafers can be used on the backside, and low-oxygen-concentration silicon wafers can be used on the functional layer side. Based on the above experimental findings and considerations, the inventors have realized an SOI wafer according to the present invention.

[0028] Hereinafter, details of embodiments of the present invention will be described with reference to the drawings. The same components are given the same reference numerals, and duplicated descriptions will be omitted.

[0029] (SOI wafer) Referring to Figure 3, an SOI wafer 100 according to one embodiment of the present invention has at least a support substrate 10 made of single crystal silicon, a silicon oxide film 20 provided on the support substrate 10, and a functional layer 30 made of single crystal silicon located on the silicon oxide film 20. Details of each component will be explained below.

[0030] <Support substrate> The support substrate 10 is obtained by grinding a single crystal silicon wafer cut from a silicon single crystal. The single crystal silicon wafer can be obtained by slicing a single crystal silicon ingot grown by the Czochralski method (CZ method) with a wire saw or the like.

[0031] <<Dopant concentration>> Here, the support substrate 10 is doped with a high concentration of phosphorus or boron during the growth stage. As described in the preliminary experiment, by using a single crystal silicon wafer doped with a high concentration of phosphorus or boron, high slip resistance can be obtained when used in the IGBT device manufacturing process.

[0032] -Phosphorus concentration- If the support substrate 10 is doped with phosphorus for the purpose of obtaining high slip resistance, the phosphorus concentration is 1.2×10 19 atoms / cm 3 Over 7.4 x 10 19 atoms / cm 3 In this case, the resistivity of the support substrate 10 is about 1 mΩ·cm or more and 5 mΩ·cm or less.

[0033] -Boron concentration- Similarly, if the support substrate 10 is doped with boron for the purpose of obtaining high slip resistance, the boron concentration is 1.8×10 18 atoms / cm 3 Over 2.0 x 10 19 atoms / cm 3 In this case, the resistivity of the support substrate 10 is about 5 mΩ·cm or more and 30 mΩ·cm or less.

[0034] <<Thickness>> The thickness of the support substrate 10 is greater than 10 μm. This is because it functions as a support substrate for the SOI wafer, and a thickness of 10 μm or less does not provide sufficient slip resistance. The thickness of the support substrate is preferably 20 μm or greater. As mentioned above in the preliminary experiments, scratches that serve as slip initiation points are mainly introduced during heat treatment, and the damage depth of the scratches is at most approximately 20 μm. Therefore, a support substrate thickness of 20 μm or greater can ensure sufficient slip resistance. For this purpose, the thickness of the support substrate is more preferably 50 μm or greater, and particularly preferably 100 μm or greater. Meanwhile, for IGBT applications, it is also important that the resistivity of the silicon wafer is high and consistent throughout the wafer. This is because when the oxygen concentration of a silicon wafer is high, oxygen atoms act as oxygen donors, which can cause fluctuations in the resistivity of the silicon wafer. In order to reliably prevent oxygen diffusion during the manufacturing process of an IGBT, the thickness of the support substrate is preferably less than 400 μm, more preferably 300 μm or less, and particularly preferably 200 μm or less.

[0035] <Silicon oxide film> The silicon oxide film 20 is provided on the support substrate 10. In this embodiment, the silicon oxide film 20 is used for the purpose of bonding the support substrate 10 and the functional layer 30. Therefore, the thickness of the silicon oxide film 20 is not particularly limited as long as this purpose can be achieved, but the thickness is, for example, 0.10 μm or more and 20 μm or less. To ensure reliable bonding between the support substrate 10 and the functional layer 30, the thickness of the silicon oxide film 20 is preferably 0.50 μm or more, and more preferably 1.0 μm or more. On the other hand, to reliably prevent oxygen diffusion in the IGBT manufacturing process and from the perspective of reducing manufacturing costs during SOI wafer manufacturing, the thickness of the silicon oxide film 20 is more preferably 5.0 μm or less, and particularly preferably 3.0 μm or more.

[0036] <Functional layer> A functional layer 30 made of silicon single crystal is located on the silicon oxide film 20. The functional layer 30 has an oxygen concentration of 4.0×10 17 atoms / cm3 The following silicon single crystals are acceptable, and can be obtained by slicing a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone melting method (FZ method) with a wire saw or the like, and then grinding the sliced ​​silicon ingot. For IGBT applications, the oxygen concentration of the functional layer 30 is 1.0×10 17 atoms / cm 3 The lower limit of the oxygen concentration in the functional layer 30 is not particularly limited, but for convenience, the oxygen concentration is set to 1.0×10 15 atoms / cm 3 or more. The oxygen concentration in this specification is a value obtained by thinning the wafer or layer to be measured by polishing and measuring the oxygen concentration at the center of the thickness and the center of the surface of the object by SIMS. Since the surface layer of the object to be measured contains a lot of noise components, it is difficult to measure the oxygen concentration accurately. Therefore, accurate measurement of the oxygen concentration is possible if measurement is made at a depth of 1 μm or more from the surface of the object to be measured, excluding the surface layer. In this specification, the measurement value at the center of the thickness of the object to be measured is used to obtain a more accurate value.

[0037] <<Thickness>> The thickness of the functional layer 30 is greater than 325 μm. This is to ensure a sufficient thickness for forming the IGBT device region. The thickness of the functional layer 30 is not particularly limited as long as it satisfies this condition, and may be 400 μm or more, or may be 500 μm or more. There is also no particular upper limit on the thickness of the functional layer 30; it is sufficient to adjust the thickness of the entire SOI wafer 100 to conform to the wafer standard. For example, the thickness of the functional layer 30 may be 1000 μm or less.

[0038] Furthermore, in the SOI wafer 100 according to this embodiment, the support substrate is used to ensure slip resistance, while the device formation region is a functional layer, so it is preferable that the thickness of the functional layer 30 is thicker than the thickness of the support substrate 10, and it is preferable that the thickness of the functional layer 30 is at least twice as thick as the thickness of the support substrate 10.

[0039] According to the SOI wafer 100 according to one embodiment of the present invention described above, it is possible to provide an SOI wafer that has a region with high slip resistance on the support substrate side and has a surface side that becomes a functional layer and has quality equivalent to that of a low-oxygen concentration wafer used in IGBTs.

[0040] (SOI wafer manufacturing method) An embodiment of the method for manufacturing the above-mentioned SOI wafer will be described. One embodiment of the method for manufacturing the SOI wafer includes at least an oxide film forming step, a bonding step, and a grinding step. The grinding step includes a first grinding step and a second grinding step. Each step and each configuration will be described in detail below with reference to FIG. 4.

[0041] <Oxide film formation process> See step A in FIG. 4. First, a silicon wafer 11 for a support substrate and a silicon wafer 31 for a functional layer are prepared. The silicon wafer 11 for a support substrate can be obtained by slicing a single crystal silicon ingot grown by the Czochralski method (CZ method) with a wire saw or the like. The dopant species and dopant concentration of the silicon wafer 11 for a support substrate only need to satisfy the dopant concentration conditions of the support substrate 10 described above after grinding. The silicon wafer 31 for a functional layer has an oxygen concentration of 4.0×10 17 atoms / cm 3Any silicon single crystal silicon wafer can be used, and a single crystal silicon ingot grown by the Czochralski method (CZ method) or the floating zone melting method (FZ method) can be sliced ​​using a wire saw or the like. The oxygen concentration conditions are the same as those for the functional layer 30. In this process, silicon oxide films are formed on the front and back surfaces of the support substrate silicon wafer 11. Specifically, in this process, a silicon oxide film 20 is formed on the front surface side and a silicon oxide film 21 is formed on the back surface side. Any method for forming the silicon oxide film can be used, and a known thermal oxidation method or a plasma CVD method can be used to form the silicon oxide film. For example, in the case of the thermal oxidation method, the support substrate silicon wafer 11 can be thermally oxidized by the LTO (Low Temperature Oxide) method at a temperature of approximately 370°C to 550°C for 10 minutes to 40 minutes. On the other hand, to avoid the effects of the heat treatment, it is preferable to use the functional layer silicon wafer 31 as is in the next process without forming a silicon oxide film.

[0042] <Laminating process> See steps B and C in Figure 4. In the bonding step, the support substrate silicon wafer 11 and the functional layer silicon wafer 31 are bonded together via the silicon oxide film 20 on the backside. This step can be performed using a method commonly used in manufacturing SOI wafers. After bonding, a bonding strengthening heat treatment can be performed. As shown schematically in Figure 5, silicon oxide films are formed on the front and backsides of the support substrate silicon wafer 11, which makes it possible to prevent dopants from the support substrate silicon wafer 11 from diffusing into the functional layer silicon wafer 31 during the bonding strengthening heat treatment.

[0043] <Grinding process> See step D in Figure 4. After the bonding step, a grinding step is performed, including a first grinding step for grinding the support substrate silicon wafer 11 and a second grinding step for grinding the functional layer silicon wafer 31, to obtain an SOI wafer 100. The first and second grinding steps may be performed by simultaneously grinding and polishing the front and back surfaces of the bonded wafer obtained in step C, or the first and second grinding steps may be performed separately, or a combination of simultaneous front and back surface grinding and grinding one surface at a time may be used. A known grinding method can be used in the first and second grinding steps, and one or both of mechanical grinding and etching can be used.

[0044] <<First grinding process>> In the first grinding step, the support substrate silicon wafer 11 is ground to form a support substrate 10 having a thickness of more than 10 μm. The grinding allowance can be determined appropriately so as to obtain the thickness of the support substrate 10 described above. At this time, the silicon oxide film 21 on the back surface side of the support substrate silicon wafer 11 is ground away.

[0045] <<Second grinding process>> In the second grinding step, the functional layer silicon wafer 31 is ground to form a functional layer 30 having a thickness of more than 325 μm. The grinding allowance can be appropriately determined so as to achieve the thickness of the support substrate 10 described above.

[0046] By going through the above steps, it is possible to manufacture an SOI wafer 100 according to one embodiment of the present invention. Furthermore, this manufacturing method makes it possible to provide an SOI wafer that has a region with high slip resistance on the support substrate side and has a surface side that becomes a functional layer and has quality equivalent to that of a low-oxygen concentration wafer used in IGBTs.

[0047] (Variation) With reference to step E of Fig. 4 and Fig. 5, an embodiment of a method for manufacturing an SOI wafer 200 according to a modification of the above-described SOI wafer manufacturing method will be described. The SOI wafer 200 according to the modification shown in Fig. 5 includes a support substrate 10 made of single crystal silicon, a silicon oxide film 20 provided on the support substrate 10, and a functional layer 30 made of single crystal silicon located on the silicon oxide film 30. The SOI wafer 200 further includes an oxide film 40 provided on the surface opposite to the functional layer 30. After the grinding step to obtain the SOI wafer 100, an oxide film formation step is performed to further form the oxide film 40 on the surface of the support substrate 10 opposite to the functional layer 30, thereby obtaining an SOI wafer 200 in which the support substrate 30 further includes the oxide film 40 on the surface opposite to the functional layer 30. Specifically, after the grinding process, the SOI wafer 200 is placed on a tray 300 with the functional layer 30 side facing downward, and LTO heat treatment is performed to form an oxide film 40 only on the backside of the support substrate 10. The wafer is then turned upside down and the surface on the functional layer 30 side is polished on one side (see FIG. 5; the belt conveyor 400 is shown schematically to clarify the layout). This allows for the production of an SOI wafer 200 that has an oxide film 40 on its backside while preventing scratches and particles on the functional layer 30 side that may have come into contact with the tray. Because the SOI wafer 200 has the oxide film 40, it is expected that autodoping during the device manufacturing process can also be suppressed.

[0048] The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples in any way. [Example]

[0049] (Conventional example) In the conventional example, the oxygen concentration is 4×10 -17 atoms / cm 3 The following is a FZ (Floating Zone) silicon wafer with a diameter of 200 mm and a thickness of 725 μm (dopant type: phosphorus, dopant concentration: 4.3 × 10 13 atoms / cm 3 , resistivity: 100 Ω·cm) was prepared.

[0050] In Experiment 1, we will explain examples and comparative examples of SOI wafers using phosphorus as a dopant. In Experiment 2, we will explain examples and comparative examples of SOI wafers using boron as a dopant. The preparation conditions for the samples in Experiments 1 and 2 are listed in Tables 1 and 2 below, along with the evaluation results.

[0051] [Experiment 1] (Comparative Example 1) First, an n-type silicon wafer (diameter: 200 mm, thickness: 725 μm, dopant type: phosphorus, dopant concentration: 7.4 × 10) obtained from a CZ single crystal was used as a support substrate silicon wafer. 19 atoms / cm 3 , resistivity: 1 mΩ·cm) was prepared.

[0052] Then, the surface of the silicon wafer for the support substrate was thermally oxidized at 400° C. for 20 minutes by the LTO method to form a silicon oxide film with a thickness of 1 μm.

[0053] Next, silicon wafers for functional layers were prepared using silicon wafers with an oxygen concentration of 4×10 -17 atoms / cm 3 Below, a CZ silicon wafer with a diameter of 200 mm and a thickness of 725 μm (dopant type: phosphorus, dopant concentration: 8.6 × 10 13 atoms / cm 3 A silicon wafer (resistivity: 50 Ω cm) was prepared and bonded to the above-mentioned silicon wafer for the support substrate via an oxide film. The bonded wafer was then transported into a vertical heat treatment device in an oxygen gas atmosphere, where the temperature inside the device was raised to 800°C and held there for two hours, and then raised to 1000°C and held there for one hour, performing a heat treatment to strengthen the bond.

[0054] Finally, the bonded wafers were ground to adjust their thickness. Specifically, the surface of the silicon wafer for the functional layer, opposite the silicon wafer for the support substrate, was ground and polished to obtain a 715 μm functional layer. The surface of the silicon wafer for the support substrate, opposite the silicon wafer for the functional layer, was ground and polished to obtain a 10 μm support substrate, thereby obtaining the SOI wafer according to Comparative Example 1. Including the thickness of the 1 μm-thick silicon oxide film, the total thickness of the SOI wafer was 726 μm.

[0055] (Examples 1 to 12 and Comparative Examples 2 to 12) SOI wafers according to Examples 1 to 12 and Comparative Examples 2 to 12 were produced by changing the grinding allowance of the surface portions of the silicon wafer portion for functional layer and the silicon wafer portion for support substrate, and the dopant concentration of the silicon wafer for support substrate in Comparative Example 1, to the conditions shown in Table 1. Note that, with the change in phosphorus concentration, the resistivity of the support substrate is as shown in Table 1. Furthermore, the dopant concentration of the silicon wafer for functional layer was not changed.

[0056] (Evaluation: slip length) To simulate the IGBT manufacturing process, each SOI wafer was placed in a vertical furnace and subjected to heat treatment at 1100°C. To investigate the slip length caused by contact scratches with the boat supporting the SOI wafer, the slip length on the backside of each SOI wafer (i.e., the backside of the support substrate) after heat treatment was measured using X-ray topography images. The slip length was evaluated according to the following criteria. The evaluation results are shown in Table 1. A: No slip progressed from the pin mark (see Figure 6(A)). B: Slippage developed from the pin mark, but was smaller than that of the conventional example (see Figure 6(B)). F: Slip from the pin mark progressed to the same extent as in the conventional example (see Figure 6(C)).

[0057] (Evaluation: Resistance fluctuation) To evaluate the resistance variation of the SOI wafer, the central portion of the front surface of the SOI wafer (i.e., the front surface of the functional layer) was measured using the four-point probe method, and the resistivity before and after the heat treatment was compared. The resistance variation was evaluated according to the following criteria. The results are shown in Table 1. A: The resistance reduction rate is 3% or less compared to the resistance at the center of the wafer before heat treatment. F: The resistance decrease rate is more than 3% compared to the resistance at the center of the wafer before heat treatment.

[0058] The thicknesses of the functional layers and support substrates of the SOI wafers according to Examples 1 to 12 and Comparative Examples 1 to 12, the phosphorus concentration of the support substrate, and the back surface resistivity are shown in Table 1. The evaluation results of the slip resistance and resistance fluctuation are also shown in Table 1. The evaluation results of the conventional example are also shown in Table 1.

[0059] [Table 1]

[0060] [Experiment 2] (Comparative Example 13) First, a p-type silicon wafer (diameter: 200 mm, thickness: 725 μm, dopant type: boron, dopant concentration: 2.0 × 10) obtained from a CZ single crystal was used as a support substrate silicon wafer. 19 atoms / cm 3 , resistivity: 5 mΩ·cm) was prepared.

[0061] As in Experiment 1, the surface of the silicon wafer for the support substrate was thermally oxidized at 400° C. for 20 minutes by the LTO method to form a silicon oxide film with a thickness of 1 μm.

[0062] Next, silicon wafers for functional layers were prepared using silicon wafers with an oxygen concentration of 4×10 -17 atoms / cm 3 Below, a CZ silicon wafer with a diameter of 200 mm and a thickness of 725 μm (dopant type: boron, dopant concentration: 8.6 × 10 13 atoms / cm 3A bonded wafer was prepared by bonding a silicon wafer (resistivity: 50 Ω cm) to the support substrate via an oxide film. As in Experiment 1, the bonded wafer was then transferred to a vertical heat treatment device in an oxygen gas atmosphere, where the temperature was raised to 800°C and held there for two hours, and then raised to 1000°C and held there for one hour, performing a heat treatment to strengthen the bond and producing a bonded wafer.

[0063] Finally, as in Comparative Example 1 of Experiment 1, the bonded wafers were subjected to a grinding process to adjust their thickness. Specifically, the surface of the silicon wafer for functional layer, opposite the silicon wafer for support substrate, was ground and polished to form a 715 μm functional layer. The surface of the silicon wafer for support substrate, opposite the silicon wafer for functional layer, was ground and polished to form a 10 μm support substrate, thereby obtaining an SOI wafer according to Comparative Example 13. Including the thickness of the 1 μm-thick silicon oxide film, the total thickness of the SOI wafer was 726 μm.

[0064] (Examples 13 to 24 and Comparative Examples 14 to 24) SOI wafers according to Examples 13 to 24 and Comparative Examples 14 to 24 were produced by changing the grinding allowance of the surface portions of the silicon wafer portion for functional layer and the silicon wafer portion for support substrate, and the dopant concentration of the silicon wafer for support substrate in Comparative Example 13, to the conditions shown in Table 2. Note that, with the change in boron concentration, the resistivity of the support substrate becomes as shown in Table 2. Furthermore, the dopant concentration of the silicon wafer for functional layer was not changed.

[0065] The thicknesses of the functional layers and support substrates of the SOI wafers according to Examples 13 to 24 and Comparative Examples 13 to 24, the boron concentration of the support substrate, and the back surface resistivity are shown in Table 2 below, along with the evaluation results of slip resistance and resistance fluctuation. The evaluation criteria were the same as those in Experiment 1.

[0066] [Table 2]

[0067] These results demonstrate that SOI wafers satisfying the requirements of the present invention can provide sufficient slip resistance while still satisfying the characteristics required for IGBT applications as a functional layer. Slip occurred when the support substrate was 10 μm thick, regardless of whether the dopant was boron or phosphorus. This is believed to be due to damage reaching the low-oxygen wafer region, which is the functional layer. Furthermore, resistance fluctuations occurred in experiments using a support substrate with a thickness of 400 μm. This is believed to be due to the resistance fluctuations caused by oxygen atoms diffusing from the BOX layer, an oxide film, during the RTA heat treatment in the slip resistance test when the support substrate was thick. Considering not only slip resistance but also resistance fluctuations, a support substrate thickness of less than 400 μm is preferable.

[0068] In this example, a wafer with a diameter of 200 mm was used. However, since slip resistance is a problem in the thickness direction, it is believed that the boron concentration, phosphorus concentration, and thickness conditions required to achieve the effects of the present invention will be the same even if the wafer diameter changes. [Industrial Applicability]

[0069] According to the present invention, it is possible to provide an SOI wafer having a highly slip-resistant region on the support substrate side and having a surface side that becomes a functional layer and has quality equivalent to that of low-oxygen concentration wafers used in IGBTs, and a method for manufacturing the same. [Explanation of symbols]

[0070] 10 Support substrate 11 Silicon wafer for support substrate 20 Silicon oxide film on the front side 21 Silicon oxide film on the back side 30 Functional Layers 31 Silicon wafers for functional layers 40 Oxide film on the back side 100 SOI wafers 200 SOI wafers 300 trays 400 conveyor belt

Claims

1. a support substrate made of single crystal silicon; a silicon oxide film provided on the support substrate; a functional layer located on the silicon oxide film and made of single crystal silicon, the support substrate is heavily doped with phosphorus or boron; The oxygen concentration of the functional layer is 4.0×10 １７ atoms / cm ３ is as follows: The thickness of the support substrate is greater than 10 μm; An SOI wafer, wherein the thickness of the functional layer is greater than 325 μm.

2. The support substrate is doped with phosphorus and has a phosphorus concentration of 1.2×10 １９ atoms / cm ３ 7.4 x 10 １９ atoms / cm ３ 2. The SOI wafer of claim 1, wherein:

3. The support substrate is doped with boron and has a boron concentration of 1.8×10 １８ atoms / cm ３ Above 2.0 x 10 １９ atoms / cm ３ 2. The SOI wafer of claim 1, wherein:

4. 4. The SOI wafer according to claim 1, wherein the thickness of the functional layer is greater than the thickness of the support substrate.

5. 4. The SOI wafer according to claim 1, wherein the thickness of the functional layer is at least twice as thick as the thickness of the support substrate.

6. 4. The SOI wafer according to claim 1, wherein the thickness of the support substrate is less than 400 μm.

7. 4. The SOI wafer according to claim 1, wherein the thickness of the support substrate is 20 μm or more.

8. 4. The SOI wafer according to claim 1, wherein the functional layer has a thickness of 500 μm or more.

9. 4. The SOI wafer according to claim 1, wherein the support substrate further has an oxide film on the surface opposite to the functional layer side.

10. an oxide film forming step of forming a silicon oxide film on the surface of the support substrate silicon wafer; a bonding step of bonding the support substrate silicon wafer and the functional layer silicon wafer together via the silicon oxide film; a grinding step after the bonding step, The grinding step includes: a first grinding step of grinding the silicon wafer for support substrate to form a support substrate having a thickness of more than 10 μm; a second grinding step of grinding the functional layer silicon wafer to form a functional layer with a thickness of more than 325 μm; the silicon wafer for the support substrate is doped with phosphorus or boron at a high concentration; The oxygen concentration of the silicon wafer for functional layer is 4.0 × 10 １７ atoms / cm ３ The method for manufacturing an SOI wafer is as follows.

11. The method for producing an SOI wafer according to claim 10 , further comprising, after the grinding step, an oxide film forming step of forming an oxide film on a surface of the support substrate opposite to the functional layer side.

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