Semiconductor device

Abstract

To suppress an increase in resistance of a channel layer in a group III nitride quantum confinement transistor.SOLUTION: There is provided a semiconductor device which includes a first AlN having a first lower surface that is a (0 0 0 1) surface and a first upper surface that is a (0 0 0 -1) surface, a second group III nitride disposed on or above the first AlN, and a third group III nitride disposed above the second group III nitride, and in which a plurality of quantum levels are formed in a conduction band of the second group III nitride. The second group III nitride has a second lower surface that is a (0 0 0 1) surface, a second upper surface that is a (0 0 0 -1) surface and is disposed above the second lower surface, and a bandgap narrower than a bandgap of the AlN. The third group III nitride has a third lower surface that is a (0 0 0 -1) surface, a third upper surface that is a (0 0 0 1) surface and is disposed above the third lower surface, and a bandgap wider than a bandgap of the second group III nitride.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] GaN (Gallium Nitride) has a high saturated electron velocity and a high dielectric breakdown field strength, and therefore, a high electron mobility transistor (HEMT; hereinafter referred to as GaN HEMT) with a GaN channel layer is expected to be a next-generation power device that combines high breakdown voltage and high output (see, for example, Patent Documents 1 to 3).

[0003] GaN HEMTs with AlGaN barrier layers (hereinafter referred to as AlGaN / GaN HEMTs) have already been put to practical use as power devices. AlGaN / GaN HEMTs are transistors with only one barrier layer. On the other hand, transistors with two AlN barrier layers sandwiching a GaN channel layer (hereinafter referred to as AlN / GaN / AlN transistors) have been proposed (see, for example, Patent Document 4). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-54352 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-55148 [Patent Document 3] Japanese Patent Application Laid-Open No. 2015-115605 [Patent Document 4] U.S. Patent No. 7,544,963 Summary of the Invention [Problem to be solved by the invention]

[0005] The energy of the conduction band electrons in an AlN / GaN / AlN transistor (hereinafter referred to as an AlN / GaN / AlN quantum-confined transistor) with a GaN channel layer of nanometer order thickness is quantized. Conduction band electrons are electrons within the conduction band.

[0006] In the GaN channel layer of an AlN / GaN / AlN quantum confined transistor, multiple quantum levels are formed due to the large band offset between the AlN barrier layer and the GaN channel layer. Therefore, with an AlN / GaN / AlN quantum confined transistor, a second quantum level with higher mobility than the first quantum level can be used for transporting electrons in the conduction band. Therefore, an AlN / GaN / AlN quantum confined transistor is expected to achieve higher electron mobility than an AlGaN / GaN HEMT.

[0007] The first quantum level is the quantum level with the lowest energy among the quantum levels formed in the quantum well, and the second quantum level is the quantum level with the second lowest energy among the quantum levels formed in the quantum well.

[0008] Furthermore, in an AlN / GaN / AlN quantum confined transistor, conduction band electrons are confined in the channel layer, so that leakage current flowing through paths other than the channel layer (for example, paths passing through regions deeper than the channel layer) can be suppressed.

[0009] Meanwhile, strong spontaneous polarization occurs in AlN. This strong spontaneous polarization generates two-dimensional carrier gas near the interface between the substrate-side AlN barrier layer and the GaN channel layer (hereinafter referred to as the substrate-side AlN / GaN interface). The type of two-dimensional carrier gas generated near the substrate-side AlN / GaN interface is determined by the plane index of the top surface of the substrate-side AlN barrier layer (i.e., the surface in contact with the GaN channel layer).

[0010] When the top surface of the AlN barrier layer on the substrate side is the (0 0 0 1) plane (a so-called metal polar plane), holes are induced in the GaN channel layer, which causes the formation of a two-dimensional hole gas near the AlN / GaN interface on the substrate side. This two-dimensional hole gas inhibits the generation of two-dimensional electron gas, making the GaN channel layer highly resistive.

[0011] On the other hand, when the top surface of the AlN barrier layer on the substrate side is the (0 0 0 -1) plane (the so-called nitrogen-polar plane), conduction band electrons are induced in the GaN channel layer, which results in the formation of a high-density two-dimensional electron gas near the AlN / GaN interface on the substrate side. However, the AlN barrier layer on the upper side of the channel layer generates a strong internal electric field inside the GaN channel layer, which causes the two-dimensional electron gas to localize, reducing the density and mobility of the two-dimensional electron gas. As a result, the GaN channel layer also becomes highly resistive in this case.

[0012] Therefore, an object of the present invention is to solve such problems. [Means for solving the problem]

[0013] In one embodiment, a semiconductor device includes a III-nitride on a substrate or a substrate, a first AlN having a first lower surface which is a (0 0 0 1) plane and a first upper surface which is a (0 0 0 -1) plane and disposed above the first lower surface, a second III-nitride having a second lower surface which is a (0 0 0 1) plane and a second upper surface which is a (0 0 0 -1) plane and disposed above the second lower surface, and a bandgap narrower than that of AlN, disposed on or above the first AlN, and a third III-nitride having a third lower surface which is a (0 0 0 -1) plane and a third upper surface which is a (0 0 0 1) plane and disposed above the third lower surface, and a bandgap wider than that of the second III-nitride, disposed above the second III-nitride.

[0014] However, the second group III nitride is In x2 Al y2 Ga 1-x2-y2N(0≦x2≦1 - y2, 0≦y2<1). The third group III nitride is In x3 Al y3 Ga 1-x3-y3 N(0≦x3≦1 - y3, 0<y3≦1). A plurality of quantum levels are formed in the conduction band of the second group III nitride.

Advantages of the Invention

[0015] On one hand, according to the present invention, since the direction of the spontaneous polarization of AlN under the channel layer is opposite to the direction of the spontaneous polarization of the group III nitride above the channel layer, the two-dimensional electron gas spreads in the channel layer, and the increase in the high resistance of the channel layer of the quantum confinement transistor formed of the group III nitride is suppressed.

Brief Description of the Drawings

[0016] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to Embodiment 1. [Figure 2] FIG. 2 is an enlarged view of the portion surrounded by the dashed line 4 in FIG. 1. [Figure 3] FIG. 3 is a diagram for explaining the polarization of each group III nitride layer (i.e., GaN channel layer 8, etc.) in the portion surrounded by the dashed line 4 (see FIG. 1). [Figure 4] FIG. 4 is a diagram showing the energy band along the line IV-IV in FIG. 3. [Figure 5] FIG. 5 is a diagram for explaining the operation of the semiconductor device 2. [Figure 6] FIG. 6 is a diagram for explaining the polarization of the AlN substrate and each group III nitride layer of Comparative Example 1. [Figure 7] FIG. 7 is an energy band diagram along the line VII-VII in FIG. 6. [Figure 8] FIG. 8 is a diagram for explaining the polarization of the AlN substrate and each group III nitride layer of Comparative Example 2. [Figure 9] FIG. 9 is a diagram showing the energy band along the line IX-IX in FIG. 8. [Figure 10]FIG. 10 is a cross-sectional view of a semiconductor device 302 having a cap layer other than AlN. [Figure 11] FIG. 11 is a diagram showing the energy band of the semiconductor device 302. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device 402 having an AlGaN barrier layer 407 between a channel layer 8 and a substrate 6. As shown in FIG. [Figure 13] FIG. 13 is a diagram showing the energy band of the semiconductor device 402. [Figure 14] 14A to 14C are cross-sectional views showing steps in an example of a method for manufacturing the semiconductor device 402 described with reference to FIGS. 12 and 13. FIG. [Figure 15] 15A to 15C are cross-sectional views showing steps in an example of a method for manufacturing the semiconductor device 402 described with reference to FIGS. 12 and 13. FIG. [Figure 16] 16A to 16C are cross-sectional views showing steps in an example of a method for manufacturing the semiconductor device 402 described with reference to FIGS. 12 and 13. FIG. [Figure 17] 17A to 17C are cross-sectional views showing steps in an example of a method for manufacturing the semiconductor device 402 described with reference to FIGS. 12 and 13. FIG. [Figure 18] 18A to 18C are cross-sectional views showing steps in one example of a method for manufacturing the semiconductor device 402 described with reference to FIGS. 12 and 13. FIG. [Figure 19] 19A to 19C are cross-sectional views showing steps in one example of a method for manufacturing the semiconductor device 402 described with reference to FIGS. 12 and 13. FIG. [Figure 20] 20A to 20C are cross-sectional views showing steps in an example of a method for manufacturing the semiconductor device 402 described with reference to FIGS. [Figure 21] FIG. 21 is a diagram showing a discrete package 44 in which only one semiconductor device according to the first embodiment is sealed. [Figure 22] FIG. 22 is a circuit diagram of a high-voltage power device 54 having the semiconductor device according to the first embodiment. [Figure 23] FIG. 23 is a diagram showing an example of a PFC circuit 64 having a high-voltage power device 54. [Figure 24]FIG. 24 is a cross-sectional view showing an example of a semiconductor device according to the second embodiment. [Figure 25] FIG. 25 is an enlarged view of the portion enclosed by the dashed line 504 in FIG. [Figure 26] FIG. 26 is a band diagram taken along line XXVI-XXVI in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and their equivalents. Parts having the same structure are designated by the same reference numerals even in different drawings, and their description will be omitted.

[0018] (Embodiment 1) (1) Structure FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to a first embodiment (hereinafter referred to as semiconductor device 2). FIG. 2 is an enlarged view of a portion surrounded by a dashed line 4 in FIG. 1. The semiconductor device 2 has a substrate 6 (see FIG. 2), a channel layer 8 disposed on the substrate 6, and a cap layer 10 disposed above the channel layer 8. The semiconductor device 2 further has a polarity inversion layer 12 disposed between the channel layer 8 and the cap layer 10.

[0019] The semiconductor device 2 further includes a source electrode 14 (see FIG. 1) in contact with the channel layer 8, a drain electrode 16 in contact with the channel layer 8, and a gate electrode 18 located between the source electrode 14 and the drain electrode 16 in contact with the cap layer 10. The semiconductor device 2 further includes a passivation film 21 covering the exposed surfaces of the cap layer 10, the source electrode 14, and the drain electrode 16.

[0020] The substrate 6 is made of aluminum nitride (AlN) and has a first lower surface 20a (see FIG. 2) that is a (0 0 0 1) plane (i.e., a metal polarity plane) and a first upper surface 22a that is a (0 0 0 -1) plane (i.e., a nitrogen polarity plane) and is disposed above the first lower surface 20a. The substrate 6 will be referred to hereinafter as an AlN substrate.

[0021] The channel layer 8 is made of GaN (gallium nitride) and has a second lower surface 20b that is a (0 0 0 1) plane and a second upper surface 22b that is a (0 0 0 -1) plane and is disposed above the second lower surface 20b. The channel layer 8 will hereinafter be referred to as a GaN channel layer.

[0022] The cap layer 10 is AlN having a third lower surface 20c which is a (0 0 0 -1) plane and a third upper surface 22c which is a (0 0 0 1) plane and disposed above the third lower surface 20c. The cap layer 10 will hereinafter be referred to as an AlN cap layer.

[0023] The polarity inversion layer 12 is an Al film (hereinafter referred to as an Al polarity inversion layer) having a lower surface 20 and an upper surface 22 disposed above the lower surface 20. The thickness of the Al polarity inversion layer 12 is preferably 2 to 4 atomic layers. The Al polarity inversion layer 12 may have another thickness (e.g., 2 to 6 atomic layers).

[0024] (2) Energy band 3 is a diagram illustrating polarization of each group III nitride layer (i.e., GaN channel layer 8, etc.) in the area surrounded by dashed line 4 (see FIG. 1). FIG. 4 is a diagram illustrating the energy band along line IV-IV in FIG.

[0025] 4 shows the conduction band minimum Ec of each III-nitride layer, the valence band maximum Ev of each III-nitride layer, and the Fermi level Ef (similar to FIG. 7, etc.). The upper part of FIG. 4 shows the area occupied by each III-nitride layer and the polarity inversion layer 12 together with its reference numeral (e.g., "8") (similar to FIG. 7, etc.).

[0026] Because the band gap of GaN is narrower than that of AlN, multiple quantum levels are formed in the GaN channel layer 8, which has a thickness on the order of nanometers and is sandwiched between the AlN substrate 6 and the AlN cap layer 10. In other words, the semiconductor device 2 is an AlN / GaN / AlN quantum confined transistor in which multiple quantum levels are formed in the conduction band of the GaN channel layer 8. The thickness of the GaN channel layer 8 is, for example, 5 nm or more and 20 nm or less (or 10 nm or more and 15 nm or less).

[0027] As described above, the first upper surface 22a (see FIG. 3) of the AlN substrate 6 is a nitrogen-polarity plane (i.e., a (0 0 0 -1) plane). It is known that the nitrogen-polarity plane of a group III nitride such as AlN is positively charged due to spontaneous polarization of AlN. This positive charging induces conduction band electrons 23 in the GaN channel layer 8, which in turn forms a two-dimensional electron gas 25 (see FIG. 4) near the interface between the AlN substrate 6 and the GaN channel layer 8 (hereinafter referred to as the substrate-side AlN / GaN interface).

[0028] 4 schematically shows a volume density distribution 24 of conduction band electrons 23. The horizontal axis (not shown) represents the position coordinate in the depth direction. The vertical axis (not shown) represents the volume density of conduction band electrons. The same applies to FIG. 9 and other figures described later.

[0029] The third lower surface 20c of the AlN cap layer 10 is also a positively charged nitrogen-polar surface (see FIG. 3). On the other hand, the third upper surface 22c of the AlN cap layer 10 is a negatively charged metal-polar surface (i.e., a (0 0 0 1) surface). Therefore, the potential at the third lower surface 20c of the AlN cap layer 10 is higher than the potential at the third upper surface 22c. Therefore, the conduction band minimum Ec1 at the third lower surface 20c of the AlN cap layer 10 (see FIG. 4) is lower than the conduction band minimum Ec2 at the third upper surface 22c of the AlN cap layer 10.

[0030] As a result, the conduction band minimum Ec0 (see Figure 4) at the second upper surface 22b of the GaN channel layer 8 is lower than when the third lower surface 20c of the AlN cap layer 10 is a negatively charged metal polar surface (hereinafter referred to as a forward configuration) (see "(4-2) Comparative Example 2" and Figure 9).

[0031] As a result, the gradient of the conduction band minimum Ec in the channel layer 8 becomes gentler than in the case of the forward configuration (see FIG. 9, which will be described later). As a result, as shown by the distribution 24 of conduction band electrons (see FIG. 4), the two-dimensional electron gas 25 generated near the AlN / GaN interface on the substrate side spreads in the GaN channel layer 8.

[0032] As a result, the peak volume density of the two-dimensional electron gas 25 decreases, and therefore, the semiconductor device 2 prevents the GaN channel layer 8 from becoming high in resistance (see "(4-2) Comparative Example 2"). In other words, the resistance of the GaN channel layer 8 decreases.

[0033] However, due to the lattice mismatch between the AlN substrate 6 and the GaN channel layer 8, strain occurs in the GaN channel layer 8. This strain causes piezoelectric polarization in the GaN channel layer 8. However, this piezoelectric polarization is sufficiently smaller than the spontaneous polarization in the AlN substrate 6 and the AlN cap layer 10, and can be ignored. The same is true for the spontaneous polarization in the GaN channel layer 8.

[0034] The carriers of the current flowing through the channel layer 8 are electrons. Therefore, the drain electrode 16 (see FIG. 1) is an electrode through which the current flowing through the channel layer 8 passes before entering the channel layer 8. On the other hand, the source electrode 14 is an electrode through which the current that has flowed through the channel layer 8 passes after exiting the channel layer 8. The gate electrode 18 is an electrode that controls the flow of the current flowing through the channel layer 8.

[0035] (3) Operation FIG. 5 is a diagram illustrating the operation of the semiconductor device 2. G represents the potential difference (=Φg-Φs) between the potential Φg of the gate electrode 18 and the potential Φs of the source electrode 14. Gis hereinafter referred to as the gate voltage.

[0036] When the gate electrode 18 is open, a two-dimensional electron gas 25 exists in the channel layer 8 immediately below the gate electrode 18. This state occurs when the gate voltage V G This is maintained even if the voltage drops to 0V or higher.

[0037] Gate voltage V G When the gate voltage V becomes negative, the conduction band minimum Ec rises in the channel layer 8 immediately below the gate electrode 18, and the concentration of the two-dimensional electron gas 25 decreases. G When the potential further decreases below a specific voltage (i.e., threshold voltage), the two-dimensional electron gas 25 disappears from the channel layer 8 immediately below the gate electrode 18. As a result, the semiconductor device 2 becomes non-conductive (i.e., in the OFF state).

[0038] On the other hand, the gate voltage V G When V ≠ ...

[0039] -composition- 1 and the like includes an AlN substrate 6. However, the semiconductor device according to the first embodiment may include, instead of the AlN substrate 6, an AlN layer having a first lower surface that is the (0 0 0 1) plane and a first upper surface that is the (0 0 0 -1) plane and is located above the first lower surface (see "(5-3) Modification 3").

[0040] That is, the semiconductor device according to the first embodiment (see FIG. 1, etc.) includes a first AlN which is a group III nitride on a substrate (e.g., an AlN layer) or a substrate (e.g., an AlN substrate 6) and has a first lower surface which is a (0 0 0 1) plane and a first upper surface which is a (0 0 0 -1) plane and is disposed above the first lower surface.

[0041] Furthermore, the semiconductor device 2 (see FIG. 1 etc.) has a GaN channel layer 8. However, the semiconductor device according to the first embodiment may include, instead of the GaN channel layer 8, a layer of another group III nitride (for example, InGaN) having a band gap narrower than that of AlN.

[0042] That is, the semiconductor device according to the first embodiment includes a second lower surface which is a (0 0 0 1) plane, a second upper surface which is a (0 0 0 -1) plane and is disposed above the second lower surface, and a second Group III nitride which has a bandgap narrower than the bandgap of AlN and is disposed on or above the first AlN (e.g., AlN substrate 6).

[0043] However, the second III-nitride is different from AlN, which has the widest bandgap among III-nitrides. Specifically, the second III-nitride is any of InAlGaN, AlGaN, InGaN, InAlN, InN, and GaN. That is, the second III-nitride is In x2 Al y2 Ga 1-x2-y2 N(0≦x2≦1-y2, 0≦y2<1).

[0044] The second group III nitride has the composition formula In x2 Al y2 Ga 1-x2-y2 The x2 and y2 in N represent the composition ratio of the Group III element in the second Group III nitride (the same applies to other composition formulas). x2 Al y2 Ga 1-x2-y2 The inequality in parentheses following N (0≦x2≦1-y2, 0≦y2<1) indicates the range that x2 and y2 can take (the same applies to other inequalities in parentheses).

[0045] The semiconductor device 2 (see FIG. 1 etc.) also has an Al polarity inversion layer 12. However, the semiconductor device according to the first embodiment may have, instead of the Al polarity inversion layer 12, another polarity inversion layer disposed between the second group III nitride (e.g., the GaN channel layer 8) and a third group III nitride (e.g., the AlN cap layer 10) described later.

[0046] The polarity inversion layer is a layer in which a group III nitride (e.g., AlN cap layer 10) having a bottom surface that is a (0 0 0 -1) plane is grown so that the bottom surface is in contact with the top surface of the polarity inversion layer (see FIG. 2). For example, AlON, GaON, InON, Al2O3, Ga2O3, and In2O3, or a mixed crystal of two or more of these, can also be a polarity inversion layer.

[0047] That is, the semiconductor device according to the first embodiment has a bottom surface and a top surface disposed above the bottom surface, and includes a polarity inversion layer (e.g., Al polarity inversion layer 12) disposed between a second group III nitride (e.g., GaN channel layer 8) and a third group III nitride (e.g., AlN cap layer 10).

[0048] However, the polarity inversion layer (e.g., Al polarity inversion layer 12) is a layer in which a group III nitride (e.g., AlN cap layer 10) having a bottom surface (e.g., third bottom surface 20c) that is a (0 0 0 -1) plane is grown so that the bottom surface is in contact with the top surface (e.g., top surface 22) of the polarity inversion layer (see FIG. 2). The "group III nitride" refers to, for example, a third group III nitride (e.g., AlN cap layer 10).

[0049] The semiconductor device 2 (see FIG. 1, etc.) also includes an AlN cap layer 10. However, the semiconductor device according to the first embodiment may include, instead of the AlN cap layer 10, another group III nitride (e.g., InAlGaN) having a band gap wider than the second group III nitride (e.g., GaN) (see "(5-1) Modification 1").

[0050] That is, the semiconductor device according to the first embodiment includes: a third lower surface which is the (0 0 0 -1) plane; a third upper surface which is the (0 0 0 1) plane and is disposed above the third lower surface; and a third Group III nitride having a bandgap wider than the bandgap of the second Group III nitride and disposed above the second Group III nitride.

[0051] However, the third group III nitride is a mixed crystal of AlN, which has the widest band gap among group III nitrides, and other group III nitrides (i.e., GaN and InN). Specifically, the third group III nitride is any of InAlGaN, AlGaN, InAlN, and AlN. That is, the third group III nitride is In x3 Al y3 Ga 1-x3-y3 N(0≦x3≦1-y3, 0 <y3≦1)である。

[0052] With the above configuration, a plurality of quantum levels are formed in the conduction band of the second group III nitride.

[0053] The second group III nitride is preferably In x2 Al y2 Ga 1-x2-y2 N (0≦x2≦0.4, 0≦y2≦0.6) (hereinafter referred to as composition condition 1). The third group III nitride is preferably In x3 Al y3 Ga 1-x3-y3 N(0≦x3≦0.2, 0.4≦y3≦1−x3) (hereinafter referred to as composition condition 2).

[0054] When composition conditions 1 and 2 are satisfied, the band discontinuity at the interface between the second Group III nitride and the third Group III nitride is likely to be large. Furthermore, the band discontinuity at the interface between the first AlN and the second Group III nitride is likely to be large. As a result, multiple quantum levels are likely to be formed in the conduction band of the second Group III nitride.

[0055] The second group III nitride is more preferably In x2 Al y2 Ga1-x2-y2 N (0≦x2≦0.2, 0≦y2≦0.3) (hereinafter referred to as composition condition 3). The third group III nitride is more preferably In x3 Al y3 Ga 1-x3-y3 N(0≦x3≦0.1, 0.6≦y3≦1−x3) (hereinafter referred to as composition condition 4). When composition conditions 3 and 4 are satisfied, it becomes easier to form multiple quantum levels in the conduction band of the second Group III nitride.

[0056] The second group III nitride is most preferably In x2 Al y2 Ga 1-x2-y2 N (0≦x2≦0.1, 0≦y2≦0.2) (hereinafter referred to as composition condition 5). The third group III nitride is most preferably In x3 Al y3 Ga 1-x3-y3 N(0≦x3≦0.05, 0.8≦y3≦1−x3) (hereinafter referred to as composition condition 6). When composition conditions 5 and 6 are satisfied, it becomes easier to form multiple quantum levels in the conduction band of the second Group III nitride.

[0057] (4) Comparative Example (4-1) Comparative Example 1 Consider a semiconductor device (hereinafter referred to as Comparative Example 1) that does not have a polarity inversion layer 12 and in which the upper surfaces of the AlN substrate and each III nitride layer are (0 0 0 1) planes (i.e., metal polarity planes). Fig. 6 is a diagram illustrating the polarization of the AlN substrate 106 and each III nitride layer included in Comparative Example 1. Fig. 7 is an energy band diagram taken along line VII-VII in Fig. 6.

[0058] The upper surface 122a of the AlN substrate 106 (hereinafter referred to as the substrate upper surface) is a metallic polarity surface (i.e., a (0 0 0 1) surface), and is therefore negatively charged due to spontaneous polarization of AlN (see FIG. 6). This negative charging induces holes 26 in the GaN channel layer 108, and a two-dimensional hole gas 28 (see FIG. 7) is formed near the interface between the AlN substrate 106 and the GaN channel layer 108 (i.e., the AlN / GaN interface on the substrate side).

[0059] The negatively charged substrate upper surface 122a makes the conduction band minimum Ec3 at the substrate-side AlN / GaN interface higher than the interior of the AlN substrate 106. In the GaN channel layer 108, an electric field (hereinafter referred to as an internal electric field) is generated from the AlN cap layer 110 toward the AlN substrate 106 due to spontaneous polarization between the AlN cap layer 110 and the AlN substrate 106. As a result, the conduction band minimum Ec4 at the interface between the AlN cap layer 110 and the GaN channel layer 108 (hereinafter referred to as the cap layer-side AlN / GaN interface) becomes lower than the elevated conduction band minimum Ec3 at the substrate-side AlN / GaN interface.

[0060] However, since the GaN channel layer 108 is formed thin enough to obtain a quantum level, the conduction band minimum Ec4 at the AlN / GaN interface on the cap layer side does not decrease significantly, and therefore the conduction band minimum Ec4 at the AlN / GaN interface on the cap layer side does not become lower than the Fermi level Ef (see "--Decrease in the conduction band minimum in the GaN channel layer--" below).

[0061] Therefore, conduction band electrons are not induced in the GaN channel layer 108, and two-dimensional electron gas is not formed (see FIG. 7). This results in a high resistance in the GaN channel layer 108. This problem does not occur in the semiconductor device 2 (see FIG. 2) in which the first upper surface 22a of the AlN substrate 6 is a nitrogen-polar surface (see FIG. 4).

[0062] 7, the Fermi level Ef on the upper surface of the AlN substrate 106 is off from the center of the forbidden band. On the other hand, the Fermi level Ef inside the AlN substrate 106 is approximately in the center of the forbidden band of AlN. The same is true for the semiconductor device 2 according to the first embodiment and the comparative example 2 described below.

[0063] - Reduction in the conduction band edge in the GaN channel layer - The decrease ΔEc (=Ec4-Ec3) of the conduction band minimum Ec due to the internal electric field of the GaN channel layer 108 is the product (=-E×d) of the electric field E in the GaN channel layer 108 and the thickness d of the cap layer. Therefore, as the layer thickness d becomes thinner, the magnitude (i.e., absolute value) of the decrease ΔEc becomes smaller. Note that the unit of the energy difference Δ is eV.

[0064] (4-2) Comparative Example 2 Consider a semiconductor device (hereinafter referred to as Comparative Example 2) that does not have a polarity inversion layer 12 and in which the upper surfaces of the AlN substrate and each III nitride layer are (0 0 0 -1) planes (i.e., nitrogen polarity planes). Fig. 8 is a diagram illustrating the polarization of the AlN substrate 206 and each III nitride layer in Comparative Example 2. Fig. 9 is a diagram showing the energy band along line IX-IX in Fig. 8.

[0065] The upper surface 222a (see FIG. 8) of the AlN substrate 206, which is a nitrogen-polarity plane (i.e., a (0 0 0 -1) plane), is positively charged due to spontaneous polarization of AlN. This positive charging induces conduction band electrons 23 in the GaN channel layer 208, and two-dimensional electron gas 225 (see FIG. 9) is formed near the interface between the AlN substrate 206 and the GaN channel layer 208. Therefore, regardless of the thickness of the GaN channel layer 208, two-dimensional electron gas 225 is formed in the GaN channel layer 208 (see FIG. 9).

[0066] However, because the AlN cap layer 210 (see FIG. 8) and the AlN substrate 206 are spontaneously polarized in the same direction, a strong electric field is generated in the GaN channel layer 208 from the AlN substrate 206 toward the AlN cap layer 210. This strong electric field causes the conduction band minimum Ec in the GaN channel layer 208 to increase sharply toward the AlN cap layer 210 (see FIG. 9).

[0067] Then, as shown by the distribution 224 of conduction band electrons (see FIG. 9), a high-concentration two-dimensional electron gas 225 localizes near the AlN / GaN interface on the substrate side. As a result, the concentration of the two-dimensional electron gas 225 (specifically, the volume concentration) becomes too high, and the mobility of the GaN channel layer 208 increases due to phonon scattering. That is, the GaN channel layer 208 becomes highly resistive.

[0068] In the semiconductor device 2 described with reference to FIG. 1 and the like, such a problem does not occur (see FIG. 4) because the lower end Ec0 of the conduction band at the AlN / GaN interface on the cap layer side is pushed down by the in-channel electric field (that is, the electric field within the channel layer) toward the AlN cap layer 10.

[0069] (5) Modified Example (5-1) Modified Example 1 The cap layer 10 shown in FIG. 1 is AlN. However, the cap layer of the semiconductor device according to Embodiment 1 may be a group III nitride other than AlN.

[0070] FIG. 10 is a cross-sectional view showing an example of such a semiconductor device (hereinafter referred to as semiconductor device 302). The semiconductor device 302 has a layer 310 of In x3 Al y3 Ga 1-x3-y3 N (0 <x3 ≤ 0.2, 0 <y3 ≤ 1 - x3) (hereinafter referred to as an InAlGaN cap layer). Similar to the AlN cap layer 10, the cap layer 310 has a third lower surface 320c that is the (0 0 0 -1) plane and a third upper surface 322c that is the (0 0 0 1) plane. Other than these matters, the semiconductor device 302 has substantially the same structure as the semiconductor device 2 described with reference to FIG. 1 and the like.

[0071] FIG. 11 is a diagram showing the energy band of the semiconductor device 302. Similar to the AlN cap layer 10 (see FIG. 2), the InAlGaN cap layer 310 has a wider bandgap than the GaN channel layer 8.

[0072] Furthermore, the InAlGaN cap layer 310 is spontaneously polarized in the same direction as the AlN cap layer 10. Therefore, the slope of the conduction band minimum Ec in the GaN channel layer 8 is gentler than in Comparative Example 1. As a result, as shown by the distribution 324 of conduction band electrons, the two-dimensional electron gas 325 is widely distributed in the channel layer 8. Therefore, similar to the semiconductor device 2 described with reference to FIG. 1 etc., the increase in resistance of the GaN channel layer 8 is suppressed.

[0073] In the above example, the Al composition ratio y3 is greater than 0 and less than or equal to 1-x3. However, the Al composition ratio y3 is preferably greater than or equal to 0.4 and less than or equal to 1-x3 (see "-Configuration-" in "(3) Operation"). In this case, crystal defects due to lattice mismatch with the AlN substrate 6 are hardly generated in the InAlGaN cap layer 310. Therefore, the two-dimensional electron gas 325 is hardly scattered by the crystal defects in the InAlGaN cap layer 310, and the electrical characteristics of the GaN channel layer 8 are hardly deteriorated.

[0074] According to the semiconductor device 302, the variations of the semiconductor device according to the first embodiment are increased.

[0075] (5-2) Variation 2 1 and 10, the GaN channel layer 8 is in contact with the AlN substrate 6. However, the semiconductor device according to the first embodiment may have another layer (hereinafter referred to as a barrier layer) between the channel layer 8 and the substrate 6.

[0076] 12 is a cross-sectional view showing an example of such a semiconductor device (hereinafter referred to as a semiconductor device 402). The semiconductor device 402 has an AlN substrate 6 and a GaN channel layer 8 between the AlN substrate 6 and the GaN channel layer 8. y4 Ga 1-y4It has a layer 407 of N(0 < y4 ≤ 1) (hereinafter referred to as an AlGaN barrier layer). The AlGaN barrier layer 407 has a lower surface 20d which is a (0 0 0 1) plane (hereinafter referred to as the fourth lower surface), and an upper surface 22d which is a (0 0 0 -1) plane and is disposed above the fourth lower surface 20d (hereinafter referred to as the fourth upper surface). Except for these, the semiconductor device 402 has substantially the same structure as the semiconductor device 302 (see “(5-1) Modified Example 1”).

[0077] FIG. 13 is a diagram showing the energy band of the semiconductor device 402. As shown in FIG. 13, the AlGaN barrier layer 407 has a wider bandgap than the GaN channel layer 8.

[0078] The fourth upper surface 22d of the AlGaN barrier layer 407 that contacts the GaN channel layer 8 is positively charged due to the spontaneous polarization of the AlGaN barrier layer 407. Due to this positive charge, electrons are induced in the GaN channel layer 8. As a result, a two-dimensional electron gas 425 (see FIG. 13) is formed in the vicinity of the interface between the AlGaN barrier layer 407 and the GaN channel layer 8.

[0079] And, similar to the semiconductor device 302 (see “(5-1) Modified Example 1”), due to the spontaneous polarization of the cap layer 310, the slope of the lower end Ec of the conduction band in the channel layer 8 becomes gentle. As a result, as shown by the distribution 424 of conduction band electrons, the two-dimensional electron gas 425 is widely distributed in the channel layer 8. Therefore, the increase in the resistance of the GaN channel layer 8 is suppressed. According to the semiconductor device 402, the variations of the semiconductor device according to Embodiment 1 increase.

[0080] The semiconductor device 402 described with reference to FIG. 12 etc. has an AlGaN barrier layer 407. However, the semiconductor device according to Embodiment 1 may include a group III nitride (for example, an InAlGaN layer) having a wider bandgap than the GaN channel layer 8 instead of the AlGaN barrier layer 407.

[0081] That is, the semiconductor device according to Embodiment 1 may include a fourth group-III nitride (e.g., an AlGaN barrier layer or an InAlGaN layer) disposed between the first AlN (e.g., the AlN substrate 6) and the second group-III nitride (e.g., the GaN channel layer 8). The fourth group-III nitride has a fourth lower surface 20d that is a (0 0 0 1) plane, a fourth upper surface 22d that is a (0 0 0 -1) plane and is disposed above the fourth lower surface 20d, and a bandgap that is wider than the bandgap of the second group-III nitride and narrower than the bandgap of AlN.

[0082] However, the fourth group-III nitride is a mixed crystal of AlN, which has the widest bandgap among group-III nitrides, and other group-III nitrides (i.e., GaN and InN). Specifically, the fourth group-III nitride is any one of InAlGaN, AlGaN, InAlN, and AlN. That is, the fourth group-III nitride has a composition formula In x4 Al y4 Ga 1-x4-y4 N (0 ≦ x4 ≦ 1 - y4, 0 < y4 ≦ 1) and is a group-III nitride represented by this formula.

[0083] (5-3) Modification 3 The semiconductor device 2 described with reference to FIG. 2 and the like has an AlN substrate 6. However, the semiconductor device according to Embodiment 1 may have a composite substrate in which an AlN layer is grown on another substrate (e.g., a Si substrate, a sapphire substrate, a ZnO substrate, a Si substrate, a single crystal diamond substrate, a GaN substrate, a Ga2O3 substrate) instead of the AlN substrate 6. However, similar to the AlN substrate 6, the above AlN layer has a first lower surface that is a (0 0 0 1) plane and a first upper surface that is a (0 0 0 -1) plane and is disposed above the first lower surface.

[0084] It is also easy to suppress the increase in the resistance of the GaN channel layer 8 by the semiconductor device 2 including the above composite substrate instead of the AlN substrate 6. The AlN layer on the substrate is an example of the first AlN described above (see "-Configuration-" in "(3) Operation").

[0085] The thickness of the first AlN is preferably 200 nm or more, more preferably 500 nm or more, and most preferably 1 μm or more.

[0086] If the thickness of the first AlN is 200 nm or more, the conduction band minimum Ec at the bottom surface of the second group III nitride is sufficiently depressed by the spontaneous polarization of the first AlN, which facilitates the generation of two-dimensional electron gas in the second group III nitride (i.e., the channel layer).

[0087] (6) Manufacturing method 14-20 are cross-sectional views showing steps in one example of a method for manufacturing the semiconductor device 402 described with reference to FIGS. 12-13.

[0088] (6-1) Growth of III-nitride layer and polarity inversion layer (see Figure 14) First, an AlGaN barrier layer 407, a GaN channel layer 8, an Al polarity inversion layer 12, and an InAlGaN cap layer 310 are grown in this order on the nitrogen polarity surface of an AlN substrate 6 by metalorganic chemical vapor deposition (MOCVD) (see FIG. 14). The growth of the AlGaN barrier layer 407 may be omitted. In this case, the semiconductor device 302 described with reference to FIGS. 10-11 is formed.

[0089] The AlN substrate 6 is a free-standing substrate. The thickness of the AlGaN barrier layer 407 is, for example, 25 nm to 100 nm (preferably, 50 nm). The thickness of the GaN channel layer 8 is, for example, 5 nm to 20 nm (preferably, 10 nm). Alternatively, the thickness of the GaN channel layer 8 is 10 nm to 15 nm. The thickness of the InAlGaN cap layer 310 is, for example, 5 nm to 20 nm (preferably, 10 nm).

[0090] The source gas for the AlGaN barrier layer 407 and the like is a mixed gas of one or more organometallic gases containing a group III element and ammonia (NH3) gas. The organometallic gas is, for example, one or more of trimethylaluminum (TMAl) gas, trimethylgallium (TMGa) gas, and trimethylindium (TMI) gas. The carrier gas is hydrogen (H2) gas or nitrogen (N2) gas. The growth pressure is, for example, 1 kPa to 100 kPa. The growth temperature is, for example, 600°C to 1500°C.

[0091] The Al polarity inversion layer 12 is formed by temporarily supplying trimethylaluminum gas instead of the above-mentioned mixed gas after the growth of the GaN channel layer 8. Then, the supply of the above-mentioned mixed gas is restarted to grow the InAlGaN cap layer 310 having the third upper surface 322c, which is a metallic polarity surface. Because InAlGaN has a lower growth temperature than AlN, the InAlGaN cap layer 310 can be grown without increasing the growth temperature after the growth of the GaN channel layer 8.

[0092] (6-2) Formation of source electrode 14 and drain electrode 16 (see Figures 15-17) - Formation of element isolation trenches - Next, the plurality of layers 32 (see FIG. 15) grown on the AlN substrate 6 are etched to form element isolation trenches (not shown) that reach the AlN substrate 6. The plurality of layers 32 will hereinafter be referred to as grown layers.

[0093] First, a photoresist film having lattice-shaped openings (not shown) is formed on the InAlGaN cap layer 310 (see FIG. 14). These openings have substantially the same shape and dimensions as the element isolation trenches in plan view.

[0094] The growth layer 32 is etched through the opening to form an isolation trench (not shown). Dry etching is used to etch the growth layer 32. The etching gas is, for example, a chlorine-based gas. The photoresist film is then removed. Instead of forming the isolation trench, the resistance between the regions that will become the semiconductor device 402 may be increased by ion implantation.

[0095] - Formation of surface protection film 34 - Next, a surface protection film 34 (see FIG. 15) is formed on the InAlGaN cap layer 310 by, for example, plasma enhanced chemical vapor deposition (hereinafter referred to as plasma CVD). The surface protection film 34 may be formed by atomic layer deposition (hereinafter referred to as ALD) or sputtering.

[0096] The surface protection film 34 is preferably an SiO2 film. The surface protection film 34 may be an oxide of any one of Al, Hf, Zr, Ti, Ta, and W. Alternatively, the surface protection film 34 may be a nitride (or oxynitride) of any one of Si, Al, Hf, Zr, Ti, Ta, and W.

[0097] - Etching of growth layer - Next, a photoresist film having openings (hereinafter referred to as first openings) corresponding to the areas where the source electrode 14 and the drain electrode 16 are to be formed is formed on the surface protection film 34. Thereafter, the surface protection film 34 and the growth layer 32 are etched through the first openings until the GaN channel layer 8 is exposed (see FIG. 16). At this time, the GaN channel layer 8 is over-etched to ensure that the GaN channel layer 8 is exposed.

[0098] Dry etching is used to etch the surface protection film 34 and the growth layer 32. The etching gas is, for example, a chlorine-based gas. Thereafter, the photoresist film having the first opening is removed.

[0099] -Electrode formation- Next, a two-layer film 36 (hereinafter referred to as Ta / Al film) having a Ta film in contact with the GaN channel layer 8 and an Al film in contact with the Ta film is formed in the recess formed by the etching (see FIG. 17). The Ta / Al film 36 is formed, for example, by a lift-off method. The thickness of the Ta film is, for example, 10 nm to 40 nm (preferably, 20 nm). The thickness of the Al film is, for example, 100 nm to 400 nm (preferably, 200 nm).

[0100] Next, the AlN substrate 6 on which the Ta / Al film 36 has been formed is heated in a nitrogen atmosphere. The heating temperature is 400°C or higher and 1000°C or lower (preferably 550°C). This heating forms an ohmic contact between the Ta / Al film 36 and the GaN channel layer 8. This completes the source electrode 14 and the drain electrode 16.

[0101] (6-3) Formation of passivation film 21 (see FIG. 18) Next, a passivation film 21 covering the InAlGaN cap layer 310, the source electrode 14, and the drain electrode 16 is formed by, for example, plasma CVD (see FIG. 18). The thickness of the passivation film 21 is, for example, 2 nm to 500 nm (preferably, 100 nm). The passivation film 21 may be formed by sputtering or ALD. The passivation film 21 is preferably a SiN film. The passivation film 21 may be a nitride of any one of Al, Hf, Zr, Ti, Ta, and W. Alternatively, the passivation film 21 may be an oxide (or oxynitride) of any one of Si, Al, Hf, Zr, Ti, Ta, and W.

[0102] (6-4) Formation of gate electrode 18 (see FIGS. 19 and 20) Next, a photoresist film having an opening (hereinafter referred to as a second opening) between the source electrode 14 and the drain electrode 16 is formed on the passivation film 21. Thereafter, the passivation film 21 is etched through the second opening (see FIG. 19). This etching forms an opening 40 (hereinafter referred to as a gate opening) in the passivation film 21.

[0103] The passivation film 21 is etched by, for example, dry etching. The etching gas is, for example, a fluorine-based gas or a chlorine-based gas. Then, the photoresist film is removed. The passivation film 21 may also be etched by wet etching. The etching liquid is, for example, hydrofluoric acid or buffered hydrofluoric acid.

[0104] Next, the gate electrode 18 is formed (FIG. 20) having a Ni film in contact with the InAlGaN cap layer 310 in the gate opening 40 and an Au film in contact with this Ni film. The gate electrode 18 is formed by, for example, a lift-off method.

[0105] The thickness of the Ni film is, for example, 15 nm or more and 60 nm or less (preferably, 30 nm). The thickness of the Au film is, for example, 200 nm or more and 800 nm or less (preferably, 400 nm). In this way, the semiconductor device 402 is completed.

[0106] As described above, the method for manufacturing a semiconductor device according to the first embodiment includes a first step of growing a second group III nitride (see "-Configuration-" in "(3) Operation") on or above the (0 0 0 -1) plane of the first AlN.

[0107] The method for manufacturing the semiconductor device of the first embodiment further includes, after the first step, a second step of growing a polarity inversion layer on the second Group III nitride (e.g., GaN channel layer 8), the polarity inversion layer having a lower surface and an upper surface disposed above the lower surface.

[0108] The method for manufacturing the semiconductor device of the first embodiment further includes, after the second step, a third step of growing a third group III nitride (see "-Configuration-" in "(3) Operation") on the polarity inversion layer (e.g., Al polarity inversion layer 12).

[0109] The method for manufacturing the semiconductor device of the first embodiment further includes, after the third step, a fourth step of forming electrodes (for example, the source electrode 14, the drain electrode 16, and the gate electrode 18).

[0110] However, the second group III nitride is In x2 Al y2 Ga 1-x2-y2 N(0≦x2≦1-y2, 0≦y2<1). The third group III nitride is In x3 Al y3 Ga 1-x3-y3N satisfies 0≦x3≦1 - y3 and 0 < y3≦1. The polarization inversion layer is a material in which a group III nitride (at least the third group III nitride) having a (0 0 0 -1) plane contacting the upper surface grows.

[0111] (7) Usage examples (7-1) Usage example 1 The semiconductor device according to Embodiment 1 can be used as a discrete device. FIG. 21 is a diagram showing a discrete package 44 in which only one semiconductor device according to Embodiment 1 is encapsulated. The discrete package 44 is an example of a discrete device.

[0112] Hereinafter, the structure of the discrete package 44 will be described according to its manufacturing method. First, the die 42 (that is, the chip) is fixed to the die pad 43 by a die attach agent 46 such as solder. The die 42 has, for example, a semiconductor device 302 (see FIG. 10), a gate pad 47g connected to the gate electrode 18, a source pad 47s connected to the source electrode 14, and a drain pad 47d connected to the drain electrode 16. The gate pad 47g is an electrode disposed on the passivation film 21 (see FIG. 10). The same applies to the source pad 47s and the drain pad 47.

[0113] Thereafter, the gate lead 48g and the gate pad 47g are connected by a bonding wire 50g. Further, the source lead 48s and the source pad 47s are connected by a bonding wire 50s. Further, the drain lead 48d and the drain pad 47d are connected by a bonding wire 50d.

[0114] Thereafter, the die 42 is encapsulated with a mold resin 52. In FIG. 21, the mold resin 52 is partially shown so that the die 42 and the like can be seen. The encapsulation is performed, for example, by a transfer molding method.

[0115] Finally, the gate lead 48g, the source lead 48s, the drain lead 48d, and the die pad 43 are separated from the lead frame (not shown). In this way, the discrete package 44 is completed.

[0116] (7-2) Usage example 2 The semiconductor device according to the first embodiment can also be used in combination with other semiconductor elements. Fig. 22 is a circuit diagram of a high-voltage power device 54 having the semiconductor device according to the first embodiment. This high-voltage power device 54 has not only the feature (i.e., high breakdown voltage) of the semiconductor device according to the first embodiment, but also a normally-off characteristic that the semiconductor device according to the first embodiment does not have.

[0117] Normally-off characteristics are an important feature of power devices. If the gate driver that controls the gate voltage of a power device with normally-on characteristics (hereafter referred to as a normally-on device) fails, an overcurrent will flow through the normally-on device. As a result, the circuit in which the normally-on device is installed may be destroyed.

[0118] On the other hand, if the gate driver that controls the gate voltage of a power device with normally-off characteristics (hereinafter referred to as a normally-off device) fails, the normally-off device becomes non-conductive. As a result, the circuit equipped with the normally-off device is protected from destruction due to overcurrent. Therefore, the normally-off characteristic is an important characteristic for power devices.

[0119] 22 includes the semiconductor device 302 described with reference to FIG. 10 and a silicon low-voltage MOSFET 56 (hereinafter referred to as LV-MOSFET). The LV-MOSFET is a MOSFET (metal-oxide-semiconductor field-effect transistor) having a positive threshold voltage (>0 V). The high-voltage power device 54 may include another semiconductor device according to the first embodiment (e.g., semiconductor device 2) instead of the semiconductor device 302.

[0120] The LV-MOSFET 56 is an n-channel MOSFET having a source electrode 58 connected to the gate electrode 18 (see FIG. 10) of the semiconductor device 302, a drain electrode 60 connected to the source electrode 14 of the semiconductor device 302, and a gate electrode 62.

[0121] The high-voltage power device 54 further has a source terminal S connected to the source electrode 58 of the LV-MOSFET 56, a gate terminal G connected to the gate electrode 62 of the LV-MOSFET 56, and a drain terminal D connected to the drain electrode 16 of the semiconductor device 302. A control signal for controlling the ON / OFF of the high-voltage power device 54 is applied between the gate terminal G and the source terminal S. The control signal is applied by a gate driver (not shown).

[0122] As is clear from FIG. 22, the source-gate voltage V SG 1 is the source-drain voltage V of the LV-MOSFET56 SD The voltage with the opposite sign of 2 (i.e., -V SD 2) Equal to the source-gate voltage V SG 1 is the gate voltage V G is.

[0123] When a voltage higher than the positive threshold (>0V) of the LV-MOSFET 56 is applied between the source electrode 58 and the gate electrode 62 of the LV-MOSFET 56, the LV-MOSFET 56 becomes conductive. SD 2 is approximately 0 V, the source-gate voltage V SG 1(=-V SD 2) also becomes approximately 0 V. As a result, the normally-on semiconductor device 302 also becomes conductive, and the high-voltage power device 54 becomes conductive (i.e., ON).

[0124] On the other hand, when a voltage lower than the positive threshold (>0V) of the LV-MOSFET 56 is applied between the source electrode 58 and the gate electrode 62 of the LV-MOSFET 56, the LV-MOSFET 56 becomes non-conductive. SD 2 rises and becomes positive, and the source-gate voltage V SG 1(=-V SD 2) will be negative.

[0125] The device parameters of the semiconductor device 302 and the LV-MOSFET 56 are the source-gate voltage V SG 1 (see FIG. 22) is designed to be smaller than the negative threshold voltage (<0V) of the semiconductor device 302. Therefore, when the LV-MOSFET 56 becomes non-conductive, the semiconductor device 302 also becomes non-conductive. As a result, the high-voltage power device 54 becomes non-conductive (i.e., OFF).

[0126] As is clear from the above explanation, when a voltage higher than the positive threshold (>0V) of the LV-MOSFET 56 is applied between the source terminal S and the gate terminal G, the high-voltage power device 54 becomes conductive. On the other hand, when a voltage lower than the positive threshold (>0V) of the LV-MOSFET 56 is applied between the source terminal S and the gate terminal G, the high-voltage power device 54 becomes non-conductive. In other words, the high-voltage power device 54 has normally-off characteristics.

[0127] Furthermore, since the semiconductor device 302 has a high breakdown voltage, the breakdown voltage of the high breakdown voltage power device 54 is also high. That is, the high breakdown voltage power device 54 has normally-off characteristics and the high breakdown voltage of the semiconductor device 302.

[0128] (7-3) Usage example 3 The high-voltage power device 54 (FIG. 22) is suitable as a switching device for an active power factor correction circuit (hereinafter referred to as a PFC circuit). FIG. 23 is a diagram showing an example of a PFC circuit 64 having the high-voltage power device 54.

[0129] The PFC circuit 64 is a power supply circuit that converts an AC voltage supplied from an AC power supply 66 into a DC voltage and supplies the DC voltage to a load 68. As shown in Fig. 23, the PFC circuit 64 includes a diode bridge 70 having a pair of input terminals T1 (hereinafter referred to as bridge input terminals) and a pair of output terminals T2 (hereinafter referred to as bridge output terminals), and a capacitor 72 connected to the bridge output terminals T2. The AC power supply 66 is connected to the bridge input terminals T1.

[0130] The PFC circuit 64 further includes a choke coil 74 having one end connected to one of the bridge output terminals T2 (hereinafter referred to as the high terminal H). The PFC circuit 64 further includes a high-voltage power device 54 having a drain terminal D connected to the other end of the choke coil 74 and a source terminal S connected to the other of the bridge output terminals T2 (hereinafter referred to as the low terminal L). A gate driver (not shown) is connected between the gate terminal G and source terminal S of the high-voltage power device 54.

[0131] The PFC circuit 64 further includes a diode 76 having an anode terminal connected to the drain terminal D of the high-voltage power device 54. The PFC circuit 64 further includes a capacitor 78 (hereinafter referred to as the output capacitor) having one end connected to the cathode terminal of the diode 76 and the other end connected to the low terminal L (i.e., the other end of the bridge output terminal T2).

[0132] A current 81 is supplied to the output capacitor 78 via the diode 76. The output capacitor 78 is charged by this current 81 (hereinafter referred to as the charging current). As a result, a DC voltage is generated across the output capacitor 78. This DC voltage is applied to the load 68.

[0133] Since the diode 76 has a rectifying effect, a charging current 81 flows only while the potential on the anode side is higher than the potential on the cathode side. When the application of an AC voltage to the PFC circuit 64 starts, a DC voltage V DCTherefore, immediately after the start of the AC voltage supply, the charging current 81 flows for most of one cycle of the AC voltage. However, as time passes, the DC voltage V DC As the voltage Vcc increases, the period during which the charging current 81 flows becomes gradually shorter.

[0134] Now, consider a circuit in which the high-voltage power device 54 and the choke coil 74 are removed from the PFC circuit 64. However, to ensure a current path from the high terminal H (i.e., one of the bridge output terminals T2) to the diode 76, the choke coil 74 is replaced with a conductor. The waveform of the charging current 81 flowing through this circuit differs significantly from the voltage waveform (e.g., a sine wave) of the AC power supply 66 due to the rectification action of the diode bridge 70 and the diode 76. For example, the charging current 81 is a current that flows intermittently.

[0135] Next, consider a circuit in which only the high-voltage power device 54 is removed from the PFC circuit 64 (i.e., a passive PFC circuit). The waveform of the charging current 81 flowing through this circuit becomes continuous due to the inductance of the choke coil 74, and approaches the waveform of AC current to a certain extent. However, there remains a non-negligible difference between the voltage waveform of the AC power supply 66 and the waveform of the charging current 81.

[0136] For this reason, the power factor of the AC power supply 66 is not very high. Moreover, the current output by the AC power supply 66 contains a large high-frequency component. In other words, the AC power supply 66 generates a large high-frequency noise.

[0137] Finally, consider the case where high-voltage power device 54 is appropriately turned on in PFC circuit 64. If current 80 flowing through choke coil 74 (hereinafter referred to as choke coil current) has a waveform substantially the same as that of a full-wave rectified wave, the power factor of AC power supply 66 will be substantially 1 even if the waveform of charging current 81 differs from the voltage waveform of AC power supply 66. Note that a full-wave rectified wave is a sine wave whose waveform is inverted in the latter half of one cycle (i.e., the negative part of the sine wave).

[0138] Choke coil current 80 is the sum of charging current 81 flowing through diode 76 and the current flowing through high-voltage power device 54. Therefore, by conducting high-voltage power device 54 at the appropriate time, choke coil current 80 can be made to approach a full-wave rectified wave. Therefore, by conducting high-voltage power device 54 at the appropriate time, it is possible to improve the power factor and reduce high-frequency noise.

[0139] However, in order to make the waveform of the choke coil current 80 approach a full-wave rectified wave, it is important that the high-voltage power device 54 operates at high speed (hereinafter referred to as requirement 1).

[0140] To further improve the power factor, it is also important that the loss in the high voltage power device 54 is small (hereinafter referred to as requirement 2). In other words, it is important that the on-resistance of the high voltage power device 54 is low.

[0141] The high voltage power device 54 can satisfy these requirements 1 and 2 because the semiconductor device 302 has high mobility. Therefore, the high voltage power device 54 is suitable as a switching device for a PFC circuit. In addition, since the high voltage power device 54 has a high withstand voltage, it can withstand a DC voltage V DC (i.e., the output voltage of the PFC circuit 64) can also be increased.

[0142] As described with reference to FIG. 3 and other figures, in the semiconductor device of the first embodiment, the direction of spontaneous polarization of the first AlN (e.g., AlN substrate 6) is opposite to the direction of spontaneous polarization of the third group III nitride (e.g., AlN cap layer 10). Therefore, the electric field strength in the second group III nitride (e.g., GaN channel layer 8) is weakened. As a result, two-dimensional electron gas induced by the spontaneous polarization of the first AlN (in other words, positive charges on the nitrogen-polarity face) is widely distributed in the second group III nitride. Therefore, according to the semiconductor device of the first embodiment, the increase in resistance of a quantum confined transistor whose channel layer and the like are formed of group III nitrides is suppressed.

[0143] (Embodiment 2) The semiconductor device according to the second embodiment is similar to the semiconductor device according to the first embodiment. Therefore, the description of the same configuration as that of the first embodiment will be omitted or simplified.

[0144] (1) Structure Fig. 24 is a cross-sectional view showing an example of a semiconductor device according to the second embodiment (hereinafter referred to as semiconductor device 502). Fig. 25 is an enlarged view of a portion surrounded by a dashed line 504 in Fig. 24. Semiconductor device 502 further includes a spacer layer 582 arranged between GaN channel layer 8 and Al polarity inversion layer 12 in semiconductor device 402 according to the first embodiment (see Fig. 12) (see Figs. 24 and 25).

[0145] The spacer layer 582 (see FIG. 25) has a lower surface 20e (hereinafter referred to as a fifth lower surface) which is a (0 0 0 1) plane, an upper surface 22e (hereinafter referred to as a fifth upper surface) which is a (0 0 0 -1) plane and is disposed above the fifth lower surface 20e, and an Al GaN channel layer 8 having a band gap wider than that of the GaN channel layer 8. x5 Ga 1-x5 N(0.4≦x5≦1).

[0146] The spacer layer 582 is a layer that is sufficiently thinner than the InAlGaN cap layer 310. The thickness of the spacer layer 582 (hereinafter referred to as the AlGaN spacer layer) is, for example, 0.5 nm to 2 nm (preferably 1 nm).

[0147] (2) Energy band 26 is a band diagram taken along line XXVI-XXVI in FIG. 25. The direction of spontaneous polarization in the AlGaN spacer layer 582 is the same as the direction of spontaneous polarization in the AlN substrate 6. Therefore, the conduction band minimum Ec in the AlGaN spacer layer 582 increases toward the GaN channel layer 8 (see FIG. 26). However, since the AlGaN spacer layer 582 is thin as described above, the AlGaN spacer layer 582 only slightly raises the conduction band minimum Ec at the second upper surface 22b of the GaN channel layer 8 (see FIG. 25).

[0148] The direction of spontaneous polarization in the InAlGaN cap layer 310 is opposite to the direction of spontaneous polarization in the AlN substrate 6. Therefore, the conduction band minimum Ec in the InAlGaN cap layer 310 decreases toward the GaN channel layer 8. As described above, since the AlGaN spacer layer 582 only slightly increases the conduction band minimum Ec, the decrease in the conduction band minimum Ec in the InAlGaN cap layer 310 (toward the GaN channel layer 8) decreases the conduction band minimum Ec at the second upper surface 22b of the GaN channel layer 8.

[0149] This reduces the gradient of the conduction band minimum Ec in the channel layer 8. As a result, the two-dimensional electron gas 525 is widely distributed in the channel layer 8 (see the distribution 524 of conduction electrons). This prevents the GaN channel layer 8 from becoming highly resistive.

[0150] The two-dimensional electron gas 525 in the GaN channel layer 8 is separated from the Al polarity inversion layer 12 by the AlGaN spacer layer 582. This suppresses scattering of the two-dimensional electron gas 525 due to crystal defects (or crystal disorder) in the Al polarity inversion layer 12, thereby increasing the mobility of the GaN channel layer 8. Therefore, the resistance of the channel layer 8 is reduced.

[0151] (3) Manufacturing method The method for manufacturing the semiconductor device 502 is similar to the method for manufacturing the semiconductor device 402 according to the first embodiment.

[0152] However, the Al polarity inversion layer 12 is not grown directly on the GaN channel layer 8, but is grown after growing an AlGaN spacer layer 582 on the channel layer 8. In other words, the Al polarity inversion layer 12 is grown above the channel layer 8.

[0153] Furthermore, when the InAlGaN cap layer 310 and the like are etched to form recesses for electrodes (see FIG. 16), the AlGaN spacer layer 582 is also etched together.

[0154] Other than these, the method for manufacturing semiconductor device 502 is substantially the same as the method for manufacturing semiconductor device 402 according to the first embodiment.

[0155] (4) How to use The method of using the semiconductor device according to the second embodiment is substantially the same as the method of using the semiconductor device according to the first embodiment (see "(7) Usage Example"). Therefore, a description of the method of using the semiconductor device according to the second embodiment will be omitted.

[0156] 24 and other drawings includes an AlGaN spacer layer 582. However, the semiconductor device according to the second embodiment may include another group III nitride (e.g., InAlGaN) instead of the AlGaN spacer layer 582.

[0157] That is, the semiconductor device according to the second embodiment is a device that further includes a fifth Group III nitride (e.g., AlGaN spacer layer 582) disposed between the second Group III nitride (e.g., GaN channel layer 8) and the polarity inversion layer (e.g., Al polarity inversion layer 12) in the semiconductor device according to the first embodiment.

[0158] The fifth III-nitride (e.g., AlGaN spacer layer 582) has a fifth lower surface 20e which is a (0 0 0 1) plane, a fifth upper surface 22e which is a (0 0 0 -1) plane and disposed above the fifth lower surface 20e, and a bandgap wider than the bandgap of the second III-nitride (e.g., GaN channel layer 8).

[0159] However, the fifth group III nitride is a mixed crystal of AlN, which has the widest band gap among group III nitrides, and other group III nitrides (i.e., GaN and InN). Specifically, the fifth group III nitride is any of InAlGaN, AlGaN, InAlN, and AlN. That is, the fifth group III nitride is In x5 Al y5 Ga 1-x5-y5 N(0≦x5≦1-y5, 0 <y5≦1)である。

[0160] The semiconductor device according to the second embodiment has a fifth group III nitride (i.e., spacer layer) between the second group III nitride (i.e., channel layer) and the polarity inversion layer, thereby suppressing scattering of two-dimensional electron gas due to crystal defects (i.e., crystal disorder) in the polarity inversion layer. Therefore, the semiconductor device according to the second embodiment improves the mobility of the second group III nitride (i.e., channel layer).

[0161] Although the embodiments of the present invention have been described above, the first and second embodiments are merely illustrative and not limiting. For example, the semiconductor device according to the first and second embodiments is a transistor having a Schottky gate structure. However, the semiconductor device of the present invention may also be a transistor having an MIS (Metal-Insulator-Semiconductor) gate structure.

[0162] The semiconductor devices according to the first and second embodiments are normally-on transistors. However, the semiconductor device of the present invention may be, for example, a normally-off transistor having a p-type GaN layer between the cap layer and the gate electrode. Alternatively, the semiconductor device according to the first and second embodiments may be a normally-off transistor in which the cap layer is thinned directly under the gate electrode.

[0163] The semiconductor devices according to the first and second embodiments are transistors. However, the semiconductor device according to the present invention may be another semiconductor device, such as a gated anode diode. A gated anode diode is a diode obtained by connecting the gate electrode of a normally-off transistor to the drain electrode.

[0164] The layer structure of each electrode described in the first and second embodiments is merely an example, and each electrode may have other layer structures, whether single-layer or multi-layer. Furthermore, the method of forming each electrode described in the first and second embodiments is merely an example, and any other method may be used to form each electrode. For example, if ohmic characteristics are obtained, the heat treatment in the process of forming the source and drain electrodes may be omitted. Similarly, if Schottky characteristics are obtained, the gate electrode material may be heated.

[0165] The following additional notes are disclosed regarding the above-described first and second embodiments.

[0166] (Appendix 1) A group III nitride on a substrate or a substrate, the first AlN having a first lower surface which is a (0 0 0 1) plane and a first upper surface which is a (0 0 0 -1) plane and is disposed above the first lower surface; a second lower surface that is a (0 0 0 1) plane; a second upper surface that is a (0 0 0 -1) plane and is disposed above the second lower surface; and a second Group III nitride having a band gap narrower than the band gap of AlN and disposed on or above the first AlN; a third lower surface that is a (0 0 0 -1) plane; a third upper surface that is a (0 0 0 1) plane and is disposed above the third lower surface; and a third Group III nitride having a band gap wider than a band gap of the second Group III nitride and disposed above the second Group III nitride; The second group III nitride is In x2 Al y2 Ga 1-x2-y2 N(0≦x2≦1-y2, 0≦y2<1), The third group III nitride is In x3 Al y3 Ga 1-x3-y3 N(0≦x3≦1-y3, 0 <y3≦1)であり、 A plurality of quantum levels are formed in the conduction band of the second Group III nitride. Semiconductor device.

[0167] (Appendix 2) a polarity inversion layer having a lower surface and an upper surface disposed above the lower surface and disposed between the second Group III nitride and the third Group III nitride; The polarity inversion layer is a layer in which a group III nitride having a bottom surface that is a (0 0 0 -1) plane grows so that the bottom surface is in contact with the top surface. 2. The semiconductor device according to claim 1,

[0168] (Appendix 3) the fourth lower surface being a (0 0 0 1) plane; a fourth upper surface being a (0 0 0 -1) plane and disposed above the fourth lower surface; and a fourth Group III nitride having a bandgap wider than that of the second Group III nitride and narrower than that of AlN and disposed between the first AlN and the second Group III nitride; The fourth group III nitride is In x4 Al y4 Ga 1-x4-y4 N(0≦x4≦1-y4, 0 <y4≦1)であることを Characterized by 3. The semiconductor device according to claim 1 or 2.

[0169] (Appendix 4) The second group III nitride is In x2 Al y2 Ga 1-x2-y2 N(0≦x2≦0.4, 0≦y2≦0.6), The third group III nitride is In x3 Al y3 Ga 1-x3-y3 N(0≦x3≦0.2, 0.4≦y3≦1-x3) 3. The semiconductor device according to claim 1 or 2.

[0170] (Appendix 5) the fifth lower surface being a (0 0 0 1) plane; a fifth upper surface being a (0 0 0 -1) plane and disposed above the fifth lower surface; and a fifth Group III nitride having a band gap wider than a band gap of the second Group III nitride and disposed between the second Group III nitride and the polarity inversion layer; The fifth group III nitride is In x5 Al y5 Ga 1-x5-y5 N(0≦x5≦1-y5, 0 <y5≦1)であることを 3. The semiconductor device according to claim 2,

[0171] (Appendix 6) The second group III nitride has a thickness of 5 nm or more and 20 nm or less. 3. The semiconductor device according to claim 1 or 2.

[0172] (Appendix 7) The thickness of the first AlN is 200 nm or more. 3. The semiconductor device according to claim 1 or 2.

[0173] (Appendix 8) The semiconductor device further comprises a drain electrode through which a current flowing in the second group III nitride passes before entering the second group III nitride, a source electrode through which the current passes after exiting the second group III nitride, and a gate electrode for controlling the flow of the current. 3. The semiconductor device according to claim 1 or 2.

[0174] (Appendix 9) The polarity inversion layer is an Al film having a thickness of 2 to 4 atomic layers. 3. The semiconductor device according to claim 2,

[0175] (Appendix 10) a first step of growing a second Group III nitride on or above the (0 0 0 -1) plane of the first AlN, the second lower surface being a (0 0 0 1) plane, a second upper surface being a (0 0 0 -1) plane and disposed above the second lower surface, and the second upper surface having a band gap narrower than the band gap of AlN; a second step of growing, after the first step, a polarity inversion layer on or above the second Group III nitride, the polarity inversion layer having a lower surface and an upper surface disposed above the lower surface; a third step of growing, after the second step, a third Group III nitride on the polarity inversion layer, the third lower surface being a (0 0 0 -1) plane, a third upper surface being a (0 0 0 1) plane and disposed above the third lower surface, and the third Group III nitride having a band gap wider than a band gap of the second Group III nitride; The second group III nitride is In x2 Al y2 Ga 1-x2-y2 N(0≦x2≦1-y2, 0≦y2<1), The third group III nitride is In x3 Al y3 Ga 1-x3-y3 N(0≦x3≦1-y3, 0 <y3≦1)であり、 The polarity inversion layer is a material on which a group III nitride having a (0 0 0 -1) plane in contact with the upper surface grows. A method for manufacturing a semiconductor device. [Explanation of symbols]

[0176] 2: Semiconductor device 6: AlN substrate 8: GaN channel layer 10: AlN cap layer 12: Al polarity inversion layer 14: Source electrode 16: Drain electrode 18: Gate electrode 20: Bottom surface 20a: 1st bottom surface 20b: 2nd bottom surface 20c: 3rd bottom surface 20d: 4th bottom surface 20e: The 5th below 22: Above 22a: The first one above 22b: The second one above 22c: The 3rd one 22d: The 4th one 22e: The 5th one 582:AlGaN スペーサ layer

Claims

1. A group III nitride on a substrate or a substrate, the first AlN having a first lower surface which is a (0 0 0 1) plane and a first upper surface which is a (0 0 0 -1) plane and is disposed above the first lower surface; a second lower surface that is a (0 0 0 1) plane; a second upper surface that is a (0 0 0 -1) plane and is disposed above the second lower surface; and a second Group III nitride having a band gap narrower than the band gap of AlN and disposed on or above the first AlN; a third lower surface that is a (0 0 0 -1) plane; a third upper surface that is a (0 0 0 1) plane and is disposed above the third lower surface; and a third Group III nitride having a band gap wider than a band gap of the second Group III nitride and disposed above the second Group III nitride, The second group III nitride is In x2 Al y2 Ga 1-x2-y2 N (0≦x2≦1-y2, 0≦y2<1), The third group III nitride is In x3 Al y3 Ga 1-x3-y3 N (0≦x3≦1-y3, 0<y3≦1), A plurality of quantum levels are formed in the conduction band of the second Group III nitride. Semiconductor device.

2. a polarity inversion layer having a lower surface and an upper surface disposed above the lower surface, the polarity inversion layer being disposed between the second Group III nitride and the third Group III nitride; The polarity inversion layer is a layer in which a group III nitride having a bottom surface that is a (0 0 0 -1) plane grows so that the bottom surface is in contact with the top surface.

2. The semiconductor device according to claim 1.

3. the fourth lower surface being a (0 0 0 1) plane; a fourth upper surface being a (0 0 0 -1) plane and disposed above the fourth lower surface; and a fourth Group III nitride having a bandgap wider than that of the second Group III nitride and narrower than that of AlN, the fourth Group III nitride being disposed between the first AlN and the second Group III nitride; The fourth group III nitride is In x4 Al y4 Ga 1-x4-y4 N (0≦x4≦1-y4, 0<y4≦1) 3. The semiconductor device according to claim 1 or 2.

4. The second group III nitride is In x2 Al y2 Ga 1-x2-y2 N (0≦x2≦0.4, 0≦y2≦0.6), The third group III nitride is In x3 Al y3 Ga 1-x3-y3 N (0≦x3≦0.2, 0.4≦y3≦1-x3) 3. The semiconductor device according to claim 1 or 2.

5. the fifth lower surface being a (0 0 0 1) plane; a fifth upper surface being a (0 0 0 -1) plane and disposed above the fifth lower surface; and a fifth Group III nitride having a band gap wider than a band gap of the second Group III nitride and disposed between the second Group III nitride and the polarity inversion layer; The fifth group III nitride is In x5 Al y5 Ga 1-x5-y5 N (0≦x5≦1-y5, 0<y5≦1) 3. The semiconductor device according to claim 2.

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