Semiconductor device

Abstract

To reduce leakage current flowing along a trench in a semiconductor element in which trench isolation is used.SOLUTION: There is provided a semiconductor device in which a first semiconductor region 12 of a first conductivity type and a second semiconductor region 13 of a second conductivity type locally formed on a surface side of the first semiconductor region 12 are formed on an embedded layer 11 of the first conductivity type having a higher concentration than the first semiconductor region 12, and a trench T penetrating the first semiconductor region 12 and the embedded layer 11 in a film thickness direction is formed at a portion of the first semiconductor region 12 where the second semiconductor region 13 is not formed. In the trench T, a conductive trench inner conductive layer 27 is formed in a floating state from surroundings by a trench inner oxide film 26 that is an insulating layer formed on an inner surface of the trench T. In the first semiconductor region 12, a third semiconductor region 15 of the first conductivity type having a higher concentration than the first semiconductor region 12 is formed so as to be in contact with a side surface of the trench T.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device using a trench element isolation structure. [Background technology]

[0002] A trench structure is known as an element isolation structure in a semiconductor substrate on which semiconductor elements are formed. Patent Document 1 describes a lateral bipolar transistor (semiconductor device) having this structure.

[0003] 6 is a cross-sectional view showing, in simplified form, a part of the structure of the semiconductor device 9. The semiconductor device 9 is formed using a silicon substrate, and in the bottom layer in FIG. 6, a high-concentration (low-resistance) n-type semiconductor layer is formed to reduce the collector resistance. + On the layer 81, a collector layer is formed. - Layer 82 is formed. - On the surface of the layer 82, a p-layer 83 serving as a base is formed, and within this, an n-type layer 84 serving as an emitter is formed. + On the surface, a LOCOS oxide film 91 is formed by locally oxidizing a portion of the surface on the semiconductor layer side to a thicker thickness, and an oxide film layer 92 is formed, which is made of a silicon oxide film that covers the surface more thinly in the region where the LOCOS oxide film 91 is not formed. - A collector electrode 93 connected to the p-layer 82, a base electrode 94 connected to the p-layer 83, and an n + The layer 84 and the emitter electrode 95 connected thereto are formed. + The lower side of layer 81 is a p-layer that serves as the substrate, or a silicon oxide layer if an SOI substrate is used, but these are not shown in Figure 6. In reality, high-concentration layers of the same conductivity type as each layer are locally formed at the locations where each layer and each electrode directly contact each other, but these are not shown. With the above structure, semiconductor device 9 functions as a bipolar transistor using collector electrode 93, base electrode 94, and emitter electrode 95.

[0004] In reality, multiple bipolar transistors with the above configuration are formed on a single semiconductor substrate, so in Figure 6, trench isolation structures are used on both sides of the above structure for element isolation. + A trench T is formed in the trench 81, and a polycrystalline silicon layer (inner trench conductive layer) 97 is formed therein via a thin trench oxide film (inner trench oxide layer) 96. This structure allows the trench T to be filled without gaps, and if the polycrystalline silicon layer 97 is heavily doped to make it conductive, its potential becomes constant, thereby maintaining a constant potential on the wall surface of the trench T and enabling stable device isolation. Although a constant potential may be applied to the polycrystalline silicon layer 97 from the outside, the polycrystalline silicon layer 97 is often left floating. Furthermore, when using the trench T to perform device isolation, it is necessary to fill the entire interior of the trench T. However, since it is not easy to fill the trench T with only a silicon oxide film, polycrystalline silicon may be used instead. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 3659186 Summary of the Invention [Problem to be solved by the invention]

[0006] When the above structure is off (or when no main current is flowing), the p-layer 83 and n-layer - The trench oxide film 96 and the n - The depletion layer also spreads from the interface with the polysilicon layer 97 and the n - As the potential difference between layer 82 increases, n -The electric field strength in layer 82 increases, and holes gather near trench T. At least some of these holes flow along trench T and are more likely to reach p-layer 83 through the depletion layer. These holes flow into p-layer 83, which serves as the base, and the leakage current of the bipolar transistor increases. In FIG. 6, if the distance between trench T and the base (p-layer 83) is increased, this leakage current decreases, but in this case the device area increases.

[0007] For this reason, it has been desired to reduce the leakage current that flows along the trench in semiconductor devices that use trench isolation.

[0008] The present disclosure has been made in consideration of these problems, and aims to provide an invention that solves the above problems. [Means for solving the problem]

[0009] In order to solve the above problems, the present disclosure has the following configuration. The present disclosure relates to a semiconductor device in which a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type formed locally on the surface side of the first semiconductor region are formed on a buried layer of the first conductivity type that has a higher concentration than the first semiconductor region, and a trench is formed in a location in the first semiconductor region where the second semiconductor region is not formed, penetrating the first semiconductor region and the buried layer in a film thickness direction, wherein a conductive trench conductive layer is formed within the trench in a floating state from the surroundings by a trench oxide film that is an insulating layer formed on the inner surface of the trench, and a third semiconductor region of the first conductivity type that has a higher concentration than the first semiconductor region is formed within the first semiconductor region so as to be in contact with the side surface of the trench. The third semiconductor region may be formed continuously over the entire area in the thickness direction of the first semiconductor region. The buried layer may be formed on the substrate semiconductor layer of the second conductivity type, and the bottom surface of the trench may reach the substrate semiconductor layer. In a plan view, the trench may be formed to surround the first semiconductor region, and the third semiconductor region may be formed along at least a portion of the trench in a depth direction. The third semiconductor region may be part of a current path of a semiconductor element. [Effects of the Invention]

[0010] Since the present disclosure is configured as described above, it is possible to reduce leakage current that flows along trenches in semiconductor devices that use trench isolation. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a diagram showing a simplified planar structure of a semiconductor device according to an embodiment of the present invention; [Figure 3] 5A to 5C are cross-sectional views showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention. [Figure 4] FIG. 2 is a cross-sectional view showing the structure of a first modified example of the semiconductor device according to the embodiment of the present invention. [Figure 5] FIG. 10 is a simplified view showing a part of a planar structure of a second modified example of the semiconductor device according to the embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view showing the structure of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0012] A semiconductor device according to an embodiment of the present invention will be described below. First, the cause of the leakage current occurring in the structure of FIG. 6 will be described. For example, when the lower substrate (not shown in FIG. 6) of the structure of FIG. 6 is set to ground potential, the collector electrode 93 is set to +100 V, the base electrode 94 is set to +60 V, and the emitter electrode 95 is set to +59.4 V, n - A depletion layer extends from the pn junction at the interface between layer 82 (collector) and p-layer 83 (base).

[0013] At this time, if the polycrystalline silicon layer 97 in the trench T is in a floating state, no potential is directly applied to it. However, in the structure of FIG. 6, the potential of the polycrystalline silicon layer 97 is determined by the capacitive coupling with each semiconductor region around the trench T, and under the above conditions, this potential is, for example, about +50 V. In this state, the region A(n + The n layer 81 and the trench T (trench oxide film 96) - In the region of layer 82), n - The corners of the layer 82, especially the n + Since the layer 81 has a high concentration, the electric field strength in the depletion layer is high (the band structure is bent more and more densely), and holes tend to be generated, as in the strong inversion state in a MOS structure. - This situation is relatively unlikely to occur in the region near the top of the trench T in the layer 82 and region B (between region A and region C).

[0014] In the case of the potential distribution described above, n - The potential difference between the layer 82 and the polycrystalline silicon layer 97 is large, and the region B(n - An inversion state occurs in the region B (the sidewall of trench T in layer 82). As a result, region B becomes a channel through which the holes flow, and the holes flow upward along the sidewall of trench T. When the depletion layer in region C expands laterally and becomes conductive, holes flow toward p-layer 83. This results in leakage current.

[0015] In the following drawings, identical or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the length ratios of each part, and other characteristics may differ from those of the actual product. Therefore, specific dimensions should be determined by taking into consideration the following description. It goes without saying that the dimensional relationships and ratios of parts differ between the drawings. The following embodiments are merely examples of devices embodying the technical concept of this invention, and the technical concept of this invention does not limit the shape, structure, or arrangement of the components to those described below. Various modifications may be made to the embodiments of this invention within the scope of the claims. In this invention, terms such as "top" and "bottom" are used for convenience of description. Even if a device is provided on a side surface, it is within the scope of the present invention as long as it is substantially identical to the constituent features of this invention. Furthermore, "top" includes not only cases where the device is formed in contact with the object, but also cases where the device is formed via another layer. Furthermore, in the present invention, "connection" is not limited to direct connection, and even if a connection is made via an intervening resistor or other element, it falls within the scope of the present invention as long as it is substantially the same as the constituent elements of the present invention.

[0016] 1 is a cross-sectional view showing the structure of a semiconductor device 1 according to an embodiment of the present invention. This semiconductor device 1 is a bipolar transistor using an element isolation structure with a trench T, similar to the semiconductor device 9 described above, and only the structure of a single bipolar transistor and the portion corresponding to the surrounding element isolation structure is shown here. Therefore, similar to the semiconductor device 9 described above, + Layer (buried layer) 11, which becomes the collector layer - layer (first semiconductor region) 12, a p-layer (second semiconductor region) 13 serving as the base, and an n-layer (first semiconductor region) 14 serving as the emitter. + A layer 14 is formed, and a LOCOS oxide film 21 and an oxide film layer 22 are formed on the surface. - A collector electrode 23 connected to the layer 12, a base electrode 24 connected to the p layer 13, and an n +The layer 14 and the emitter electrode 25 connected thereto are formed. + Layer 11 is the collector layer. - It has a sufficiently lower resistance (higher impurity concentration) than the layer 12. + Below layer 11 is a p-layer that serves as the substrate, or a silicon oxide layer if an SOI substrate is used, but this is not shown in FIG.

[0017] 1, for element isolation, trenches T are formed on both sides of the above structure, with conductive polycrystalline silicon layers (inner-trench conductive layers) 27 formed therein via thin trench oxide films (inner-trench oxide films) 26. Polycrystalline silicon layer 27 is not connected to at least any of collector electrode 23, base electrode 24, and emitter electrode 25, and is in a floating state.

[0018] Here, in FIG. 1, n on both sides of the groove T - In the layer 12, a thin n + A layer (third semiconductor region) 15 is formed. + Layer 15 is n + As with layer 11, n - It has a higher impurity concentration than layer 12. + The layer 15 maintains the n-type potential even when the potential of the polycrystalline silicon layer 27 becomes more negative than the collector potential. - Inversion is less likely to occur in the p-layer 13 than in the layer 12. This suppresses holes from flowing upward along the sidewalls of the trench T. It also reduces the possibility of a conduction state in the region C due to the lateral expansion of the depletion layer. As a result, holes are prevented from flowing into the p-layer 13, and the leakage current can be reduced.

[0019] In addition, n + The impurity concentration in layer 15 may be constant or may vary in the depth direction. + The impurity concentration in the deep part of the layer 15 is n + By increasing the impurity concentration of the layer 15 to a level higher than that of the shallow portion, holes flowing upward along the sidewall of the trench T are further suppressed, thereby reducing the leakage current.+ The layer 15 is formed from the top of the trench T to the n + The grooves 11 are formed so as to reach the layer 11, but may be formed partially along the side surfaces of the grooves T. For example, the grooves 11 may be provided in at least one of the regions A, B, and C in FIG.

[0020] FIG. 2 is a diagram showing a schematic planar structure in which bipolar transistors having the structure shown in FIG. 1 are arranged. - layer 12, p layer 13, n + Layer 14, n + 1 shows only the planar structure of the layer 15 and the trench T, and the trench oxide film 26 and polycrystalline silicon layer 27 in the trench T are omitted. The structure in FIG. 1 corresponds to the cross section in the DD direction in FIG. 2, and the element region X in FIG. 1 is the region surrounded by the trench T.

[0021] As shown here, each element region X is a region between the trenches T, and the outermost periphery of the element region X is the thin n + Layer 15 is made up of 15 layers. + 2, bipolar transistors having a common structure are two-dimensionally arranged in the element region X, but semiconductor elements other than bipolar transistors may be formed in at least a part of the element region X. Such other semiconductor elements include, for example, n + There are diodes in which the layer 14 and the emitter electrode 25 are not provided.

[0022] Next, n + The method for forming the layer 15 will be described with reference to the cross-sectional process diagrams of FIG. 3. As described above, in practice, in FIG. + A p-layer or an oxide film layer is provided below the layer 11, but here it is assumed that a p-layer (substrate semiconductor layer) 16 is provided.

[0023] As shown in FIG. 3(a), the p-layer 16, n + Layer 11, n -A trench T is formed in the stacked structure of the layer 12. This process is performed by dry etching silicon through an opening formed in a mask 100, which is made of a stacked structure of, for example, photoresist, a thick CVD oxide film, a silicon nitride film, etc. Here, the bottom of the trench T and the n + Although the interface between the layer 11 and the p-layer 16 is described as being coincident, from the viewpoint of element isolation, it is not necessary for them to actually be coincident. + It is sufficient that the layer 11 is penetrated and reaches the p-layer 16 .

[0024] Next, as shown in FIG. 3(b), boron (B) or the like is ion-implanted to act as an acceptor, thereby forming p + A layer 16A is formed. In this case, the incident angle of the B ions is set to approximately 0° (perpendicular to the semiconductor substrate surface).

[0025] Next, as shown in FIG. 3(c), the donor element (ion species) is ion-implanted by increasing the incident angle to, for example, 30° to 40°. - The layer 12 has a portion along the side of the groove T, n + At this time, the bottom of the trench T is provided with a p + Since the layer 16A is formed, an n layer is not formed at the bottom of the trench T, and element isolation is performed appropriately. + Since the layer 11 has a high impurity concentration in advance, the n-type ions on the right side of the trench T are substantially implanted by this ion implantation. + Layer 11 and the n on the left side of the groove T + In FIG. 3(c), the influence of conduction between the n + Layer 15 is n - Although it is assumed that the layer 12 is formed only in the + Impurities are also implanted into the layer 11. As mentioned above, when an SOI substrate is used, n + The layer 11 is provided with a silicon oxide layer instead of the p-layer 16, but in this case the p + Layer 16A (FIG. 3(b)) is not required.

[0026] Here, in order not to affect the operation of the bipolar transistor, + The thickness of the layer 15 in the lateral direction is preferably small, 4 μm or less. For this purpose, it is particularly preferable to use, as the ion species, As and Sb, which have a small diffusion coefficient among the elements that serve as donors. By using an element with a small diffusion coefficient, a deep and narrow n + A layer 15 can be formed.

[0027] Thereafter, the mask 100 is removed to obtain the structure shown in FIG. 3(d), and then, as shown in FIG. 3(e), a trench oxide film 26 and a polycrystalline silicon layer 27 are sequentially formed inside the trench T. This process is the same as that for manufacturing the conventional semiconductor device 9. Note that the activation process after the ion implantation (FIGS. 3(b) and 3(c)) is performed in the same manner as the activation process for the other layers (n + As with layer 14, this is done as appropriate after implantation.

[0028] As mentioned above, n in Figure 1 + The layer 15 can be formed by performing oblique ion implantation (FIG. 3(c)) especially after the formation of the trench T. + Forming layer 15 or further p + The steps other than forming the layer 16A are the same as those for manufacturing the semiconductor device 9 of FIG.

[0029] Next, a description will be given of the structure of a semiconductor device 2, which is a modification of the semiconductor device 1. Fig. 4 is a cross-sectional view showing the structure of the semiconductor device 2 in correspondence with Fig. 1. In this structure, n + Layer 15 is n - Not only along the side of the trench T in the layer 12, but also + In contact with layer 11, n - The layer 12 has a surface area adjacent to the groove T. + As the layer 15A, the n of the side of the groove T + It is formed in connection with layer 15 .

[0030] In this case, the same n as above + The effect of layer 15 is obtained, and the n of the surface connected to it + The layer 15A is connected to the collector electrode 23. + n through layer 15 + The collector resistance can be further reduced without increasing the chip area. + By providing layer 15, the collector resistance can be further reduced.

[0031] n + Layer 15A is actually n + 4 can be formed simultaneously with the n-type layer 14 in the manufacturing process of the semiconductor device 1 shown in FIG. + It can be easily manufactured by simply changing the mask used to form the layer 14 .

[0032] 5 is a diagram corresponding to FIG. 2, showing a planar structure of a semiconductor device 3 which is a further modified example (second modified example) of the above-mentioned semiconductor device. In this example, a trench T and an n + In addition to the layer 15, the n + The p-layer (substrate semiconductor layer) 16 below the layer 11 is exposed.

[0033] For example, n + Layer 15 is formed, and n + A trench T is formed so as to surround the layer 15, and the trench T has n + In the adjacent element region X (upper right in the drawing), a layer 15 is formed. + Layer 15 is formed, and n + A trench T is formed so as to surround the layer 15, and the trench T has n +In this case, the upper left trench T and the upper right trench T in the figure are spaced apart from each other, and a p-layer (substrate semiconductor layer) 16 is formed between the trenches T. A further p-layer may be provided on the p-layer (substrate semiconductor layer) 16 between these trenches T. In this case, two spaced trenches T (and n + Since the p-layer is sandwiched between the layers 15, these semiconductor elements are more reliably separated.

[0034] In the above example, a bipolar transistor is formed in the element region X. However, the element formed in the element region X may have a well-known semiconductor element structure such as a diode or an IGBT. In the case of a diode, for example, + This results in a structure without the layer 14 and the emitter electrode 25. Even in this case, it is clear that the flow of holes along the groove T as described above causes a leakage current in the diode. + It is clear that providing a layer (third semiconductor region) is effective.

[0035] In the above example, as shown in FIGS. 2 and 5, the grooves T and n + The layer (third semiconductor region) 15 is formed to surround the entire periphery of each element region X. However, the shape of the trench T is appropriately set depending on the configuration of each layer in the element region, and the trench may be formed only in a part of the periphery of the element region as long as sufficient element isolation characteristics are obtained.

[0036] In addition, if the leakage current path is concentrated in one region of the trench in plan view, the third semiconductor region may be provided only in this region. For example, in FIG. 1, the n-type semiconductor region may be provided only on the side wall of the trench T on the right side where the distance between the trench T and the p-type layer 13 is short. + The layer 15 is provided on the side wall of the left trench T where the distance between the trench T and the p-layer 13 is relatively large. + It is not necessary to provide the layer 15. In other words, it is not necessary to form the trench and the third semiconductor region so as to surround the entire periphery of the element region.

[0037] Also, in Figure 1 etc., n + The layer (third semiconductor region) 15 is formed along the trench T. - The third semiconductor region is formed continuously over the entire area along the thickness direction of the layer (first semiconductor region) 12. However, from the viewpoint of blocking the path of the leakage current, a sufficient effect can be obtained even if the third semiconductor region is formed only in a partial area along the thickness direction of the first semiconductor region. However, according to the manufacturing method of FIG. 3, the third semiconductor region is formed over the entire area of ​​the trench T in a plan view and - The layer (first semiconductor region) 12 is easily n + A layer (third semiconductor region) 15 can be formed.

[0038] In the above example, the collector layer and emitter layer are n-type (first conductivity type) and the base layer is p-type (second conductivity type). However, even if these conductivity types are reversed, the conduction of electrons along the grooves can be suppressed, and it is clear that the above configuration is effective. [Explanation of symbols]

[0039] 1 to 3, 9 Semiconductor device 11, 81 n + Layer (embedding layer) 12, 82n - layer (first semiconductor region) 13, 83 p layer (second semiconductor region) 14, 84 n + layer 15n + layer (third semiconductor region) 16 p-layer (substrate semiconductor layer) 16A p + layer 21, 91 LOCOS oxide film 22, 92 Oxide layer 23, 93 Collector electrode 24, 94 base electrodes 25, 95 Emitter electrode 26, 96 Trench oxide film (in-groove oxide film) 27, 97 Polycrystalline silicon layer (in-trench conductive layer) 100 masks T-groove (trench) X element area

Claims

1. a semiconductor device including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type opposite to the first conductivity type, which is formed locally on a surface side of the first semiconductor region, formed on a buried layer of the first conductivity type having a higher concentration than the first semiconductor region, and a trench penetrating the first semiconductor region and the buried layer in a film thickness direction in a location in the first semiconductor region where the second semiconductor region is not formed, A conductive in-groove conductive layer is formed in the groove in a floating state from the surroundings by an in-groove oxide film, which is an insulating layer formed on the inner surface of the groove, A semiconductor device comprising: a third semiconductor region of the first conductivity type having a higher concentration than the first semiconductor region; and a third semiconductor region formed in the first semiconductor region so as to contact a side surface of the trench.

2. 2. The semiconductor device according to claim 1, wherein the third semiconductor region is formed continuously over the entire area of ​​the first semiconductor region in the thickness direction.

3. 3. The semiconductor device according to claim 1, wherein the buried layer is formed on the substrate semiconductor layer of the second conductivity type, and the bottom surface of the groove reaches the substrate semiconductor layer.

4. 3. The semiconductor device according to claim 1, wherein, in a plan view, the trench is formed to surround the first semiconductor region, and the third semiconductor region is formed along at least a portion of the trench in a depth direction.

5. 3. The semiconductor device according to claim 1, wherein the third semiconductor region forms a part of a current path of a semiconductor element.

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