Fibonacci-type high step-up DC-DC converter

Abstract

To provide a new Fibonacci-type high step-up DC-DC converter.SOLUTION: A power conversion circuit includes a first-stage circuit on an input side and a second-stage circuit on an output side. The power conversion circuit operates in the order of a first operation mode (1), a second operation mode (2), a first operation mode (3), and a third operation mode (4). In the first operation mode (1), a first capacitor and an inductance of the first stage and a second inductor of the second stage are charged from a power supply terminal, in the second operation mode (2), energy charged into the first capacitor and the inductance of the first stage is charged into a second capacitor and an inductance of the second stage, in the first operation mode (3), the first capacitor and the inductance of the first stage and the second inductor of the second stage are charged from the power supply terminal, and in the third operation mode (4), energy charged into the second capacitor and the second inductor of the second stage is output to an output terminal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power conversion circuit, and in particular to a Fibonacci type high boost DC-DC converter that can be used in PV (Photovoltaic Cell: solar cell) and FC (Fuel Cell: fuel cell) that require high boost. [Background technology]

[0002] There is a trend towards greater decentralization of power supply. The DC bus voltage of DC microgrids used in distributed power sources is 400V. Mega solar power plants, which gain voltage by connecting PV panels in series, require a large site area and are not suitable for distributed power supply. A high-step-up DC-DC converter is required that can connect even a single PV panel (20V) to a DC microgrid. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] P. Kumar, et al.: “Z-Network Plus Switched-Capacitor Boost DC-DC Converter,” IEEE J. Emerging and Selected Topics in Power Electron. 9 (2021) 791 (DOI: 10.1109 / JESTPE.2019.2959078) [Non-patent document 2] R. Rahimi, et al.: “Z-Source-Based High Step-Up DC-DC Converters for Photovoltaic Applications,” IEEE J. Emerging and Selected Topics in Power Electronics, 10 (2022) 4738 (DOI: 10.1109 / JESTPE.2021.3131996). [Non-patent document 3] Alzahrani, et al.: “A Family of Scalable Non-Isolated Interleaved DC-DC Boost Converters With Voltage Multiplier Cells,” IEEE Access 7 (11707) (DOI: 10.1109 / ACCESS.2019.2891625). Summary of the Invention [Problem to be solved by the invention]

[0004] One aspect of the present invention aims to provide a high-step-up DC-DC converter with a new configuration that can solve the technical problems described above and can connect even a single PV panel (20V) to a DC microgrid (400V). [Means for solving the problem]

[0005] According to one aspect of the present invention, A power conversion circuit comprising a first stage circuit on the input side and a second stage circuit on the output side, the power conversion circuit operates in the order of a first operation mode (1), a second operation mode (2), a first operation mode (3), and a third operation mode (4); In the first operation mode (1), the first capacitor and inductance of the first stage and the second inductor of the second stage are charged from the input power terminal; In the second operation mode (2), the energy stored in the first capacitor and inductance of the first stage is stored in the second capacitor and inductance of the second stage, In the first operation mode (3), the first capacitor and inductance of the first stage and the second inductor of the second stage are charged from the input power terminal; In the third operation mode (4), the energy stored in the second capacitor and the second inductor of the second stage is output to an output terminal. [Effects of the Invention]

[0006] The power conversion circuit of the present invention can reduce the number of elements, thereby providing technical effects such as a reduced mounting area, reduced costs, and improved reliability.

[0007] Other objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 shows the circuit proposed in this embodiment. [Figure 2] FIG. 2 shows a timing chart used in the proposed circuit of this embodiment. [Figure 3(a)] FIG. 3(a) shows the operation of each state in the proposed circuit of this embodiment. [Figure 3(b)] FIG. 3(b) shows the operation of each state in the proposed circuit of this embodiment. [Figure 3(c)] FIG. 3(c) shows the operation of each state in the proposed circuit of this embodiment. [Figure 3(d)] FIG. 3(d) shows the operation of each state in the proposed circuit of this embodiment. [Figure 4] FIG. 4 shows the simulation results of the circuit proposed in this embodiment. [Figure 5] Figure 5 shows the simulation results of the output voltage and input voltage. [Figure 6(a)] Figure 6(a) shows the simulated waveforms of the inductor current IL1, the voltage at node X (VX), the inductor current IL2, and the interleaved clocks S11 and S12. [Figure 6(b)] Figure 6(b) shows the simulated waveforms of the voltage at node Y (VY), the voltage at node A (VA), the voltage at node B (VB), and the interleaved clocks S11 and S12. [Figure 7] FIG. 7 shows the theoretical CR (calculated results (Calc.) of Equation (8)) and simulation results (Sim.) of the output voltage Vo when D is changed from 0.5 to 0.9. [Figure 8] FIG. 8 shows a timing chart of the complementary clocks. [Figure 9] Figure 9 shows a photograph of a prototype with a volume size of 125 mm (L) × 100 mm (W) × 43 mm (H). [Figure 10] FIG. 10 shows a block diagram of the measurement setup of FIG. [Figure 11] FIG. 11 shows the measurement results for the setup of FIGS. [Figure 12] FIG. 12 shows the measured output voltage Vo versus duty cycle D along with the calculated gain as a dotted line. [Figure 13] FIG. 13 shows an application example using the power conversion circuit of this embodiment, and shows in block diagram an example of application to a distributed power supply network such as a so-called picogrid (synonymous with a DC microgrid). DETAILED DESCRIPTION OF THE INVENTION

[0009] Figure 1 shows the proposed circuit of this example. In Figure 1, Vg is the input voltage, Vo is the output voltage, D3 is the output diode, Co is the output capacitor (load capacitance), and Ro is the output load resistance. Stage 1 and Stage 2 have the same configuration and are cascade-connected. Stage 1 and Stage 2 are connected in series. In each stage, an inductor is used instead of the switches found in the stages of a conventional Fibonacci converter. Note that if L1 and L2 in Figure 1 are replaced with transistor switches, it becomes a typical X3 Fibonacci converter.

[0010] Figure 2 shows the timing chart used in the proposed circuit of this embodiment. This circuit operates with an interleaved clock. Furthermore, this circuit has three operating modes (operating mode 1, operating mode 2, and operating mode 3), and the converter state changes in the order of (1), (2), (3), and (4). In operating mode 1 (1), transistors M1 and M2 are ON. In operating mode 2 (2), M1 is OFF and M2 is ON. In operating mode 1 (3), transistors M1 and M2 are ON. In operating mode 3 (4), M1 is ON and M2 is OFF. Because M1 and M2 are interleaved, the M2 clock is 180 degrees out of phase with the M1 clock. Because the input voltage of Stage 1 is a constant voltage Vg, the inductor current IL1 changes in a triangular waveform. Meanwhile, the input voltage (VX) of Stage 2 changes in a stepped manner, so the inductor current IL2 changes piecewise linearly. As VX increases in a step-like manner, the slope of IL2 increases and the energy stored in L2 also increases. Here, IL1 is the current flowing through inductor L1, VX is the voltage at node X, and IL2 is the current flowing through inductor L2.

[0011] Figures 3(a) to 3(d) show the operation of each state in the proposed circuit of this embodiment. The operation modes of this embodiment correspond to the four phases ((1), (2), (3), and (4)) in Figure 2. Figure 3(a) shows operation mode 1 (1), in which M1 and M2 are ON. Figure 3(b) shows operation mode 2 (2), in which M1 is OFF and M2 is ON. Figure 3(c) shows operation mode 1 (3), in which M1 and M2 are ON. Figure 3(d) shows operation mode 3 (4), in which M1 is ON and M2 is OFF. The circuit operates in continuous current mode (CCM).

[0012] Below, the operation modes 1(1), 2(2), 1(3), and 3(4) will be explained in this order.

[0013] Figure 3(a) shows the equivalent circuit for operating mode 1(1). In this mode, transistors M1, M2, and D1 are ON. Diodes D2 and D3 are negative and OFF. Inductor currents IL1 and IL2 increase at the start of this mode. Capacitor voltage C1 is charged to Vg, and C2 maintains the Vg(2-D) / (1-D) charged in the previous operating mode 2. Nodes X and Y are Vg and Vg(2-D) / (1-D), respectively.

[0014] The equivalent circuit for operation mode 2(2) is shown in Figure 3(b). In Stage 1, transistor M1 and diode D1 are turned off. The voltage at node X is given by equation (1), which is the sum of the boost voltage Vg / (1-D) (=VA) and VC1 (=Vg), which was charged to Vg prior to operation mode 1.

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[0015] The equivalent circuit for operation mode 1(3) is shown in Figure 3(c). In this mode, M1, M2, and D1 are ON. D2 and D3 are OFF. C1 is charged to the input voltage Vg, and C2 maintains the voltage Vg(2-D) / (1-D).

[0016] Figure 3(d) shows the equivalent circuit for operating mode 3(4). In Stage 1, M1 and D1 are turned on, and C1 is charged to the input voltage Vg. The node voltage B is calculated as equations (2)-(4) due to boost operation. During the charging period of L2, the product of the voltage of L2 and its period is Vg(D-D') in operating mode 1(1) + operating mode 1(3), and KD' during the ON period of M2 in operating mode 2(2). The discharge period of L2 is (Vg-VB)D' in operating mode 3(4) when M2 is OFF. Therefore, applying voltage-second balance to L2 results in equation (2). Rewriting equation (2) yields equation (3), and as a result, the voltage node B can be summarized as equation (4). Here, K=(2-D) / (1-D).

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[0017] The calculation of the conversion ratio (CR) will be described below. To propose a converter operating in continuous current mode (CCM), we apply volt-second balance to inductor IL2, resulting in equation (5).

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[0018] Figure 4 shows the simulation circuit for the circuit proposed in this example. In this example, the input voltage Vg = 20 V, the load resistance Ro = 400 Ω, L1 = L2 = 300 μH, C1 = C2 = CO = 20 μF, the interleaved clock fclk = 100 kHz, and D = 0.8. Signals S11 and S21 are connected to the gates of Q1 and Q2. Here, the default parasitic parameters of Q1 and Q2 are Rds = 48 mΩ, VFDi = 3 V, and RD = 1 mΩ. The other elements are ideal elements.

[0019] Figure 5 shows the simulation results for the output voltage and input voltage. As a result of the simulation, the output voltage Vo was 318V when Vg was 20V, and CR was 318 / 20=15.9, which is in good agreement with equation (8). In addition, VC1 was 19.2V and VC2 was 120V, which is in good agreement with Vg and Vg(2-D) / (1-D) when D=0.8.

[0020] Figure 6(a) shows the simulated waveforms of the inductor current IL1, the voltage at node X (VX), the inductor current IL2, and the interleaved clocks S11 and S12. Figure 6(b) shows the simulated waveforms of the voltage at node Y (VY), the voltage at node A (VA), the voltage at node B (VB), and the interleaved clocks S11 and S12. It can be seen that IL1 changes in a triangular pattern, VX has a step-like voltage, and IL2 changes piecewise linearly. The changes in IL1 and IL2, △IL1 and △IL2, were theoretically calculated using equations (9) and (10), respectively, and were consistent with the simulation results.

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[0021] Figure 7 shows the theoretical CR (Equation (8) calculation results (Calc.) and simulation results (Sim.) of the output voltage Vo when D is changed from 0.5 to 0.9. In Figure 7, the horizontal axis is the duty cycle D, which is varied from 0.5 to 0.9. The vertical axis is the output voltage Vo. The calculation results and simulation results match well, and it can be seen that an output voltage of 400 V was obtained when D was around 0.84.

[0022] Figure 8 shows the timing diagram of the complementary clocks. Applying the volt-second balance law to IL2, <il2>The calculation for =0 is as follows:

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[0023] Table 1 shows a comparison table showing the performance of this embodiment with conventional (existing) technology. It can be seen that the total number of elements is smaller than that of the conventional technology. Specifically, the total number of elements in this embodiment is 10, the smallest. Among the components, the inductor L is generally the most expensive, followed by the capacitor C. The configuration of this embodiment has the smallest L and C (there are configurations with the same number of L and C). CR = 16 times can be obtained at D = 0.8. At D = 0.8, CR is smaller than that of the existing converter (Patent Document 3), but if D = 0.84 is increased, theoretically CR = 20 can be obtained. Actual measurements confirmed that CR = 19.5 times can be obtained at D = 0.85. [Table 1]

[0024] Figure 9 shows a photograph of the prototype with a volume size of 125 mm (L) × 100 mm (W) × 43 mm (H). The component values ​​and part numbers are listed in Table 2. [Table 2]

[0025] Figure 10 shows the block diagram of the measurement setup shown in Figure 9. The dotted line indicates the prototype DC-DC converter (Figure 9). Transistors M1 and M2 are driven via a driver IC. An electronic load with an output resistance Ro of 500 Ω is used as the load. The interleaved clock is supplied from a function generator. The operating clock frequency is set to 100 kHz for all measurements. The duty cycle D is varied from 0.55 to 0.85 using a Textronix AFG3120 function generator. The power supply voltage VDD of the gate drivers (IC1 and IC2) is set to 8 V, and a gate resistance of 51 Ω is selected. The output voltage Vo is connected to a current load Array3710A with an output resistance Ro of 500 Ω. Because the absolute maximum voltage of the Array3710A is limited to 350 V (the withstand voltage of the electronic load is less than 350 V), the input voltage Vg is set to 10 V instead of 20 V. As an input filter, an electrolytic capacitor CIN (3300uF) was connected between Vg and GND.

[0026] FIG. 11 shows the measurement results for the setup of FIGS. Figure 11 shows the measured waveforms of VX, VX, CK1, and CK2 when D = 0.8. The signal waveforms were measured using a Textoronix MD034 oscilloscope and a passive probe TPP0250 with an attenuation of 10:1.

[0027] FIG. 12 shows the measured output voltage Vo versus duty cycle D along with the calculated gain as a dotted line. The horizontal axis is the duty cycle D, where D = 0.55 to 0.85, and shows the output voltage Vo and efficiency η. The dotted line is the theoretical value, the black circles are the measured values, and the black triangles are the efficiency. The duty cycle D changed from 0.55 to 0.85 when the input voltage Vg = 10V and Ro = 500Ω. The black dotted line is the ideal output voltage calculated using equation (8). The blue line is the measured output voltage Vo, and the red line is the measured efficiency η. The measured output voltage agrees well with the ideal calculated result. When the duty cycle D is large, the output voltage Vo is slightly lower than the theoretical value. This is due to the forward voltage VF of the diodes D1, D2, and D3, and the parasitic resistance of the inductors (L1, L2) and transistors (M1, M2). According to Figure 12, CR = 19.5 (= 19.5V / 10V) was obtained. The peak efficiency was 90.7% when D = 0.8. When D = 0.85, the output voltage Vo = 195.1V, i.e., CR = 19.5 (= 195.1V / 10V) was obtained.

[0028] This high-boost DC-DC converter for DC microgrids is improved by replacing two switches with two inductors and applying an interleaved clock instead of a complementary clock. These improvements make the input voltage of the second stage step-like, and the inductor current IL2 changes piecewise linearly, increasing the energy stored in IL2. The effect of this embodiment (technical effect compared to the prior art) is that CR=20 at D=0.84 is achieved with 10 components. Experimental results of the laboratory prototype verified CR=19.5 at D=0.85. The total number of components is less than that of conventional major high-step-up DC-DC converters. As a result, costs are reduced, packaging volume is reduced, and reliability is improved.

[0029] FIG. 13 shows an application example using the power conversion circuit of this embodiment, and is a block diagram illustrating an example in which the power conversion circuit is applied to a distributed power supply network such as a picogrid (synonymous with a microgrid). A picogrid uses a highly efficient, easily controlled DC-DC converter to connect solar cells, fuel cells, and the like to the grid. In the power conversion circuit shown in FIG. 7, the input power supply side of the power conversion circuit is a solar cell, and the output terminal side of the power conversion circuit is a load (grid). Here, the grid is, for example, a DC microgrid (380 V to 400 V), and various DC loads (for example, a charging station for electric vehicles) are connected to the DC microgrid (via a step-down DC / DC converter, if necessary).

[0030] As another example, the input power supply may be a lithium ion battery (2.7V to 4.2V), an electric vehicle battery (48V), a server power supply (48V), or the like.

[0031] Although the embodiments of the present invention have been described above, various alternatives, modifications, and variations are possible for those skilled in the art based on the above description, and the present invention includes the various alternatives, modifications, and variations described above within the scope of the present invention. [Industrial Applicability]

[0032] In the future, we will see an increase in distributed power supply networks, such as picogrids, at the city or town level. Picogrids use highly efficient, easy-to-control DC-DC converters to connect solar cells, fuel cells, and other devices to the grid.

[0033] An example of a product to which this embodiment can be applied is a DC-DC converter used in places where high voltage boost is required. Specifically, it is a DC-DC converter that can connect from a PV panel (20V) to a DC grid (400V). In addition to PV, it can also be applied to high voltage boost applications from button batteries (3.3V) such as FC (Fuel Cell) and IoT. Fields: Renewable energy field, IoT field.

Claims

1. A power conversion circuit comprising a first stage circuit on the input side and a second stage circuit on the output side, The power conversion circuit operates in the order of a first operation mode (1), a second operation mode (2), a first operation mode (3), and a third operation mode (4), In the first operation mode (1), the first capacitor and inductance of the first stage and the second inductor of the second stage are charged from the input power terminal; In the second operating mode (2), the energy stored in the first capacitor and inductor of the first stage is stored in the second capacitor and inductor of the second stage, In the first operation mode (3), the first capacitor and inductance of the first stage and the second inductor of the second stage are charged from the input power terminal; In the third operating mode (4), the energy stored in the second capacitor and the second inductor of the second stage is output to an output terminal.

2. A power conversion circuit comprising a first stage circuit on the input side and a second stage circuit on the output side, the first stage circuit and the second stage circuit are connected in series; the first stage circuit and the second stage circuit each include a switch, an inductor, a capacitor, and a diode; The power conversion circuit operates in the order of a first operation mode (1), a second operation mode (2), a first operation mode (3), and a third operation mode (4), In the first operation mode (1), the switch of the first stage circuit and the switch of the second stage circuit are turned on, In the second operating mode (2), the first stage circuit is switched on and the second stage circuit is switched off; In the first operation mode (3), the switch of the first stage circuit and the switch of the second stage circuit are turned on, In the third operating mode (4), the first stage circuit is switched off and the second stage circuit is switched on. A power conversion circuit comprising:

3. 2. The power conversion circuit according to claim 1, wherein in the third operating mode, an output terminal of the second stage circuit is conductive to a load circuit connected to the second stage circuit.

4. When the first stage circuit is switched on, the potential across the inductor and capacitor of the first stage is set to ground potential; When the switch of the first stage circuit is turned off, the inductor and capacitor of the first stage form a series circuit, When the second stage circuit is switched on, the potential across the inductor and capacitor of the second stage is set to ground potential; 2. The power conversion circuit of claim 1, wherein when the second stage circuit is switched off, the inductor and capacitor of the second stage form a series circuit.

5. 2. The power conversion circuit according to claim 1, wherein the on / off of the switches of the first stage circuit and the on / off of the switches of the second stage circuit are controlled by interleaved clocks having a phase difference of 180 degrees.

6. The step-up ratio CR of the input voltage Vg and the output voltage Vg is expressed as follows when the duty ratio D is used:

2. The power conversion circuit of claim 1, wherein the power conversion circuit is obtained by:

7. 2. The power conversion circuit according to claim 1, wherein the output voltage Vo can be increased by connecting a plurality of first-stage circuits and a plurality of second-stage circuits in series.

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