Multiphase-controlled high step-up DC-DC converter

Abstract

To provide a new multiphase-controlled high step-up DC-DC converter.SOLUTION: The present invention provides a power conversion circuit including a first-stage circuit and a second-stage circuit, the first-stage circuit including a first switch, the second-stage circuit including a second switch and a second capacitor, the power conversion circuit being configured such that current flows from an input terminal to the second capacitor when the first switch is off, and current flows from the second capacitor to an output terminal when the second switch is off.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power conversion circuit, and more particularly to a high-boost DC-DC converter that can be used in PV (Photovoltaic Cell: solar cell) and FC (Fuel Cell: fuel cell) that require high boost voltage. [Background technology]

[0002] There is a trend towards greater decentralization of power supply. The DC bus voltage of DC microgrids used in distributed power sources is 400V. Mega solar power plants, which gain voltage by connecting PV panels in series, require a large site area and are not suitable for distributed power supply. A high-step-up DC-DC converter is required that can connect even a single PV panel (20V) to a DC microgrid. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] R. Rahimi, S. Habibi, M. Ferdowsi, and P. Shamsi, “Z-Source-Based High Step-Up DC-DC Converters for Photovoltaic Applications,” IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 10, no. 4, pp. 4783-4796, August 2022 [Non-patent document 2] VAK Prabhala, P. Fajri, VSP Gouribhatla, BP Baddipadiga, and M. Ferdowsi, “A DC-DC Converter With High Voltage Gain and Two Input Boost Stages,” IEEE Trans. Power Electronics, vol. 31, no. 6, pp. 4206-4215, June 2016. [Non-patent document 3] BP Baddipadiga and M. Ferdowsi, “A High-Voltage-Gain DC-DC Converter Based on Modified Dickson Charge Pump Voltage Multiplier,” IEEE Trans. Power Electronics, vol. 32, no. 10, pp. 7707-7715, October 2017. Summary of the Invention [Problem to be solved by the invention]

[0004] One aspect of the present invention aims to provide a high-step-up DC-DC converter (power conversion circuit) with a new configuration that can solve the technical problems described above and that can connect even a single PV panel (20V) to a DC microgrid (400V). [Means for solving the problem]

[0005] One aspect of the present invention provides a four-coil boost DC-DC converter circuit with high voltage gain and high output power. This converter circuit uses a multiphase control scheme to directly boost a 20V solar module voltage to a 400V microgrid voltage, for example. Specifically, four coils with four different clock phases are used to drive three parallel-series capacitor boost converters. The reverse bias voltages of the transistor switches and diodes only need to be 1 / 4 and 1 / 2 of the output voltage, respectively, thereby avoiding reliability issues.

[0006] According to one aspect of the present invention, a power conversion circuit includes a first stage circuit having a coil and a switch, second stage, third stage, and fourth stage circuits each having a coil, a capacitor, and a switch, and an output stage circuit. The first stage circuit, second stage circuit, third stage circuit, and fourth stage circuit are connected in parallel via diodes. The output stage circuit is composed of a diode, a capacitor, and a load current. The switches are controlled by multilayer clocks. The first multilayer clock charges the inductor energy of the first stage to the capacitor of the second stage. The next multilayer clock charges the inductor energy of the second stage via the capacitor of the second stage to the capacitor of the third stage. The next multilayer clock charges the inductor energy of the third stage via the capacitor of the third stage to the capacitor of the fourth stage. As a result, the inductor energy of the fourth stage and the capacitor voltage of the fourth stage are supplied to the output stage circuit. A power conversion circuit characterized by this configuration is provided. [Effects of the Invention]

[0007] The power conversion circuit of the present invention has technical advantages over existing technologies, such as being able to supply a large current capacity with high efficiency, and being able to use a smaller number of devices in the circuit of the present invention.

[0008] The power circuit of the present invention (a DC-DC boost converter circuit that achieves high voltage gain and high driving capability) uses a capacitor connected in series to a coil, multiple parallel connections, and multi-layer control to achieve high output current while maintaining high voltage gain, high power efficiency, low device stress, and a small number of components. Therefore, it is suitable for use as an interface between solar cells and a DC microgrid.

[0009] Other objects, features and advantages of the present invention will become apparent from the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 shows a step-up DC-DC converter circuit according to this embodiment. [Figure 2] FIG. 2 shows a timing chart of the step-up DC-DC converter circuit of this embodiment. [Figure 3(a)] FIG. 3(a) shows the operation of the step-up DC-DC converter circuit of this embodiment in each state. [Figure 3(b)] FIG. 3(b) shows the operation of the step-up DC-DC converter circuit of this embodiment in each state. [Figure 3(c)] FIG. 3(c) shows the operation of the step-up DC-DC converter circuit of this embodiment in each state. [Figure 3(d)] FIG. 3(d) shows the operation of the step-up DC-DC converter circuit of this embodiment in each state. [Figure 4] FIG. 4 shows the results of a simulation of the step-up DC-DC converter circuit of this embodiment. [Figure 5] FIG. 5 shows the results of a simulation of the step-up DC-DC converter circuit of this embodiment. [Figure 6] FIG. 6 shows the results of a simulation of the step-up DC-DC converter circuit of this embodiment. [Figure 7] FIG. 7 shows an application example using the power conversion circuit of this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] <<1. Circuit of this Example>> Fig. 1 shows a step-up DC-DC converter circuit of this embodiment, in which Vin is the input voltage, Vout is the output voltage, Cout is the load capacitance, and Iout is the load current. The step-up DC-DC converter circuit of this embodiment is composed of four inductors L1 to L4, four switches SW1 to SW4, output capacitors C1 to C4, four diodes DD2 to DD5, an input voltage source Vi, and an output current source Iout. The switches SW are composed of MOS transistors and protection diodes. When the gate voltage Vgn (n=1, 2, 3, 4) of each switch SW increases, the switch turns on, and when Vgn decreases, the switch turns off. Although not shown in the circuit in Figure 1, the inductor and capacitor each have parasitic components such as series resistance rL and effective series resistance (ESR) RC. These parasitic components are taken into account in the simulation of the boost DC-DC converter circuit, which will be explained in Figure 4 and subsequent figures.

[0012] <<2. Timing Chart>> The outline of the step-up DC-DC converter circuit of this embodiment will be explained below. Figure 2 shows a timing chart for the step-up DC-DC converter circuit of this embodiment. It operates in four modes. The top four lines in Figure 2 represent the voltages at nodes CLK1 to CLK4 in Figure 1. For CLK1, SW1 is OFF for period D1, and the voltage is Vin / D1. Here, D1 = 1 - D. However, as will be explained later, D is the usual duty ratio notation that represents the period when the switch is ON, with one clock cycle period being 1. For CLK2, SW2 is OFF for period D2, and the voltage is Vin / D2. The same applies below. The SWs are phase-shifted during their OFF periods, and are never turned OFF simultaneously. The bottom four lines in Figure 2 show the voltages at nodes A1 to A3. Figure 3 shows the operation in each state.

[0013] Figure 3(a) shows when SW1 is OFF, Figure 3(b) shows when SW2 is OFF, Figure 3(c) shows when SW3 is OFF, and Figure 3(d) shows when SW4 is OFF. Grey components indicate inactive states. The output voltage Vout is calculated using the following formula, where D' = 1 - D. However, D1 = D2 = D3 = D4 = D'.

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[0014] The technical effects of the boost converter circuit of this embodiment (technical effects compared to the prior art) are that it has good energy saving effects and large current output characteristics.

[0015] <<3. Operating Principle>> Next, we will explain the operating principle of the boost converter circuit in Figure 1. Figure 2 explains the circuit operation divided into four phases. The gate voltages Vg1-Vg4 in Figure 1 alternately go low in the order of Vg1 to Vg4. The interval between low gate voltage states does not exceed one-fourth of one control period Ts, and the connections change as shown in Figure 2 (a) to (d). For the purpose of explanation, Figure 2 shows the voltage waveforms of CLK1-CLK4 and A1-A3.

[0016] (3.1) SW1=OFF, SW2, 3, 4=ON Consider the case where Vg1 changes from high to low while Vg2-Vg4 are high. In this case, as shown in Figure 3(a), switch SW1 turns off and the other switches SW2-SW4 all turn on. Diodes DD3-DD5 become reverse biased. Then, inductor L1 releases energy, boosting terminal CLK1 to a voltage Vin / D1. At the same time, this energy charges capacitor C2 via diode DD2, and ignoring the forward bias voltage of DD2, both the voltage at terminal A1 and the voltage across C2 become Vin / D1. Note that D1 is the time interval during which the switch remains off. This notation differs from the conventional duty ratio notation D. The relationship between the two is D1=1-D.

[0017] (3.2) SW2=OFF, SW1, 3, 4=ON During this time interval, Vg2 goes low, while Vg1, Vg3, and Vg4 remain high. Therefore, switches SW1, SW3, and SW4 turn on, inductors L1, L3, and L4 charge, and L2 releases energy. Diodes DD2, DD4, and DD5 are reverse-biased as shown in Figure 3(b). In this case, terminal CLK2 is boosted to Vin / D2 as shown in Figure 3. Then, the voltage at terminal A1 becomes:

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[0018] (3.3) SW3=OFF, SW1, 2, 4=ON During this time interval, vg3 goes low, while Vg1, Vg2, and Vg4 remain high. Therefore, switches SW1, SW2, and SW4 are turned on, allowing inductors L1, L2, and L4 to charge, while L3 releases energy. Diodes DD2, DD3, and DD5 are reverse biased as shown in Figure 3(c). Terminal CLK3 is boosted to Vin / D3 as shown in Figure 2. 、 The voltage at terminal A2 is:

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[0019] (3.4) SW4=OFF, SW1, 2, 3=ON Now, vg4 goes low, while Vg1, Vg2, and Vg3 remain high. Therefore, switches SW1, SW2, and SW3 are turned on, allowing inductors L1, L2, and L3 to charge, while L4 releases energy. Diodes DD2, DD3, and DD4 are reverse biased as shown in Figure 3(d). Terminal CLK4 is boosted to Vin / D3 as shown in Figure 2. 、 The voltage at terminal A3 is:

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[0020] <<4.Current distribution>> Consider the current distribution. Calculate the current flowing through each inductor.

[0021] (4.1) Calculation of ilL4 The current iL4 of inductor L4 flows through capacitor C4 and becomes current Iout. The charging current of capacitor Cout changes over the time interval D4·Ts, as shown in Figures 1 and 3. Therefore, the increase in the voltage of capacitor Cout, i.e., Vout during this period D4, is as follows:

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[0022] (4.2) Calculation of iL3 During the time interval D3Ts, the capacitor C4 is charged up by the current flowing through L3 and C3, i.e., iL3(ic3). Thus, equation (9) is obtained.

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[0023] (4.3) Calculation of ilL2 By applying a similar method, equations (12) and (13) can be obtained.

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[0024] (4.4) Calculation of il1 By applying a similar method, equations (15) and (16) can be obtained.

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[0025] <<5. Power consumption>> Below we will explain the limitations imposed on the elements and the power consumption of the circuit, specifically (5.1) the maximum reverse bias voltage of the elements, (5.2) power dissipation, and (5.3) output voltage ripple.

[0026] (5.1) The maximum reverse bias voltage of the element is explained. First, assume that all duties are equal, i.e., D1 = D2 = D3 = D4 = D'. The maximum voltage of inductor L1 is Vin(1-D') / D'. The same voltage is observed for each inductor from L2 to L4. Next, the maximum voltage of the transistors and diodes of switches SW1 to SW4 is Vin / D'. The reverse bias voltages of capacitors C2, C3, C4, and Cout are Vin / D', 2Vin / D', 3Vin / D', and 4Vin / D'. Furthermore, the reverse bias voltages of DD2, DD3, DD4, and DD5 are 2Vin / D', 2Vin / D', 2Vin / D', and 2Vin / D', respectively. The voltage stress on the devices is low.

[0027] (5.2) Explain power loss. Let rL be the series resistance of the inductor and rON be the on-resistance of the transistor. Assuming that the equivalent series resistance of the capacitor is zero, the power loss due to rL and rON is as follows:

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[0028] (5.3) Explain output voltage ripple. The output capacitor Cout is charged during the time interval D4·Ts. The voltage difference between the charging and discharging processes remains the same even in steady-state operation. For the remaining time interval (1-D4), Cout is discharged by the current source Iout. The voltage drop is:

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[0029] <<6. Simulation Results>> A circuit simulation was performed to verify the effectiveness of the high-gain, high-power boost DC-DC converter shown in Figure 1. Table 1 shows the devices and parameters used in the simulation. [Table 1] The values ​​of L and C were set to 1 mH and 10 μF, respectively. Considering parasitic components, a series resistance of 100 mΩ was used for each inductor (L1 to L4), and an effective series resistance (ESR) of 10 mΩ was used for each capacitor (C2 to C4) and Cout. The clock frequency was 50 kHz. The device parameters of the transistors and diodes were commercially available, and the simulation results are believed to be close to the performance of the actual circuit.

[0030] Figure 4 shows the relationship between voltage gain and turn-off time D', where D' is the time interval during which the transistor switches SW1 to SW4 in Figure 1 remain off. As shown in Figure 4, the ideal voltage gain for D' = 0.2 is 20, while the simulated voltage gain is 19.9. There is not much difference between the ideal and simulated values. However, the simulated circuit includes the series resistance of the inductor and the ESR of the capacitor. Also, commercially available device parameters for the transistors and diodes were used. However, the degradation of voltage gain is very small.

[0031] Figure 5 shows the simulation results. The horizontal axis represents the output current Iout, and the vertical axis represents the output voltage Vout. The dots indicate the proposed circuit, and the crosses indicate the configuration of Patent Document 2 in Table 2. Figure 5 also shows the output current dependence of the output voltage. Vin is 20V, and the dots indicate the simulated characteristics of the four-coil circuit in Figure 1. All parasitic components are included. As the output current increases, circuit losses increase and the output voltage decreases. Even when the output voltage drops to 350V, an output current of approximately 2.5A can still be supplied. In other words, an output power of 875W can be obtained. It can be seen that the Vout drop is improved with increasing output current Iout. Conversely, the crosses in Figure 5 represent the simulation results when the two-coil circuit in Figure 2 of Patent Document 2 is expanded to three stages. For comparison, the relationship between output voltage and output current is plotted.

[0032] This simulation used the exact same parameters as the four-coil circuit shown in Figure 1. As can be seen from Figure 5, the circuit in Patent Document 2 uses only two coils, and the current flowing through the inductor, diode, and transistor is twice that of the four-coil circuit, so the output voltage is significantly lower than that of the four-coil circuit.

[0033] Figure 6 shows the relationship between output current and power. Simulation results of the input power (Pin) and output power (Pout) of the four-coil circuit shown in Figure 1, and the power loss due to the series resistance of the four inductors (PRL), four switches (PSW), and four diodes (PDD) are plotted. For comparison, the output power of the two-coil circuit in Patent Document 2 is plotted. Because the transistors used in the simulation have a large current capacity, the on-resistance does not change much with the drain current, and is considered to be constant within the output current range of up to 10 A. Therefore, the curves of PRL and PSW in Figure 6 show the difference between the power I 2 Since they are proportional to R, both are quadratic functions. These curves match well with the results of equations (20) and (21). Because the diode PDD operates only during the turn-on time D', its power consumption is small and does not significantly affect circuit operation. From the figure, it is clear that the main causes of power loss are the series resistance of the inductor and the on-resistance of the transistor switch. Table 2 compares the power efficiency of the four-coil circuit in Figure 1 and the two-coil circuit in Patent Document 2 as the output current changes. [Table 2]

[0034] As can be seen in Figure 6, the on-resistance of the transistor appears to be constant even when the drain current changes. It was approximately 60 mΩ. Furthermore, the main causes of the circuit's power consumption are the series resistance of the coil and the on-resistance of the transistor, and the degradation of the power efficiency of both DC-DC converters in Table 2 appears to be proportional to the change in output current, especially in the range above 1 A. Overall, the simulation results verified that the boost converter shown in Figure 1 simultaneously achieves large voltage gain and power driving capability.

[0035] Furthermore, Table 3 compares the performance of various solar panel designs. Patent Document 1 is based on a Z-source configuration. However, because the transistor and load are floating, it is not suitable for use in DC grid systems. On the other hand, the Dickson type is suitable for DC systems, but as shown in Table 2, it has a small output current capacity and its power efficiency drops sharply as the output current increases. In contrast, this research has improved the output current tolerance to twice that of the Dickson type. If an output current capacity equivalent to that of this work is required, the Dickson type requires the use of two converters in parallel, which means that the number of parts is greater than this work. [Table 3]

[0036] A comparison of the existing technology and the embodiments of the present application in Table 3 provides the following technical advantages. For example, it is easy to use because there are no floating (different GND reference) transistors. Iout can flow up to 1.5 A. Higher efficiency than existing technology.

[0037] FIG. 7 shows an application example using the power conversion circuit of this embodiment, and is a block diagram illustrating an example in which the power conversion circuit is applied to a distributed power supply network such as a picogrid. In a picogrid, a highly efficient, easily controlled DC-DC converter is used to connect solar cells, fuel cells, and the like to the grid. In the power conversion circuit shown in FIG. 7, the input power supply side of the power conversion circuit is a solar cell, and the output terminal side of the power conversion circuit is a load (grid). Here, the grid is, for example, a DC grid (380 V to 400 V), and various DC loads (for example, a power supply station for electric vehicles) are connected to the DC grid (via a step-down DC / DC converter, if necessary).

[0038] As another example, the input power source may be a lithium ion battery (2.7V to 4.2V), an electric vehicle battery (48V), a server power source (48V), a solar panel (15V to 40V), or the like.

[0039] Although the embodiments of the present invention have been described above, various alternatives, modifications, and variations are possible for those skilled in the art based on the above description, and the present invention includes the various alternatives, modifications, and variations described above within the scope of the present invention. [Industrial Applicability]

[0040] In the future, we will see an increase in distributed power supply networks, such as picogrids, at the city or town level. Picogrids use highly efficient, easy-to-control DC-DC converters to connect solar cells, fuel cells, and other devices to the grid.

[0041] An example of a product to which this embodiment can be applied is a DC-DC converter used in places where high voltage boost is required, such as in the renewable energy and IoT fields. Specifically, it is a DC-DC converter that can connect from a PV panel (20V) to a DC grid (400V). In addition to PV, it can also be applied to boosting voltage from button batteries (3.3V) such as FCs (Fuel Cells) and IoT.

Claims

1. 1. A power conversion circuit comprising a first stage circuit and a second stage circuit, the first stage circuit includes a first switch; the second stage circuit includes a second switch and a second capacitor; When the first switch is turned off, a current flows from the input terminal to the second capacitor; A power conversion circuit configured such that, when the second switch is off, a current flows from the second capacitor to an output terminal.

2. 1. A power conversion circuit comprising a first stage circuit, a second stage circuit, and a third stage circuit, the first stage circuit includes a first switch; the second stage circuit includes a second switch and a second capacitor; the third stage circuit includes a third switch and a third capacitor; When the first switch is turned off, a current flows from the input terminal to the second capacitor; When the second switch is turned off, a current flows from the second capacitor to the third capacitor; A power conversion circuit configured such that, when the third switch is off, a current flows from the third capacitor to an output terminal.

3. A power conversion circuit comprising a first stage circuit, a second stage circuit, a third stage circuit, and fourth, fifth, ..., Nth stage circuits, wherein the first stage circuit and the second stage circuit have the configuration of claim 1, and the third stage circuit, the fourth, fifth, ..., Nth stage circuits each have the same configuration as the third stage circuit of claim 2, and are configured so that current flows from the capacitor of the Nth stage circuit to the output terminal.

4. The power conversion circuit according to any one of claims 1 to 3, wherein any one of the first switch, the second switch, the third switch, and the fourth, fifth, ..., Nth switch operates by inputting N different clock phases.

5. The power conversion circuit according to any one of claims 1 to 4, wherein the output voltage can be set to any value by setting the off-feedback (D1, D2, D3, D4, ... DN) of N different clocks as D1+D2+D3+D4+ ... +DN≦1.

6. 6. The power conversion circuit according to claim 1, wherein the power conversion circuit is a step-up DC-DC converter circuit.

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