Semiconductor device

Abstract

To reduce the on-state resistance of a semiconductor device and improve the withstanding voltage.SOLUTION: A semiconductor device 10 includes a semiconductor layer 12 having a first surface 12A, a trench 20 including a side wall 20A extending from the first surface 12A to the inside of the semiconductor layer 12, an insulating layer 14 existing on the first surface 12A of the semiconductor layer 12 and covering the side wall 20A of the trench 20, a first electrode 40 existing in the trench 20, and a second electrode 42 existing in the trench 20 and separated from the first electrode 40 by the insulating layer 14. In a depth direction intersecting with the first surface 12A, the second electrode 42 exists between the first electrode 40 and the first surface 12A. The first electrode 40 includes a lower electrode part 46, and an upper electrode part 48 having a larger width than the lower electrode part 46. The second electrode 42 includes a concave part 52, and has a larger width than the upper electrode part 48 of the first electrode 40. A part of the upper electrode part 48 of the first electrode 40 exists in the concave part 52.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including multiple trench gate structures, each of which has a vertical split electrode structure in which a first electrode and a second electrode are arranged separately in the depth direction of the gate trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-125649

[0004] [overview] In a semiconductor device having a trench gate structure, it is desired to reduce the on-resistance and improve the breakdown voltage.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer having a first surface, a trench having a sidewall extending from the first surface into the semiconductor layer, an insulating layer located on the first surface of the semiconductor layer and covering the sidewall of the trench, a first electrode located in the trench, and a second electrode located in the trench and separated from the first electrode by the insulating layer. In a depth direction intersecting the first surface, the second electrode is located between the first electrode and the first surface. The first electrode includes a lower electrode portion and an upper electrode portion having a width greater than that of the lower electrode portion. The second electrode includes a recess and has a width greater than that of an upper electrode portion of the first electrode. A portion of the upper electrode portion of the first electrode is located in the recess.

[0006] Other features and aspects will become apparent from the following detailed description, drawings, and claims. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to one embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic cross-sectional view of the semiconductor device taken along line F2-F2 in FIG. [Figure 3] FIG. 3 is an enlarged view of a portion of FIG. [Figure 4] 4A to 4C are schematic cross-sectional views illustrating exemplary manufacturing steps for a semiconductor device. [Figure 5] FIG. 5 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of a semiconductor device according to a modified example. [Figure 16] FIG. 16 is an enlarged view of a portion of FIG.

[0008] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout the drawings and detailed description. The drawings may not be to scale, and the relative size, proportions, and depictions of elements in the drawings may be exaggerated for clarity, explanation, and convenience.

[0009] The following detailed description provides a comprehensive understanding of the described methods, devices, and / or systems. Modifications and equivalents of the described methods, devices, and / or systems will be apparent to those skilled in the art. Except for operations that necessarily occur in a particular order, the order of operations is illustrative and may be changed as would be apparent to one skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted. Example embodiments may have different forms and are not limited to the described examples.

[0010] An exemplary semiconductor device 10 according to an embodiment of the present disclosure will be described with reference to Figures 1 to 3. Figure 1 is a schematic plan view of the semiconductor device 10. Figure 2 is a schematic cross-sectional view of the semiconductor device 10 taken along line F2-F2 in Figure 1. Figure 3 is an enlarged view of a portion of Figure 2. As will be described below, the semiconductor device 10 may be configured as a metal-insulator-semiconductor field-effect transistor (MISFET) having a trench gate structure.

[0011] As shown in FIGS. 1 to 3, a semiconductor device 10 includes a semiconductor layer 12 having a first surface 12A (see FIG. 2, etc.). The semiconductor layer 12 may be formed of, for example, silicon (Si). The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 and other drawings is a direction that intersects (e.g., is perpendicular to) the first surface 12A of the semiconductor layer 12. As used herein, the term "plan view" refers to a view drawn from a perspective looking down on an object from above along the Z-axis direction, unless explicitly stated otherwise.

[0012] (Plane layout of semiconductor device) 1, the semiconductor layer 12 may have a rectangular shape in a plan view. In the illustrated example, the semiconductor layer 12 includes two side surfaces 12X1 and 12X2 extending along the X-axis direction in a plan view and two side surfaces 12Y1 and 12Y2 extending along the Y-axis direction in a plan view.

[0013] The semiconductor device 10 includes an insulating layer 14 located on the semiconductor layer 12. In one example, the insulating layer 14 may include at least one of a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, and a silicon oxynitride (SiON) layer.

[0014] The semiconductor device 10 may include a gate wiring 16 located on the insulating layer 14. In the example shown in FIG. 1 , the gate wiring 16 includes a gate pad portion 16P, a first gate wiring portion 16Y1 and a second gate wiring portion 16Y2 extending in the Y-axis direction, and a third gate wiring portion 16X extending in the X-axis direction. The gate pad portion 16P is located relatively close to a corner of the semiconductor device 10 (e.g., a position where the side surface 12Y1 and the side surface 12X2 of the semiconductor layer 12 intersect). The first gate wiring portion 16Y1 and the second gate wiring portion 16Y2 are located relatively close to the side surface 12Y1 and the side surface 12Y2 of the semiconductor layer 12, respectively. The third gate wiring portion 16X is located relatively close to the side surface 12X2 of the semiconductor layer 12. The first gate wiring portion 16Y1 is connected to the gate pad portion 16P. The second gate wiring portion 16Y2 is connected to the third gate wiring portion 16X. The third gate wiring portion 16X connects the gate pad portion 16P and the second gate wiring portion 16Y2.

[0015] The semiconductor device 10 may include a source wiring 18 located on the insulating layer 14. The source wiring 18 is spaced apart from the gate wiring 16. In the example shown in FIG. 1 , the source wiring 18 includes an inner source wiring portion 18A and a peripheral source wiring portion 18B. The inner source wiring portion 18A may be at least partially surrounded by the gate wiring 16 in a planar view. The peripheral source wiring portion 18B may surround the gate wiring 16 in a planar view. The inner source wiring portion 18A is electrically connected to the peripheral source wiring portion 18B. The inner source wiring portion 18A and the peripheral source wiring portion 18B are integrally formed by being connected in a region between an end of the first gate wiring portion 16Y1 and an end of the second gate wiring portion 16Y2.

[0016] The gate wiring 16 and the source wiring 18 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), aluminum (Al), a copper alloy, and an aluminum alloy.

[0017] The layout of the gate wiring 16 and the source wiring 18 is not limited to the illustrated example. As will be understood by those skilled in the art, different layouts of the gate wiring 16 and the source wiring 18 can be adopted depending on the desired characteristics of the semiconductor device 10.

[0018] (Trench placement) The semiconductor device 10 includes a gate trench 20. In the present disclosure, the term "gate trench" can refer to a trench (or a portion of a trench) in which at least an electrode to which a gate voltage is applied (e.g., an electrode to which a gate voltage is applied to form a channel in the semiconductor layer 12, such as the second electrode 42 described below) is disposed. In the present disclosure, the gate trench 20 may also be simply referred to as a trench.

[0019] The semiconductor device 10 may include a plurality of gate trenches 20. The plurality of gate trenches 20 may intersect with the first gate wiring portion 16Y1 or the second gate wiring portion 16Y2 in a plan view. In this case, each of the plurality of gate trenches 20 may extend in the X-axis direction in a plan view and have a width in the Y-axis direction. That is, in the illustrated example, the longitudinal direction of the gate trench 20 is the X-axis direction, and the width direction of the gate trench 20 is the Y-axis direction. In the present disclosure, the width direction of the gate trench 20 may be referred to as the first direction, and the longitudinal direction may be referred to as the second direction. The first direction, which is the width direction, is a direction perpendicular to the second direction, which is the longitudinal direction.

[0020] The plurality of gate trenches 20 are arranged at intervals. In one example, the plurality of gate trenches 20 may be aligned at a constant pitch in the first direction. Optionally, the semiconductor device 10 may further include one or more field plate trenches 22 formed in the semiconductor layer 12. A field plate electrode (not shown) electrically connected to the source wiring 18 may be disposed in each field plate trench 22. Each field plate trench 22 may be disposed so as to at least partially surround some of the multiple gate trenches 20 in a planar view. In the illustrated example, each field plate trench 22 forms a rectangular loop so as to surround some of the gate trenches 20 in a planar view. Furthermore, the gate trenches 20 surrounded by each field plate trench 22 may be in communication with the field plate trench 22.

[0021] The layout of the gate trenches 20 and the field plate trenches 22 is not limited to the illustrated example. As will be understood by those skilled in the art, different layouts of the gate trenches 20 and the field plate trenches 22 can be adopted depending on the desired characteristics of the semiconductor device 10. For example, the semiconductor device 10 may further include a plurality of additional gate trenches (not shown) extending in the Y-axis direction in a plan view. Also, for example, the gate trenches 20 may be separated from the field plate trenches 22.

[0022] (Contact plug placement) The semiconductor device 10 may include a plurality of source contact plugs 24 that connect the source wiring 18 to the semiconductor layer 12. The plurality of source contact plugs 24 may be positioned so as to overlap the inner source wiring portion 18A in a plan view. The plurality of source contact plugs 24 may be arranged so that each gate trench 20 is located between two of the plurality of source contact plugs 24 in a plan view. Each source contact plug 24 may extend parallel to the gate trench 20 (i.e., along the longitudinal direction of the gate trench 20) in a plan view.

[0023] The semiconductor device 10 may include a plurality of gate electrode contact plugs 26 and a plurality of field plate electrode contact plugs 28. Each gate electrode contact plug 26 may be disposed within a region where the gate wiring 16 and the gate trench 20 overlap in a plan view. The gate wiring 16 may be electrically connected to an electrode (e.g., a first electrode 40 and a second electrode 42, which will be described later with reference to FIG. 2 ) disposed within the gate trench 20 via the plurality of gate electrode contact plugs 26. Each field plate electrode contact plug 28 may be disposed within a region where the source wiring 18 and the field plate trench 22 overlap in a plan view. The source wiring 18 may be electrically connected to an electrode (e.g., the above-mentioned field plate electrode) disposed within the field plate trench 22 via the plurality of field plate electrode contact plugs 28.

[0024] (Details of the semiconductor layer) 2 , the semiconductor layer 12 may have a first surface 12A and a second surface 12B opposite the first surface 12A. The semiconductor layer 12 may include an n-type drain region 30, an n-type drift region located on the drain region 30, a p-type body region 34 located on the drift region 32, and an n-type source region 36 located on the body region 34. The drain region 30 may include at least a portion of the second surface 12B of the semiconductor layer 12. The source region 36 may include at least a portion of the first surface 12A of the semiconductor layer 12.

[0025] The drain region 30 is a region containing n-type impurities. The n-type impurity concentration of the drain region 30 is 1×10 18 cm -3 More than 1×10 21 cm -3 The drain region 30 may have a thickness of 10 μm or more and 450 μm or less.

[0026] The drift region 32 is a region containing n-type impurities at a concentration lower than that of the drain region 30. The n-type impurity concentration of the drift region 32 is 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 32 may have a thickness of 1 μm or more and 25 μm or less.

[0027] The body region 34 is a region containing p-type impurities. The p-type impurity concentration of the body region 34 is 1×10 15 cm -3 More than 1×10 18 cm -3 The body region 34 may have a thickness of not less than 0.5 μm and not more than 1.5 μm.

[0028] The source region 36 is a region containing n-type impurities at a higher concentration than the drift region 32. The n-type impurity concentration of the source region 36 is 1×10 19 cm -3 More than 1×10 21 cm -3The source region 36 may have a thickness of 0.1 μm or more and 1 μm or less.

[0029] In one example, the drift region 32 may be formed from a Si substrate, and the drift region 32, the body region 34, and the source region 36 may be formed from a Si epitaxial layer.

[0030] In this disclosure, n-type may be referred to as the first conductivity type, and p-type may be referred to as the second conductivity type. The n-type impurities may include, for example, phosphorus (P), arsenic (As), and / or antimony (Sb). The p-type impurities may include, for example, boron (B), aluminum (Al), gallium (Ga), and / or indium (In).

[0031] The semiconductor device 10 may include a drain electrode 38 in contact with the second surface 12B of the semiconductor layer 12. The drain electrode 38 is electrically connected to the drain region 30. The drain electrode 38 may be formed from at least one of titanium (Ti), nickel (Ni), gold (Au), silver (Ag), copper (Cu), Al, a Cu alloy, and an Al alloy.

[0032] (Explanation of trench gate structure) Next, a description will be given of the trench gate structure of the semiconductor device 10. As mentioned above, the semiconductor device 10 may include multiple gate trenches 20. While the following description generally focuses on one gate trench 20, it will be understood that such description is equally applicable to other gate trenches 20.

[0033] The gate trench 20 has a sidewall 20A that extends from the first surface 12A into the semiconductor layer 12. The insulating layer 14 is located on the first surface 12A of the semiconductor layer 12 and covers the sidewall 20A of the gate trench 20.

[0034] The gate trench 20 may extend through the source region 36 and the body region 34 to the drift region 32. In one example, the gate trench 20 may have a depth of not less than 1 μm and not more than 15 μm.

[0035] The semiconductor device 10 includes a first electrode 40 located in the gate trench 20 and a second electrode 42 located in the gate trench 20 and separated from the first electrode 40 by an insulating layer 14. In a depth direction (the Z-axis direction in the illustrated example) intersecting the first surface 12A, the second electrode 42 is located between the first electrode 40 and the first surface 12A. The first electrode 40 may be disposed so as to face at least the drift region 32 with the insulating layer 14 interposed therebetween. The second electrode 42 may be disposed so as to face at least the body region 34 with the insulating layer 14 interposed therebetween. Details of the shapes of the first electrode 40 and the second electrode 42 will be described later with reference to FIG. 3 .

[0036] The first electrode 40 and the second electrode 42 may each include conductive polysilicon. In this embodiment, the first electrode 40 may be electrically connected to the second electrode 42. More specifically, the first electrode 40 and the second electrode 42 may be electrically connected to the gate wiring 16 (see FIG. 1).

[0037] As described above, the gate trench 20 may be located between two of the source contact plugs 24 in a plan view. Each source contact plug 24 may be partially embedded in the semiconductor layer 12.

[0038] The semiconductor layer 12 may include p-type contact regions 44 that are in contact with each source contact plug 24. The contact regions 44 are regions that contain p-type impurities at a higher concentration than the body region 34. In one example, the p-type impurity concentration of the contact regions 44 is 1×10 19 cm -3 More than 1×10 21 cm -3Each source contact plug 24 can electrically connect the source wiring 18 located on the insulating layer 14 to the semiconductor layer 12.

[0039] (Shapes of the first and second electrodes) 3, the first electrode 40 includes a lower electrode portion 46 and an upper electrode portion 48 having a width greater than that of the lower electrode portion 46. The lower electrode portion 46 and the upper electrode portion 48 have widths W1b and W1t, respectively. Here, the width W1b of the lower electrode portion 46 and the width W1t of the upper electrode portion 48 may be the dimensions of the lower electrode portion 46 and the upper electrode portion 48 in the width direction of the gate trench 20 (the Y-axis direction in the illustrated example).

[0040] In this embodiment, the lower electrode portion 46 may be adjacent to the upper electrode portion 48. The first electrode 40 may include a stepped surface 50 formed by the difference in width between the upper electrode portion 48 and the lower electrode portion 46. In one example, the stepped surface 50 may be curved.

[0041] The second electrode 42 includes a recess 52 and has a width W2 that is larger than the upper electrode portion 48 of the first electrode 40. The width W2 of the second electrode 42 may be the dimension of the second electrode 42 in the width direction of the gate trench 20 (the Y-axis direction in the illustrated example).

[0042] The second electrode 42 includes an upper surface 42A and a bottom surface 42B. The recess 52 is formed in the bottom surface 42B of the second electrode 42. The recess 52 is recessed from the bottom surface 42B toward the upper surface 42A.

[0043] A part of the upper electrode portion 48 of the first electrode 40 is located within the recess 52. The first electrode 40 may include an upper surface 40A located between the bottom surface 42B of the second electrode 42 and the upper surface 42A of the second electrode 42 in the depth direction. The upper surface 40A of the first electrode 40 faces the recess 52 in the depth direction.

[0044] Additionally, the upper electrode portion 48 of the first electrode 40 includes a side surface 48 A. At least a portion of the side surface 48 A of the upper electrode portion 48 may face the second electrode 42 with the insulating layer 14 interposed therebetween.

[0045] The boundary between the drift region 32 and the body region 34 may be located in the depth direction near the bottom surface 42B of the second electrode 42. In addition, the boundary between the drift region 32 and the body region 34 may be located in the depth direction between the bottom surface 42B and the top surface 42A. Furthermore, the boundary between the drift region 32 and the body region 34 may be located in the depth direction within the range in which the upper electrode portion 48 extends (i.e., between the top surface 40A of the first electrode 40 and the step surface 50).

[0046] The boundary between the body region 34 and the source region 36 in the depth direction may be located near the top surface 42A of the second electrode 42. In addition, the boundary between the body region 34 and the source region 36 in the depth direction may be located between the bottom surface 42B and the top surface 42A.

[0047] The insulating layer 14 includes a first insulating portion 54 extending between the first electrode 40 and the sidewall 20A of the gate trench 20. The first insulating portion 54 has a first thickness T1b between the lower electrode portion 46 of the first electrode 40 and the sidewall 20A, and a second thickness T1t between the upper electrode portion 48 of the first electrode 40 and the sidewall 20A. Because the upper electrode portion 48 has a width greater than the lower electrode portion 46, the second thickness T1t is smaller than the first thickness T1b.

[0048] The lower electrode portion 46 of the first electrode 40 may have a dimension in the depth direction that is greater than that of the upper electrode portion 48 of the first electrode 40. Therefore, in the first insulating portion 54, the proportion of the portion having the first thickness T1b is greater than the proportion of the portion having the second thickness T1t.

[0049] The insulating layer 14 includes a second insulating portion 56 that extends between the second electrode 42 and the sidewall 20A of the gate trench 20. At least a portion of the second insulating portion 56 may be located between the body region 34 and the second electrode 42. The second insulating portion 56 has a thickness smaller than that of the first insulating portion 54. Specifically, the second insulating portion 56 has a thickness T2 between the second electrode 42 and the sidewall 20A, and the thickness T2 is smaller than both the first thickness T1b and the second thickness T1t of the first insulating portion 54.

[0050] The insulating layer 14 includes an inter-electrode insulating portion 58 extending between the first electrode 40 and the second electrode 42. The inter-electrode insulating portion 58 extends along the recess 52. The inter-electrode insulating portion 58 has a thickness smaller than that of the first insulating portion 54. Specifically, the inter-electrode insulating portion 58 has a thickness T3 between the upper surface 40A of the first electrode 40 and the recess 52 of the second electrode 42, and the thickness T3 is smaller than both the first thickness T1b and the second thickness T1t of the first insulating portion 54. The inter-electrode insulating portion 58 also has a thickness T4 between the side surface 48A of the upper electrode portion 48 and the recess 52 of the second electrode 42, and the thickness T4 is smaller than both the first thickness T1b and the second thickness T1t of the first insulating portion 54. The thickness T4 may be equal to the thickness T3. In this disclosure, the term "equal dimensions (including thickness, width, length, distance, etc.)" means that they are within a manufacturing variation range (for example, ±20%).

[0051] The inter-electrode insulating portion 58 can have a substantially uniform thickness and extend between the upper electrode portion 48 and the recess 52, so that the recess 52 can have a shape that follows a portion of the upper electrode portion 48 of the first electrode 40.

[0052] Furthermore, the inter-electrode insulating portion 58 may have the same thickness as the second insulating portion 56. Specifically, the thicknesses T3 and T4 of the inter-electrode insulating portion 58 may be equal to the thickness T2 of the second insulating portion 56.

[0053] The thicknesses T1b, T1t, T2, and T4 may be the dimensions of the respective portions of the insulating layer 14 in the width direction (Y-axis direction in the illustrated example) of the gate trench 20. On the other hand, the thickness T3 may be the dimension of the inter-electrode insulating portion 58 in the depth direction (Z-axis direction in the illustrated example).

[0054] In this way, the first insulating portion 54 may have a thickness greater than the second insulating portion 56 and the inter-electrode insulating portion 58 . (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing the semiconductor device 10 will be described with reference to Figures 4 to 14. Figures 4 to 14 are schematic cross-sectional views showing exemplary manufacturing steps for the semiconductor device 10. For ease of understanding, in Figures 4 to 14, the same components as those shown in Figures 1 to 3 are denoted by the same reference numerals.

[0055] As shown in FIG. 4 , the method for manufacturing the semiconductor device 10 includes forming a semiconductor layer 12. Forming the semiconductor layer 12 may include forming an epitaxial layer 62 on a semiconductor substrate 60. In one example, the semiconductor substrate 60 may be a Si substrate containing n-type impurities. The epitaxial layer 62 may be an n-type Si layer epitaxially grown on the semiconductor substrate 60 while being doped with n-type impurities. The semiconductor layer 12 includes a first surface 12A and a second surface 12B opposite the first surface 12A. The semiconductor substrate 60 may include the second surface 12B of the semiconductor layer 12, and the epitaxial layer 62 may include the first surface 12A of the semiconductor layer 12.

[0056] Fig. 5 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 4. As shown in Fig. 5, the manufacturing method for semiconductor device 10 includes forming a gate trench 20 having a sidewall 20A extending from first surface 12A into semiconductor layer 12. Gate trench 20 can be formed by selectively removing (e.g., etching) a portion of epitaxial layer 62.

[0057] Fig. 6 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 5. As shown in Fig. 6, the manufacturing method of the semiconductor device 10 includes forming a first insulating layer 64 on the first surface 12A of the semiconductor layer 12 and the sidewall 20A of the gate trench 20, and forming a first conductive layer 66 on the first insulating layer 64. The gate trench 20 is filled with the first insulating layer 64 formed along the sidewall 20A of the gate trench 20 and the first conductive layer 66 formed on the first insulating layer 64.

[0058] In one example, the first insulating layer 64 may include SiO2 formed by thermal oxidation. In another example, the first insulating layer 64 may be formed by chemical vapor deposition (CVD). The first conductive layer 66 may include conductive polysilicon.

[0059] Fig. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 6. As shown in Fig. 7, the manufacturing method of the semiconductor device 10 includes removing a portion of the first conductive layer 66. More specifically, by removing the portions of the first conductive layer 66 outside the gate trench 20 and in the upper part of the gate trench 20, the surface of the first conductive layer 66 becomes located midway in the depth direction of the gate trench 20.

[0060] Fig. 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 7. As shown in Fig. 8, the manufacturing method for the semiconductor device 10 includes removing a portion of the first insulating layer 64. More specifically, the surface portion of the first insulating layer 64 that was exposed in Fig. 7 is removed. As a result, the gap formed by the surface 64A of the first insulating layer 64 in the gate trench 20 has a width greater than that of the first conductor layer 66.

[0061] FIG. 9 is a schematic cross-sectional view illustrating a manufacturing step subsequent to the step illustrated in FIG. 8 . As illustrated in FIG. 9 , the manufacturing method for the semiconductor device 10 includes forming a second conductive layer 68 on a first conductive layer 66. The second conductive layer 68 may include conductive polysilicon. The second conductive layer 68 is embedded in a gap formed by the surface 64A of the first insulating layer 64 in the gate trench 20. Because the gap has a width greater than that of the first conductive layer 66, the second conductive layer 68 embedded in the gap also has a width greater than that of the first conductive layer 66. By forming the second conductive layer 68 having a width greater than that of the first conductive layer 66 on the first conductive layer 66, the first electrode 40 including the lower electrode portion 46 and the upper electrode portion 48 as illustrated in FIG. 2 can be formed.

[0062] 9. As shown in FIG. 10, the method for manufacturing the semiconductor device 10 includes partially removing the first insulating layer 64. The first insulating layer 64 is etched so that a surface 64A of the first insulating layer 64 is located below the upper surface 40A of the first electrode 40. This exposes the first surface 12A of the semiconductor layer 12, a portion of the sidewall 20A of the gate trench 20, and a portion of the side surface 48A of the upper electrode portion 48.

[0063] 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. 11, the manufacturing method for the semiconductor device 10 includes forming a second insulating layer 70. The second insulating layer 70 is formed along the first surface 12A of the semiconductor layer 12, a portion of the sidewall 20A of the gate trench 20, the surface 64A of the first insulating layer 64, a portion of the side surface 48A of the upper electrode portion 48, and the upper surface 40A of the first electrode 40. The profile of such second insulating layer 70 within the gate trench 20 can partially correspond to the shape of the second electrode 42 (e.g., the bottom surface 42B and the recess 52) as shown in FIG. 2.

[0064] 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 11. As shown in Fig. 12, the manufacturing method of the semiconductor device 10 includes forming a third conductive layer 72 on the second insulating layer 70. The third conductive layer 72 may include conductive polysilicon. The third conductive layer 72 is embedded in the upper part of the gate trench 20.

[0065] Fig. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 12. As shown in Fig. 13, the manufacturing method for semiconductor device 10 includes partially removing third conductive layer 72 to form second electrode 42. Third conductive layer 72 is removed so that upper surface 42A of second electrode 42 is located below first surface 12A of semiconductor layer 12 in the depth direction.

[0066] Fig. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in Fig. 13. As shown in Fig. 14, the manufacturing method of the semiconductor device 10 includes forming the body region 34 and the source region 36 in the semiconductor layer 12, and forming a third insulating layer 74 so as to cover the exposed second insulating layer 70 and the upper surface 42A of the second electrode 42.

[0067] The body region 34 and the source region 36 may be formed by ion implantation in the epitaxial layer 62 shown in Figure 13. Note that the drain region 30 corresponds to the semiconductor substrate 60 shown in Figure 13, and the drift region 32 corresponds to a part of the epitaxial layer 62 shown in Figure 13.

[0068] In one example, the third insulating layer 74 may be formed by a CVD method. The first insulating layer 64, the second insulating layer 70, and the third insulating layer 74 may constitute the insulating layer 14 shown in FIG.

[0069] After the process shown in FIG. 14, the semiconductor device 10 can be obtained by forming the contact region 44, the source contact plug 24, the drain electrode 38, the source wiring 18, and the gate wiring 16 (see FIGS. 1 and 2).

[0070] (Function of Semiconductor Device) The following describes the operation of the semiconductor device 10. The semiconductor device 10 includes a semiconductor layer 12 having a first surface 12A, a gate trench 20 having a sidewall 20A extending from the first surface 12A into the semiconductor layer 12, an insulating layer 14 located on the first surface 12A of the semiconductor layer 12 and covering the sidewall 20A of the gate trench 20, a first electrode 40 located in the gate trench 20, and a second electrode 42 located in the gate trench 20 and separated from the first electrode 40 by the insulating layer 14. In a depth direction intersecting with the first surface 12A, the second electrode 42 is located between the first electrode 40 and the first surface 12A.

[0071] The second electrode 42 embedded in the gate trench 20 faces the body region 34 of the semiconductor layer 12 via the insulating layer 14. When a predetermined voltage (e.g., a voltage equal to or greater than the gate threshold voltage) is applied to the second electrode 42, an inversion layer is formed in the body region 34 along the sidewall 20A of the gate trench 20. The inversion layer in the p-type body region 34 functions as a channel between the n-type source region 36 and the n-type drift region 32. This puts the semiconductor device 10 in an on state. On the other hand, when the voltage applied to the second electrode 42 is less than the gate threshold voltage, the semiconductor device 10 is in an off state in which no inversion layer is formed in the body region 34.

[0072] The electric field distribution in the semiconductor layer 12 in the off state affects the breakdown voltage of the semiconductor device 10. Specifically, localized electric field concentration in the semiconductor layer 12 can cause a decrease in the breakdown voltage of the semiconductor device 10. The electric field strength in the semiconductor layer 12 can have peaks at multiple positions along the sidewall 20A of the gate trench 20 due to various structural factors of the semiconductor device 10 (e.g., the pn junction interface between the body region 34 and the drift region 32, the shape of the first electrode 40, the thickness of the insulating layer 14 in the gate trench 20, etc.).

[0073] In this embodiment, the first electrode 40 includes a lower electrode portion 46 and an upper electrode portion 48 having a width greater than that of the lower electrode portion 46. This allows the electric field intensity in the semiconductor layer 12 to have additional peaks near the positions where the width of the first electrode 40 changes. Increasing the number of peaks of the electric field intensity in the semiconductor layer 12 compared to when the width of the first electrode 40 is relatively uniform makes it possible to alleviate local electric field concentrations in the semiconductor layer 12 (e.g., reduce the occurrence of abrupt changes in the electric field intensity). This can improve the breakdown voltage of the semiconductor device 10. Furthermore, alleviating the local electric field concentrations in the semiconductor layer 12 makes it possible to increase the impurity concentration of the semiconductor layer 12, thereby reducing the on-resistance, while maintaining the breakdown voltage of the semiconductor device 10.

[0074] Furthermore, the second electrode 42 includes a recess 52 and has a width greater than that of the upper electrode portion 48 of the first electrode 40. A portion of the upper electrode portion 48 of the first electrode 40 is located within the recess 52. This allows the area occupied by the first electrode 40 and the second electrode 42 in the gate trench 20 to be reduced in the depth direction. Therefore, by reducing the dimension of the gate trench 20 in the depth direction, the on-resistance of the semiconductor device 10 can be reduced.

[0075] The semiconductor device 10 according to the first embodiment has the following advantages. (1) The first electrode 40 includes a lower electrode portion 46 and an upper electrode portion 48 that has a width greater than that of the lower electrode portion 46. The second electrode 42 includes a recess 52 and has a width greater than that of the upper electrode portion 48 of the first electrode 40. A portion of the upper electrode portion 48 of the first electrode 40 is located within the recess 52.

[0076] This configuration increases the number of peaks of the electric field strength in the semiconductor layer 12 compared to when the width of the first electrode 40 is relatively uniform, thereby alleviating localized electric field concentration in the semiconductor layer 12. Furthermore, the area occupied by the first electrode 40 and the second electrode 42 in the gate trench 20 can be reduced in the depth direction, making it possible to reduce the dimension of the gate trench 20 in the depth direction. This therefore improves the breakdown voltage of the semiconductor device 10 and reduces the on-resistance.

[0077] (2) The recess 52 may have a shape that follows a part of the upper electrode portion 48 of the first electrode 40. This configuration allows the second electrode 42 and the first electrode 40 to be disposed close to each other, thereby reducing the on-resistance of the semiconductor device 10.

[0078] (3) The insulating layer 14 includes a first insulating portion 54 extending between the first electrode 40 and the sidewall 20A of the gate trench 20, a second insulating portion 56 extending between the second electrode 42 and the sidewall 20A of the gate trench 20, and an inter-electrode insulating portion 58 extending between the first electrode 40 and the second electrode 42. The first insulating portion 54 may have a thickness greater than the second insulating portion 56 and the inter-electrode insulating portion 58. With this configuration, the drift region 32 around the first insulating portion 54 can be depleted while the electric field can be alleviated, thereby improving the breakdown voltage of the semiconductor device 10.

[0079] (4) The lower electrode portion 46 of the first electrode 40 may have a dimension in the depth direction that is greater than that of the upper electrode portion 48 of the first electrode 40. With this configuration, the proportion of the first insulating portion 54 that has a relatively large thickness can be increased, thereby improving the breakdown voltage of the semiconductor device 10.

[0080] (5) The step surface 50 formed by the difference in width between the upper electrode portion 48 and the lower electrode portion 46 may be curved. This configuration can alleviate electric field concentration in the semiconductor layer 12, thereby improving the breakdown voltage of the semiconductor device 10.

[0081] <Example of changing the first electrode> Next, an exemplary semiconductor device 100 according to a modified example will be described with reference to Figures 15 and 16. Figure 15 is a schematic cross-sectional view of the semiconductor device 100. Figure 16 is an enlarged view of a portion of Figure 15. In Figures 15 and 16, components similar to those in the semiconductor device 10 are denoted by the same reference numerals. Detailed description of components similar to those in the semiconductor device 10 will be omitted.

[0082] 15, the semiconductor device 100 includes a first electrode 102 located in the gate trench 20, and a second electrode 42 located in the gate trench 20 and separated from the first electrode 102 by an insulating layer 14. In a depth direction (the Z-axis direction in the illustrated example) intersecting the first surface 12A, the second electrode 42 is located between the first electrode 102 and the first surface 12A. The first electrode 102 may be disposed so as to face at least the drift region 32 with the insulating layer 14 interposed therebetween. The second electrode 42 may be disposed so as to face at least the body region 34 with the insulating layer 14 interposed therebetween.

[0083] The first electrode 102 and the second electrode 42 may each include conductive polysilicon. In this embodiment, the first electrode 102 may be electrically connected to the second electrode 42. More specifically, the first electrode 102 and the second electrode 42 may be electrically connected to the gate wiring 16 (see FIG. 1).

[0084] 16, the first electrode 102 includes a lower electrode portion 104, an intermediate electrode portion 106, and an upper electrode portion 108. The upper electrode portion 108 has a width greater than that of the lower electrode portion 104. The intermediate electrode portion 106 has a width greater than that of the lower electrode portion 104 and smaller than that of the upper electrode portion 108.

[0085] The lower electrode portion 104, the intermediate electrode portion 106, and the upper electrode portion 108 have widths W1b, W1i, and W1t, respectively. Here, the width W1b of the lower electrode portion 104, the width W1i of the intermediate electrode portion 106, and the width W1t of the upper electrode portion 108 may be the dimensions of the lower electrode portion 104, the intermediate electrode portion 106, and the upper electrode portion 108 in the width direction of the gate trench 20 (the Y-axis direction in the illustrated example).

[0086] In the illustrated example, the lower electrode portion 104 may be adjacent to the intermediate electrode portion 106. The intermediate electrode portion 106 may be adjacent to the upper electrode portion 48. The first electrode 102 may include a first stepped surface 110 formed by a difference in width between the intermediate electrode portion 106 and the lower electrode portion 104, and a second stepped surface 112 formed by a difference in width between the upper electrode portion 108 and the intermediate electrode portion 106. In one example, the first stepped surface 110 and / or the second stepped surface 112 may be curved.

[0087] The second electrode 42 includes the recess 52 and has a width W2 that is larger than the upper electrode portion 108 of the first electrode 102. The width W2 of the second electrode 42 may be the dimension of the second electrode 42 in the width direction of the gate trench 20 (the Y-axis direction in the illustrated example).

[0088] The second electrode 42 includes an upper surface 42A and a bottom surface 42B. The recess 52 is formed in the bottom surface 42B of the second electrode 42. The recess 52 is recessed from the bottom surface 42B toward the upper surface 42A.

[0089] A part of the upper electrode portion 108 of the first electrode 102 is located within the recess 52. The first electrode 102 may include an upper surface 102A located between the bottom surface 42B of the second electrode 42 and the upper surface 42A of the second electrode 42 in the depth direction. The upper surface 102A of the first electrode 102 faces the recess 52 in the depth direction.

[0090] Additionally, the upper electrode portion 108 of the first electrode 102 includes a side surface 108 A. At least a part of the side surface 108 A of the upper electrode portion 108 may face the second electrode 42 with the insulating layer 14 interposed therebetween.

[0091] The boundary between the drift region 32 and the body region 34 may be located in the depth direction near the bottom surface 42B of the second electrode 42. In addition, the boundary between the drift region 32 and the body region 34 may be located in the depth direction between the bottom surface 42B and the top surface 42A. Furthermore, the boundary between the drift region 32 and the body region 34 may be located in the depth direction within the range in which the upper electrode portion 108 extends (i.e., between the top surface 102A of the first electrode 102 and the second step surface 112).

[0092] The boundary between the body region 34 and the source region 36 in the depth direction may be located near the top surface 42A of the second electrode 42. In addition, the boundary between the body region 34 and the source region 36 in the depth direction may be located between the bottom surface 42B and the top surface 42A.

[0093] The insulating layer 14 includes a first insulating portion 54 extending between the first electrode 102 and the sidewall 20A of the gate trench 20. The first insulating portion 54 has a first thickness T1b between the lower electrode portion 104 of the first electrode 102 and the sidewall 20A, a second thickness T1i between the middle electrode portion 106 of the first electrode 102 and the sidewall 20A, and a third thickness T1t between the upper electrode portion 108 and the sidewall 20A. Because the upper electrode portion 108 has a larger width than the middle electrode portion 106, the third thickness T1t is smaller than the second thickness T1i. Because the middle electrode portion 106 has a larger width than the lower electrode portion 104, the second thickness T1i is smaller than the first thickness T1b.

[0094] The insulating layer 14 includes a second insulating portion 56 extending between the second electrode 42 and the sidewall 20A of the gate trench 20. At least a portion of the second insulating portion 56 may be located between the body region 34 and the second electrode 42. The second insulating portion 56 has a thickness smaller than that of the first insulating portion 54. Specifically, the second insulating portion 56 has a thickness T2 between the second electrode 42 and the sidewall 20A, and the thickness T2 is smaller than any of the first thickness T1b, the second thickness T1i, and the third thickness T1t of the first insulating portion 54.

[0095] The insulating layer 14 includes an inter-electrode insulating portion 58 extending between the first electrode 102 and the second electrode 42. The inter-electrode insulating portion 58 extends along the recess 52. The inter-electrode insulating portion 58 has a thickness smaller than that of the first insulating portion 54. Specifically, the inter-electrode insulating portion 58 has a thickness T3 between the upper surface 40A of the first electrode 40 and the recess 52 of the second electrode 42, and the thickness T3 is smaller than the first thickness T1b, the second thickness T1i, and the third thickness T1t of the first insulating portion 54. The inter-electrode insulating portion 58 also has a thickness T4 between the side surface 108A of the upper electrode portion 108 and the recess 52 of the second electrode 42, and the thickness T4 is smaller than the first thickness T1b, the second thickness T1i, and the third thickness T1t of the first insulating portion 54. The thickness T4 may be equal to the thickness T3.

[0096] The inter-electrode insulating portion 58 can have a substantially uniform thickness and extend between the upper electrode portion 108 and the recess 52, so that the recess 52 can have a shape that follows a portion of the upper electrode portion 108 of the first electrode 102.

[0097] Furthermore, the inter-electrode insulating portion 58 may have the same thickness as the second insulating portion 56. Specifically, the thicknesses T3 and T4 of the inter-electrode insulating portion 58 may be equal to the thickness T2 of the second insulating portion 56.

[0098] The thicknesses T1b, T1t, T2, and T4 may be the dimensions of the respective portions of the insulating layer 14 in the width direction (Y-axis direction in the illustrated example) of the gate trench 20. On the other hand, the thickness T3 may be the dimension of the inter-electrode insulating portion 58 in the depth direction (Z-axis direction in the illustrated example).

[0099] In this way, the first insulating portion 54 may have a thickness greater than the second insulating portion 56 and the inter-electrode insulating portion 58 . In the semiconductor device 100 according to the modified example, the first electrode 102 includes a lower electrode portion 104, an intermediate electrode portion 106, and an upper electrode portion 108. The intermediate electrode portion 106 has a width greater than that of the lower electrode portion 104 but smaller than that of the upper electrode portion 108. This allows the electric field intensity in the semiconductor layer 12 to have two additional peaks near two positions where the width of the first electrode 102 changes. Increasing the number of peaks of the electric field intensity in the semiconductor layer 12 compared to that of the semiconductor device 10 makes it possible to further alleviate local electric field concentration in the semiconductor layer 12. This improves the breakdown voltage of the semiconductor device 100. Furthermore, alleviating the local electric field concentration in the semiconductor layer 12 allows the impurity concentration of the semiconductor layer 12 to be increased, reducing the on-resistance, while maintaining the breakdown voltage of the semiconductor device 100.

[0100] <Other change examples> The above embodiment can be modified as follows. 15 and 16, the first electrode 102 includes one intermediate electrode portion 106, but in another example, the first electrode 102 may include multiple intermediate electrode portions 106 having different widths located between the lower electrode portion 104 and the upper electrode portion 108. Each of the multiple intermediate electrode portions 106 has a width that is larger than the lower electrode portion 104 and smaller than the upper electrode portion 108. Furthermore, the multiple intermediate electrode portions 106 closer to the upper electrode portion 108 may have a larger width.

[0101] The first electrode 40 does not have to be electrically connected to the second electrode 42. More specifically, the first electrode 40 may be electrically connected to the source line 18 (see FIG. 1), and the second electrode 42 may be electrically connected to the gate line 16 (see FIG. 1).

[0102] 3, the step surface 50 is curved, but in another example, the step surface 50 may be flat. Similarly, in the example of FIG. 16, the first step surface 110 and the second step surface 112 are curved, but in another example, the first step surface 110 and / or the second step surface 112 may be flat.

[0103] 1, no trench is provided that intersects with the third gate wiring portion 16X in a plan view, but in another example, multiple trenches that intersect with the third gate wiring portion 16X in a plan view may be provided. Such trenches may correspond to the gate trench 20 shown in FIG. 1 rotated 90 degrees in a plan view.

[0104] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "A only, or B only, or both A and B."

[0105] The term "on" as used in this disclosure can mean both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer can be placed directly on the second layer in contact with the second layer, while in other embodiments, the first layer can be placed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0106] Directional terms such as "vertical," "horizontal," "upper," "lower," "top," "bottom," "front," "rear," "longitudinal," "lateral," "left," "right," "front," and "rear" used in this disclosure depend on the particular orientation of the device being described and illustrated. Various alternative orientations are contemplated in this disclosure, and therefore these directional terms should not be construed narrowly.

[0107] For example, the Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (e.g., the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described herein being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0108] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0109] (Appendix 1) a semiconductor layer (12) having a first surface (12A); a trench (20) having a sidewall (20A) extending from the first surface (12A) into the semiconductor layer (12); an insulating layer (14) located on the first surface (12A) of the semiconductor layer (12) and covering a sidewall (20A) of the trench (20); a first electrode (40) located within the trench (20); a second electrode (42) located within the trench (20) and separated from the first electrode (40) by the insulating layer (14); In a depth direction intersecting with the first surface (12A), the second electrode (42) is located between the first electrode (40) and the first surface (12A), The first electrode (40) includes a lower electrode portion (46) and an upper electrode portion (48) having a width greater than that of the lower electrode portion (46); the second electrode (42) includes a recess (52) and has a width greater than that of the upper electrode portion (48) of the first electrode (40); A semiconductor device, wherein a part of the upper electrode portion (48) of the first electrode (40) is located within the recess (52).

[0110] (Appendix 2) 2. The semiconductor device according to claim 1, wherein the recess (52) has a shape that follows a part of the upper electrode portion (48) of the first electrode (40).

[0111] (Appendix 3) The insulating layer (14) is a first insulating portion (54) extending between the first electrode (40) and a sidewall (20A) of the trench (20); a second insulating portion (56) extending between the second electrode (42) and the sidewall (20A) of the trench (20); an inter-electrode insulating portion (58) extending between the first electrode (40) and the second electrode (42); 3. The semiconductor device according to claim 1, wherein the first insulating portion (54) has a thickness greater than the second insulating portion (56) and the inter-electrode insulating portion (58).

[0112] (Appendix 4) 4. The semiconductor device according to claim 3, wherein the inter-electrode insulating portion (58) has a thickness equal to that of the second insulating portion (56).

[0113] (Appendix 5) 5. The semiconductor device according to claim 3, wherein the inter-electrode insulating portion (58) extends along the recess (52).

[0114] (Appendix 6) the second electrode (42) includes an upper surface (42A) and a bottom surface (42B), and the recess (52) is recessed from the bottom surface (42B) toward the upper surface (42A); The semiconductor device according to any one of Appendices 1 to 5, wherein the first electrode (40) includes an upper surface (40A) located between the bottom surface (42B) of the second electrode (42) and the upper surface (42A) of the second electrode (42) in the depth direction.

[0115] (Appendix 7) The semiconductor device according to any one of appendices 1 to 6, wherein the lower electrode portion (46) of the first electrode (40) has a dimension in the depth direction that is larger than the upper electrode portion (48) of the first electrode (40).

[0116] (Appendix 8) 8. The semiconductor device according to any one of claims 1 to 7, wherein the first electrode (40) is electrically connected to the second electrode (42).

[0117] (Appendix 9) The semiconductor device according to any one of appendices 1 to 8, wherein the first electrode (40) includes a step surface (50) formed by the difference in width between the upper electrode portion (48) and the lower electrode portion (46).

[0118] (Appendix 10) 10. The semiconductor device according to claim 9, wherein the step surface (50) is curved. (Appendix 11) The semiconductor device according to any one of appendices 1 to 10, wherein the first electrode (102) includes an intermediate electrode portion (106) located between the lower electrode portion (104) and the upper electrode portion (108), and the intermediate electrode portion (106) has a width that is larger than that of the lower electrode portion (46) and smaller than that of the upper electrode portion (48).

[0119] (Appendix 12) The semiconductor device described in Appendix 11, wherein the first electrode (102) includes a first step surface (110) formed by the difference in width between the intermediate electrode portion (106) and the lower electrode portion (104), and a second step surface (112) formed by the difference in width between the upper electrode portion (108) and the intermediate electrode portion (106).

[0120] (Appendix 13) The semiconductor device according to any one of appendices 1 to 10, wherein the first electrode (102) includes a plurality of intermediate electrode portions (106) having different widths and located between the lower electrode portion (104) and the upper electrode portion (108), each of the plurality of intermediate electrode portions (106) having a width greater than that of the lower electrode portion (104) and smaller than that of the upper electrode portion (108), and the width of the plurality of intermediate electrode portions (106) increases as they approach the upper electrode portion (108).

[0121] (Appendix 14) Further provided is a gate wiring (16) located on the insulating layer (14), 14. The semiconductor device according to any one of claims 1 to 13, wherein the first electrode (40) and the second electrode (42) are electrically connected to the gate wiring (16).

[0122] (Appendix 15) the semiconductor layer (12) includes a drift region (32) of a first conductivity type, a body region (34) of a second conductivity type located on the drift region (32), and a source region (36) of the first conductivity type located on the body region (34), the source region (36) including at least a portion of the first surface (12A) of the semiconductor layer (12); 15. The semiconductor device according to any one of claims 1 to 14, wherein the boundary between the drift region (32) and the body region (34) is located within a range in which the upper electrode portion (48) extends in the depth direction.

[0123] (Appendix 16) The semiconductor device according to any one of appendixes 1 to 15, wherein the upper electrode portion (48) of the first electrode (40) includes a side surface (48A), and at least a portion of the side surface (48A) of the upper electrode portion (48) faces the second electrode (42) via the insulating layer (14).

[0124] Various changes in form and detail may be made to the above-described examples without departing from the scope of the claims and their equivalents. The above-described examples are illustrative and not limiting. The description of a feature in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the sequential events are performed in a different order and / or if components within the described systems, architectures, devices, or circuits are combined in a different manner and / or replaced or supplemented by other components or their equivalents. The scope of the present disclosure is defined not by the detailed description, but by the claims and their equivalents. All variations within the scope of the claims and their equivalents are included herein. [Explanation of symbols]

[0125] 10,100...Semiconductor equipment 12...Semiconductor layer 12A…Side 1 12B…Second side 12X1,12X2,12Y1,12Y2…Side 14...Insulating layer 16...Gate wiring 16P...Gate pad 16Y1...First gate wiring section 16Y2...Second gate wiring section 16X...Third gate wiring section 18...Source wiring 18A...Inner source wiring section 18B...Outer source wiring section 20...Gate trench 20A...Side wall 22...Field plate trench 24...Source contact plug 26...Gate electrode contact plug 28...Field plate electrode contact plug 30...Drain region 32...Drift region 34...Body area 36...Source region 38...Drain electrode 40,102...1st electrode 40A, 102A…Top surface 42…Second electrode 42A…Top surface 42B...bottom 44...Contact area 46,104…lower electrode part 48,108...upper electrode part 48A, 108A…side 50...Step surface 52...recess 54...First insulating section 56...Second insulating section 58...Inter-electrode insulation part 60...Semiconductor substrate 62...Epitaxial layer 64...First insulating layer 64A…Surface 66...First conductive layer 68...Second conductive layer 70...Second insulating layer 72...Third conductive layer 74...Third insulating layer 106…Intermediate electrode part 110…1st step surface 112...2nd step surface W1b, W1i, W1t, W2...Width T1b, T1t, T2, T3, T4...Thickness

Claims

1. a semiconductor layer having a first surface; a trench having sidewalls extending from the first surface into the semiconductor layer; an insulating layer located on the first surface of the semiconductor layer and covering a sidewall of the trench; a first electrode located within the trench; a second electrode located in the trench and separated from the first electrode by the insulating layer; the second electrode is located between the first electrode and the first surface in a depth direction intersecting with the first surface, the first electrode includes a lower electrode portion and an upper electrode portion having a width greater than that of the lower electrode portion; the second electrode includes a recess and has a width greater than that of an upper electrode portion of the first electrode; A semiconductor device, wherein a portion of the upper electrode portion of the first electrode is located within the recess.

2. The semiconductor device according to claim 1 , wherein the recess has a shape that follows a part of the upper electrode portion of the first electrode.

3. The insulating layer is a first insulating portion extending between the first electrode and a sidewall of the trench; a second insulating portion extending between the second electrode and a sidewall of the trench; an inter-electrode insulating portion extending between the first electrode and the second electrode; 3. The semiconductor device according to claim 1, wherein the first insulating portion has a thickness greater than that of the second insulating portion and the inter-electrode insulating portion.

4. The semiconductor device according to claim 3 , wherein said inter-electrode insulating portion has a thickness equal to that of said second insulating portion.

5. The semiconductor device according to claim 3 , wherein said inter-electrode insulating portion extends along said recess.

6. the second electrode includes a top surface and a bottom surface, and the recess is recessed from the bottom surface toward the top surface; 3. The semiconductor device according to claim 1, wherein the first electrode includes an upper surface located between the bottom surface of the second electrode and the upper surface of the second electrode in the depth direction.

7. 3. The semiconductor device according to claim 1, wherein the lower electrode portion of the first electrode has a dimension in the depth direction greater than that of the upper electrode portion of the first electrode.

8. The semiconductor device according to claim 1 , wherein the first electrode is electrically connected to the second electrode.

9. 3. The semiconductor device according to claim 1, wherein said first electrode includes a stepped surface formed by a difference in width between said upper electrode portion and said lower electrode portion.

10. The semiconductor device according to claim 9 , wherein the step surface is curved.

11. 3. The semiconductor device according to claim 1, wherein the first electrode includes an intermediate electrode portion located between the lower electrode portion and the upper electrode portion, and the intermediate electrode portion has a width larger than that of the lower electrode portion and smaller than that of the upper electrode portion.

12. 12. The semiconductor device according to claim 11, wherein the first electrode includes a first step surface formed by a difference in width between the intermediate electrode portion and the lower electrode portion, and a second step surface formed by a difference in width between the upper electrode portion and the intermediate electrode portion.

13. 3. The semiconductor device according to claim 1, wherein the first electrode includes a plurality of intermediate electrode portions having different widths and located between the lower electrode portion and the upper electrode portion, each of the plurality of intermediate electrode portions having a width greater than that of the lower electrode portion and smaller than that of the upper electrode portion, and the intermediate electrode portions have a width greater the closer they are to the upper electrode portion.

14. further comprising a gate wiring located on the insulating layer; 3. The semiconductor device according to claim 1, wherein the first electrode and the second electrode are electrically connected to the gate wiring.

15. the semiconductor layer includes a drift region of a first conductivity type, a body region of a second conductivity type located on the drift region, and a source region of the first conductivity type located on the body region, the source region including at least a portion of the first surface of the semiconductor layer; 3. The semiconductor device according to claim 1, wherein the boundary between said drift region and said body region is located within a range in which said upper electrode portion extends in said depth direction.

16. 3 . The semiconductor device according to claim 1 , wherein the upper electrode portion of the first electrode includes a side surface, and at least a part of the side surface of the upper electrode portion faces the second electrode with the insulating layer interposed therebetween.

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