Manufacturing method for thin-film transistor substrate, and thin-film transistor substrate

Abstract

To realize both anti-static measures and anti-corrosion measures.SOLUTION: A manufacturing method for a thin-film transistor substrate comprises: forming, on a substrate, a first conductive layer 12 that crosses a planned cutting plane after manufacturing and functions as a short ring; forming a first insulating layer 13 on the first conductive layer and on a substrate on which the first conductive layer is not formed, forming contact holes at locations at least a certain distance away from the cutting plane in two opposite directions in the first insulating layer formed on the first conductive layer, and forming an opening part in the first insulating layer at least above a portion of the first conductive layer that crosses the cutting plane; forming, on the first insulating layer, a second conductive layer 14 that conducts to the first conductive layer through the contact holes, crosses the cutting plane, and functions as a short ring different from the short ring, and further removing a portion of the first conductive layer below the opening part; and forming a second insulating layer that fills at least a space opened by the removal.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a thin film transistor substrate and a thin film transistor substrate. [Background technology]

[0002] In the manufacturing process of thin-film transistor substrates used in liquid crystal display devices, etc., a common method is to connect adjacent elements (for example, elements corresponding to individual display panels) with metal wiring called a short ring so that each element is at the same potential, in order to prevent element destruction due to static electricity sparks caused by charging. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-295214 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-210713 Summary of the Invention [Problem to be solved by the invention]

[0004] In order to ensure thorough countermeasures against static electricity, it is desirable to have the above-mentioned short ring continuously present throughout the entire manufacturing process of the thin film transistor substrate, specifically from the stage of forming the first layer on the glass substrate to the stage of separating each element at the end. However, after separating each element at the final stage, the cross section of the wiring carrying the short ring is exposed, and depending on the type of metal used for the wiring, there is a concern that corrosion may occur from that cross section.

[0005] An object of the present invention is to provide a method for manufacturing a thin film transistor substrate and a thin film transistor substrate that can provide both anti-static and anti-corrosion measures. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a method for manufacturing a thin film transistor substrate, including the steps of: forming a first conductive layer on a substrate, the first conductive layer crossing a cut surface along which cutting is planned after manufacturing and functioning as a short ring; forming a first insulating layer on the first conductive layer and on a portion of the substrate on which the first conductive layer is not formed, and forming contact holes in the first insulating layer formed on the first conductive layer at locations that are at least a certain distance from the cut surface in two opposite directions, and forming an opening in the first insulating layer at least above a portion of the first conductive layer that crosses the cut surface; forming a second conductive layer on the first insulating layer, the second conductive layer being electrically connected to the first conductive layer through the contact hole, crossing the cut surface, and functioning as a short ring different from the short ring; further removing a portion of the first conductive layer below the opening; and forming a second insulating layer to fill at least a space opened by the removal.

[0007] According to another aspect of the present invention, there is provided a thin film transistor substrate manufactured by the method for manufacturing a thin film transistor substrate. [Effects of the Invention]

[0008] According to the present invention, it is possible to achieve both measures against static electricity and measures against corrosion. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a conceptual diagram showing a schematic configuration of a thin film transistor substrate according to the first and second embodiments. [Figure 2] FIG. 2 is a top view showing the shape of the first conductive layer 12 formed on the glass substrate 11. As shown in FIG. [Figure 3] FIG. 3 is a cross-sectional view showing a cross-sectional shape taken along the line III-III in FIG. [Figure 4]Figure 4 is a top view showing the shape when a first insulating layer 13 is formed on the first conductive layer 12 shown in Figures 2 and 3 and on a glass substrate 11 on which the first conductive layer 12 is not formed. [Figure 5] FIG. 5 is a cross-sectional view showing a cross-sectional shape taken along the line VV in FIG. [Figure 6] Figure 6 is a top view showing the shape when a second conductive layer 14 that functions as a short ring different from the short ring realized by the first conductive layer 12 is formed on the first insulating layer 13 shown in Figures 4 and 5, and a portion of the first conductive layer 12 below the opening 13H is further removed. [Figure 7] FIG. 7 is a cross-sectional view showing a cross-sectional shape taken along the line VII-VII in FIG. [Figure 8] FIG. 8 is a top view showing the shape when second insulating layer 15 is formed so as to fill space 13S shown in FIGS. 6 and 7 and to entirely cover each layer that has already been formed from above. [Figure 9] FIG. 9 is a cross-sectional view showing a cross-sectional shape taken along the line IX-IX in FIG. [Figure 10] FIG. 10 is a cross-sectional view showing a cross-sectional shape taken along the line XX in FIG. [Figure 11] FIG. 11 is a top view showing the shape of the first conductive layer 12 formed on the glass substrate 11. As shown in FIG. [Figure 12] FIG. 12 is a cross-sectional view showing a cross-sectional shape taken along the line XII-XII in FIG. [Figure 13] Figure 13 is a top view showing the shape when a first insulating layer 13 is formed on the first conductive layer 12 shown in Figures 11 and 12 and on a glass substrate 11 on which the first conductive layer 12 is not formed. [Figure 14] 14 is a cross-sectional view showing a cross-sectional shape taken along the line XIV-XIV in FIG. [Figure 15] Figure 15 is a top view showing the shape when a second conductive layer 16 that functions as a separate short ring different from the short ring realized by the first conductive layer 12 is formed on the first insulating layer 13 shown in Figures 13 and 14. [Figure 16] 16 is a cross-sectional view showing a cross-sectional shape taken along the line XVI-XVI in FIG. [Figure 17] Figure 17 is a top view showing the shape when a third conductive layer 17 is formed on the first insulating layer 13 shown in Figures 15 and 16 at a location away from the second conductive layer 16, and a portion of the first conductive layer 12 below the opening 13H is further removed. [Figure 18] FIG. 18 is a cross-sectional view showing a cross-sectional shape taken along the line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a top view showing the shape when the second insulating layer 18 is formed so as to fill the space 13S shown in FIGS. 17 and 18 and to entirely cover the layers that have already been formed from above. [Figure 20] FIG. 20 is a cross-sectional view showing a cross-sectional shape taken along the line XX-XX in FIG. [Figure 21] FIG. 21 is a cross-sectional view showing a cross-sectional shape taken along the arrows XXI-XXI in FIG. [Figure 22] 22 is a cross-sectional view showing a cross-sectional shape taken along the line XXII-XXII in FIG. [Figure 23] 23 is a cross-sectional view showing a cross-sectional shape taken along the line XXIII-XXIII in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, an embodiment will be described with reference to the drawings.

[0011] First Embodiment First, the first embodiment will be described.

[0012] Fig. 1 is a conceptual diagram showing a schematic configuration of a thin film transistor substrate according to the first embodiment. The configuration of the thin film transistor substrate shown in Fig. 1 is also applied to a second embodiment described later.

[0013] 1 is manufactured, for example, during the manufacturing process of a liquid crystal display device, and has elements 2 corresponding to a plurality of display areas (or panels) arranged on a glass substrate, and short rings 3 connecting adjacent elements 2. Each element 2 is formed by patterning individual layers that make up a TFT (Thin Film Transistor).

[0014] 1 also shows a cut line CL, which indicates the position of the cutting plane when the thin film transistor substrate 1 is finally cut into four elements 2.

[0015] Note that the configuration example shown in Fig. 1 is just an example, and is not limited to the shape and size shown in Fig. 1. For example, the position at which the short ring 3 is connected is not limited to the position shown in Fig. 1, and it may be connected at a position near each corner of each element 2, for example.

[0016] 2 to 10, the method for manufacturing the thin film transistor substrate according to the first embodiment will be described in order of manufacturing steps. To avoid complicating the description, the description will focus on one short ring 3 and parts of the elements 2 on both sides of the short ring 3 in FIG. 1.

[0017] Step A1: Formation of the first conductive layer 12 Fig. 2 is a top view showing the shape of the first conductive layer 12 formed on the glass substrate 11. Fig. 3 is a cross-sectional view showing the cross-sectional shape as seen from the arrow III-III in Fig. 2. The position of the dashed dotted line indicated by the arrow III-III corresponds to the position of the cut line CL described above.

[0018] 2 and 3, a first conductive layer 12 that crosses the cutting plane planned for cutting after manufacturing and functions as a short ring is formed on a glass substrate 11. The first conductive layer 12 is made of a metal that corrodes relatively easily, and is formed of Al, AlNd, or Cu.

[0019] Step A2: Formation of the first insulating layer 13 Fig. 4 is a top view showing the shape when a first insulating layer 13 is formed on the first conductive layer 12 shown in Fig. 2 and Fig. 3 and on the glass substrate 11 on which the first conductive layer 12 is not formed. Fig. 5 is a cross-sectional view showing the cross-sectional shape as seen in the direction of arrows VV in Fig. 4. The position of the dashed dotted line shown as seen in the direction of arrows VV corresponds to the position of the cut line CL described above.

[0020] Specifically, as shown in Figures 4 and 5, a first insulating layer 13 is formed on the first conductive layer 12 shown in Figures 2 and 3 and on a glass substrate 11 on which the first conductive layer 12 is not formed, and contact holes CH are formed in the first insulating layer 13 formed on the first conductive layer 12 at locations that are at least a certain distance away from the cut surface in two opposite directions, and an opening 13H is formed in the first insulating layer 13 at least above a portion of the first conductive layer 12 that crosses the cut surface.

[0021] Here, the opening 13H is formed not only above a portion of the first conductive layer 12 but also on a portion of both short side surfaces of the first conductive layer 12. In this way, the portion of the first conductive layer 12 below the opening 13H can be reliably removed without leaving any residue in the etching process described below.

[0022] Step A3: Forming the second conductive layer 14 and removing a portion of the first conductive layer 12 Fig. 6 is a top view showing the shape when a second conductive layer 14 that functions as a short ring different from the short ring realized by the first conductive layer 12 is formed on the first insulating layer 13 shown in Fig. 4 and Fig. 5, and a part of the first conductive layer 12 below the opening 13H is further removed. Fig. 7 is a cross-sectional view showing the cross-sectional shape along arrow VII-VII in Fig. 6. The position of the dashed dotted line indicated by arrow VII-VII corresponds to the position of the cut line CL described above.

[0023] 6 and 7, a second conductive layer 14 is formed on the first insulating layer 13 shown in FIGS. 4 and 5. The second conductive layer 14 is electrically connected to the first conductive layer 12 through the contact hole CH, crosses the cut surface, and functions as a short ring different from the short ring realized by the first conductive layer 12. At this time, a portion of the second conductive layer 14 is filled in the contact hole CH, forming a contact 14C that is electrically connected to the first conductive layer 12. The second conductive layer 14 is made of a material that is less susceptible to corrosion than the first conductive layer 12. In this example, the second conductive layer 14 is made of MoNb or MoTa.

[0024] Furthermore, the portion of the first conductive layer 12 below the opening 13H is removed (peeled off) using an etching solution, and a space 13S is generated in the portion of the first conductive layer 12 that has been removed.

[0025] The removal of a portion (unnecessary portion) of the second conductive layer 14 when forming it and the removal of a portion of the first conductive layer 12 can be carried out simultaneously using the same etching solution.

[0026] As a result, the second conductive layer 14 functions as a short ring instead of the first conductive layer 12 which has previously functioned as a short ring. In other words, the effective short ring is switched.

[0027] Step A4: Formation of second insulating layer 15 Fig. 8 is a top view showing the shape when second insulating layer 15 is formed to fill space 13S shown in Figs. 6 and 7 and completely cover each layer that has already been formed from above. Fig. 9 is a cross-sectional view showing the cross-sectional shape as seen from arrow IX-IX in Fig. 8. The position of the dashed dotted line indicated by arrow IX-IX corresponds to the position of the cut line CL described above. Fig. 10 is a cross-sectional view showing the cross-sectional shape as seen from arrow XX in Fig. 8.

[0028] 8 to 10, a second insulating layer 15 is formed on the glass substrate 11 where the first insulating layer 13 is not formed so as to fill the space 13S shown in Figures 6 and 7, and the second insulating layer 15 is also formed on the second conductive layer 14 and on the first insulating layer 13 where the second conductive layer 14 is not formed, so that the second insulating layer 15 entirely covers each layer from above. As a result, a portion 15C of the second insulating layer 15 is filled in the area where the space 13S was previously.

[0029] Although detailed description is omitted here, in addition to the above-mentioned steps, there are various other steps, such as a step of forming a semiconductor layer, a step of forming an ITO (Indium Tin Oxide) conductive layer, etc. For example, when a layer similar to the first conductive layer 12 is separately formed, the short ring can be switched in the same manner as above.

[0030] The individual conductive layers described above are connected to the portions corresponding to the gate, source, or drain of the TFT in the display area through protective elements (not shown).

[0031] As described above, according to the first embodiment, by manufacturing the thin film transistor substrate 1 using the above-described method, the short ring can be continuously present from the beginning to the end of the manufacturing process of the thin film transistor substrate 1, thereby providing thorough measures against static electricity.

[0032] Furthermore, according to the first embodiment, when the thin film transistor substrate 1 manufactured by the above-described method is cut along the above-described cut line CL, the cross section of the first conductive layer 12 is not exposed, as can be seen from the cross-sectional view of Fig. 9. This makes it possible to prevent corrosion of the cross section of the first conductive layer 12. On the other hand, although the cross section of the second conductive layer 14 is exposed, corrosion can be suppressed because the second conductive layer 14 is made of a metal that is resistant to corrosion.

[0033] <Second embodiment> Next, a second embodiment will be described, focusing on the differences from the first embodiment.

[0034] The configuration of the thin film transistor substrate according to the second embodiment is the same as that shown in Fig. 1. Fig. 1 is a conceptual diagram showing.

[0035] Hereinafter, the method for manufacturing the thin film transistor substrate according to the second embodiment will be described in order of manufacturing steps with reference to FIGS.

[0036] Step B1: Formation of the first conductive layer 12 Fig. 11 is a top view showing the shape of the first conductive layer 12 formed on the glass substrate 11. Fig. 12 is a cross-sectional view showing the cross-sectional shape taken along the line XII-XII in Fig. 11. The position of the dashed dotted line indicated by the line XII-XII corresponds to the position of the cut line CL described above.

[0037] 11 and 12, a first conductive layer 12 is formed on a glass substrate 11 to cross the cutting plane where cutting is planned after manufacturing and to function as a short ring. From this point on, the first conductive layer 12 functions as a short ring. In this example, the first conductive layer 12 is made of a metal that corrodes relatively easily, and is formed of Al, AlNd, or Cu.

[0038] Step B2: Formation of the first insulating layer 13 Fig. 13 is a top view showing the shape when a first insulating layer 13 is formed on the first conductive layer 12 shown in Fig. 11 and Fig. 12 and on the glass substrate 11 on which the first conductive layer 12 is not formed. Fig. 14 is a cross-sectional view showing the cross-sectional shape taken along the line XIV-XIV in Fig. 13. The position of the dashed dotted line indicated by the line XIV-XIV corresponds to the position of the cut line CL described above.

[0039] Specifically, as shown in Figures 13 and 14, a first insulating layer 13 is formed on the first conductive layer 12 shown in Figures 11 and 12 and on a glass substrate 11 on which the first conductive layer 12 is not formed, and contact holes CH are formed in the first insulating layer 13 formed on the first conductive layer 12 at locations that are at least a certain distance away from the cut surface in two opposite directions, and an opening 13H is formed in the first insulating layer 13 at least above a portion of the first conductive layer 12 that crosses the cut surface.

[0040] Here, the opening 13H is formed not only above a portion of the first conductive layer 12 but also on a portion of both short side surfaces of the first conductive layer 12. In this way, the portion of the first conductive layer 12 below the opening 13H can be reliably removed without leaving any residue in the etching process described below.

[0041] Step B3: Formation of the second conductive layer 16 Fig. 15 is a top view showing the shape when a second conductive layer 16 that functions as a short ring different from the short ring realized by the first conductive layer 12 is formed on the first insulating layer 13 shown in Fig. 13 and Fig. 14. Fig. 16 is a cross-sectional view showing the cross-sectional shape taken along the arrow XVI-XVI in Fig. 15. The position of the dashed dotted line indicated by the arrow XVI-XVI corresponds to the position of the cut line CL described above.

[0042] 15 and 16, a second conductive layer 16 is formed on the first insulating layer 13 shown in FIGS. 13 and 14. The second conductive layer 16 is electrically connected to the first conductive layer 12 through the contact hole CH, crosses the cut surface, and functions as a short ring different from the short ring realized by the first conductive layer 12. At this time, a portion of the second conductive layer 16 is filled in the contact hole CH, forming a contact 16C that is electrically connected to the first conductive layer 12. The second conductive layer 16 is made of a material that is less susceptible to corrosion than the first conductive layer 12. In this example, the second conductive layer 16 is made of ITO.

[0043] Furthermore, the portion of the first conductive layer 12 below the opening 13H is removed (peeled off) using an etching solution, and a space 13S is generated in the portion of the first conductive layer 12 that has been removed.

[0044] In addition, when removing a portion (unnecessary portion) of the second conductive layer 16, an etching liquid different from the etching liquid used to remove a portion of the first conductive layer 12 is used.

[0045] As a result, the second conductive layer 16 functions as a short ring instead of the first conductive layer 12 which has previously functioned as a short ring. In other words, the effective short ring is switched.

[0046] Step B4: Forming the third conductive layer 17 and removing a portion of the first conductive layer 12 Fig. 17 is a top view showing the shape when a third conductive layer 17 that does not cross the cut plane is formed on the first insulating layer 13 shown in Fig. 15 and Fig. 16 at a location away from the second conductive layer 16, and a portion of the first conductive layer 12 below the opening 13H is further removed. Fig. 18 is a cross-sectional view showing the cross-sectional shape taken along arrows XVIII-XVIII in Fig. 17. The position of the dashed dotted line indicated by the arrows XVIII-XVIII corresponds to the position of the cut line CL described above.

[0047] 17 and 18, a third conductive layer 17 is formed on the first insulating layer 13 shown in FIGS. 15 and 16 at a location away from the second conductive layer 16 so as not to cross the cut surface. The third conductive layer 17 is made of the same material as the first conductive layer 12. That is, the third conductive layer 17 is made of a metal that corrodes relatively easily, such as Al, AlNd, or Cu.

[0048] Furthermore, the portion of the first conductive layer 12 below the opening 13H is removed (peeled off) using an etching solution, and a space 13S is generated in the portion of the first conductive layer 12 that has been removed.

[0049] The removal of a portion (unnecessary portion) of third conductive layer 17 when forming it and the removal of a portion of first conductive layer 12 can be carried out simultaneously using the same etching solution.

[0050] Step B5: Formation of second insulating layer 18 FIG. 19 is a top view showing the shape when a second insulating layer 18 is formed to fill the space 13S shown in FIGS. 17 and 18 and completely cover the previously formed layers from above. FIG. 20 is a cross-sectional view showing the cross-sectional shape taken along the line XX-XX in FIG. 19. The position of the dashed dotted line indicated by the line XX-XX corresponds to the position of the cut line CL described above. FIG. 21 is a cross-sectional view showing the cross-sectional shape taken along the line XXI-XXI in FIG. 19. FIG. 22 is a cross-sectional view showing the cross-sectional shape taken along the line XXII-XXII in FIG. 19. FIG. 23 is a cross-sectional view showing the cross-sectional shape taken along the line XXIII-XXIII in FIG. 19.

[0051] 19 to 23, a second insulating layer 18 is formed on the glass substrate 11 where the first insulating layer 13 is not formed so as to fill the space 13S shown in Figures 17 and 18, and the second insulating layer 18 is also formed on the second conductive layer 16 and the third conductive layer 17 and on the first insulating layer 13 where the second conductive layer 16 and the third conductive layer 17 are not formed, so that the second insulating layer 18 entirely covers each layer from above. As a result, a portion 18C of the second insulating layer 18 is filled in the area where the space 13S was previously.

[0052] Although detailed description will be omitted here, in addition to the above-mentioned steps, there are various other steps such as a step of forming a semiconductor layer.

[0053] The individual conductive layers described above are connected to the portions corresponding to the gate, source, or drain of the TFT in the display area through protective elements (not shown).

[0054] In the manufacturing process of a TFT, for example, if 1) gate, 2) semiconductor layer, 3) pixel electrode, 4) source / drain, 5) contact hole, and 6) common electrode are formed in this order, the materials used to form these are A) metal, B) silicon, C) ITO, D) metal, E) silicon nitride film, and F) ITO, respectively.

[0055] The first conductive layer 12 corresponds to the gate of the TFT, and the third conductive layer 17 corresponds to the source or drain of the TFT. In this case, for example, an inverted staggered TFT can be formed. However, this is not limiting, and for example, the first conductive layer 12 may correspond to the source or drain of the TFT, and the third conductive layer 17 may correspond to the gate of the TFT. In this case, for example, a planar TFT can be formed.

[0056] As described above, according to the second embodiment, by manufacturing the thin film transistor substrate 1 using the above-mentioned method, the short ring can be continuously present from the beginning to the end of the manufacturing process of the thin film transistor substrate 1, thereby providing thorough measures against static electricity.

[0057] Furthermore, according to the second embodiment, when the thin film transistor substrate 1 manufactured by the above-described method is cut along the above-described cut line CL, the cross section of the first conductive layer 12 is not exposed, as can be seen from the cross-sectional view of FIG. 20 . The cross section of the third conductive layer 17 is also not exposed. Therefore, corrosion of the cross section of the first conductive layer 12 can be prevented, and corrosion of the cross section of the third conductive layer 17 can also be prevented. On the other hand, although the cross section of the second conductive layer 16 is exposed, corrosion can be suppressed because the second conductive layer 16 is made of ITO, which is resistant to corrosion.

[0058] The present invention is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit of the invention. Furthermore, the embodiments may be implemented in appropriate combinations, in which case the combined effects can be obtained. Furthermore, the above-described embodiments include various inventions, and various inventions can be extracted by combining selected elements from the disclosed elements. For example, if the problem can be solved and the desired effect can be obtained even if some elements are deleted from all elements shown in the embodiments, the configuration from which these elements are deleted can be extracted as an invention. [Explanation of symbols]

[0059] 1...thin film transistor substrate, 2...element (display area), 3...short ring, 11...glass substrate, 12...first conductive layer, 13...first insulating layer, 13H...opening, 13S...space, 14...second conductive layer, 14C...contact, 15...second insulating layer, 15C...part of the second insulating layer, 16...second conductive layer, 16C...contact, 17...third conductive layer, 18...second insulating layer, 18C...part of the second insulating layer, CH...contact hole.

Claims

1. forming a first conductive layer on a substrate, the first conductive layer crossing a cutting plane along which cutting is planned after manufacturing and functioning as a short ring; forming a first insulating layer on the first conductive layer and on the substrate on which the first conductive layer is not formed, forming contact holes in the first insulating layer formed on the first conductive layer at locations that are at least a certain distance away from the cut surface in two opposite directions, and forming an opening in the first insulating layer at least above a portion of the first conductive layer that crosses the cut surface; forming a second conductive layer on the first insulating layer, the second conductive layer being electrically connected to the first conductive layer through the contact hole, crossing the cut surface, and functioning as another short ring different from the short ring; removing a portion of the first conductive layer below the opening; forming a second insulating layer that fills at least the space opened by the removal; A method for manufacturing a thin film transistor substrate, comprising:

2. the second conductive layer is formed of a material that is less susceptible to corrosion than the first conductive layer; The method for manufacturing the thin film transistor substrate according to claim 1 .

3. the second conductive layer is formed of MoNb or MoTa; The method for manufacturing the thin film transistor substrate according to claim 1 .

4. The second conductive layer is formed of ITO. The method for manufacturing a thin film transistor substrate according to claim 2 .

5. The method further includes forming a third conductive layer on the first insulating layer at a location away from the second conductive layer and not across the cutting plane. The method for manufacturing the thin film transistor substrate according to claim 1 .

6. the first conductive layer and the third conductive layer are formed of the same material; The method for manufacturing a thin film transistor substrate according to claim 5 .

7. the first conductive layer corresponds to a gate of a TFT; the third conductive layer corresponds to the source or drain of the TFT; The method for manufacturing a thin film transistor substrate according to claim 5 .

8. the first conductive layer corresponds to a source or a drain of a TFT, the third conductive layer corresponds to the gate of the TFT; The method for manufacturing a thin film transistor substrate according to claim 5 .

9. A thin film transistor substrate manufactured by the method for manufacturing a thin film transistor substrate according to any one of claims 1 to 8.

Images