Semiconductor device

Abstract

To provide a semiconductor device with electric characteristics improved.SOLUTION: A semiconductor device 1 includes a substrate 10, an electron transit layer 22 provided over the substrate 10, a threshold adjustment layer 28 provided over the electron transit layer 22, a gate electrode 32 provided on an upper surface of the threshold adjustment layer 28, a source electrode 34 electrically connected to the electron transit layer and provided apart from the threshold adjustment layer 28 and the gate electrode 32, a drain electrode 36 provided below the substrate 10, and a reflection layer 70 including Ag or Al and provided over the gate electrode 32. In a plan view of the substrate 10, an element region that contributes to the modulation operation and an element separation region including a pad to which a wire for feeding power to at least one of the gate electrode 32, the source electrode 34, and the drain electrode 36 is connected are provided. The reflection layer 70 is provided in the element region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Nitride semiconductors, typified by GaN, are wide-gap semiconductors characterized by a large breakdown field and a high saturated drift velocity of electrons. For example, the band gaps of GaN and AlN are 3.4 eV and 6.2 eV, respectively, at room temperature. For this reason, research and development of power transistors using nitride semiconductors, which are advantageous for achieving high output and high voltage resistance, is currently being actively conducted.

[0003] Furthermore, compound semiconductors such as GaN and GaAs are direct transition semiconductors, which means they have high light generation efficiency. This makes them useful for light-emitting devices. The emission wavelength depends on the band gap; for example, GaN emits ultraviolet light (approximately 365 nm), while GaAs emits infrared light (approximately 885 nm).

[0004] As semiconductor devices using GaN or the like, for example, Patent Documents 1 and 2 disclose field effect transistors (FETs) having an AlGaN / GaN heterostructure. Non-Patent Document 1 also discloses a technique for forming a transistor and a Schottky light emitting diode (LED) on the same wafer.

[0005] In addition, in devices with an AlGaN / GaN heterostructure, spontaneous polarization and piezoelectric polarization on the (0001) plane generate a high concentration of two-dimensional electron gas (2DEG) near the heterointerface. Therefore, even in an undoped state, a high concentration of 1×10 13 cm -2 The sheet carrier concentration can be obtained as high as 1000 ppm or more. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 7195306 [Patent Document 2] Japanese Patent Application Publication No. 2014-222724 [Non-patent literature]

[0007] [Non-Patent Document 1] Baikui Li et al., “Optical pumping of deep traps in AlGaN / GaN-on-Si HEMTs using an on-chip Schottky-on-heterojunction light-emitting diode”, Applied Physics Letters, March 2015, Vol. 106, Issue 9 Summary of the Invention [Problem to be solved by the invention]

[0008] Conventional semiconductor devices have room for improvement in electrical properties such as resistance or current flow.

[0009] Thus, the present disclosure provides a semiconductor device with improved electrical properties. [Means for solving the problem]

[0010] A semiconductor device according to one embodiment of the present disclosure comprises a substrate, a first semiconductor layer provided above the substrate, a p-type semiconductor layer provided above the first semiconductor layer, a gate electrode provided on an upper surface of the p-type semiconductor layer, a source electrode electrically connected to the first semiconductor layer and provided at a distance from the p-type semiconductor layer and the gate electrode, a drain electrode provided below the substrate, and a reflective layer containing Ag or Al and provided above the gate electrode, wherein, in a planar view of the substrate, an element region contributing to modulation operation and an element isolation region in which a pad to which a wire for supplying power to at least one of the gate electrode, the source electrode, and the drain electrode is connected is provided, and the reflective layer is provided in the element region.

[0011] A semiconductor device according to another aspect of the present disclosure includes a substrate, a first semiconductor layer provided above the substrate, a p-type semiconductor layer provided above the first semiconductor layer, an anode electrode provided on an upper surface of the p-type semiconductor layer, a cathode electrode provided below the substrate, and a reflective layer provided above the anode electrode, wherein, in a planar view of the substrate, an element region contributing to rectification operation and an element isolation region in which a pad to which a wire for supplying power to at least one of the anode electrode and the cathode electrode is connected is provided, and the reflective layer is provided in the element region.

[0012] A semiconductor device according to another embodiment of the present disclosure comprises a substrate, a first semiconductor layer provided above the substrate, a p-type semiconductor layer provided above the first semiconductor layer, a first electrode provided on an upper surface of the p-type semiconductor layer, a second electrode electrically connected to the first semiconductor layer and provided at a distance from the p-type semiconductor layer and the first electrode, and a reflective layer provided above the first electrode, wherein, in a planar view of the substrate, an element region including a main path of current flowing through the first semiconductor layer and an element isolation region in which a pad to which a wire for supplying power to at least one of the first electrode and the second electrode is connected is provided, and the main path does not pass through the substrate, and the reflective layer is provided in the element region. [Effects of the Invention]

[0013] According to the present disclosure, a semiconductor device with improved electrical characteristics can be provided. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2A] FIG. 2A is a cross-sectional view for explaining a problem with a semiconductor device according to a comparative example. [Figure 2B] FIG. 2B is a cross-sectional view for explaining the effect of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a diagram showing the wavelength dependence of the reflection coefficient of a metal. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view of a semiconductor device according to the second modification of the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 7A] FIG. 7A is a cross-sectional view of a semiconductor device according to a modification of the second embodiment. [Figure 7B] FIG. 7B is a cross-sectional view of a semiconductor device according to another modification of the second embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a semiconductor device according to the third embodiment. [Figure 9A] FIG. 9A is a cross-sectional view of a semiconductor device according to a modification of the third embodiment. [Figure 9B] FIG. 9B is a cross-sectional view of a semiconductor device according to another modification of the third embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device according to the fourth embodiment. [Figure 11] FIG. 11 is a cross-sectional view of a semiconductor device according to a first modification of the fourth embodiment. [Figure 12]FIG. 12 is a cross-sectional view of a semiconductor device according to the second modification of the fourth embodiment. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to a third modification of the fourth embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a semiconductor device according to the fifth embodiment. [Figure 15] FIG. 15 is a cross-sectional view of a semiconductor device according to a modification of the fifth embodiment. [Figure 16A] FIG. 16A is a top view of the semiconductor device according to the first embodiment. [Figure 16B] FIG. 16B is a top view of the semiconductor device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] (Findings that formed the basis of this disclosure) Table 1 below shows the sheet resistance and on-resistance of the two-dimensional electron gas when a vertical transistor having an AlGaN / GaN heterostructure is irradiated with light from outside.

[0016] [Table 1]

[0017] Irradiation with light excites carriers near the heterointerface. As a result, as shown in Table 1, the sheet resistance of the two-dimensional electron gas decreases by approximately 16% and the on-resistance decreases by approximately 7%. This shows that irradiating semiconductor devices with heterostructures with light can be expected to improve their electrical characteristics.

[0018] In the vertical transistor disclosed in Patent Document 1, a p-type AlGaN layer is provided between the gate electrode and the AlGaN / GaN heterostructure to achieve normally-off characteristics. The p-type AlGaN layer and two-dimensional electron gas generated near the heterointerface form a pn junction, which generates light during modulation and amplification.

[0019] The transistors disclosed in Patent Documents 1 and 2 both have poor efficiency in utilizing the light they generate, which leaves room for improvement in their electrical characteristics.

[0020] Furthermore, Non-Patent Document 1 shows that the light emitted by a Schottky LED improves the current collapse of a transistor formed on the same wafer. However, the structure disclosed in Non-Patent Document 1 requires LEDs that are larger than the transistors to be connected in parallel, which leads to an increase in chip area.

[0021] Therefore, the present disclosure provides a semiconductor device with improved electrical characteristics that efficiently utilizes light generated during operation.

[0022] A semiconductor device according to a first aspect of the present disclosure comprises a substrate, a first semiconductor layer provided above the substrate, a p-type semiconductor layer provided above the first semiconductor layer, a gate electrode provided on an upper surface of the p-type semiconductor layer, a source electrode electrically connected to the first semiconductor layer and provided at a distance from the p-type semiconductor layer and the gate electrode, a drain electrode provided below the substrate, and a reflective layer containing Ag or Al and provided above the gate electrode, wherein, in a planar view of the substrate, an element region contributing to modulation operation and an element isolation region in which a pad to which a wire for supplying power to at least one of the gate electrode, the source electrode, and the drain electrode is connected is provided, and the reflective layer is provided in the element region.

[0023] As a result, the reflective layer containing Ag or Al has a large reflection coefficient for self-excited light due to the photon recycling effect, thereby improving light utilization efficiency. This improves the electrical characteristics of semiconductor devices containing vertical transistors, such as reducing on-resistance, increasing drain current, and suppressing current collapse. Furthermore, since there is no need to form a separate LED as in Non-Patent Document 1, the area of ​​the semiconductor device can be reduced.

[0024] A semiconductor device according to a second aspect of the present disclosure is the semiconductor device according to the first aspect, wherein the reflective layer is not electrically connected to either the source electrode or the gate electrode.

[0025] This allows the operating section of the vertical transistor and the reflective layer to be electrically isolated, increasing the degree of freedom in designing the planar layout of the reflective layer. For example, the reflective layer can be provided so as to cover the entire surface of the semiconductor device, further improving the light utilization efficiency.

[0026] A semiconductor device according to a third aspect of the present disclosure is the semiconductor device according to the first aspect, wherein the reflective layer is electrically connected to the source electrode.

[0027] This makes it possible to increase the capacitance (Ciss) between the gate and source, thereby suppressing false ignition during switching operations.

[0028] A semiconductor device according to a fourth aspect of the present disclosure is a semiconductor device according to any one of the first to third aspects, comprising: a first insulating layer provided above the gate electrode; a source wiring provided above the first insulating layer and connected to the source electrode through an opening provided in the first insulating layer; and a second insulating layer provided above the source wiring, wherein the reflective layer is provided above the second insulating layer.

[0029] This allows the operating section of the vertical transistor and the reflective layer to be spatially separated, thereby increasing the degree of freedom in designing the planar layout of the reflective layer. For example, the reflective layer can be provided so as to cover the entire surface of the semiconductor device, further improving the light utilization efficiency.

[0030] A semiconductor device according to a fifth aspect of the present disclosure is a semiconductor device according to any one of the first to third aspects, comprising a first insulating layer provided above the gate electrode and a source wiring provided above the first insulating layer and connected to the source electrode through an opening provided in the first insulating layer, wherein the first insulating layer has a stacked structure of multiple insulating layers, and the reflective layer is provided within the first insulating layer.

[0031] This allows a reflective layer to be provided in the light-emitting region located near the heterostructure, thereby further improving the light utilization efficiency.

[0032] A semiconductor device according to a sixth aspect of the present disclosure comprises a substrate, a first semiconductor layer provided above the substrate, a p-type semiconductor layer provided above the first semiconductor layer, an anode electrode provided on an upper surface of the p-type semiconductor layer, a cathode electrode provided below the substrate, and a reflective layer provided above the anode electrode, wherein, in a planar view of the substrate, an element region contributing to rectification operation and an element isolation region in which a pad to which a wire for supplying power to at least one of the anode electrode and the cathode electrode is connected is provided, and the reflective layer is provided in the element region.

[0033] This provides a reflective layer that reflects self-excited light due to the photon recycling effect, thereby improving light utilization efficiency. This improves the electrical characteristics of semiconductor devices containing vertical diodes, such as increasing forward current. Furthermore, since there is no need to form a separate LED as in Non-Patent Document 1, the area of ​​the semiconductor device can be reduced.

[0034] A semiconductor device according to a seventh aspect of the present disclosure is the semiconductor device according to the sixth aspect, wherein the first semiconductor layer includes an electron transit layer and an electron supply layer provided above the electron transit layer, and the p-type semiconductor layer is provided on and in contact with the electron supply layer.

[0035] This makes it possible to improve the electrical characteristics of a semiconductor device including a vertical pn junction diode that utilizes the pn junction between the p-type semiconductor layer and the two-dimensional electron gas generated near the interface between the electron supply layer and the electron transit layer.

[0036] A semiconductor device according to an eighth aspect of the present disclosure is the semiconductor device according to the sixth aspect, wherein the first semiconductor layer includes an n-type semiconductor layer.

[0037] This makes it possible to improve the electrical characteristics of semiconductor devices including vertical pn junction diodes.

[0038] A semiconductor device according to a ninth aspect of the present disclosure is the semiconductor device according to any one of the sixth to eighth aspects, wherein the reflective layer contains Ag or Al.

[0039] This allows the reflective layer containing Ag or Al to have a large reflection coefficient for light self-excited by the photon recycling effect, thereby improving the light utilization efficiency.

[0040] A semiconductor device according to a tenth aspect of the present disclosure is the semiconductor device according to any one of the sixth to ninth aspects, wherein the reflective layer is not electrically connected to the anode electrode.

[0041] This allows the operating section of the vertical diode and the reflective layer to be electrically separated, increasing the degree of freedom in designing the planar layout of the reflective layer. For example, the reflective layer can be provided so as to cover the entire surface of the semiconductor device, further improving the light utilization efficiency.

[0042] A semiconductor device according to an eleventh aspect of the present disclosure is the semiconductor device according to any one of the sixth to ninth aspects, wherein the reflective layer is electrically connected to the anode electrode.

[0043] This allows the reflective layer to mitigate electric field concentration, thereby increasing the breakdown voltage of the semiconductor device and contributing to shortening the manufacturing process, for example, by omitting the formation of an insulating layer between the reflective layer and the anode electrode.

[0044] A semiconductor device according to a twelfth aspect of the present disclosure comprises a substrate, a first semiconductor layer provided above the substrate, a p-type semiconductor layer provided above the first semiconductor layer, a first electrode provided on an upper surface of the p-type semiconductor layer, a second electrode electrically connected to the first semiconductor layer and provided at a distance from the p-type semiconductor layer and the first electrode, and a reflective layer provided above the first electrode, wherein, in a planar view of the substrate, an element region including a main path of current flowing through the first semiconductor layer and an element isolation region in which a pad to which a wire for supplying power to at least one of the first electrode and the second electrode is connected is provided, and the main path does not pass through the substrate, and the reflective layer is provided in the element region.

[0045] This provides a reflective layer that reflects self-excited light due to the photon recycling effect, thereby increasing the light utilization efficiency. This improves the electrical characteristics of lateral semiconductor devices. Furthermore, since there is no need to form a separate LED as in Non-Patent Document 1, the area of ​​the semiconductor device can be reduced.

[0046] A semiconductor device according to a thirteenth aspect of the present disclosure is a semiconductor device according to the twelfth aspect, comprising a source electrode electrically connected to the first semiconductor layer and sandwiching the p-type semiconductor layer and the first electrode between the first electrode and the second electrode, the first electrode being a gate electrode and the second electrode being a drain electrode.

[0047] This makes it possible to improve the electrical characteristics of a semiconductor device including a lateral transistor, such as reducing the on-resistance, increasing the drain current, or suppressing current collapse.

[0048] A semiconductor device according to a fourteenth aspect of the present disclosure is a semiconductor device according to the thirteenth aspect, comprising a first insulating layer provided between the first electrode and the reflective layer, the first insulating layer including a thin film portion located between the gate electrode and the drain electrode in a planar view of the substrate, and a thick film portion located between the gate electrode and the source electrode in a planar view of the substrate, and the thickness of the thin film portion is thinner than the thickness of the thick film portion.

[0049] This allows a reflective layer to be provided in the light-emitting region located near the heterostructure, thereby further improving the light utilization efficiency.

[0050] A semiconductor device according to a fifteenth aspect of the present disclosure is a semiconductor device according to the fourteenth aspect, wherein the first insulating layer includes a first film covering an upper surface of the first semiconductor layer, a second film provided above the first film, and a third film provided above the second film, the second film having a different composition from the third film, and the third film being provided only in the thick film portion of the thin film portion and the thick film portion.

[0051] This allows the third film to function as an etching stopper layer during etching. This makes it easier to form the first insulating layer as designed, thereby suppressing variations in electrical characteristics caused by manufacturing variations.

[0052] A semiconductor device according to a sixteenth aspect of the present disclosure is the semiconductor device according to the twelfth aspect, wherein the first electrode is an anode electrode and the second electrode is a cathode electrode.

[0053] This makes it possible to improve the electrical characteristics of semiconductor devices including lateral diodes, such as increasing the forward current.

[0054] A semiconductor device according to a seventeenth aspect of the present disclosure is the semiconductor device according to any one of the twelfth to sixteenth aspects, wherein the reflective layer contains Ag or Al.

[0055] This allows the reflective layer containing Ag or Al to have a large reflection coefficient for light self-excited by the photon recycling effect, thereby improving the light utilization efficiency.

[0056] A semiconductor device according to an eighteenth aspect of the present disclosure is a semiconductor device according to any one of the twelfth to seventeenth aspects, in which the reflective layer is not electrically connected to either the first electrode or the second electrode.

[0057] This allows the active section of the semiconductor device and the reflective layer to be electrically isolated, thereby increasing the degree of freedom in designing the planar layout of the reflective layer. For example, the reflective layer can be provided so as to cover the entire surface of the semiconductor device, thereby further improving the light utilization efficiency.

[0058] A semiconductor device according to a nineteenth aspect of the present disclosure is the semiconductor device according to any one of the twelfth to eighteenth aspects, wherein the reflective layer is electrically connected to the second electrode.

[0059] This increases the gate-source capacitance (Ciss), which can suppress false ignition during switching operations. The reflective layer also reduces electric field concentration, which can increase the breakdown voltage of the semiconductor device. It can also contribute to shortening the manufacturing process, for example, by eliminating the need to form an insulating layer between the reflective layer and the second electrode.

[0060] A semiconductor device according to a twentieth aspect of the present disclosure is the semiconductor device according to any one of the first to nineteenth aspects, wherein the first semiconductor layer and the p-type semiconductor layer each contain a nitride semiconductor as a main component.

[0061] This makes it possible to realize a semiconductor device with a large dielectric breakdown field and a high electron drift velocity.

[0062] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0063] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0064] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0065] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as rectangle or trapezoid, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0066] In this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may be referred to as the "lateral direction." A "vertical" semiconductor device refers to a device in which the main path of current, such as drain current or forward current, is vertical, i.e., a device in which the main current passes vertically through the substrate. A "lateral" semiconductor device refers to a device in which the main path of current, such as drain current or forward current, is horizontal, i.e., a device in which the main current does not pass through the substrate.

[0067] Also, the side on which the hetero-structure is provided with respect to the substrate is regarded as "upper" or "upper side", and the opposite side is regarded as "lower" or "lower side". In this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in the absolute spatial recognition, but are used as terms defined by the relative positional relationship based on the stacking order in the stacked structure. Further, the terms "upper" and "lower" are applicable not only when two components are arranged with a gap therebetween and another component exists between the two components, but also when the two components are arranged in close contact with each other and the two components are in contact with each other.

[0068] Also, in this specification, "plan view" means, unless otherwise specified, when viewed from a direction perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, when the main surface of the substrate is viewed from the front.

[0069] Also, in this specification, "A and B overlap in plan view" means that at least a part of A and at least a part of B overlap. That is, it includes cases where only a part of A and only a part of B overlap, cases where all of A overlaps B, cases where all of B overlaps A, cases where A and B completely overlap each other, and the like.

[0070] Also, in this specification, AlGaN refers to ternary mixed crystal Al x Ga 1-x N (0 < x < 1). Hereinafter, the multi-component mixed crystal is abbreviated with the array of the respective constituent element symbols, for example, AlInN, GaInN, etc. For example, Al x Ga 1-x-y In y N (0 < x < 1, 0 < y < 1, and 0 < x + y < 1) is abbreviated as AlGaInN. x, 1 - x - y, and y respectively represent the composition ratios of Al, Ga, and In.

[0071] Furthermore, "A contains B as a main component" means that B has the highest composition ratio among the elements constituting A. Furthermore, a layer made of material X such as GaN or AlGaN, and a layer constituted by material X, mean that the layer contains substantially only material X. However, the layer may contain other elements as impurities, such as elements that are unavoidable in manufacturing, at a rate of 1 at% or less.

[0072] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0073] (Embodiment 1) [composition] First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG.

[0074] Fig. 1 is a cross-sectional view of a semiconductor device 1 according to embodiment 1. In Fig. 1, each component, such as a semiconductor layer, an insulating layer, and an electrode, is shaded with diagonal lines to indicate a cross section. This also applies to Fig. 2A and subsequent cross-sectional views.

[0075] The semiconductor device 1 is a normally-off vertical FET. In the semiconductor device 1, for example, the source electrode 34 is grounded, and a positive potential is applied to the drain electrode 36. The potential applied to the drain electrode 36 is, for example, 100 V or more and 1200 V or less, but is not limited thereto. The semiconductor device 1 performs modulation according to the potential applied to the gate electrode 32. For example, when 0 V or a negative potential (e.g., −5 V) is applied to the gate electrode 32, no current flows between the drain electrode 36 and the source electrode 34. In other words, the semiconductor device 1 is in a non-conductive state (off). When a positive potential (e.g., +5 V) is applied to the gate electrode 32, a current flows from the drain electrode 36 to the source electrode 34. In other words, the semiconductor device 1 is in a conductive state (on). The current flowing from the drain electrode 36 to the source electrode 34 when the semiconductor device 1 is on is called a drain current. The drain current flows through the substrate 10 in the thickness direction (i.e., vertical direction).

[0076] 1, the semiconductor device 1 includes a substrate 10, a drift layer 12, an underlayer 14, a block layer 16, an underlayer 18, an electron transit layer 22, an electron supply layer 24, a threshold adjustment layer 28, a gate electrode 32, a source electrode 34, and a drain electrode 36. The semiconductor device 1 also includes an insulating layer 40, a via conductor 50, a source wiring 52, a protective layer 60, and a reflective layer 70. The semiconductor device 1 also includes a gate opening 20 and a source opening 30.

[0077] The semiconductor device 1 is a nitride semiconductor device in which a semiconductor layer including a channel contains a nitride semiconductor as a main component. Specifically, the drift layer 12, the underlayer 14, the block layer 16, the underlayer 18, the electron transit layer 22, the electron supply layer 24, and the threshold adjustment layer 28 each contain a nitride semiconductor as a main component.

[0078] Each of the components of the semiconductor device 1 will be described in detail below.

[0079] The substrate 10 is made of a nitride semiconductor. The shape of the substrate 10 in plan view is, for example, rectangular, but is not limited to this.

[0080] The substrate 10 has a thickness of 300 μm and a carrier concentration of 1×10 18 cm -3 n + The substrate is made of n-type GaN. Note that n-type and p-type refer to the conductivity type of the semiconductor. + The n-type indicates a state in which a semiconductor is heavily doped with n-type dopants. - The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopants, a so-called light doping. + Type and n - Both types are examples of n-type, and may be referred to as n-type without distinction. + Type and p - The same is true for types.

[0081] The substrate 10 does not have to be a nitride semiconductor substrate, but may be, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0082] The drift layer 12 is an example of an n-type semiconductor layer provided above the substrate 10. The drift layer 12 is, for example, an n-type semiconductor layer having a thickness of 8 μm. - The drift layer 12 is a film made of GaN. The donor concentration of the drift layer 12 is, for example, 1×10 15 cm -3 More than 1×10 17 cm -3 For example, 1 x 10 16 cm -3 The carbon concentration (C concentration) of the drift layer 12 is, for example, 1×10 15 cm -3 Over 2×10 17 cm -3 The drift layer 12 is provided in contact with the upper surface (main surface) of the substrate 10, for example.

[0083] The underlayer 14 is an example of a semiconductor layer provided between the drift layer 12 and the block layer 16. The underlayer 14 is, for example, a 100 nm thick film made of carbon-doped GaN (C-GaN). The carbon concentration of the underlayer 14 is, for example, 3×10 17 cm -3 That's all, but 1 x 10 18 cm -3 The underlayer 14 is provided in contact with each of the drift layer 12 and the block layer 16. The underlayer 14 may contain n-type impurities such as Si. The concentration of the n-type impurities contained in the underlayer 14 is lower than the carbon concentration and oxygen concentration of the underlayer 14, and may be, for example, 5×10 16 cm -3 or less than or equal to 2 x 10 16 cm -3 It may be the following:

[0084] The provision of the underlayer 14 can suppress punch-through and increase the breakdown voltage of the semiconductor device 1. Note that the underlayer 14 does not necessarily have to be provided, and the drift layer 12 and the block layer 16 may be in contact with each other.

[0085] The block layer 16 is an example of a p-type semiconductor layer provided above the drift layer 12. The block layer 16 has a thickness of 400 nm and a carrier concentration of 1×10 17 cm -3 The blocking layer 16 is provided in contact with the upper surface of the underlayer 14.

[0086] Although the block layer 16 is formed by crystal growth, it may be formed by, for example, implanting magnesium (Mg) into the deposited i-GaN. Furthermore, the block layer 16 may be an insulating layer obtained by implanting iron (Fe) or boron (B) instead of a p-type nitride semiconductor layer.

[0087] In this embodiment, as shown in FIG. 1 , the block layer 16 is in contact with the source electrode 34. Therefore, the block layer 16 is fixed to the source potential applied to the source electrode 34. This allows the semiconductor device 1 to have a high breakdown voltage. For example, when a reverse voltage is applied to the pn junction formed between the block layer 16 and the drift layer 12, specifically when the drain electrode 36 has a higher potential than the source electrode 34, a depletion layer extends to the drift layer 12, thereby enabling the semiconductor device 1 to have a high breakdown voltage. In this embodiment, the drain electrode 36 has a higher potential than the source electrode 34 in both the off state and the on state, except in the case of reverse conduction. This allows the semiconductor device 1 to have a high breakdown voltage.

[0088] The underlayer 18 is an example of a semiconductor layer provided between the block layer 16 and the electron transit layer 22. The underlayer 18 is a high-resistance layer having a higher resistance than the block layer 16. The underlayer 18 is, for example, a film made of undoped GaN (i-GaN) with a thickness of 200 nm. The underlayer 18 is provided in contact with both the block layer 16 and the electron transit layer 22.

[0089] The underlayer 18 may be an insulating layer or a semi-insulating layer. For example, the underlayer 18 may be a film made of carbon-doped GaN (C-GaN). The carbon concentration of the underlayer 18 is, for example, 3×10 17 cm -3 That's all, but 1 x 10 18 cm -3 The underlayer 18 may contain n-type impurities such as Si. The concentration of the n-type impurities contained in the underlayer 18 is lower than the carbon concentration and oxygen concentration of the underlayer 18, for example, 5×10 16 cm -3 or less than or equal to 2 x 10 16 cm -3 It may be the following:

[0090] The gate opening 20 is an example of a first opening that penetrates the block layer 16. Specifically, the gate opening 20 penetrates the underlayer 18, the block layer 16, and the underlayer 14, and reaches the drift layer 12. A bottom surface 20a of the gate opening 20 is part of the upper surface of the drift layer 12. As shown in FIG. 1 , the bottom surface 20a is located below the lower surface of the underlayer 14. The lower surface of the underlayer 14 corresponds to the interface between the underlayer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the major surface of the substrate 10. When the semiconductor device 1 is on, a drain current flows between the drain electrode 36 and the source electrode 34 through the bottom surface 20a of the gate opening 20.

[0091] In this embodiment, gate opening 20 is formed so that the opening area increases with increasing distance from substrate 10. Specifically, side surface 20b of gate opening 20 is inclined obliquely. As shown in FIG. 1, the cross-sectional shape of gate opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0092] The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 80°, but may be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the c-plane, thereby improving the film quality of the electron transit layer 22 and other layers formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the more effectively the gate opening 20 is prevented from becoming too large, thereby achieving a more compact semiconductor device 1. The side surface 20b may be perpendicular to the bottom surface 20a.

[0093] The electron transit layer 22 is an example of a first regrown layer provided to cover the side surface 20b and bottom surface 20a of the gate opening 20 and the upper surface of the underlayer 18. Specifically, a portion of the electron transit layer 22 is provided along the bottom surface 20a and side surface 20b of the gate opening 20, and another portion of the electron transit layer 22 is provided above the block layer 16 and on the upper surface of the underlayer 18. The electron transit layer 22 is, for example, a 150 nm-thick film made of undoped GaN. Note that although the electron transit layer 22 is assumed to be undoped, a portion of it may be made n-type by, for example, doping with Si.

[0094] The electron transit layer 22 is in contact with the drift layer 12 at the bottom surface 20a and the side surface 20b of the gate opening 20. The electron transit layer 22 is in contact with the underlayer 14, the block layer 16, and the underlayer 18 at the side surface 20b of the gate opening 20. Furthermore, the electron transit layer 22 is in contact with the upper surface of the underlayer 18.

[0095] The electron transit layer 22 has a channel region. Specifically, two-dimensional electron gas, which serves as a channel, is generated near the interface between the electron transit layer 22 and the electron supply layer 24. The two-dimensional electron gas bends along the interface between the electron transit layer 22 and the electron supply layer 24, i.e., along the inner surface of the gate opening 20.

[0096] Although not shown in Fig. 1, an AlN layer with a thickness of about 1 nm is provided as a second regrowth layer between the electron transit layer 22 and the electron supply layer 24. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. However, the AlN layer is not necessarily required.

[0097] The electron supply layer 24 is an example of a third regrowth layer provided to cover the side surface 20b and bottom surface 20a of the gate opening 20 and the upper surface of the underlayer 18. The electron transit layer 22 and the electron supply layer 24 are provided in this order from the substrate 10 side. The electron supply layer 24 is, for example, a film made of undoped AlGaN with a thickness of 20 nm. The electron supply layer 24 is formed to a shape that conforms to the upper surface of the electron transit layer 22 and has a substantially uniform thickness.

[0098] The electron supply layer 24 has a larger band gap than the electron transit layer 22. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 24 and the electron transit layer 22. The electron supply layer 24 supplies electrons to a channel region (two-dimensional electron gas) formed in the electron transit layer 22.

[0099] In this embodiment, the electron transit layer 22 and the electron supply layer 24 are both layers included in a first semiconductor layer included in the semiconductor device 1. The first semiconductor layer is provided above the substrate .

[0100] The threshold adjustment layer 28 is an example of a p-type semiconductor layer provided above the first semiconductor layer. Specifically, the threshold adjustment layer 28 is provided between the electron supply layer 24 and the gate electrode 32. More specifically, the threshold adjustment layer 28 is disposed so as to be in direct contact with the upper surface of the electron supply layer 24 at a position overlapping the gate opening 20 in a plan view of the substrate 10. The threshold adjustment layer 28 and the source electrode 34 are disposed at a distance from each other and are electrically isolated from each other.

[0101] The threshold adjustment layer 28 has a thickness of 200 nm and a carrier concentration of 1×10 19 cm -3 It is a film made of p-type GaN, where p is a GaN film. The thickness and carrier concentration of the threshold adjustment layer 28 are merely examples and can be changed as appropriate.

[0102] The provision of the threshold adjustment layer 28 raises the potential of the conduction band edge in the channel portion. This reduces the carrier concentration directly below the gate electrode 32, shifting the threshold voltage of the transistor to the positive side. This allows the semiconductor device 1 to be easily realized as a normally-off FET. The threshold adjustment layer 28 may be a film made of p-type AlGaN.

[0103] The source opening 30 is an example of a second opening that penetrates the electron supply layer 24 and the electron transit layer 22 at a position away from the gate electrode 32 in a plan view of the substrate 10, and reaches the block layer 16. Specifically, the source opening 30 penetrates not only the electron supply layer 24 and the electron transit layer 22, but also the underlayer 18. The source opening 30 is provided at a position away from both the gate electrode 32 and the threshold adjustment layer 28 in a plan view of the substrate 10.

[0104] 1, the bottom surface 30a of the source opening 30 is part of the upper surface of the block layer 16. In the example shown in FIG. 1, the bottom surface 30a may be located lower than the lower surface of the underlayer 18. The lower surface of the underlayer 18 corresponds to the interface between the underlayer 18 and the block layer 16. The bottom surface 30a is parallel to the major surface of the substrate 10, for example.

[0105] As shown in FIG. 1 , the source opening 30 is formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the side surface 30b of the source opening 30 is obliquely inclined. For example, the cross-sectional shape of the source opening 30 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the side surface 30b with respect to the bottom surface 30a is, for example, in the range of 30° to 60°. The oblique inclination of the side surface 30b increases the contact area between the source electrode 34 and the electron transit layer 22 (two-dimensional electron gas), making it easier to achieve ohmic contact. The two-dimensional electron gas is exposed at the side surface 30b of the source opening 30 and connected to the source electrode 34 at the exposed portion. The side surface 30b may be perpendicular to the bottom surface 30a.

[0106] The provision of the source opening 30 reduces the ohmic contact resistance between the two-dimensional electron gas functioning as a channel and the source electrode 34. That is, the on-resistance of the semiconductor device 1 can be reduced. Furthermore, the blocking layer 16 and the source electrode 34 can be electrically connected, which stabilizes the potential of the blocking layer 16 and improves the breakdown voltage. Note that the source opening 30 may not be provided, and the source electrode 34 may be provided in contact with the upper surface of the electron supply layer 24 at a position away from the threshold adjustment layer 28.

[0107] The gate electrode 32 is provided on the upper surface of the threshold adjustment layer 28. Specifically, the gate electrode 32 is provided in contact with the upper surface of the threshold adjustment layer 28 at a position overlapping the gate opening 20 in a plan view of the substrate 10. The gate electrode 32 is provided at a position overlapping the bottom surface 20a of the gate opening 20 in a plan view.

[0108] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 may be made of a material that forms an ohmic contact with the p-type GaN layer, but is not limited to this. A material that forms a Schottky contact with the p-type GaN layer may also be used. For example, palladium (Pd), nickel (Ni)-based material, tungsten silicide (WSi), gold (Au), etc. may be used.

[0109] The source electrode 34 is electrically connected to the first semiconductor layer and is provided away from the threshold adjustment layer 28 and the gate electrode 32. Specifically, the source electrode 34 is provided in contact with the bottom surface 30a and the side surface 30b of the source opening 30. The source electrode 34 is in direct contact with the two-dimensional electron gas at the side surface 30b of the source opening 30. This reduces the contact resistance between the source electrode 34 and the two-dimensional electron gas, thereby reducing the on-resistance of the semiconductor device 1. The source electrode 34 is also electrically connected to the block layer 16 exposed at the bottom surface 30a of the source opening 30.

[0110] The source electrode 34 is formed using a conductive material such as a metal. The material of the source electrode 34 may be, for example, Ti / Al (a laminated structure of a Ti layer and an Al layer), which can be ohmically connected to the n-type GaN layer by heat treatment.

[0111] The drain electrode 36 is provided below the substrate 10. Specifically, the drain electrode 36 is provided in contact with the lower surface of the substrate 10.

[0112] The drain electrode 36 is formed using a conductive material such as a metal. As with the material of the source electrode 34, the material of the drain electrode 36 may be a material that forms an ohmic contact with n-type GaN, such as Ti / Al.

[0113] The insulating layer 40 is an example of a first insulating layer, and is provided above the gate electrode 32. The insulating layer 40 has a stacked structure of multiple insulating layers. Specifically, as shown in FIG. 1, the insulating layer 40 includes an interlayer insulating film 41 and a protective insulating film 42.

[0114] Although not shown in FIG. 1, a gate wiring electrically connected to the gate electrode 32 is provided in a layer above the gate electrode 32. The gate wiring (not shown) and the source wiring 52 are provided in different layers to avoid contact or proximity with each other. This makes it possible to reduce parasitic capacitance between the gate and source. In addition, since the gate wiring and the source wiring 52 are formed in different layers, the insulating layer 40 has a stacked structure of multiple insulating layers.

[0115] The interlayer insulating film 41 is an insulating film made of, for example, silicon nitride (SiN), and can suppress electron traps on the surface of the electron supply layer 24.

[0116] The protective insulating film 42 has a layered structure of, for example, an insulating film made of silicon oxide (SiO2) and an insulating film made of aluminum oxide (Al2O3). The insulating film made of SiN, the insulating film made of SiO2, and the insulating film made of Al2O3 are layered in this order from the bottom. The thickness of each insulating film is not particularly limited. The interlayer insulating film 41 and the protective insulating film 42 are provided so that the upper surface of the protective insulating film 42 is a flat surface parallel to the main surface of the substrate 10.

[0117] The via conductor 50 penetrates the insulating layer 40 and electrically connects the source electrode 34 and the source wiring 52. An opening is provided in the insulating layer 40 to expose the source electrode 34, and the via conductor 50 is provided in the opening. The via conductor 50 is formed using a conductive material such as a metal. For example, the via conductor 50 has a layered structure of a Ti film, an Al film, a Ni film, and an Au film, which are layered in this order from the source electrode 34 side.

[0118] The source wiring 52 is provided above the insulating layer 40 and is connected to the source electrode 34 through an opening provided in the insulating layer 40. Specifically, the source wiring 52 is electrically connected to the source electrode 34 through a via conductor 50. The source wiring 52 is formed using a conductive material such as a metal. For example, the source wiring 52 is a plated film made of Au. The source wiring 52 and the Au film included in the via conductor 50 may be formed integrally. The via conductor 50 may be considered to be part of the source wiring 52.

[0119] The protective layer 60 is an example of a second insulating layer and is provided above the source wiring 52. The protective layer 60 has a laminated structure of, for example, an insulating film made of SiN and an insulating film made of Al2O3. The insulating film made of SiN and the insulating film made of Al2O3 are laminated in this order from the bottom. There are no particular limitations on the thickness of each insulating film.

[0120] The reflective layer 70 is provided above the gate electrode 32. Specifically, the reflective layer 70 is provided above the insulating layer 40. More specifically, the reflective layer 70 is provided above the protective layer 60. The reflective layer 70 is provided, for example, so as to cover and contact the upper surface of the protective layer 60. The reflective layer 70 is also provided above the source wiring 52.

[0121] The reflective layer 70 is a metal reflective layer containing silver (Ag) or aluminum (Al). For example, the reflective layer 70 has a layered structure of a Ti film and an Ag film stacked in this order from the bottom, or a layered structure of a Ti film and an Al film stacked in this order from the bottom.

[0122] In this embodiment, the reflective layer 70 is not electrically connected to either the source electrode 34 or the gate electrode 32. For example, the reflective layer 70 is in an electrically floating state.

[0123] The reflective layer 70 is provided in the element region of the semiconductor device 1. Details will be described later with reference to FIG. 16A , but the semiconductor device 1 has an element region and an element isolation region when viewed from above on the substrate 10. The element region is a region that contributes to the modulation operation of the semiconductor device 1 when viewed from above on the substrate 10. Specifically, the element region includes, when viewed from above, a region (source region) overlapping the source electrode 34, a region (gate region) overlapping the gate electrode 32, and a region (gate-source region) overlapping the region between the gate electrode 32 and the source electrode 34. In this embodiment, the reflective layer 70 is provided so as to straddle each of the source region, the gate region, and the gate-source region when viewed from above on the substrate 10. Furthermore, the reflective layer 70 is provided so as to overlap the source wiring 52 in the element region when viewed from above on the substrate 10.

[0124] The semiconductor device 1 configured as above is manufactured, for example, by the method described below.

[0125] First, a nitride semiconductor is crystal-grown on the main surface of substrate 10 by epitaxial growth using a method such as MOVPE (Metal Organic Vapor Phase Epitaxy) or HVPE (Hydride Vapor Phase Epitaxy). For example, an n-type GaN film that will become drift layer 12, a carbon-doped GaN film that will become underlayer 14, a p-type GaN film that will become block layer 16, and an undoped GaN film that will become underlayer 18 are formed in this order on the main surface of substrate 10. Thereafter, the carbon-doped GaN film, the p-type GaN film, the undoped GaN film, and surface portions of the n-type GaN film are partially removed by dry etching or the like to form gate opening 20.

[0126] Furthermore, crystal regrowth of a nitride semiconductor is performed by epitaxial growth such as MOVPE or HVPE so as to cover the gate opening 20. For example, an undoped GaN film to become the electron transit layer 22, an undoped AlGaN film to become the electron supply layer 24, and a p-type GaN film to become the threshold adjustment layer 28 are formed in this order so as to cover the gate opening 20. Thereafter, the p-type GaN film is patterned into a predetermined shape by dry etching or the like, and a source opening 30 is formed.

[0127] Next, a metal film is formed by electron beam evaporation, sputtering, or the like so as to cover the threshold adjustment layer 28, and unnecessary portions are removed by etching, lift-off, or the like to form the gate electrode 32. Furthermore, a metal film is formed so as to cover the source opening 30, and unnecessary portions are removed by etching, lift-off, or the like to form the source electrode 34. Either the gate electrode 32 or the source electrode 34 may be formed first. Furthermore, a metal film is formed on the lower surface of the substrate 10 by electron beam evaporation, sputtering, or the like to form the drain electrode 36. The drain electrode 36 may be formed after the source wiring 52, the reflective layer 70, and the like are formed.

[0128] After the gate electrode 32 and the source electrode 34 are formed, the insulating layer 40 is formed. The insulating layer 40 is formed by, for example, plasma CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). After the insulating layer 40 is formed, an opening is formed in the insulating layer 40 by dry etching or the like to expose at least a portion of the source electrode 34. Thereafter, the via conductor 50 and the source wiring 52 are formed so as to fill the opening. The via conductor 50 and the source wiring 52 are formed by, for example, sequentially depositing films of Ti, Al, Ni, etc. by sputtering or electron beam evaporation, followed by Au plating.

[0129] Furthermore, a protective layer 60 is formed so as to cover the source wiring 52. The protective layer 60 is formed by, for example, a plasma CVD method or an ALD method. After the protective layer 60 is formed, a reflective layer 70 is formed by sputtering, electron beam evaporation, plating, or the like. The reflective layer 70 may also be formed by bonding another substrate on which a metal reflective film is formed.

[0130] In this way, it is possible to manufacture the semiconductor device 1 shown in Fig. 1. The above-described method for manufacturing the semiconductor device 1 is merely an example, and is not particularly limited.

[0131] [Characteristic composition] Next, the main characteristic configuration of the semiconductor device 1 according to this embodiment will be described. Specifically, the function and effect of the reflective layer 70 included in the semiconductor device 1 will be described in comparison with a comparative example.

[0132] 2A is a cross-sectional view illustrating a problem with a semiconductor device 1x according to a comparative example. FIG. 2B is a cross-sectional view illustrating an effect of the semiconductor device 1 according to the first embodiment. The semiconductor device 1x illustrated in FIG. 2A differs from the semiconductor device 1 illustrated in FIGS. 1 and 2B in that it does not include a reflective layer 70. The cross-sectional shape of the protective layer 60 is also different, but the protective layer 60 may be the same.

[0133] In the semiconductor devices 1 and 1x, when a voltage equal to or greater than the threshold voltage is applied to the gate electrode 32, light is emitted near the pn junction between the threshold adjustment layer 28, which is a p-type semiconductor layer, and the electron transit layer 22, which contains two-dimensional electron gas. In the semiconductor device 1x, as shown in FIG. 2A, the emitted light is emitted upward through the insulating layer 40. The light generated near the pn junction has a wavelength corresponding to the band gap of GaN, specifically, near-ultraviolet light or visible light ranging from violet to blue. More specifically, light in the range of 330 nm to 400 nm is emitted.

[0134] In contrast, in this embodiment, a reflective layer 70 containing Al or Ag is provided. As shown in FIG. 3, Al or Ag has a high reflection coefficient for the wavelength of light generated near the pn junction. FIG. 3 is a diagram showing the wavelength dependency of the reflection coefficient of metals. In FIG. 3, the horizontal axis represents wavelength, and the vertical axis represents reflection coefficient. In the case of aluminum (Al) and silver (Ag), the reflection coefficient is 90% or more. Therefore, the reflective layer 70 can reflect light.

[0135] As a result, the light reflected by the reflective layer 70 is absorbed near the p-n junction, generating electron-hole pairs. Some of the generated electron-hole pairs recombine to emit light, which is reflected by the reflective layer 70. The reflective layer 70 can increase the utilization efficiency of self-excited light through the photon recycling effect, which repeats light emission and absorption. This can improve the electrical characteristics of the semiconductor device 1, such as reducing the on-resistance, increasing the drain current, or suppressing current collapse. Note that the reflection by the reflective layer 70 is mirror reflection. Light from the light-emitting portion located below the reflective layer 70 (i.e., near the p-n junction) can be efficiently reflected back to the light-emitting portion.

[0136] In the semiconductor device 1x according to the comparative example, the reflective layer 70 is not provided, so light leaks outside the semiconductor device 1x, resulting in low absorption efficiency. Furthermore, the source wiring 52 is a metal layer containing Au as a main component. However, as shown in FIG. 3, Au has a low reflectance coefficient for light in the range of 330 nm to 400 nm, and therefore does not function effectively as a reflective layer. Therefore, the semiconductor device 1 according to the present embodiment can have improved electrical characteristics compared to the semiconductor device 1x according to the comparative example. For example, the reduced on-resistance can result in a semiconductor device 1 with excellent low-loss switching operation.

[0137] Furthermore, in this embodiment, light emitted by the vertical transistor itself is used, eliminating the need for a separate light-emitting element such as a light-emitting diode, thereby enabling the chip area of ​​the semiconductor device 1 to be reduced.

[0138] [Variations] Next, a description will be given of a modification of embodiment 1. The following description will focus on the differences from embodiment 1, and the description of the commonalities will be omitted or simplified.

[0139] <Variation 1> 4 is a cross-sectional view of a semiconductor device 1A according to a first modification of the first embodiment. The semiconductor device 1A according to this modification differs from the semiconductor device 1 in that a reflective layer 70 is electrically connected to the source electrode 34. Specifically, as shown in FIG. 4, the semiconductor device 1A does not include a protective layer 60. The reflective layer 70 is provided so as to be in contact with the source wiring 52, and is electrically connected to the source electrode 34 via the source wiring 52 and the via conductor 50.

[0140] As a result, the reflective layer 70 has the same potential as the source electrode 34, thereby increasing the capacitance (Ciss) between the gate and source. This makes it possible to suppress false ignition during switching operations. Furthermore, since the protective layer 60 is not provided, the reflective layer 70 and the light-emitting section can be placed closer to each other, thereby improving the light utilization efficiency. This makes it possible to realize a semiconductor device 1A with improved electrical characteristics.

[0141] <Variation 2> 5 is a cross-sectional view of a semiconductor device 1B according to a second modification of the first embodiment. The semiconductor device 1B according to this modification differs from the semiconductor device 1 in that it includes a reflective layer 71 instead of the reflective layer 70. Specifically, as shown in FIG. 4, the reflective layer 71 is provided in the insulating layer 40. More specifically, the reflective layer 71 is provided between the interlayer insulating film 41 and the protective insulating film 42. The reflective layer 71 is provided below the source wiring 52.

[0142] This allows the reflective layer 71 and the light emitting section to be closer to each other, thereby improving the light utilization efficiency, and thus realizing a semiconductor device 1B with improved electrical characteristics.

[0143] (Embodiment 2) Next, a second embodiment will be described.

[0144] The semiconductor device according to the second embodiment is mainly different from the semiconductor device according to the first embodiment in that it includes a vertical diode instead of a vertical FET. The following description will focus on the differences from the first embodiment, and description of the commonalities will be omitted or simplified.

[0145] FIG. 6 is a cross-sectional view of a semiconductor device 2 according to a second embodiment. The semiconductor device 2 is a vertical diode. Specifically, the semiconductor device 2 is a pn diode formed by a p-type semiconductor layer 128 and two-dimensional electron gas generated by a heterostructure. The semiconductor device 2 performs a rectifying operation in response to a voltage applied between the anode electrode 132 and the cathode electrode 136. A forward current flowing from the anode electrode 132 to the cathode electrode 136 flows through the substrate 10 in its thickness direction (i.e., vertical direction). The semiconductor device 2 shown in FIG. 6 can be manufactured, for example, by the same process using the same wafer as the semiconductor device 1, 1A, or 1B according to the first embodiment and its modifications.

[0146] 6, the semiconductor device 2 includes a substrate 10, a drift layer 12, an underlayer 14, a block layer 16, an underlayer 18, an electron transit layer 22, an electron supply layer 24, a p-type semiconductor layer 128, an anode electrode 132, a cathode electrode 136, an insulating layer 40, a via conductor 150, an anode wiring 152, a protective layer 60, and a reflective layer 70. The components other than the p-type semiconductor layer 128, the anode electrode 132, the cathode electrode 136, the via conductor 150, and the anode wiring 152 are the same as the components included in the semiconductor device 1 according to the first embodiment.

[0147] The p-type semiconductor layer 128, the anode electrode 132, and the cathode electrode 136 correspond to the threshold adjustment layer 28, the gate electrode 32, and the drain electrode 36, respectively, of the semiconductor device 1. The p-type semiconductor layer 128, the anode electrode 132, and the cathode electrode 136 function as the p-type layer, the anode electrode, and the cathode electrode, respectively, of the pn diode.

[0148] The via conductor 150 corresponds to a via conductor (not shown in FIG. 1) for a gate wiring (not shown in FIG. 1) included in the semiconductor device 1. The via conductor 150 penetrates the interlayer insulating film 41 and electrically connects the anode electrode 132 and the anode wiring 152. In this embodiment, the interlayer insulating film 41 corresponds to the first insulating layer according to the present disclosure. The interlayer insulating film 41 has an opening for exposing the anode electrode 132, and the via conductor 150 is provided in the opening. The via conductor 150 is formed using a conductive material such as metal. For example, the via conductor 150 has a layered structure of a Ti film, an Al film, a Ni film, and an Au film, which are layered in this order from the anode electrode 132 side.

[0149] The anode wiring 152 corresponds to a gate wiring (not shown in FIG. 1) included in the semiconductor device 1. The anode wiring 152 is electrically connected to the anode electrode 132 through a via conductor 150. As shown in FIG. 6, the anode wiring 152 is provided between the interlayer insulating film 41 and the protective insulating film 42. The anode wiring 152 may be provided on the upper surface of the protective insulating film 42. The anode wiring 152 is formed using a conductive material such as metal. For example, the anode wiring 152 is a plated film made of Au.

[0150] In this embodiment, the reflective layer 70 is provided above the anode electrode 132. Specifically, the reflective layer 70 is provided above the anode wiring 152. More specifically, the reflective layer 70 is provided above the protective layer 60. The reflective layer 70 is provided, for example, so as to contact and cover the upper surface of the protective layer 60. The reflective layer 70 is larger than both the anode electrode 132 and the anode wiring 152 in a plan view of the substrate 10. The reflective layer 70 is also provided in an area where neither the anode electrode 132 nor the anode wiring 152 is provided in a plan view of the substrate 10.

[0151] In this embodiment, the reflective layer 70 is not electrically connected to either the anode electrode 132 or the cathode electrode 136. For example, the reflective layer 70 is in an electrically floating state.

[0152] The reflective layer 70 is provided in the element region of the semiconductor device 2. In a plan view of the substrate 10, the semiconductor device 2 is provided with an element region and an element isolation region. The element region is a region that contributes to the rectifying operation of the semiconductor device 2 when the substrate 10 is viewed in a plan view. Specifically, the element region includes a region that overlaps with the anode electrode 132 when viewed in a plan view. In this embodiment, the reflective layer 70 is provided so as to overlap with the anode wiring 152 and a region adjacent to the anode wiring 152 when the substrate 10 is viewed in a plan view.

[0153] During rectification of the semiconductor device 2, a forward voltage is applied between the anode electrode 132 and the cathode electrode 136, causing a forward current to flow from the anode electrode 132 to the cathode electrode 136. When a forward current flows through the pn junction, light is generated near the pn junction. The light generated near the pn junction has a wavelength corresponding to the band gap of GaN, specifically, near-ultraviolet light or visible light ranging from violet to blue. More specifically, light in the range of 330 nm to 400 nm is emitted.

[0154] In this embodiment, as in the first embodiment, the reflective layer 70 is provided, so that the utilization efficiency of self-excited light can be increased by the photon recycling effect, thereby improving the electrical characteristics of the semiconductor device 2 including the vertical diode, such as increasing the forward current.

[0155] Furthermore, in this embodiment, light emitted by the vertical diode itself is used, eliminating the need for a separate light emitting element such as a light emitting diode, thereby enabling the chip area of ​​the semiconductor device 2 to be reduced.

[0156] An Ag film or an Al film may be provided on the lower surface of the anode wiring 152. Furthermore, when the anode wiring 152 has a laminated structure of a Ti film and an Au plating layer, an Ag film or an Al film may be provided between the Ti film and the Au plating layer. This can suppress light absorption by the Au plating and improve light utilization efficiency.

[0157] [Variations] Next, a description will be given of a modification of embodiment 2. The following description will focus on the differences from embodiment 2, and the description of commonalities will be omitted or simplified.

[0158] 7A is a cross-sectional view of a semiconductor device 2A according to a modification of the second embodiment. The semiconductor device 2A according to this modification differs from the semiconductor device 2 in that the reflective layer 70 is electrically connected to the anode electrode 132. Specifically, as shown in FIG. 7A, the semiconductor device 2A does not include the protective layer 60 and the protective insulating film 42. The reflective layer 70 is provided so as to be in contact with the anode wiring 152 and is electrically connected to the anode electrode 132 via the anode wiring 152 and the via conductor 150.

[0159] The reflective layer 70 may be provided between the anode wiring 152 and the anode electrode 132. For example, as in a semiconductor device 2B shown in FIG. 7B , the reflective layer 70 may be provided between the anode wiring 152 and the via conductor 150. In this case, the reflective layer 70 is in contact with and electrically connected to both the anode wiring 152 and the via conductor 150.

[0160] As a result, the reflective layer 70 has the same potential as the anode electrode 132, thereby alleviating electric field concentration on the anode electrode 132. This increases the breakdown voltage of the semiconductor device 2A or 2B. Furthermore, since the protective layer 60 and the protective insulating film 42 are not provided, the distance between the reflective layer 70 and the light-emitting section can be reduced, thereby increasing the light utilization efficiency. This makes it possible to realize a semiconductor device 2A or 2B with improved electrical characteristics.

[0161] (Embodiment 3) Next, a third embodiment will be described.

[0162] The semiconductor device according to the third embodiment differs from the semiconductor device according to the second embodiment mainly in that it does not include the electron transit layer 22 and the electron supply layer 24. The following description will focus on the differences from the second embodiment, and the description of the commonalities will be omitted or simplified.

[0163] 8 is a cross-sectional view of a semiconductor device 3 according to the third embodiment. The semiconductor device 3 is a vertical diode. Specifically, the semiconductor device 3 is a pn diode formed by a p-type semiconductor layer 216 and a drift layer 12. The semiconductor device 3 shown in FIG. 8 can be manufactured using the same wafer and process as the semiconductor device 1, 1A, or 1B according to the first embodiment and its modifications, for example.

[0164] 8, the semiconductor device 3 includes a substrate 10, a drift layer 12, an underlayer 14, a p-type semiconductor layer 216, an anode electrode 232, a cathode electrode 136, an insulating layer 40, a via conductor 150, an anode wiring 152, a protective layer 60, and a reflective layer 70. The components other than the p-type semiconductor layer 216 and the anode electrode 232 are the same as the components included in the semiconductor device 2 according to the second embodiment.

[0165] The p-type semiconductor layer 216 corresponds to the block layer 16 included in the semiconductor device 2. The p-type semiconductor layer 216 functions as a p-type layer of the p-n diode. In this embodiment, the drift layer 12 functions as an n-type layer of the p-n diode. The drift layer 12 is an example of an n-type semiconductor layer included in a first semiconductor layer provided above the substrate 10.

[0166] An underlayer 14 is provided between the drift layer 12 and the p-type semiconductor layer 216. This is because, for example, the semiconductor device 3 is manufactured using the same wafer and process as the semiconductor device 1, 1A, or 1B according to the first embodiment and its modifications. Using the same process leads to a reduction in the manufacturing process.

[0167] On the other hand, the drift layer 12 and the p-type semiconductor layer 216 may be in contact with each other without providing the base layer 14. For example, the nitride semiconductor layered above the drift layer 12 may be removed by etching or the like, and then the p-type semiconductor layer 216 made of p-type GaN or the like may be formed by epitaxial growth. By not providing the base layer 14, which has high resistance, the resistance can be reduced and the forward current can be increased.

[0168] The anode electrode 232 corresponds to the anode electrode 132 included in the semiconductor device 2, and differs in that it is provided on the upper surface of the p-type semiconductor layer 216. The anode electrode 232 can be formed using the same material as the gate electrode 32.

[0169] In this embodiment, as in the second embodiment, the reflective layer 70 is provided, and therefore the utilization efficiency of self-excited light can be increased by the photon recycling effect, thereby improving the electrical characteristics of the semiconductor device 3 including the vertical diode, such as increasing the forward current.

[0170] Furthermore, in this embodiment, light emitted by the vertical diode itself is used, eliminating the need for a separate light emitting element such as a light emitting diode, thereby enabling the chip area of ​​the semiconductor device 3 to be reduced.

[0171] [Variations] Next, a description will be given of a modification of embodiment 3. The following description will focus on the differences from embodiment 3, and the description of commonalities will be omitted or simplified.

[0172] 9A is a cross-sectional view of a semiconductor device 3A according to a modification of the third embodiment. The semiconductor device 3A according to this modification differs from the semiconductor device 3 in that the reflective layer 70 is electrically connected to the anode electrode 232. Specifically, as shown in FIG. 9A, the semiconductor device 3A does not include the protective layer 60 and the protective insulating film 42. The reflective layer 70 is provided so as to be in contact with the anode wiring 152 and is electrically connected to the anode electrode 232 via the anode wiring 152 and the via conductor 150.

[0173] The reflective layer 70 may be provided between the anode wiring 152 and the anode electrode 232. For example, as in a semiconductor device 2B shown in FIG. 9B , the reflective layer 70 may be provided between the anode wiring 152 and the via conductor 150. In this case, the reflective layer 70 is in contact with and electrically connected to both the anode wiring 152 and the via conductor 150.

[0174] As a result, the reflective layer 70 has the same potential as the anode electrode 232, thereby alleviating electric field concentration on the anode electrode 232. This increases the breakdown voltage of the semiconductor device 3A or 3B. Furthermore, since the protective layer 60 and the protective insulating film 42 are not provided, the reflective layer 70 and the light-emitting section can be placed closer to each other, thereby increasing the light utilization efficiency. This makes it possible to realize the semiconductor device 3A or 3B with improved electrical characteristics.

[0175] (Fourth embodiment) Next, a fourth embodiment will be described.

[0176] The semiconductor device according to the fourth embodiment is a lateral device in which the main path of current flowing during operation is parallel to the substrate. The following description will focus on the differences from the first to third embodiments, and the description of the commonalities will be omitted or simplified.

[0177] [composition] FIG. 10 is a cross-sectional view of a semiconductor device 4 according to a fourth embodiment. The semiconductor device 4 shown in FIG. 10 is a normally-off lateral FET. The semiconductor device 4 performs modulation according to the potential applied to the gate electrode 332. For example, when 0 V or a negative potential is applied to the gate electrode 332, no current flows between the drain electrode 336 and the source electrode 334. That is, the semiconductor device 4 is in a non-conductive state (off). When a positive potential is applied to the gate electrode 332, a current flows from the drain electrode 336 to the source electrode 334. That is, the semiconductor device 4 is in a conductive state (on). The current flowing from the drain electrode 336 to the source electrode 334 when the semiconductor device 4 is on is called a drain current. The drain current flows in a direction parallel to the main surface of the substrate 310 (i.e., laterally) near the interface between the electron transit layer 322 and the electron supply layer 324. The main path of the drain current does not pass through the substrate 310.

[0178] 10 , the semiconductor device 4 includes a substrate 310, a depletion layer-forming layer 312, a buffer layer 314, a breakdown voltage improving layer 316, an electron transit layer 322, an electron supply layer 324, a threshold adjustment layer 328, a gate electrode 332, a source electrode 334, and a drain electrode 336. The semiconductor device 4 further includes an insulating layer 340, a source wiring 352, a drain wiring 354, a reflective layer 370, a protective film 380, and a back electrode 390. The insulating layer 340 has a stacked structure of multiple insulating films, but this is not shown in the figure.

[0179] The semiconductor device 4 is a nitride semiconductor device in which a semiconductor layer including a channel contains a nitride semiconductor as a main component. Specifically, the depletion layer-forming layer 312, the buffer layer 314, the breakdown voltage improving layer 316, the electron transit layer 322, the electron supply layer 324, and the threshold adjustment layer 328 each contain a nitride semiconductor as a main component.

[0180] The substrate 310 is made of a nitride semiconductor. The shape of the substrate 310 in plan view is, for example, rectangular, but is not limited to this. In this embodiment, the substrate 310 includes a substrate body 310a, an n-type GaN layer 310b, and an undoped GaN layer 310c.

[0181] The substrate body 310a is, for example, a 300 μm-thick substrate body made of n-type GaN. The n-type GaN layer 310b is, for example, a 1 μm-thick layer made of n-type GaN. The undoped GaN layer 310c is, for example, a 200 nm-thick layer made of undoped GaN. The n-type GaN layer 310b and the undoped GaN layer 310c are stacked in this order on the primary surface of the substrate body 310a. The carrier concentrations of the substrate body 310a and the n-type GaN layer 310b are, for example, the same as the carrier concentrations of the substrate 10 of the first embodiment, but are not particularly limited thereto.

[0182] The substrate 310 may include only the substrate body 310a. Alternatively, the substrate 310 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, or the like. The substrate 310 may also be an insulating substrate such as sapphire.

[0183] The depletion layer-forming layer 312 is provided in contact with the upper surface of the substrate 310. The depletion layer-forming layer 312 is, for example, a 400 nm-thick film made of p-type GaN. The depletion layer-forming layer 312 is joined to the n-type GaN layer 310b via the undoped GaN layer 310c, thereby forming a depletion layer. This increases the breakdown voltage between the back electrode 390 provided on the lower surface of the substrate 310 and the drain electrode 336. Furthermore, when the substrate body 310a is a GaN substrate, it is possible to reduce variations in carbon concentration due to the off-angle. This makes it possible to maintain a constant breakdown voltage between the back electrode 390 and the back electrode 390. A source potential (for example, 0 V) ​​is applied to the back electrode 390.

[0184] The depletion layer-forming layer 312 is formed by, for example, crystal growth, but may also be formed by, for example, injecting magnesium (Mg) into the formed i-GaN. Furthermore, the depletion layer-forming layer 312 may not be a p-type nitride semiconductor layer, but may be an insulating layer obtained by injecting iron (Fe) or boron (B).

[0185] The buffer layer 314 is provided in contact with the upper surface of the depletion layer forming layer 312. The buffer layer 314 is, for example, a film made of undoped GaN with a thickness of 7 μm.

[0186] The buffer layer 314 may be an insulating layer or a semi-insulating layer. For example, the buffer layer 314 may be a film made of carbon-doped GaN (C-GaN). The carbon concentration of the buffer layer 314 may be, for example, 3×10 17 cm -3 That's all, but 1 x 10 18 cm -3The buffer layer 314 may contain n-type impurities such as Si. The concentration of the n-type impurities contained in the buffer layer 314 is lower than the carbon concentration and oxygen concentration of the buffer layer 314, and may be, for example, 5×10 16 cm -3 or less than or equal to 2 x 10 16 cm -3 It may be the following:

[0187] The breakdown voltage improving layer 316 is provided in contact with the upper surface of the buffer layer 314. In this embodiment, the breakdown voltage improving layer 316 is made of an undoped AlGaN layer. The breakdown voltage improving layer 316 is provided between the buffer layer 314 and the electron transit layer 322 and forms a heterojunction with the electron transit layer 322, thereby increasing the breakdown voltage between the back electrode 390 and the drain electrode 336.

[0188] The breakdown voltage improving layer 316 may be an insulating layer or a semi-insulating layer. For example, the breakdown voltage improving layer 316 may be a film made of carbon-doped AlGaN (C-AlGaN). The carbon concentration of the breakdown voltage improving layer 316 is, for example, 3×10 17 cm -3 That's all, but 1 x 10 18 cm -3 It may be more than that.

[0189] The provision of the depletion layer-forming layer 312, the buffer layer 314, and the breakdown voltage improving layer 316 makes it possible to suppress so-called punch-through, in which electrons leak from two-dimensional electron gas generated near the interface between the electron supply layer 324 and the electron transit layer 322 to the substrate 310. This increases the breakdown voltage of the semiconductor device 3. Note that at least one of the depletion layer-forming layer 312, the buffer layer 314, and the breakdown voltage improving layer 316 does not necessarily have to be provided.

[0190] The electron transit layer 322 is provided above the substrate 310. Specifically, the electron transit layer 322 is provided on the upper surface of the breakdown voltage improving layer 316. The electron transit layer 322 is, for example, a 150 nm thick film made of undoped GaN. Note that although the electron transit layer 322 is assumed to be undoped, it may be partially doped with Si to be n-type.

[0191] The electron transit layer 322 has a channel region. Specifically, two-dimensional electron gas, which serves as a channel, is generated near the interface between the electron transit layer 322 and the electron supply layer 324. The two-dimensional electron gas extends parallel to the major surface of the substrate 310 along the interface between the electron transit layer 322 and the electron supply layer 324.

[0192] 10, an AlN layer with a thickness of about 1 nm is provided between the electron transit layer 322 and the electron supply layer 324. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. However, the AlN layer is not necessarily required.

[0193] The electron supply layer 324 is provided to cover the upper surface of the electron transit layer 322. The electron supply layer 324 is, for example, a film made of undoped AlGaN with a thickness of 50 nm or 60 nm. The electron supply layer 324 has a larger band gap than the electron transit layer 322. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 324 and the electron transit layer 322. The electron supply layer 324 supplies electrons to a channel region (two-dimensional electron gas) formed in the electron transit layer 322.

[0194] In this embodiment, the electron transit layer 322 and the electron supply layer 324 are both layers included in a first semiconductor layer included in the semiconductor device 4. The first semiconductor layer is provided above the substrate 310.

[0195] The electron supply layer 324 is provided with a gate recess 320. The gate recess 320 is a recess provided in the upper surface of the electron supply layer 324. By providing the gate recess 320, the electric field applied to the gate electrode 332 can be more easily concentrated at the end of the gate recess 320, thereby improving gate controllability. Note that the gate recess 320 does not necessarily have to be provided.

[0196] The threshold adjustment layer 328 is an example of a p-type semiconductor layer provided above the first semiconductor layer. Specifically, the threshold adjustment layer 328 is provided between the electron supply layer 324 and the gate electrode 332. In this embodiment, the threshold adjustment layer 328 is provided so as to fill the gate recess 320. The threshold adjustment layer 328 is disposed apart from each of the source electrode 334 and the drain electrode 336 and is electrically isolated from them.

[0197] The threshold adjustment layer 328 has a thickness of 200 nm and a carrier concentration of 1×10 19 cm -3 It is a film made of p-type GaN, where p is a GaN film. The thickness and carrier concentration of the threshold adjustment layer 328 are merely examples and can be changed as appropriate.

[0198] The provision of the threshold adjustment layer 328 raises the potential of the conduction band edge in the channel portion. This reduces the carrier concentration directly below the gate electrode 332, shifting the threshold voltage of the transistor to the positive side. This allows the semiconductor device 4 to be easily realized as a normally-off FET. The threshold adjustment layer 328 may be a film made of p-type AlGaN.

[0199] In addition, a source opening 330s and a drain opening 330d are provided that penetrate the electron supply layer 324. The source opening 330s and the drain opening 330d are formed by removing at least a portion of the electron supply layer 324 and the electron transit layer 322, respectively.

[0200] The source opening 330s and the drain opening 330d are each formed so that the opening area increases with increasing distance from the substrate 310. That is, the side surfaces of the source opening 330s and the drain opening 330d are obliquely inclined. For example, the cross-sectional shape of each of the source opening 330s and the drain opening 330d is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. The inclination angle of the side surface with respect to the bottom surface of the source opening 330s is, for example, in the range of 30° to 60°. The obliquely inclined side surfaces increase the contact area between the source electrode 334 and the electron transit layer 322 (two-dimensional electron gas), thereby facilitating ohmic contact. The two-dimensional electron gas is exposed at the side surfaces of the source opening 330s and connected to the source electrode 334 at the exposed portions. The side surfaces of the source opening 330s may be perpendicular to the bottom surface of the source opening 330s. The same applies to the drain opening 330d.

[0201] Thus, by providing the source opening 330s and the drain opening 330d, it is possible to reduce the ohmic contact resistance between the two-dimensional electron gas functioning as a channel and the source electrode 334 and the drain electrode 336. That is, it is possible to reduce the on-resistance of the semiconductor device 4. Note that the source opening 330s and the drain opening 330d may not be provided, and the source electrode 334 and the drain electrode 336 may be provided in contact with the upper surface of the electron supply layer 324 at a position away from the threshold adjustment layer 328.

[0202] The gate electrode 332 is an example of a first electrode provided on the upper surface of the p-type semiconductor layer. Specifically, the gate electrode 332 is provided on the upper surface of the threshold adjustment layer 328. The gate electrode 332 is formed using a conductive material such as a metal. For example, the gate electrode 332 may be made of a material that forms an ohmic contact with the p-type GaN layer, but is not limited thereto, and may be made of a material that forms a Schottky contact with the p-type GaN layer. For example, palladium (Pd), nickel (Ni)-based material, tungsten silicide (WSi), gold (Au), etc. may be used.

[0203] The source electrode 334 is electrically connected to the first semiconductor layer and is provided apart from the threshold adjustment layer 328 and the gate electrode 332. The source electrode 334 is provided so as to sandwich the threshold adjustment layer 328 and the gate electrode 332 between the source electrode 334 and the drain electrode 336. Specifically, the source electrode 334 is provided in contact with the bottom and side surfaces of the source opening 330s. The source electrode 334 is in direct contact with the two-dimensional electron gas on the side surface of the source opening 330s. This reduces the contact resistance between the source electrode 334 and the two-dimensional electron gas, thereby reducing the on-resistance of the semiconductor device 4.

[0204] The source electrode 334 is formed using a conductive material such as a metal. The material of the source electrode 334 may be, for example, Ti / Al (a laminated structure of a Ti layer and an Al layer), which can be ohmically connected to the n-type GaN layer by heat treatment.

[0205] The drain electrode 336 is an example of a second electrode electrically connected to the first semiconductor layer, and is provided away from the threshold adjustment layer 328 and the gate electrode 332. Specifically, the drain electrode 336 is provided in contact with the bottom and side surfaces of the drain opening 330d. The drain electrode 336 is in direct contact with the two-dimensional electron gas on the side surfaces of the drain opening 330d. This reduces the contact resistance between the drain electrode 336 and the two-dimensional electron gas, thereby reducing the on-resistance of the semiconductor device 4.

[0206] The drain electrode 336 is formed using a conductive material such as a metal. As with the material of the source electrode 334, the material of the drain electrode 336 may be a material that forms an ohmic contact with n-type GaN, such as Ti / Al.

[0207] The insulating layer 340 is an example of a layer including a first insulating layer provided above the first electrode and a second insulating layer provided above the wiring connected to the second electrode. Specifically, the insulating layer 340 has a laminated structure including an interlayer insulating layer covering the gate electrode 332 and a protective layer covering the source wiring 352 and the drain wiring 354. Although not shown in FIG. 10 , the interlayer insulating layer and the protective layer included in the insulating layer 340 may each have a laminated structure of multiple insulating layers.

[0208] For example, the insulating layer 340, which is the lowest layer in the stacked structure and is in contact with the electron supply layer 324, is a SiN film. This can suppress electron traps on the surface of the electron supply layer 324. Other insulating films included in the insulating layer 340 include, for example, silicon nitride (SiN), silicon oxide (SiO2), and aluminum oxide (Al2O3). Alternatively, the insulating layer 340 may include an insulating film formed using an insulating resin material such as a photosensitive polymer. The insulating layer 340 corresponds to the insulating layer 40 and the protective layer 60 included in the semiconductor device 1 according to the first embodiment.

[0209] The source wiring 352 is provided above the source electrode 334 and is connected to the source electrode 334 through an opening provided in the insulating layer 340. Specifically, the source wiring 352 is electrically connected to the source electrode 334 through a via conductor. The source wiring 352 is formed using a conductive material such as a metal. For example, the source wiring 352 is a plated film made of Au. The via conductor has a layered structure of a Ti film, an Al film, a Ni film, and an Au film, which are layered in this order from the source electrode 334 side.

[0210] In this embodiment, the source wiring 352 is provided so as to extend from the source electrode 334 beyond the gate electrode 332 toward the drain electrode 336. That is, in a plan view of the substrate 310, the source wiring 352 overlaps the gate electrode 332. This allows the source wiring 352 to function as a source field plate, thereby reducing the parasitic capacitance between the gate and the drain.

[0211] The drain wiring 354 is provided above the drain electrode 336 and is connected to the drain electrode 336 through an opening provided in the insulating layer 340. Specifically, the drain wiring 354 is electrically connected to the drain electrode 336 through a via conductor. The drain wiring 354 is formed using a conductive material such as a metal. For example, the drain wiring 354 is a plated film made of Au. The via conductor has a layered structure of a Ti film, an Al film, a Ni film, and an Au film, which are layered in this order from the drain electrode 336 side.

[0212] The reflective layer 370 is provided above the gate electrode 332. The reflective layer 370 is also provided above the source wiring 352 and the drain wiring 354. Specifically, the reflective layer 370 is provided above the insulating layer 340. More specifically, the reflective layer 370 is provided so as to cover and contact the upper surface of the insulating layer 340, for example.

[0213] The reflective layer 370 is a metal reflective layer containing silver (Ag) or aluminum (Al). For example, the reflective layer 370 has a layered structure of a Ti film and an Ag film stacked in this order from the bottom, or a layered structure of a Ti film and an Al film stacked in this order from the bottom.

[0214] In this embodiment, the reflective layer 370 is not electrically connected to any of the gate electrode 332, the source electrode 334, and the drain electrode 336. For example, the reflective layer 370 is in an electrically floating state.

[0215] The reflective layer 370 is provided in the element region of the semiconductor device 4. Details will be described later with reference to FIG. 16B , but the semiconductor device 4 has an element region and an element isolation region when viewed from above on the substrate 310. The element region is a region that contributes to the modulation operation of the semiconductor device 4 when the substrate 310 is viewed from above. Specifically, the element region includes, when viewed from above, a region overlapping the gate electrode 332 (gate region), a region overlapping the source electrode 334 (source region), a region overlapping the drain electrode 336 (drain region), a region overlapping the region between the gate electrode 332 and the source electrode 334 (gate-source region), and a region overlapping the region between the gate electrode 332 and the drain electrode 336 (gate-drain region). In this embodiment, the reflective layer 370 is provided so as to straddle each of the gate region, source region, drain region, gate-source region, and gate-drain region when viewed from above on the substrate 310. The reflective layer 370 is provided so as to overlap the source wiring 352 when the substrate 310 is seen in plan view.

[0216] The protective film 380 is provided to protect the reflective layer 370. For example, the protective film 380 is formed using a polymer material such as polybenzoxazole (PBO) that has excellent heat resistance, insulating properties, and water resistance.

[0217] The semiconductor device 4 configured as above is manufactured, for example, by the method described below.

[0218] First, a nitride semiconductor is crystal-grown on the primary surface of the substrate body 310a by epitaxial growth, such as MOVPE or HVPE. For example, an n-type GaN layer 310b, an undoped GaN layer 310c, a p-type GaN film serving as the depletion layer-forming layer 312, an undoped GaN film serving as the buffer layer 314, an AlGaN film serving as the breakdown voltage improving layer 316, an undoped GaN film serving as the electron transit layer 322, and an undoped AlGaN film serving as the electron supply layer 324 are formed in this order on the primary surface of the substrate body 310a. Then, portions of the undoped AlGaN film and the undoped GaN film are partially removed by dry etching or the like to form the gate recess 320, the source opening 330s, and the drain opening 330d. Then, a p-type GaN film serving as the threshold adjustment layer 328 is formed by epitaxial growth, such as MOVPE or HVPE, so as to cover the gate recess 320. Then, the p-type GaN film is patterned into a predetermined shape by dry etching or the like.

[0219] Next, a metal film is formed by electron beam evaporation, sputtering, or the like to cover the threshold adjustment layer 328, and unnecessary portions are removed by etching, lift-off, or the like to form the gate electrode 332. Furthermore, a metal film is formed to cover the source opening 330s and the drain opening 330d, and unnecessary portions are removed by etching, lift-off, or the like to form the source electrode 334 and the drain electrode 336. The order in which the gate electrode 332, the source electrode 334, and the drain electrode 336 are formed may be arbitrary. Furthermore, a metal film is formed on the lower surface of the substrate 310 by electron beam evaporation, sputtering, or the like to form the back electrode 390. The back electrode 390 may be formed after the source wiring 352, the reflective layer 370, and the like are formed. Alternatively, the back electrode 390 may not be formed.

[0220] After forming the gate electrode 332, the source electrode 334, and the drain electrode 336, the lower portion of the insulating layer 340 is formed. The lower portion of the insulating layer 340 is formed by, for example, plasma CVD or atomic layer deposition. After forming the lower portion of the insulating layer 340, openings are formed in the lower portion of the insulating layer 340 by, for example, dry etching, to expose at least a portion of the source electrode 334 and the drain electrode 336. Thereafter, the source wiring 352 and the drain wiring 354 are formed so as to fill the openings. The source wiring 352 and the drain wiring 354 are formed by, for example, sequentially depositing films of Ti, Al, Ni, etc. by sputtering or electron beam evaporation, followed by Au plating.

[0221] Furthermore, an upper portion of the insulating layer 340 is formed so as to cover the source wiring 352 and the drain wiring 354. The upper portion of the insulating layer 340 is formed by, for example, a plasma CVD method or an ALD method. After the upper portion of the insulating layer 340 is formed, the reflective layer 370 is formed by sputtering, electron beam evaporation, plating, or the like. The reflective layer 370 may also be formed by bonding another substrate on which a metal reflective film is formed.

[0222] In this way, it is possible to manufacture the semiconductor device 4 shown in Fig. 10. The above-described method for manufacturing the semiconductor device 4 is merely an example, and is not particularly limited.

[0223] [Characteristic composition] Next, the main characteristic configuration of the semiconductor device 4 according to this embodiment will be described.

[0224] In the semiconductor device 4 according to this embodiment, when a voltage is applied to the gate electrode 332, light is emitted near the pn junction between the threshold adjustment layer 328, which is a p-type semiconductor layer, and the electron transit layer 322 containing two-dimensional electron gas, and in a region of the electron transit layer 322 between the gate electrode 332 and the drain electrode 336. The emitted light has a wavelength corresponding to the band gap of GaN, specifically, near-ultraviolet light or visible light ranging from violet to blue. More specifically, light in the range of 330 nm to 400 nm is emitted.

[0225] In this embodiment, a reflective layer 370 containing Al or Ag is provided. As shown in FIG. 3, Al or Ag has a high reflection coefficient for the wavelength of light generated near the pn junction. In the case of aluminum (Al) and silver (Ag), the reflection coefficient is 90% or more. Therefore, the reflective layer 370 can reflect light.

[0226] As a result, the light reflected by the reflective layer 370 is absorbed by the electron transit layer 322, generating electron-hole pairs. Some of the generated electron-hole pairs recombine to emit light, which is reflected by the reflective layer 370. The reflective layer 370 can increase the utilization efficiency of self-excited light through the photon recycling effect, which repeats light emission and absorption. This can improve the electrical characteristics of the semiconductor device 4, such as reducing the on-resistance, increasing the drain current, or suppressing current collapse. Note that the reflection by the reflective layer 370 is mirror reflection. Light from a light-emitting section located below the reflective layer 370 can be efficiently reflected back to the light-emitting section.

[0227] Furthermore, in this embodiment, light emitted by the lateral transistor itself is used, eliminating the need for a separate light emitting element such as a light emitting diode, thereby enabling the chip area of ​​the semiconductor device 4 to be reduced.

[0228] [Variations] Next, a description will be given of a modification of embodiment 4. The following description will focus on the differences from embodiment 4, and the description of commonalities will be omitted or simplified.

[0229] <Variation 1> 11 is a cross-sectional view of a semiconductor device 4A according to a first modification of the fourth embodiment. The semiconductor device 4A according to this modification is different from the semiconductor device 4 in that an insulating layer 440 is provided instead of the insulating layer 340. The insulating layer 440 is different in that it is partially thinner than the insulating layer 340. Specifically, in the semiconductor device 4A, as shown in FIG. 11, the insulating layer 440 includes a thin film portion 440a and a thick film portion 440b.

[0230] The thin film portion 440a is a part of the insulating layer 440 and is a portion located between the gate electrode 332 and the drain electrode 336 in a plan view of the substrate 310. The thick film portion 440b is a part of the insulating layer 440 and is a portion located between the gate electrode 332 and the source electrode 334 in a plan view of the substrate 310. The thick film portion 440b can be considered to be a portion overlapping the source wiring 352 in a plan view. As shown in FIG. 11 , the source wiring 352 protrudes toward the drain electrode 336 more than the gate electrode 332, so a portion of the thick film portion 440b is located between the gate electrode 332 and the drain electrode 336. The thin film portion 440a is located between the thick film portion 440b and the drain electrode 336.

[0231] The thickness of the thin film portion 440a is thinner than the thickness of the thick film portion 440b. As a result, in the semiconductor device 4A, the reflective layer 370 is closer to the electron transit layer 322, which is the light-emitting portion, between the gate and the drain, compared to the semiconductor device 4 according to the fourth embodiment. This increases the light reflection efficiency of the reflective layer 370, and improves the light utilization efficiency due to the photon recycling effect. This can improve the electrical characteristics of the semiconductor device 4A, such as reducing the on-resistance, increasing the drain current, and suppressing current collapse.

[0232] The thickness of the thin film portion 440a is not particularly limited, but is, for example, thinner than the thickness of the source electrode 334. The thickness of the thin film portion 440a may also be thinner than the thickness of the threshold adjustment layer 328. In other words, the lower surface of the reflective layer 370 in contact with the thin film portion 440a may be located lower than the upper surface of the source electrode 334 or the upper surface of the threshold adjustment layer 328. The thin film portion 440a is formed by stacking an insulating film and then removing part of the stacked insulating film by dry etching or the like in the region where the thin film portion 440a is to be formed.

[0233] <Variation 2> 12 is a cross-sectional view of a semiconductor device 4B according to Modification 2 of Embodiment 4. Semiconductor device 4B according to this modification differs from semiconductor device 4A in that it includes an insulating layer 441 instead of insulating layer 440. Insulating layer 441 includes a first film 442, a second film 443, and a third film 444.

[0234] The first film 442 is an insulating film that covers the upper surface of the electron supply layer 324. The first film 442 is, for example, a SiN film. The first film 442 may also cover the upper surface of the threshold adjustment layer 328. In this case, the first film 442 has an opening that exposes a portion of the upper surface of the threshold adjustment layer 328 and allows the gate electrode 332 and the threshold adjustment layer 328 to come into contact with each other.

[0235] The second film 443 is an insulating film provided above the first film 442. In this modification, the second film 443 has a different composition from the third film 444. Specifically, the second film 443 is a film containing at least one of Al and Ga and at least one of O and N. For example, the second film 443 is an Al2O3 film. Alternatively, the second film 443 may be a GaO film. The second film 443 may cover the upper surfaces of the gate electrode 332, the source electrode 334, and the drain electrode 336. In this case, the second film 443 has an opening that exposes a portion of the upper surface of the source electrode 334 and provides a via conductor that electrically connects the source wiring 352 and the source electrode 334. The same applies to the portion covering the drain electrode 336 or the gate electrode 332.

[0236] The third film 444 is an insulating film provided above the second film 443. The third film 444 is an SiO2 film, a SiN film, or the like. In this modification, the third film 444 is provided only on the thick film portion 440b out of the thin film portion 440a and the thick film portion 440b. In other words, the third film 444 is not provided on the thin film portion 440a. In the region where the thin film portion 440a is to be formed, the third film 444 is completely removed.

[0237] The removal of the third film 444 in the thin film portion 440a is performed by, for example, etching. At this time, the second film 443 functions as an etching stopper layer. For example, the second film 443 is a film having a lower etching rate than the third film 444. This prevents the third film 444 from being easily removed when etching is performed, and makes it possible to easily form the thin film portion 440a with the desired thickness.

[0238] This allows the distance between the reflective layer 370 and the electron transit layer 322, which is the light-emitting portion, to be closer to the designed value. This increases the light reflection efficiency of the reflective layer 370, and improves the light utilization efficiency due to the photon recycling effect. This allows for improved electrical characteristics of the semiconductor device 4B, such as reduced on-resistance, increased drain current, and suppression of current collapse.

[0239] <Variation 3> 13 is a cross-sectional view of a semiconductor device 4C according to Modification 3 of Embodiment 4. The semiconductor device 4C according to this modification differs from the semiconductor device 4B in that the reflective layer 370 is electrically connected to the source electrode 334. Specifically, in the semiconductor device 4C, as shown in FIG. 13, an opening that exposes the source wiring 352 is provided in the third film 444 of the insulating layer 441, and the reflective layer 370 is electrically connected to the source wiring 352 through the opening, and is electrically connected to the source electrode 334 via the source wiring 352.

[0240] This allows the reflective layer 370 to have the same potential as the source electrode 334, thereby increasing the capacitance (Ciss) between the gate and the source. This makes it possible to suppress false ignition during switching operations. As a result, a semiconductor device 4C with improved electrical characteristics can be realized.

[0241] The third film 444 does not have to be provided on the upper surface of the source wiring 352, and the reflective layer 370 may be in direct contact with the source wiring 352. When the reflective layer 370 is in contact with the source wiring 352, it is necessary to avoid contact between the reflective layer 370 and the drain electrode 336 and the drain wiring 354. For this reason, for example, an insulating film is provided between the reflective layer 370 and each of the drain electrode 336 and the drain wiring 354, ensuring a certain distance.

[0242] Furthermore, the reflective layer 370 may be used as a source field plate. That is, the source wiring 352 does not need to extend further toward the drain electrode 336 than the gate electrode 332. In this case, the area of ​​the source wiring 352 containing Au, which has a low reflection coefficient, is reduced, and the amount of light reflected by the reflective layer 370 can be increased. This further increases the light utilization efficiency, and further improves the electrical characteristics of the semiconductor device 4C.

[0243] (Embodiment 5) Next, a fifth embodiment will be described.

[0244] The semiconductor device according to the fifth embodiment is mainly different from the semiconductor device according to the fourth embodiment in that it includes a lateral diode instead of a lateral FET. The following description will focus on the differences from the fourth embodiment, and description of commonalities will be omitted or simplified.

[0245] FIG. 14 is a cross-sectional view of a semiconductor device 5 according to a fifth embodiment. The semiconductor device 5 is a lateral diode. Specifically, the semiconductor device 5 is a pn diode formed by a p-type semiconductor layer 528 and two-dimensional electron gas generated by the heterostructure. The semiconductor device 5 performs a rectifying operation in response to a voltage applied between the anode electrode 532 and the cathode electrode 536. A forward current flowing from the anode electrode 532 to the cathode electrode 536 flows in a direction parallel to the main surface of the substrate 310 (i.e., a lateral direction). The main path of the forward current does not pass through the substrate 310. The semiconductor device 5 shown in FIG. 14 can be manufactured, for example, by the same process and using the same wafer as the semiconductor devices 4, 4A, 4B, or 4C according to the fourth embodiment and its modifications.

[0246] 14, the semiconductor device 5 includes a substrate 310, a depletion layer-forming layer 312, a buffer layer 314, a breakdown voltage improving layer 316, an electron transit layer 322, an electron supply layer 324, a p-type semiconductor layer 528, an anode electrode 532, a cathode electrode 536, an insulating layer 340, a cathode wiring 554, a reflective layer 370, and a back surface electrode 390. The components other than the p-type semiconductor layer 528, the anode electrode 532, the cathode electrode 536, and the cathode wiring 554 are the same as the components included in the semiconductor device 4 according to the fourth embodiment.

[0247] The p-type semiconductor layer 528, the anode electrode 532, and the cathode electrode 536 correspond to the threshold adjustment layer 328, the gate electrode 332, and the drain electrode 336, respectively, of the semiconductor device 4. The p-type semiconductor layer 528, the anode electrode 532, and the cathode electrode 536 function as the p-type layer, the anode electrode, and the cathode electrode, respectively, of the pn diode. The anode electrode 532 is an example of a first electrode according to the present disclosure, and the cathode electrode 536 is an example of a second electrode according to the present disclosure.

[0248] The electron supply layer 324 has a recess 520 provided directly below the anode electrode 532, and an opening 530 provided directly below the cathode electrode 536. The recess 520 and the opening 530 are the same as the gate recess 320 and the drain opening 330d provided in the semiconductor device 4 according to the fourth embodiment, respectively. The recess 520 and the opening 530 do not necessarily have to be provided.

[0249] The cathode wiring 554 corresponds to the drain wiring 354 included in the semiconductor device 4. The cathode wiring 554 is provided above the cathode electrode 536 and is electrically connected to the cathode electrode 536 through an opening provided in the insulating layer 340. Specifically, the cathode wiring 554 is electrically connected to the cathode electrode 536 through a via conductor. The cathode wiring 554 is formed using a conductive material such as a metal. For example, the cathode wiring 554 is a plated film made of Au. The via conductor has a layered structure of a Ti film, an Al film, a Ni film, and an Au film, which are layered in this order from the cathode electrode 536 side.

[0250] In this embodiment, the reflective layer 370 is provided above the anode electrode 532. The reflective layer 370 is also provided above the cathode electrode 536. Specifically, the reflective layer 370 is provided above the insulating layer 340. The reflective layer 370 is provided, for example, so as to contact and cover the upper surface of the insulating layer 340.

[0251] In this embodiment, the reflective layer 370 is not electrically connected to either the anode electrode 532 or the cathode electrode 536. For example, the reflective layer 370 is in an electrically floating state.

[0252] The reflective layer 370 is provided in the element region of the semiconductor device 5. In a plan view of the substrate 310, the semiconductor device 5 is provided with an element region and an element isolation region. The element region is a region that contributes to the rectifying operation of the semiconductor device 5 when the substrate 310 is viewed in a plan view. Specifically, in a plan view, the element region includes a region (anode region) overlapping with the anode electrode 532, a region (cathode region) overlapping with the cathode electrode 536, and a region (main operating region) between the anode electrode 532 and the cathode electrode 536. In the present embodiment, the reflective layer 370 is provided so as to overlap with the anode region, the cathode region, and the main operating region when the substrate 310 is viewed in a plan view.

[0253] During rectification of the semiconductor device 5, a forward voltage is applied between the anode electrode 532 and the cathode electrode 536, causing a forward current to flow from the anode electrode 532 to the cathode electrode 536. When a forward current flows through the pn junction, light is generated near the pn junction. The light generated near the pn junction has a wavelength corresponding to the band gap of GaN, specifically, near-ultraviolet light or visible light ranging from violet to blue. More specifically, light in the range of 330 nm to 400 nm is emitted.

[0254] In this embodiment, as in the fourth embodiment, the reflective layer 370 is provided, and therefore the utilization efficiency of self-excited light can be improved by the photon recycling effect, thereby improving the electrical characteristics of the semiconductor device 5 including the lateral diode, such as increasing the forward current.

[0255] Furthermore, in this embodiment, the light emitted by the lateral diode itself is used, eliminating the need for a separate light emitting element such as a light emitting diode, thereby enabling the chip area of ​​the semiconductor device 5 to be reduced.

[0256] An Ag film or an Al film may be provided on the lower surface of the cathode wiring 554. Furthermore, when the cathode wiring 554 has a laminated structure of a Ti film and an Au plating layer, an Ag film or an Al film may be provided between the Ti film and the Au plating layer. This can suppress light absorption by the Au plating and improve light utilization efficiency. Furthermore, although not shown, an anode wiring connected to the anode electrode 532 may be provided. The anode wiring may also be modified in a manner that is applicable to the cathode wiring 554.

[0257] [Variations] Next, a description will be given of a variation of embodiment 5. The following description will focus on the differences from embodiment 5, and the description of commonalities will be omitted or simplified.

[0258] 15 is a cross-sectional view of a semiconductor device 5A according to a modification of the fifth embodiment. The semiconductor device 5A according to this modification differs from the semiconductor device 5 in that the reflective layer 370 is electrically connected to the cathode electrode 536. Specifically, in the semiconductor device 5A, as shown in FIG. 15, an opening that exposes the cathode wiring 554 is provided in the insulating layer 340, and the reflective layer 370 is electrically connected to the cathode wiring 554 through the opening, and is electrically connected to the cathode electrode 536 through the cathode wiring 554. The reflective layer 370 may be provided so as to be in direct contact with the upper surface of the cathode wiring 554.

[0259] This allows the reflective layer 370 to have the same potential as the cathode electrode 536, thereby reducing the concentration of the electric field on the cathode electrode 536. This increases the breakdown voltage of the semiconductor device 5A, thereby achieving a semiconductor device 5A with improved electrical characteristics.

[0260] Furthermore, the reflective layer 370 may be electrically connected to the anode electrode 532 without being connected to the cathode electrode 536. For example, an opening for exposing the anode wiring (not shown) may be provided in the insulating layer 340, and the reflective layer 370 may be connected to the anode electrode 532 through the opening. Alternatively, the reflective layer 370 may be provided so as to be in direct contact with the upper surface of the anode electrode 532.

[0261] (flat layout) Next, an example of a planar layout of electrodes of a semiconductor device according to each of the above-described embodiments and modifications will be described with reference to FIGS. 16A and 16B. FIG.

[0262] 16A is a top view of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 shown in FIG. 16A is provided with a plurality of gate electrodes 32 and a plurality of source electrodes 34. The gate electrodes 32 and the source electrodes 34 each have a shape that is elongated in one direction (the y-axis direction). The gate electrodes 32 and the source electrodes 34 are arranged alternately, one by one, along the short side direction of each electrode. The cross section taken along line II in FIG. 16A corresponds to FIG. 1.

[0263] In the semiconductor device 1, an element region 10A and an element isolation region 10B are provided on the substrate 10 in plan view.

[0264] The element region 10A is a region that contributes to the modulation operation of the transistor. The element region 10A is also a region that includes the main path of the drain current. Specifically, the element region 10A includes a gate region where the gate electrode 32 is provided, a source region where the source electrode 34 is provided, and a gate-source region between the gate electrode 32 and the source electrode 34.

[0265] The element isolation region 10B is a region where pads to which wires for supplying power to at least one of the gate electrode 32, the source electrode 34, and the drain electrode 36 are connected are provided. For example, as shown in FIG. 16A , a gate pad 32G and a source pad 34S are provided in the element isolation region 10B. Note that the element isolation region 10B may also be provided with a pad to which a wire for supplying power to the drain electrode 36 is connected. Alternatively, power may be supplied directly to the drain electrode 36 from the back surface of the semiconductor device 1.

[0266] The region from which the semiconductor device 1 emits light during operation is mainly the element region 10A. For this reason, the reflective layer 70 of the semiconductor device 1 is provided in the element region 10A. This allows the light generated in the element region 10A to be efficiently reflected, and the light utilization efficiency can be improved by the photon recycling effect.

[0267] The semiconductor devices 1A and 1B according to the modified example of the first embodiment also have the same planar layout. The semiconductor devices 2, 2A, 3, and 3A including vertical diodes also have the same planar layout as that shown in FIG. 16A. In the case of a semiconductor device including a vertical diode, the element region 10A is a region that contributes to rectification operation rather than modulation operation and includes a main path of forward current. For example, the element isolation region 10B shown in FIG. 16A may be provided with pads to which wires for supplying power to the anode electrode 132 are connected, instead of the gate pad 32G and the source pad 34S. In a semiconductor device including a vertical diode, the element isolation region 10B may be provided with pads to which wires for supplying power to the cathode electrode 136 are connected. Alternatively, power may be supplied directly to the cathode electrode 136 from the rear surface of each semiconductor device. 7A, 7B, 9A, and 9B, power may be supplied directly to the reflective layer 70 and the anode electrode 132 in the element region 10A. This eliminates the need for an element isolation region for providing a pad for the anode electrode 132, thereby improving area efficiency.

[0268] 16B is a top view of a semiconductor device 4 according to the fourth embodiment. The semiconductor device 4 shown in FIG. 16B is provided with a plurality of gate electrodes 332, a plurality of source electrodes 334, and a plurality of drain electrodes 336. The gate electrodes 332, the source electrodes 334, and the drain electrodes 336 are each elongated in one direction (the y-axis direction). The source electrodes 334, the gate electrodes 332, and the drain electrodes 336 are repeatedly arranged in this order along the respective short-side directions. The cross section taken along the line XX shown in FIG. 16B corresponds to FIG. 10.

[0269] In the semiconductor device 4, an element region 310A and an element isolation region 310B are provided on the substrate 310 in plan view.

[0270] The element region 310A is a region that contributes to the modulation operation of the transistor. The element region 310A is also a region that includes the main path of the drain current. Specifically, the element region 310A includes a gate region where the gate electrode 332 is provided, a source region where the source electrode 334 is provided, a drain region where the drain electrode 336 is provided, a gate-source region between the gate electrode 332 and the source electrode 334, and a gate-drain region between the gate electrode 332 and the drain electrode 336.

[0271] The element isolation region 310B is a region where pads to which wires for supplying power to at least one of the gate electrode 332, the source electrode 334, and the drain electrode 336 are connected are provided. For example, as shown in FIG. 16B, the element isolation region 310B is provided with a source pad 334S and a drain pad 336D. Although not included in FIG. 16B for convenience, the region where the gate pad 332G is provided is also part of the element isolation region 310B.

[0272] The region from which the semiconductor device 4 emits light during operation is mainly the element region 310A. For this reason, the reflective layer 370 of the semiconductor device 4 is provided in the element region 310A. This allows the light generated in the element region 310A to be efficiently reflected, and the light utilization efficiency can be improved by the photon recycling effect.

[0273] The semiconductor devices 4A, 4B, and 4C according to the modifications of the fourth embodiment also have the same planar layout. The semiconductor devices 5 and 5A including a lateral diode also have the same planar layout as that shown in FIG. 16B. In the case of a semiconductor device including a lateral diode, the element region 310A is a region that contributes to rectification operation rather than modulation operation and includes a main path of forward current. For example, the element isolation region 310B shown in FIG. 16B may be provided with a pad to which a wire for supplying power to the anode electrode 532 is connected and a pad to which a wire for supplying power to the cathode electrode 536 is connected, instead of the gate pad 332G, the source pad 334S, and the drain pad 336D. In the case of the semiconductor device 5A shown in FIG. 15, power may be directly supplied to the reflective layer 370 and the cathode electrode 536 in the element region 310A. The element isolation region may be provided with a pad to which a wire for supplying power to the anode electrode 532 is connected. Since an element isolation region for providing a pad for the cathode electrode 536 is not required, area efficiency can be improved.

[0274] (Other embodiments) Although the semiconductor device according to one or more aspects has been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as it does not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0275] For example, in the above embodiment, numerical values ​​such as the thickness and carrier concentration of each layer are given, but the above numerical values ​​are merely examples and are not limited to the above numerical values.

[0276] Furthermore, for example, the semiconductor layers included in the semiconductor device may contain a semiconductor other than a nitride semiconductor as a main component. For example, the first semiconductor layer and the p-type semiconductor layer according to the present disclosure may each contain gallium arsenide (GaAs) as a main component. Alternatively, the first semiconductor layer and the p-type semiconductor layer may each contain Si or SiC as a main component.

[0277] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents. [Industrial Applicability]

[0278] The present disclosure can be used in power devices used in power supply circuits or inverter circuits of electrical equipment. [Explanation of symbols]

[0279] 1, 1A, 1B, 2, 2A, 2B, 3, 3A, 3B, 4, 4A, 4B, 4C, 5, 5A semiconductor device 10,310 board 10A, 310A element area 10B, 310B element isolation region 12 Drift Layer 14, 18 Base layer 16 Block Layer 20 Gate opening 20a, 30a bottom 20b, 30b side 22, 322 Electron transit layer 24, 324 electron supply layer 28, 328 Threshold adjustment layer 30, 330s Source opening 32, 332 gate electrode 32G, 332G gate pad 34, 334 Source electrode 34S, 334S Saucepad 36, 336 Drain electrode 40, 340, 440, 441 Insulation layer 41 Interlayer insulating film 42 Protective insulating film 50, 150 via conductor 52, 352 Source wiring 60 protective layer 70, 71, 370 reflective layer 128, 216, 528 p-type semiconductor layer 132, 232, 532 Anode electrode 136, 536 cathode electrode 152 Anode wiring 310a Board body 310b n-type GaN layer 310c Undoped GaN layer 312 Depletion layer formation layer 314 Buffer Layer 316 Pressure resistance improvement layer 320 Gate Recess 330d drain opening 336D Drain Pad 354 Drain wiring 380 Protective film 390 Back electrode 440a Thin film part 440b Thick film part 442 1st membrane 443 Second membrane 444 Third membrane 520 Recess 530 Opening 554 Cathode wiring

Claims

1. A substrate; a first semiconductor layer provided above the substrate; a p-type semiconductor layer provided above the first semiconductor layer; a gate electrode provided on an upper surface of the p-type semiconductor layer; a source electrode electrically connected to the first semiconductor layer and provided apart from the p-type semiconductor layer and the gate electrode; a drain electrode provided below the substrate; a reflective layer containing Ag or Al and provided above the gate electrode; In a plan view of the substrate, an element region that contributes to modulation operation; an element isolation region in which a pad to which a wire for supplying power to at least one of the gate electrode, the source electrode, and the drain electrode is connected is provided; the reflective layer is provided in the element region; Semiconductor devices.

2. the reflective layer is not electrically connected to either the source electrode or the gate electrode; The semiconductor device of claim 1 .

3. the reflective layer is electrically connected to the source electrode; The semiconductor device of claim 1 .

4. a first insulating layer provided above the gate electrode; a source wiring provided above the first insulating layer and connected to the source electrode through an opening provided in the first insulating layer; a second insulating layer provided above the source wiring; The reflective layer is provided above the second insulating layer. The semiconductor device according to any one of claims 1 to 3.

5. a first insulating layer provided above the gate electrode; a source wiring provided above the first insulating layer and connected to the source electrode through an opening provided in the first insulating layer; the first insulating layer has a laminated structure of a plurality of insulating layers, The reflective layer is provided within the first insulating layer. The semiconductor device according to any one of claims 1 to 3.

6. A substrate; a first semiconductor layer provided above the substrate; a p-type semiconductor layer provided above the first semiconductor layer; an anode electrode provided on an upper surface of the p-type semiconductor layer; a cathode electrode provided below the substrate; a reflective layer provided above the anode electrode, In a plan view of the substrate, an element region that contributes to a rectifying operation; an element isolation region in which a pad to which a wire for supplying power to at least one of the anode electrode and the cathode electrode is connected is provided; the reflective layer is provided in the element region; Semiconductor devices.

7. the first semiconductor layer includes an electron transit layer and an electron supply layer provided above the electron transit layer, the p-type semiconductor layer is provided on and in contact with the electron supply layer. The semiconductor device of claim 6.

8. The first semiconductor layer includes an n-type semiconductor layer. The semiconductor device of claim 6.

9. The reflective layer contains Ag or Al.

9. The semiconductor device according to claim 6.

10. the reflective layer is not electrically connected to the anode electrode; 9. The semiconductor device according to claim 6.

11. the reflective layer is electrically connected to the anode electrode; 9. The semiconductor device according to claim 6.

12. A substrate; a first semiconductor layer provided above the substrate; a p-type semiconductor layer provided above the first semiconductor layer; a first electrode provided on an upper surface of the p-type semiconductor layer; a second electrode electrically connected to the first semiconductor layer and provided apart from the p-type semiconductor layer and the first electrode; a reflective layer provided above the first electrode, In a plan view of the substrate, an element region including a main path of current flowing through the first semiconductor layer; an element isolation region in which a pad to which a wire for supplying power to at least one of the first electrode and the second electrode is connected is provided; the main path does not pass through the substrate; the reflective layer is provided in the element region; Semiconductor devices.

13. a source electrode electrically connected to the first semiconductor layer and provided so as to sandwich the p-type semiconductor layer and the first electrode between the source electrode and the second electrode; the first electrode is a gate electrode, the second electrode is a drain electrode; The semiconductor device of claim 12.

14. a first insulating layer provided between the first electrode and the reflective layer; The first insulating layer is a thin film portion located between the gate electrode and the drain electrode in a plan view of the substrate; a thick film portion located between the gate electrode and the source electrode in a plan view of the substrate, The thickness of the thin film portion is thinner than the thickness of the thick film portion.

14. The semiconductor device of claim 13.

15. The first insulating layer is a first film covering an upper surface of the first semiconductor layer; a second film provided above the first film; a third film provided above the second film, the second film has a different composition than the third film; the third film is provided only in the thick film portion of the thin film portion and the thick film portion; 15. The semiconductor device of claim 14.

16. the first electrode is an anode electrode, the second electrode is a cathode electrode; The semiconductor device of claim 12.

17. The reflective layer contains Ag or Al.

17. The semiconductor device according to any one of claims 12 to 16.

18. the reflective layer is electrically connected to neither the first electrode nor the second electrode; 17. The semiconductor device according to any one of claims 12 to 16.

19. the reflective layer is electrically connected to the second electrode; 17. The semiconductor device according to any one of claims 12 to 16.

20. the first semiconductor layer and the p-type semiconductor layer each contain a nitride semiconductor as a main component; 17. The semiconductor device according to any one of claims 1 to 3, 6 to 8, and 12 to 16.

Images