Metal contamination evaluation method for sheet heat treatment furnace and method for manufacturing semiconductor wafer

Abstract

To provide a new method for evaluating metal contamination of a sheet heat treatment furnace.SOLUTION: A metal contamination evaluation method for a sheet heat treatment furnace includes: mounting a plurality of semiconductor wafers on a mounting member provided in a sheet heat treatment furnace to be evaluated and executing heat treatment on the semiconductor wafers in the heat treatment furnace; and acquiring in-plane characteristic value distribution information for each of the plurality of semiconductor wafers after the heat treatment, wherein the plurality of semiconductor wafers are different from each other in the angle θ formed by a reference direction of the semiconductor wafer with respect to a reference angle direction during mounting on the mounting member, and correction treatment is executed on one or more pieces of the acquired in-plane characteristic value distribution information. The correction treatment is to determine a reference angle θr of the angle θ, and perform coordinate correction based on the difference between angles θ and θr for the in-plane characteristic value distribution information of the semiconductor wafers with the angle θ other than θr to correct the positional coordinates of the in-plane characteristic value distribution information to the positional coordinates on the mounting member when the semiconductor wafers are mounted at the reference angle θr, and metal contamination of the heat treatment furnace is evaluated on the basis of whether a characteristic value abnormal position is observed in the same region in the plurality of pieces of in-plane characteristic value distribution information including the in-plane characteristic value distribution information after the correction treatment.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present invention relates to a method for evaluating metal contamination in a single-wafer heat treatment furnace and a method for manufacturing semiconductor wafers. [Background technology]

[0002] Examples of processes carried out during the manufacturing process of semiconductor wafers such as silicon wafers include various heat treatments such as epitaxial layer formation, annealing, and thermal oxide film formation (see Patent Document 1).

[0003] Metal contamination of semiconductor wafers can occur due to heat treatments performed during the manufacture of semiconductor wafers (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4797514 specification [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-143325 Summary of the Invention [Problem to be solved by the invention]

[0005] Metal contamination of semiconductor wafers causes a decrease in the performance of semiconductor devices that use the wafers as substrates. Therefore, semiconductor wafers with reduced metal contamination are required to enable the provision of high-performance semiconductor devices.

[0006] In order to manufacture semiconductor wafers with little metal contamination, it is desirable to understand the cause of metal contamination during heat treatment of semiconductor wafers and to carry out metal contamination reduction treatment according to the identified cause of metal contamination.

[0007] Single-wafer heat treatment furnaces are widely used for the heat treatment of semiconductor wafers (see Patent Document 1). In single-wafer heat treatment furnaces, semiconductor wafers placed on a support member undergo heat treatment. For example, if metal components adhere to the wafer-supporting surface of the support member, these metal components adhere to the backside of the semiconductor wafer, which is the contact surface with the support member. If these metal components diffuse from the backside to the front side during heat treatment, localized metal contamination occurs on the front side of the semiconductor wafer. For example, metal contamination of semiconductor wafers can occur due to a single-wafer heat treatment furnace. Therefore, evaluating metal contamination in a single-wafer heat treatment furnace and, based on the evaluation results, performing metal contamination reduction measures (e.g., replacing or cleaning the support member) as necessary will enable the production of semiconductor wafers with reduced metal contamination. Furthermore, improving the productivity of semiconductor wafers that can withstand strict requirements for metal contamination, such as those for imaging devices, can contribute to society.

[0008] In view of the above, an object of one aspect of the present invention is to provide a new method for evaluating local metal contamination in a single-wafer heat treatment furnace. [Means for solving the problem]

[0009] Semiconductor wafers loaded into a single-wafer heat treatment furnace typically have a notch or orientation flat (OF) as a mark indicating the crystal orientation of the semiconductor wafer. When multiple semiconductor wafers are sequentially heat-treated in a single-wafer heat treatment furnace, the angle between a specific crystal orientation of the semiconductor wafer and the extension direction of the transfer blade is set within an appropriate range to reduce thermal deformation and prevent damage to the semiconductor wafers during transport (see, for example, paragraph 0016 of Patent Document 1). In this case, multiple semiconductor wafers may be sequentially loaded into the single-wafer heat treatment furnace with different angles between the reference direction of the semiconductor wafer and the reference angular direction when placed on the support member, with the notch direction or OF direction being used as the reference direction of the semiconductor wafer. The present inventors have conducted extensive research to find a method for evaluating metal contamination in a single-wafer heat treatment furnace for such cases, and have completed a new method for evaluating metal contamination in a single-wafer heat treatment furnace, including performing a correction process, as described in detail below.

[0010] That is, one aspect of the present invention is as follows. [1] In a single-wafer heat treatment furnace (hereinafter simply referred to as a "heat treatment furnace") to be evaluated, a plurality of semiconductor wafers are placed on a mounting member provided in the heat treatment furnace and heat-treated; acquiring in-plane characteristic value distribution information for each of the plurality of semiconductor wafers after the heat treatment, wherein the plurality of semiconductor wafers are different from each other in angle θ (hereinafter also referred to as "loading angle") formed by the reference direction of the semiconductor wafer with respect to the reference angle direction at the time of loading on the loading member; performing a correction process on one or more of the acquired pieces of in-plane characteristic value distribution information; Including, the correction process determines a reference angle θr of the angle θ, and performs coordinate correction based on the angle difference between θ and θr for in-plane characteristic value distribution information of a semiconductor wafer whose angle θ is other than θr, thereby correcting position coordinates of the in-plane characteristic value distribution information to position coordinates on the mounting member when the semiconductor wafer is placed at the reference angle θr; A metal contamination evaluation method for a single-wafer heat treatment furnace, which evaluates metal contamination in the heat treatment furnace based on whether or not an abnormal characteristic value position is observed within the same region in multiple in-plane characteristic value distribution information including the in-plane characteristic value distribution information after the correction process. [2] The method for evaluating metal contamination in a single-wafer heat treatment furnace according to [1], wherein the reference direction of the semiconductor wafer is the notch direction or the orientation flat direction of the semiconductor wafer. [3] The metal contamination evaluation method for a single-wafer heat treatment furnace described in [1] or [2] further includes, when an abnormal value of a characteristic value is confirmed in the same region in a plurality of in-plane characteristic value distribution information including the in-plane characteristic value distribution information after the correction process, determining that a cause of metal contamination exists in the region of the mounting member. [4] The method for evaluating metal contamination in a single-wafer heat treatment furnace according to any one of [1] to [3], wherein the single-wafer heat treatment furnace is an epitaxial growth furnace, and the mounting member is a susceptor. [5] The method for evaluating metal contamination in a single-wafer heat treatment furnace according to any one of [1] to [4], wherein the characteristic value is a recombination lifetime. [6] The reference direction of the semiconductor wafer is the notch direction or the orientation flat direction of the semiconductor wafer, The method further includes determining that a cause of metal contamination exists in the same region of the mounting member when abnormal values ​​of the characteristic values ​​are confirmed in the same region of the plurality of pieces of in-plane characteristic value distribution information including the in-plane characteristic value distribution information after the correction process, The single-wafer heat treatment furnace is an epitaxial growth furnace, the mounting member is a susceptor; and The method for evaluating metal contamination in a single-wafer heat treatment furnace according to [1], wherein the characteristic value is a recombination lifetime. [7] Evaluating metal contamination in a single-wafer heat treatment furnace by the method described in any one of [1] to [6]; and Based on the results of the evaluation, determining whether or not metal contamination reduction treatment is required for the single-wafer heat treatment furnace; Including, A method for manufacturing a semiconductor wafer, comprising: performing metal contamination reduction treatment when it is determined that metal contamination reduction treatment is required, and then heat treating the semiconductor wafer in the single-wafer heat treatment furnace without performing metal contamination reduction treatment when it is determined that metal contamination reduction treatment is not required. [8] The single-wafer heat treatment furnace is an epitaxial growth furnace, The method for producing a semiconductor wafer according to [7], wherein the heat treatment of the semiconductor wafer in the single-wafer heat treatment furnace is the formation of an epitaxial layer. [Effects of the Invention]

[0011] According to one aspect of the present invention, a new method for evaluating local metal contamination in a single-wafer heat treatment furnace can be provided. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 10 is an explanatory diagram of the relationship between the input angle θ and the abnormal position of the characteristic value appearing on the wafer metal contamination map. [Figure 2] FIG. 1 is a flow diagram of an example method for evaluating and managing a thermal processing furnace using a plurality of semiconductor wafers. [Figure 3] The results of measurements of wafers A to C in the example by the μ-PCD method are shown. DETAILED DESCRIPTION OF THE INVENTION

[0013] [Method for evaluating metal contamination in single-wafer heat treatment furnaces] One aspect of the present invention relates to a method for evaluating metal contamination in a single-wafer heat treatment furnace (hereinafter also referred to simply as the "evaluation method"), which includes: placing semiconductor wafers on a mounting member provided in a single-wafer heat treatment furnace to be evaluated and performing heat treatment on a plurality of semiconductor wafers; acquiring in-plane characteristic value distribution information for each of the plurality of semiconductor wafers after the heat treatment, where the plurality of semiconductor wafers have different angles θ formed by the reference direction of the semiconductor wafer with respect to a reference angle direction at the time of placement on the mounting member; and performing a correction process on one or more of the acquired in-plane characteristic value distribution information. The correction process determines a reference angle θr for the angle θ, and performs coordinate correction based on the angular difference between θ and θr for the in-plane characteristic value distribution information of semiconductor wafers whose angle θ is other than θr, thereby correcting the position coordinates of the in-plane characteristic value distribution information to the position coordinates on the mounting member when the semiconductor wafer is placed at the reference angle θr. In the evaluation method, metal contamination in the heat treatment furnace is evaluated based on whether or not abnormal characteristic value positions are observed within the same region in multiple pieces of in-plane characteristic value distribution information, including the in-plane characteristic value distribution information after the correction process. The above evaluation methods will be explained in more detail below.

[0014] <Single-wafer heat treatment furnace> Examples of single-wafer heat treatment furnaces to be evaluated include epitaxial growth furnaces for forming epitaxial layers on semiconductor wafers, annealing furnaces for annealing semiconductor wafers, thermal oxidation furnaces for forming thermal oxide films on semiconductor wafers, etc. The configurations of these heat treatment furnaces are publicly known.

[0015] In a single-wafer heat treatment furnace, a semiconductor wafer is placed on a mounting member provided in the heat treatment furnace, such as a susceptor or a heat treatment boat, and then heat treatment is performed in the furnace.

[0016] <Semiconductor wafer> Examples of semiconductor wafers to be heat-treated in the single-wafer heat treatment furnace to be evaluated include various semiconductor wafers such as silicon wafers. For example, wafers cut from an ingot of semiconductor material grown by a known method (e.g., silicon single crystal wafers cut from a silicon single crystal ingot) can be optionally subjected to one or more processes such as planarization, polishing such as mirror polishing, processing such as chamfering, and cleaning, and then loaded into the heat treatment furnace for heat treatment. The conductivity type of the semiconductor wafer may be either p-type or n-type.

[0017] <Specific form of evaluation method> Hereinafter, as one example of a specific form of an evaluation method according to one aspect of the present invention, an embodiment in which a susceptor is used as a mounting member will be described with reference to the drawings.

[0018] 1 is an explanatory diagram of the relationship between the incidence angle θ and the abnormal position of characteristic values ​​appearing on a wafer metal contamination map. A metal contamination map is a map showing the in-plane distribution of characteristic values ​​that can be used as an index of the degree of metal contamination. The metal contamination map can be, for example, a map showing the in-plane distribution of characteristic values ​​(recombination lifetime, minority carrier diffusion length, metal impurity concentration, etc.) described below. In the embodiment shown in FIG. 1, the positions of the susceptor on the wafer mounting surface shown in FIG. 1(a) indicated by x are metal contamination positions. In Figure 1, the dotted line indicates the reference angle direction when the wafer is placed, and the solid line indicates the reference direction of the semiconductor wafer. In Figure 1, the reference direction of the semiconductor wafer is the notch direction. For semiconductor wafers that have an orientation flat instead of a notch, the orientation flat direction can be used as the reference direction of the semiconductor wafer. The "notch direction" refers to the direction in which the notch exists, and the "orientation flat direction" refers to the direction in which the orientation flat exists.

[0019] In Figure 1(b), the angle θ (throw angle) formed by the reference direction of the semiconductor wafer (wafer 1) relative to the reference angle direction at the time of placement on the susceptor is 0°. In contrast, in Figure 1(c), the throw angle of the semiconductor wafer (wafer 2) is 45°. In other words, the throw angle θ is different between Figures 1(b) and (c). The susceptors on which the wafers are placed in Figures 1(b) and 1(c) are the same.

[0020] In Figure 1(b), a susceptor with a wafer 1 positioned as shown in Figure 1(b)(1) is placed in a heat treatment furnace, where the wafer 1 is heat-treated (Figure 1(b)(2)). After heat treatment, the susceptor is removed from the heat treatment furnace, and the wafer 1 is then removed from the susceptor (Figure 2(b)(3)). Measurements are then performed on the wafer 1 removed from the susceptor to obtain in-plane characteristic value distribution information for the front or back surface of the wafer. The measurement is performed by aligning the reference direction of the semiconductor wafer with the reference angular direction during measurement. For example, the notch direction or orientation flat direction is aligned with the reference angular direction during measurement. Note that the term "alignment" allows for errors that may normally occur during measurement preparation. In Figure 1(b)(4), the notch direction is the reference angular direction during measurement.

[0021] The in-plane characteristic value distribution information can be various in-plane characteristic value distribution information typically used for evaluating metal contamination on semiconductor wafers. Specific examples of characteristic values ​​include the recombination lifetime determined by a photoconductivity decay (PCD) method (e.g., microwave photoconductivity decay (μ-PCD)), the minority carrier diffusion length determined by a surface photovoltage (SPV) method, and the metal impurity concentration (e.g., Fe concentration) calculated from the minority carrier diffusion length determined by the SPV method. Because each of the above characteristic values ​​varies depending on the presence and degree of metal contamination, the in-plane characteristic value distribution information of such characteristic values ​​can identify the location of localized metal contamination within the semiconductor wafer. During heat treatment, metal components are transferred to the backside of the wafer 1 at positions in contact with the metal contamination positions on the susceptor mounting surface. As these metal components diffuse within the wafer due to the heat treatment, changes in the characteristic values ​​due to the metal components occur on the front and backside of the wafer 1 at coordinate positions corresponding to the metal contamination positions on the susceptor mounting surface. Therefore, when a localized characteristic value abnormality (e.g., a local decrease or increase in a characteristic value) is confirmed in the in-plane characteristic value distribution information on the front or back surface of the wafer 1, the coordinate position on the susceptor mounting surface can be estimated to be a metal contamination position. In Figures 1(b)(3) and (4), the position indicated by an "x" can be estimated to be a position where a localized characteristic value abnormality (e.g., a local decrease or increase in a characteristic value) has occurred due to the transfer and diffusion of metal contamination from the metal contamination position on the susceptor. However, with only the in-plane characteristic value distribution information of a single wafer, it is possible that the localized characteristic value abnormality within the wafer plane is caused by metal contamination other than the susceptor. One example of a metal contamination cause other than the susceptor is localized metal contamination of the wafer itself (e.g., particle adhesion to the wafer surface). Therefore, in an evaluation method according to one aspect of the present invention, metal contamination in a heat treatment furnace is evaluated based on the in-plane characteristic value distribution information of multiple semiconductor wafers, for example, as follows.

[0022] In Figure 1(c), as shown in Figure 1(c)(1), a susceptor with wafer 2 placed on it is aligned at a different angle (θ = 45°) from wafer 1, and then loaded into a heat treatment furnace, where wafer 2 is heat-treated (Figure 1(c)(2)). The wafer loading angle can be measured, for example, by aligning the wafer according to its notch or orientation flat during the process of loading the wafer into a transport cassette before loading into the heat treatment furnace, and then confirming the resulting data. After heat treatment, the susceptor is removed from the heat treatment furnace, and wafer 2 is then removed from the susceptor (Figure 2(c)(3)). Similarly to wafer 1, measurements are performed on wafer 2 removed from the susceptor to obtain in-plane characteristic distribution information for the front and back surfaces of the wafer (Figure 1(c)(4)). In Figures 1(c)(3) and (4), the positions indicated by "x" indicate positions (characteristic abnormality positions) where localized characteristic abnormalities (e.g., localized decreases or increases in characteristic values) were confirmed. These measurements are also performed by aligning the reference direction of the semiconductor wafer with the reference angular direction during measurement. For example, the notch direction or orientation flat direction is aligned with the reference angular direction during measurement. In Figure 1(c)(4), the notch direction is the reference angular direction during measurement. Therefore, the reference direction of the semiconductor wafer is aligned in the same direction during measurements of wafer 1 and wafer 2. Furthermore, even when one or more wafers are placed on a susceptor at a loading angle θ different from that of wafer 1 and wafer 2 and then loaded into a heat treatment furnace for heat treatment, measurements can be performed to obtain in-plane characteristic distribution information by aligning the reference direction of the semiconductor wafer with the reference angular direction during measurement.

[0023] The characteristic value anomalies for wafer 1 and wafer 2 are caused by the same metal contamination location on the susceptor. However, because wafer 1 and wafer 2 use different input angles θ during heat treatment, comparing FIG. 1(b)(4) with FIG. 1(c)(4) reveals that the coordinates of the characteristic value anomaly locations on the in-plane characteristic value distribution information (the "metal contamination map" in FIG. 1) are different. Therefore, in the embodiment shown in FIG. 1, a correction process is performed on the in-plane characteristic value distribution information acquired for wafer 2 (FIG. 1(c)(5)). Specifically, the input angle of wafer 1 is used as the reference angle θr for the input angle θ, and coordinate correction is performed based on the angular difference between the input angles of wafer 1 and wafer 2. Here, the input angle of wafer 1 is used as the reference angle θr for the input angle θ. However, the reference angle θr is not limited to any of the input angles of wafers actually subjected to heat treatment and can be set to any angle. In the embodiment shown in FIG. 1 , the input angle θ of wafer 1 is 0°, and the input angle θ of wafer 2 is 45°, so coordinate correction is performed based on the angle difference of 45°. Examples of coordinate correction methods include rotating the metal contamination map by the angle of the angle difference (45° for wafer 2) and multiplying the coordinate matrix by an operator to correct the position coordinates of each position on the metal contamination map acquired for wafer 2 by the angle difference (45° for wafer 2). Comparing FIG. 1(b)(4) with FIG. 1(c)(5) after coordinate correction, characteristic value abnormality positions (marked with "x" in the figure) appear within the same region. For example, if characteristic value abnormality positions are observed within the same region in multiple pieces of in-wafer characteristic value distribution information, including in-wafer characteristic value distribution information after correction, it can be determined that the metal contamination source exists in the same region (e.g., the region with the same position coordinates) on the wafer mounting surface of the susceptor used to mount the wafer during heat treatment. On the other hand, if abnormal characteristic value positions appear in different regions in multiple pieces of in-plane characteristic value distribution information, including the in-plane characteristic value distribution information after the correction process, and if an abnormal characteristic value position appears in one wafer among multiple heat-treated wafers but no abnormal characteristic value position is observed in the other wafers, it can be determined that the susceptor is not the cause of metal contamination.The threshold for whether the characteristic value is an abnormal value can be arbitrarily set according to the quality requirements for the product wafer, etc.

[0024] Next, an example of a method for evaluating and managing a heat treatment furnace using a plurality of semiconductor wafers will be described.

[0025] FIG. 2 is a flowchart of an example of a method for evaluating and managing a heat treatment furnace using a plurality of semiconductor wafers.

[0026] In the same single-wafer heat treatment furnace, using the same susceptor, heat treatment of a plurality of semiconductor wafers (total number of wafers: X) is sequentially performed (start in FIG. 2). In FIG. 2, n is an integer of 1 or more, m is an integer of 2 or more, n < X, and m ≤ X. m may be n + 1, or may be n + 2 or n + 3 or more. The input angle θ may be different for all of the plurality of wafers input into the heat treatment furnace, or some of the plurality of wafers input into the heat treatment furnace may be input at the same input angle θ. The two wafers for confirming the presence or absence of coincidence of the position coordinates in S11 described later are wafers with different input angles θ.

[0027] Measure the input angle θ of the susceptor on which the n-th wafer is placed (S1). In FIG. 2, S1 is described before S2, but the measurement of the input angle θ can be performed at an arbitrary stage. This also applies to S6 in FIG. 2. After performing the heat treatment of the n-th wafer (S2), the susceptor is taken out from the heat treatment furnace, the characteristic values of the wafer removed from the susceptor are measured, and in-plane characteristic value distribution information (for example, metal contamination Map) is obtained (S3). When the input angle θ of the n-th wafer is an angle other than the reference angle θr, correction processing of the metal contamination Map is performed (S4). On the other hand, when the input angle θ of the n-th wafer is the reference angle θr, the correction processing (S4) is not performed. Then, check for the presence or absence of an abnormal position of the characteristic value of the obtained metal contamination Map. The threshold for determining that the characteristic value is abnormal can be arbitrarily set as described above. When an abnormal characteristic value position is confirmed, obtain the position coordinates of the characteristic value position (S5).

[0028] Similarly, for an mth wafer, different from the nth wafer, the insertion angle θ of the susceptor on which the wafer is placed is measured (S6). After the wafer is heat-treated (S7), the susceptor is removed from the heat treatment furnace, and the characteristic values ​​of the wafer removed from the susceptor are measured to obtain in-plane characteristic value distribution information (e.g., a metal contamination map) (S8). If the insertion angle θ of the mth wafer is an angle other than the reference angle θr, a correction process for the metal contamination map is performed (S9). On the other hand, if the insertion angle θ of the nth wafer is the reference angle θr, the correction process (S9) is not performed. Thereafter, the presence or absence of an abnormal characteristic value position in the obtained metal contamination map is confirmed. If an abnormal characteristic value position is confirmed, the position coordinates of the characteristic value position are obtained (S10).

[0029] Then, the position coordinates of the abnormal characteristic value acquired for the nth wafer are compared with the position coordinates of the abnormal characteristic value position acquired for the mth wafer. Here, for one or both of the nth and mth wafers, the metal contamination map is the metal contamination map after the correction process. Therefore, if the position coordinates of the two abnormal characteristic value positions match as a result of comparing the position coordinates, it is determined that a cause of metal contamination exists at the same position coordinates of the susceptor on which the wafers were placed, and the heat treatment is stopped (S12). After the heat treatment is stopped, a metal contamination reduction process is performed on the heat treatment furnace. In the present invention and this specification, the metal contamination reduction process for the heat treatment furnace also includes a metal contamination reduction process for components used to load, position, and / or load wafers into the heat treatment furnace. Specific examples of metal contamination reduction treatments include one or more of the following: cleaning of mounting members such as susceptors and heat treatment boats (including cleaning with a cleaning liquid, the same applies below), replacing mounting members, repairing coatings formed on the mounting surfaces of mounting members, and cleaning of transport members that come into contact with the mounting surfaces of mounting members. On the other hand, if the position coordinates do not match in S11, it is determined that there is no metal contamination cause at the position on the susceptor that has the same position coordinates as the characteristic value abnormality position of wafer 1 and the same position coordinates as the characteristic value abnormality position of wafer 2, and the heat treatment of the (m+1)th and subsequent wafers is continued using the same susceptor in the same heat treatment furnace (S13). If m=X, the heat treatment is terminated (END in FIG. 2). The above steps may be further performed using wafers other than the nth and mth wafers until the end of the heat treatment (end in FIG. 2).

[0030] An example of a specific embodiment of the evaluation method according to one aspect of the present invention has been described above with reference to Figures 1 and 2. However, the above embodiment is merely an example, and the present invention is not limited to the illustrated embodiment.

[0031] [Semiconductor wafer manufacturing method] One aspect of the present invention relates to a semiconductor wafer manufacturing method (hereinafter also simply referred to as "manufacturing method") that includes evaluating metal contamination in a single-wafer heat treatment furnace by the above-mentioned evaluation method, and determining whether or not metal contamination reduction treatment is required for the single-wafer heat treatment furnace based on the results of the above-mentioned evaluation. The manufacturing method includes heat treating semiconductor wafers in the single-wafer heat treatment furnace after performing the metal contamination reduction treatment if it is determined that the metal contamination reduction treatment is required, or without performing the metal contamination reduction treatment if it is determined that the metal contamination reduction treatment is not required.

[0032] The semiconductor wafers subjected to the heat treatment in the above manufacturing method can be wafers sliced ​​from an ingot of semiconductor material grown by a known method such as the CZ method (Czochralski method) or the FZ (Floating Zone) method. Such wafers can be wafers that have been optionally subjected to one or more processes such as planarization, polishing such as mirror polishing, processing such as chamfering, cleaning, etc. Specific examples of heat treatments and details of evaluation methods are as described above. In one embodiment, the single-wafer heat treatment furnace can be an epitaxial growth furnace, and the heat treatment of the semiconductor wafers in the single-wafer heat treatment furnace can be the formation of an epitaxial layer (in other words, epitaxial growth). [Example]

[0033] The present invention will be further described below based on examples, but the present invention is not limited to the embodiments shown in the examples.

[0034] Epitaxial layers were formed on the surfaces of three silicon single crystal wafers (wafers A, B, and C) using the same susceptor in the same single-wafer epitaxial growth furnace. The input angle θ, with the notch direction as the reference direction, was set to θ = 0° for wafer A, θ = 45° for wafer B, and θ = 180° for wafer C. Recombination lifetime measurements were performed on the epitaxial layer surface of each wafer using the μ-PCD method, and μ-PCD lifetime maps were obtained. The input angle of wafer A was set as the reference angle θr, and as a correction process, the μ-PCD lifetime map for wafer B was rotated 45° and the μ-PCD lifetime map for wafer C was rotated 180°.

[0035] Figure 3 shows the results of measurements using the μ-PCD method for wafers A to C. Without correction, the coordinates of the locations where the recombination lifetime values ​​locally decreased (i.e., the characteristic value abnormality locations) were significantly different. In contrast, when correction was performed on the μ-PCD lifetime maps for wafers B and C, the characteristic value abnormality locations were confirmed at the same locations on the μ-PCD lifetime maps for wafers A, B, and C. From these results, it can be determined that the metal contamination source exists on the mounting surface of the susceptor on which wafers A to C were placed, at the same locations where the characteristic value abnormality locations were confirmed on the μ-PCD lifetime maps. Note that Figure 3 also shows the average and minimum values ​​of the recombination lifetime values ​​on the μ-PCD lifetime maps for wafers A to C as reference values. However, these values ​​cannot be used to determine whether or not the susceptor contains a metal contamination source, nor can they identify the location of the metal contamination source on the susceptor. [Industrial Applicability]

[0036] According to one aspect of the present invention, semiconductor wafers with reduced metal contamination can be manufactured by evaluating metal contamination in a single-wafer heat treatment furnace and, based on the evaluation results, performing metal contamination reduction treatment on the single-wafer heat treatment furnace as needed. This enables improved productivity of semiconductor wafers that can withstand strict requirements for metal contamination, such as for imaging devices. Improving semiconductor wafer productivity leads to reduced environmental impact and contributes to society by contributing to the achievement of the Sustainable Development Goals (SDGs).

Claims

1. In a single-wafer heat treatment furnace to be evaluated, a plurality of semiconductor wafers are placed on a mounting member provided in the heat treatment furnace and heat-treated; acquiring in-plane characteristic value distribution information for each of the plurality of semiconductor wafers after the heat treatment, wherein the plurality of semiconductor wafers have different angles θ formed by the reference direction of the semiconductor wafer with respect to the reference angle direction at the time of placement on the placement member; performing a correction process on one or more of the acquired pieces of in-plane characteristic value distribution information; Including, the correction process determines a reference angle θr of the angle θ, and performs coordinate correction based on the angle difference between θ and θr for in-plane characteristic value distribution information of a semiconductor wafer whose angle θ is other than θr, thereby correcting position coordinates of the in-plane characteristic value distribution information to position coordinates on the mounting member when the semiconductor wafer is placed at the reference angle θr; A method for evaluating metal contamination in a single-wafer heat treatment furnace, which evaluates metal contamination in the heat treatment furnace based on whether or not an abnormal characteristic value position is observed within the same region in multiple pieces of in-plane characteristic value distribution information including the in-plane characteristic value distribution information after the correction process.

2. 2. The method for evaluating metal contamination in a single-wafer heat treatment furnace according to claim 1, wherein the reference direction of the semiconductor wafer is a notch direction or an orientation flat direction of the semiconductor wafer.

3. 2. The metal contamination evaluation method for a single-wafer heat treatment furnace according to claim 1, further comprising: determining, when an abnormal value of a characteristic value is confirmed in the same region in a plurality of pieces of in-plane characteristic value distribution information including the in-plane characteristic value distribution information after the correction process, that a cause of metal contamination exists in the region of the mounting member.

4. 2. The method for evaluating metal contamination in a single-wafer heat treatment furnace according to claim 1, wherein the single-wafer heat treatment furnace is an epitaxial growth furnace, and the mounting member is a susceptor.

5. 2. The method for evaluating metal contamination in a single-wafer heat treatment furnace according to claim 1, wherein the characteristic value is a recombination lifetime.

6. the reference direction of the semiconductor wafer is a notch direction or an orientation flat direction of the semiconductor wafer, The method further includes determining that a cause of metal contamination exists in the same region of the mounting member when abnormal values ​​of the characteristic values ​​are confirmed in the same region of the plurality of pieces of in-plane characteristic value distribution information including the in-plane characteristic value distribution information after the correction process, the single-wafer heat treatment furnace is an epitaxial growth furnace, the mounting member is a susceptor, and 2. The method for evaluating metal contamination in a single-wafer heat treatment furnace according to claim 1, wherein the characteristic value is a recombination lifetime.

7. Evaluating metal contamination in a single-wafer heat treatment furnace by the method according to any one of claims 1 to 6; and determining whether or not metal contamination reduction treatment is required for the single-wafer heat treatment furnace based on the results of the evaluation; Including, a heat treatment of the semiconductor wafer in the single-wafer heat treatment furnace after performing the metal contamination reduction treatment if it is determined that the metal contamination reduction treatment is required, and after performing the metal contamination reduction treatment if it is determined that the metal contamination reduction treatment is not required, without performing the metal contamination reduction treatment.

8. the single-wafer heat treatment furnace is an epitaxial growth furnace, 8. The method for producing a semiconductor wafer according to claim 7, wherein the heat treatment of the semiconductor wafer in the single-wafer heat treatment furnace is for forming an epitaxial layer.

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