Power source control device

Abstract

To detect, in a distinguishable manner, abnormality of a plurality of voltage generation circuits.SOLUTION: In a power source device, the state of an output-stage circuit is controlled based on a feedback voltage (Vfb) according to an output voltage, and a reference voltage (Vref) generated in a first voltage generation circuit (11); thus, the output voltage is stabilized to be a target voltage. Based on the feedback voltage and an output monitor voltage (V_H, V_L) generated in a second voltage generation circuit (12), the abnormality of the output voltage is monitored. Based on a first determination voltage (V1a, V1b) generated in the first voltage generation circuit, a second determination voltage (V2a, V2b) generated in the second voltage generation circuit, and a third determination voltage (V3a, V3b, V3c, V3d) generated in a third voltage generation circuit, the abnormality of the first and second voltage generation circuits is distinguishably detected.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device. [Background technology]

[0002] In power supply devices that generate an output voltage from an input voltage, the output voltage is often stabilized by feedback control based on the error between a feedback voltage corresponding to the output voltage and a reference voltage (see, for example, Patent Document 1 listed below). A power supply control device is used to control the operation of the power supply device, and a reference voltage is generated within the power supply control device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 054027

[0004] [overview] This type of power supply control device is required to have a function for detecting various abnormalities that may occur within the power supply control device.

[0005] A power supply control device according to one embodiment of the present disclosure is a power supply control device that constitutes a power supply device having an output stage circuit arranged between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and that is configured to generate the output voltage from the input voltage, and that includes: a first voltage generation circuit; a control circuit configured to stabilize the output voltage to a target voltage by controlling the state of the output stage circuit based on a feedback voltage corresponding to the output voltage and a reference voltage generated by the first voltage generation circuit; a second voltage generation circuit; an output abnormality monitoring circuit configured to monitor abnormalities in the output voltage based on the feedback voltage and an output monitoring voltage generated by the second voltage generation circuit; a third voltage generation circuit; and a state detection circuit configured to distinguish and detect abnormalities in the first voltage generation circuit and the second voltage generation circuit based on a first determination voltage generated by the first voltage generation circuit, a second determination voltage generated by the second voltage generation circuit, and a third determination voltage generated by the third voltage generation circuit. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic overall configuration diagram of a system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is an external perspective view of a power supply control device according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a configuration diagram of a power supply device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a configuration diagram of a reference power supply device according to a first reference example. [Figure 5] FIG. 5 is a configuration diagram of a reference power supply device according to the second reference example. [Figure 6] FIG. 6 is a diagram illustrating the internal configuration of a state detection circuit according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is an explanatory diagram of a detection method and detection contents of a state detection circuit according to a first example of an embodiment of the present disclosure. [Figure 8] FIG. 8 is an explanatory diagram of a method for detecting an abnormality in a voltage generating circuit according to a first example of an embodiment of the present disclosure. [Figure 9]FIG. 9 is an explanatory diagram of a method for detecting an abnormality in a voltage generating circuit according to a first example of an embodiment of the present disclosure. [Figure 10] FIG. 10 is an explanatory diagram of a method for detecting an abnormality in a voltage generating circuit according to a first example of an embodiment of the present disclosure. [Figure 11] FIG. 11 is an explanatory diagram of a method for detecting an abnormality in a voltage generating circuit according to a first example of an embodiment of the present disclosure. [Figure 12] FIG. 12 relates to a second example belonging to an embodiment of the present disclosure, and is a diagram illustrating a method of dealing with an abnormality occurring in a voltage generating circuit that generates a reference voltage. [Figure 13] FIG. 13 is a diagram showing a modified configuration of an output stage circuit according to a fourth example belonging to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a diagram showing a modified configuration of an output stage circuit according to a fourth example belonging to an embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0V (zero volts), or refers to the 0V potential itself. The reference conductor may be formed using a conductor such as metal. The 0V potential is sometimes referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. Level refers to the level (height) of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0009] For any transistor configured as a FET (field-effect transistor) exemplified by a MOSFET, the on-state refers to the state where there is conduction between the drain and source of the transistor, and the off-state refers to the state where there is non-conduction (cut-off state) between the drain and source of the transistor. The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source.

[0010] Hereinafter, for any transistor, the on-state and off-state may also be simply expressed as on and off, respectively. Also, for any transistor, the period during which the transistor is in the on-state is referred to as the on-period, and the period during which the transistor is in the off-state is referred to as the off-period. Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.

[0011] When any two voltages to be compared are voltage v1 and voltage v2, "v1>v2" represents that voltage v1 is higher than voltage v2, "v1<v2" represents that voltage v1 is lower than voltage v2, and "v1=v2" represents that the value of voltage v1 is the same as the value of voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0012] Fig. 1 is an overall configuration diagram of a system according to an embodiment of the present disclosure. The system of Fig. 1 includes a power supply device 1 and an MPU (Micro Processing Unit) 4. The power supply device 1 includes a power supply control device 2 that controls the operation of the power supply device 1, and a discrete component group 3 made up of a plurality of discrete components that are externally connected to the power supply control device 2. The MPU 4 is an example of an external device that is provided outside the power supply control device 2. The MPU 4 is connected to the power supply control device 2. The power supply control device 2 and the MPU 4 may be connected in a manner that allows two-way communication with each other.

[0013] Figure 2 shows an external perspective view of the power supply control device 2. The power supply control device 2 is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing CS (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed from the housing CS to the outside of the power supply control device 2. The power supply control device 2 is formed by sealing the semiconductor chip in a housing CS made of resin. Note that the number of external terminals of the power supply control device 2 and the type of housing CS of the power supply control device 2 shown in Figure 2 are merely examples, and can be designed as desired.

[0014] Figure 3 shows the configuration of power supply device 1A, which is an example of power supply device 1. Power supply device 1A includes a power supply control device 2A as a power supply control device 2. A group of discrete components 3 in power supply device 1A includes a coil L1, an output capacitor C1, and feedback resistors R1 and R2. The pull-up resistor R3 shown in Figure 3 may be understood as not being included in the components of power supply device 1A, or as being included in the components of power supply device 1A (included in the components of discrete component group 3).

[0015] The power supply device 1A is configured as a step-down switching power supply device (DC / DC converter) that generates a desired output voltage Vout from an input voltage Vin supplied from a voltage source (not shown). The output voltage Vout is generated at the output terminal OUT. That is, the output terminal OUT is the application terminal (terminal to which the output voltage Vout is applied) of the output voltage Vout. The output voltage Vout is supplied to a load LD connected to the output terminal OUT. In the power supply device 1A, the input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. For example, when the input voltage Vin is 12V, the output voltage Vout can be stabilized at a desired positive voltage value (e.g., 3.3V or 5V) less than 12V by adjusting the resistance values ​​of the feedback resistors R1 and R2. While FIG. 3 shows only the input terminal IN, switch terminal SW, feedback terminal FB, ground terminal GND, and power-good terminal PG as some of the multiple external terminals provided on the power supply control device 2A, other external terminals (e.g., an enable terminal and a boot terminal) may also be provided on the power supply control device 2A.

[0016] The external configuration of the power supply control device 2A will now be described. An input voltage Vin is supplied to the input terminal IN from a DC voltage source (not shown) external to the power supply control device 2A. A coil L1 is connected in series between the switch terminal SW and the output terminal OUT. A first terminal of the coil L1 is connected to the switch terminal SW, and a second terminal of the coil L1 is connected to the output terminal OUT. The output terminal OUT is also connected to ground via an output capacitor C1. A first terminal of the output capacitor C1 is connected to the output terminal OUT, and a second terminal of the output capacitor C1 is connected to ground. Furthermore, the output terminal OUT is connected to a first terminal of a feedback resistor R1, a second terminal of the feedback resistor R1 is connected to a first terminal of a feedback resistor R2, and a second terminal of the feedback resistor R2 is connected to ground. A feedback voltage Vfb is generated at the connection node between the feedback resistors R1 and R2. The connection node between the feedback resistors R1 and R2 is connected to a feedback terminal FB, thereby inputting the feedback voltage Vfb to the feedback terminal FB. The ground terminal GND is connected to ground. The current flowing through the coil L1 is referred to as a coil current IL.

[0017] The wiring WRpg is an external wiring. A first end of the wiring WRpg is connected to the power good terminal PG, and a second end of the wiring WRpg is connected to the input terminal of the MPU4. The signal on the wiring WRpg is referred to as the signal Spg. The wiring WRpg is a wiring for transmitting the signal Spg to the MPU4. A first end of the pull-up resistor R3 is connected to the application terminal of the power supply voltage VDD (the terminal to which the power supply voltage VDD is applied), and a second end of the pull-up resistor R3 is connected to the wiring WRpg. The power supply voltage VDD is a positive DC voltage. The MPU4 is connected to the application terminal of the power supply voltage VDD and ground, and is driven based on the power supply voltage VDD.

[0018] The internal configuration of the power supply control device 2A will be described. The power supply control device 2A includes an output stage circuit MM and a control circuit 14 for controlling the output stage circuit MM, as well as voltage generation circuits 11, 12, and 13, an output abnormality monitoring circuit 15, a status detection circuit 16, and a signal output circuit 17. The signal output circuit 17 includes a transistor 17a, which is an N-channel MOSFET.

[0019] The output stage circuit MM includes transistors MH and ML configured as N-channel MOSFETs. The transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (i.e., ground). When they are switched, the input voltage Vin is switched, and a square-wave switch voltage Vsw appears at the switch terminal SW. The transistor MH is provided on a higher potential side than the transistor ML. Specifically, the drain of the transistor MH is connected to the input terminal IN, which is the application terminal of the input voltage Vin, and is supplied with the input voltage Vin. The source of the transistor MH and the drain of the transistor ML are commonly connected to the switch terminal SW. The source of the transistor ML is connected to ground. However, a resistor for current detection may be inserted between the source of the transistor ML and ground.

[0020] The transistor MH functions as an output element (output transistor), and the transistor ML functions as a rectifier element (synchronous rectifier transistor). The control circuit 14 controls the switching of the output stage circuit MM. The transistors MH and ML are alternately turned on and off during the switching control of the output stage circuit MM. The coil L1 and output capacitor C1 form a rectifying and smoothing circuit that rectifies and smoothes the rectangular switch voltage Vsw appearing at the switch terminal SW to generate the output voltage Vout. The feedback resistors R1 and R2 form a feedback voltage generating circuit that divides the output voltage Vout to generate a feedback voltage Vfb corresponding to the output voltage Vout. The feedback voltage Vfb is proportional to the output voltage Vout, and the feedback voltage Vfb also rises and falls as the output voltage Vout rises and falls. Note that a modification may be made in which the output voltage Vout itself is used as the feedback voltage Vfb. In either case, the feedback voltage Vfb is a voltage corresponding to the output voltage Vout.

[0021] Gate signals GH and GL are supplied to the gates of the transistors MH and ML, respectively, as drive signals, and the transistors MH and ML are turned on and off in response to the gate signals GH and GL. When the gate signal GH is at a high level, the transistor MH is on, and when the gate signal GH is at a low level, the transistor MH is off. Similarly, when the gate signal GL is at a high level, the transistor ML is on, and when the gate signal GL is at a low level, the transistor ML is off. Basically, the transistors MH and ML are alternately turned on and off, but there are also cases where both the transistors MH and ML are maintained in an off state. The transistors MH and ML are never turned on simultaneously. The output stage circuit MM may be provided external to the power supply control device 2A. In this case, the output stage circuit MM provided external to the power supply control device 2A is connected to the power supply control device 2A.

[0022] In a situation where the coil current IL flows from the switch terminal SW to the output terminal OUT, the coil current IL flows through the channel (between the drain and source) of the transistor MH during the on period of the transistor MH, and the coil current IL flows through the channel of the transistor ML or the parasitic diode of the transistor ML during the off period of the transistor MH.

[0023] The control circuit 14 is connected to the feedback terminal FB and receives a feedback voltage Vfb at the feedback terminal FB. The control circuit 14 controls the switching of the output stage circuit MM based on the feedback voltage Vfb and the reference voltage Vref supplied from the voltage generating circuit 11. In controlling the switching of the output stage circuit MM, the control circuit 14 controls the on / off states of the transistors MH and ML by controlling the levels of the gate signals GH and GL so that the error between the feedback voltage Vfb and the reference voltage Vref approaches zero (ideally so that it matches zero), thereby stabilizing the output voltage Vout at a predetermined target voltage Vtg. When the error between the feedback voltage Vfb and the reference voltage Vref is zero, the output voltage Vout matches the target voltage Vtg (i.e., the value of the output voltage Vout matches the value of the target voltage Vtg).

[0024] The voltage generating circuit 11 is a voltage generating circuit for output control. The voltage generating circuit 11 generates a reference voltage Vref as a voltage for controlling the output voltage Vout. The voltage generating circuit 11 generates the reference voltage Vref so that the reference voltage Vref has a predetermined positive DC voltage value.

[0025] The voltage generating circuit 11 also generates voltages V1a and V1b and outputs them to the state detecting circuit 16. The voltages V1a and V1b are examples of components of the first determination voltage. A reference voltage Vref and the voltages V1a and V1b are generated as three voltages proportional to the output voltage of a single DC voltage source 11a provided in the voltage generating circuit 11. For example, the reference voltage Vref and the voltages V1a and V1b are generated by dividing the output voltage of the DC voltage source 11a using a ladder resistor. However, the reference voltage Vref, the voltage V1a, or the voltage V1b may be the voltage before the division.

[0026] In any case, the reference voltage Vref, the voltage V1a, and the voltage V1b are proportional to each other. That is, the first determination voltages (V1a, V1b) are proportional to the reference voltage Vref. Therefore, if the output voltage of the reference voltage source 11a is the voltage V11a, then "Vref = k1 × V11a," "V1a = k1a × V11a," and "V1b = k1b × V11a" are established.

[0027] k1, k1a, and k1b are predetermined positive proportional coefficients. At least one of the proportional coefficients k1, k1a, and k1b may be 1. The proportional coefficients k1, k1a, and k1b may be different from each other. Any two or more of the proportional coefficients k1, k1a, and k1b may have the same value. "k1=k1a" may be true, in which case the reference voltage Vref and the voltage V1a are a common voltage. "k1=k1b" may be true, in which case the reference voltage Vref and the voltage V1b are a common voltage. "k1a=k1b" may be true, in which case the voltage V1a and the voltage V1b are a common voltage.

[0028] The voltage generation circuit 12 is a voltage generation circuit for output monitoring. The voltage generation circuit 12 generates voltages V_H and V_L as output monitoring voltages used to monitor whether the output voltage Vout is within a predetermined normal voltage range. The voltage generation circuit 12 generates the voltages V_H and V_L so that the voltages V_H and V_L have positive DC voltage values ​​and the relationship "V_H>V_L" holds. Therefore, if the voltage generation circuit 12 is operating normally, the relationship "V_H>V_L>0" holds.

[0029] The voltage generation circuit 12 also generates voltages V2a and V2b and outputs them to the state detection circuit 16. The voltages V2a and V2b are examples of components of the second determination voltage. The voltages V_H, V_L, V2a, and V2b are generated as four voltages proportional to the output voltage of a single DC voltage source 12a provided in the voltage generation circuit 12. For example, the voltages V_H, V_L, V2a, and V2b are generated by dividing the output voltage of the DC voltage source 12a using a ladder resistor. However, the voltages V_H, V_L, V2a, and V2b may be the voltages before division.

[0030] In any case, the voltages V_H, V_L, V2a, and V2b are proportional to one another, and the second determination voltages (V2a, V2b) are proportional to the output monitoring voltages (V_H, V_L). Therefore, if the output voltage of the reference voltage source 12a is voltage V12a, then "V_H=k2_H×V12a", "V_L=k2_L×V12a", "V2a=k2a×V12a", and "V2b=k2b×V12a" hold true.

[0031] k2_H, k2_L, k2a, and k2b are predetermined positive proportional coefficients. At least one of the proportional coefficients k2_H, k2_L, k2a, and k2b may be 1. However, the proportional coefficient k2_H is greater than the proportional coefficient k2_L. The proportional coefficients k2_H, k2_L, k2a, and k2b may be different from each other. "k2_H = k2a" may be satisfied, in which case the voltage V_H and the voltage V2a are a common voltage. Alternatively, "k2_L = k2a" may be satisfied, in which case the voltage V_L and the voltage V2a are a common voltage. Alternatively, "k2_H = k2b" may be satisfied, in which case the voltage V_H and the voltage V2b are a common voltage. Alternatively, "k2_L = k2b" may be satisfied, in which case the voltage V_L and the voltage V2b are a common voltage. It is also possible for "k2a=k2b", in which case the voltage V2a and the voltage V2b are a common voltage.

[0032] The voltage generation circuit 13 is a voltage generation circuit for voltage monitoring (a circuit for monitoring the voltages generated by the voltage generation circuits 11 and 12). The voltage generation circuit 13 generates voltages V3a, V3b, V3c, and V3d used to determine whether the voltages generated by the voltage generation circuits 11 and 12 are normal or abnormal, and outputs the voltages to the state detection circuit 16. The voltages V3a, V3b, V3c, and V3d are examples of components of a third determination voltage. The voltages V3a, V3b, V3c, and V3d are generated as four voltages proportional to the output voltage of a single DC voltage source 13a provided in the voltage generation circuit 13. For example, the voltages V3a, V3b, V3c, and V3d are generated by dividing the output voltage of the DC voltage source 13a using a ladder resistor. However, the voltages V3a, V3b, V3c, and V3d may be the voltages before division.

[0033] In any case, the voltages V3a, V3b, V3c, and V3d are proportional to one another. Therefore, if the output voltage of the reference voltage source 13a is the voltage V13a, then "V3a = k3a × V13a," "V3b = k3b × V13a," "V3c = k3c × V13a," and "V3d = k3d × V13a" are established.

[0034] k3a, k3b, k3c, and k3d are predetermined positive proportional coefficients. At least one of the proportional coefficients k3a, k3b, k3c, and k3d may be 1. The proportional coefficients k3a, k3b, k3c, and k3d may be different from each other. Any two or more of the proportional coefficients k3a, k3b, k3c, and k3d may have the same value. For example, if "k3a = k3b," the voltages V3a and V3b are a common voltage, and if "k3b = k3c," the voltages V3b and V3c are a common voltage. The same applies to other combinations of the proportional coefficients k3a, k3b, k3c, and k3d.

[0035] A feedback voltage Vfb is supplied to the output abnormality monitoring circuit 15 through the feedback terminal FB, and voltages V_H and V_L are supplied from the voltage generation circuit 12. The output abnormality monitoring circuit 15 includes comparators 15_H and 15_L. Each of the comparators 15_H and 15_L is a two-input comparator. In the present embodiment, any two-input comparator has a non-inverting input terminal, an inverting input terminal, and an output terminal, compares the positive-side comparison voltage which is the voltage of the non-inverting input terminal with the negative-side comparison voltage which is the voltage of the inverting input terminal, and outputs a comparison result signal indicating the comparison result from its own output terminal. At this time, if the positive-side comparison voltage is higher than the negative-side comparison voltage, the two-input comparator outputs a high-level comparison result signal; if the negative-side comparison voltage is higher than the positive-side comparison voltage, the two-input comparator outputs a low-level comparison result signal; if the positive-side comparison voltage and the negative-side comparison voltage are equal, the two-input comparator outputs a high-level or low-level comparison result signal.

[0036] The feedback voltage Vfb is input to the non-inverting input terminal of the comparator 15_H, and the voltage V_H is input to the inverting input terminal of the comparator 15_H. A comparison result signal CMP_H indicating the high-low relationship between the feedback voltage Vfb and the voltage V_H is output from the output terminal of the comparator 15_H. Therefore, during the period when "Vfb > V_H" holds, the comparison result signal CMP_H has a high level, and during the period when "Vfb < V_H" holds, the comparison result signal CMP_H has a low level.

[0037] The feedback voltage Vfb is input to the inverting input terminal of the comparator 15_L, and the voltage V_L is input to the non-inverting input terminal of the comparator 15_L. A comparison result signal CMP_L indicating the high-low relationship between the feedback voltage Vfb and the voltage V_L is output from the output terminal of the comparator 15_L. Therefore, during the period when "Vfb < V_L" holds, the comparison result signal CMP_L has a high level, and during the period when "Vfb > V_L" holds, the comparison result signal CMP_L has a low level.

[0038] The comparators 15_H and 15_L form a window comparator that determines whether the output voltage Vout is within a predetermined normal voltage range. In other words, the output abnormality monitoring circuit 15 monitors the output voltage Vout for abnormalities based on the feedback voltage Vfb and the output monitoring voltages (voltages V_H and V_L) generated by the voltage generating circuit 12. This monitoring corresponds to monitoring whether the output voltage Vout is within the predetermined normal voltage range. Monitoring whether the output voltage Vout is within the normal voltage range is achieved by monitoring whether the feedback voltage Vfb is within a voltage range from voltage V_L (first output monitoring voltage) to voltage V_H (second output monitoring voltage) higher than voltage V_L. A high-level comparison result signal CMP_H or CMP_L indicates that the output voltage Vout is outside the normal voltage range. Specifically, a high-level comparison result signal CMP_H indicates that the output voltage Vout exceeds the upper limit of the normal voltage range, and a high-level comparison result signal CMP_L indicates that the output voltage Vout is below the lower limit of the normal voltage range. When the comparison result signals CMP_H and CMP_L are both at a low level, the comparison result signals CMP_H and CMP_L indicate that the output voltage Vout falls within the normal voltage range.

[0039] The comparison result signals CMP_H and CMP_L are input to the state detection circuit 16, along with voltages V1a, V1b, V2a, V2b, V3a, V3b, V3c, and V3d. Hereinafter, the group of voltages V1a, V1b, V2a, V2b, V3a, V3b, V3c, and V3d may be referred to as a group of determination voltages for convenience. The state detection circuit 16 controls the gate voltage of an open-drain transistor 17a based on the comparison result signals CMP_H and CMP_L, thereby turning the transistor 17a on or off. When the comparison result signal CMP_H or CMP_L is high, the state detection circuit 16 turns the transistor 17a on. When both the comparison result signals CMP_H and CMP_L are low, the state detection circuit 16 turns the transistor 17a off. However, the state detection circuit 16 may control the state of the transistor 17a based on not only the comparison result signals CMP_H and CMP_L but also the group of determination voltages.

[0040] The drain of the transistor 17a is connected to the power-good terminal PG, and the source of the transistor 17a is connected to ground. Therefore, when the transistor 17a is off, the signal Spg has a high level (the level of the power supply voltage VDD), and when the transistor 17a is on, the signal Spg has a low level (substantially a level of 0 V). The low-level signal Spg indicates that the output voltage Vout is abnormal or that there is a possibility that the output voltage Vout is abnormal. An abnormality in the output voltage Vout refers to a state in which the error between the output voltage Vout and the target voltage Vtg is greater than the product of the output voltage Vout and a certain coefficient (e.g., 3%).

[0041] In addition, the state detection circuit 16 detects whether each of the voltage generation circuits 11, 12, and 13 is normal or abnormal based on the group of determination voltages (details will be described later).

[0042] Although not specifically shown, the power supply control device 2A is provided with an internal power supply circuit that generates an internal power supply voltage based on the input voltage Vin. Each circuit in the power supply control device 2A is driven by the input voltage Vin or the internal power supply voltage. Although not specifically shown, each circuit in the power supply control device 2A is connected to ground. Furthermore, the gate signal GL is a signal referenced to the ground potential, while the gate signal GH is a signal referenced to the potential of the switch terminal SW. A low-level gate signal GH has the potential of the switch terminal SW, and a high-level gate signal GH is a predetermined voltage higher than the potential of the switch terminal SW. This predetermined voltage is greater than the gate threshold voltage of the transistor MH. A well-known bootstrap circuit (not shown) can be used to generate a boost power supply for generating the gate signal GH. The transistor MH may be configured as a P-channel MOSFET, in which case a boost power supply is not required.

[0043] Alternatively, the power supply 1A may employ a diode rectification system. In this case, instead of the transistor ML, a synchronous rectification diode having an anode connected to the ground terminal GND and a cathode connected to the switch terminal SW is provided in the power supply 1A as the rectification element. In this case, only the output element (MH) is turned on and off during switching operation of the output stage circuit MM. In either case, the output element (MH) is switched on and off during switching operation of the output stage circuit MM, and an output voltage Vout is generated based on the current (IL) flowing through the coil L1.

[0044] Prior to a detailed description of the state detection circuit 16, a reference power supply device according to a reference example different from the power supply device 1 (1A) of this embodiment will be described.

[0045] <1st reference example> FIG. 4 shows the configuration of a reference power supply 910 according to a first embodiment. The reference power supply 910 is a step-down switching power supply equipped with a power supply control device 920, which generates an output voltage Vout from an input voltage Vin through switching control of an output stage circuit MM. In the power supply control device 920, a control circuit 924 controls the switching of the output stage circuit MM so that the error between a feedback voltage Vfb corresponding to the output voltage Vout and a reference voltage Vref from a voltage generation circuit (reference voltage source) 921 approaches zero. The voltage generation circuit 921 generates not only a reference voltage Vref, but also two voltages Vref_H and Vref_L that are proportional to the reference voltage Vref, such that "Vref_H>Vref>Vref_L." In the reference power supply 910, an output abnormality monitoring circuit 925 having a window comparator compares the feedback voltage Vfb with each of the voltages Vref_H and Vref_L to determine whether the output voltage Vout is within a normal voltage range. The reference power supply 910 uses a transistor 927a with an open drain configuration, and when it is determined that the output voltage Vout is within the normal voltage range, the transistor 927a is turned off, causing the signal Spg to go high, and when it is determined that the output voltage Vout is outside the normal voltage range, the transistor 927a is turned on, causing the signal Spg to go low. In the reference power supply 910, the high-level signal Spg functions as an output normal signal indicating that the output voltage Vout is normal, and the low-level signal Spg functions as an output abnormal signal indicating that the output voltage Vout is abnormal (the same applies to the reference power supply 930 in FIG. 5, which will be described later).

[0046] In the reference power supply device 910, the signal Spg may be maintained at a high level even if the output voltage Vout is abnormal due to an abnormality occurring in the voltage generation circuit 921. That is, when the reference voltage Vref rises above the design voltage due to an abnormality in the DC voltage source in the voltage generation circuit 921, the output voltage Vout also rises above the design voltage and the feedback voltage Vfb also rises, but the voltages Vref_H and Vref_L also rise in conjunction with the rise in the reference voltage Vref, so the signal Spg remains at a high level. Conversely, when the reference voltage Vref falls below the design voltage due to an abnormality in the DC voltage source in the voltage generation circuit 921, the output voltage Vout also falls below the design voltage and the feedback voltage Vfb also falls, but the voltages Vref_H and Vref_L also fall in conjunction with the fall in the reference voltage Vref, so the signal Spg remains at a high level.

[0047] <Second reference example> FIG. 5 shows the configuration of a reference power supply 930 according to a second reference example. The reference power supply 930 is a step-down switching power supply equipped with a power supply control device 940. Similar to the reference power supply 910 of FIG. 4, the reference power supply 930 generates an output voltage Vout from an input voltage Vin through switching control of an output stage circuit MM. In the power supply control device 940, a control circuit 944 controls the switching of the output stage circuit MM so that the error between a feedback voltage Vfb corresponding to the output voltage Vout and a reference voltage Vref from a voltage generation circuit (reference voltage source) 941 approaches zero. The power supply control device 940 is provided with a voltage generation circuit 942 for output monitoring, separate from the voltage generation circuit 941 for output control. The voltage generation circuit 942 generates a voltage V_H and a voltage V_L lower than voltage V_H. In the reference power supply 930, an output abnormality monitoring circuit 945 having a window comparator compares the feedback voltage Vfb with each of voltages V_H and V_L to determine whether the output voltage Vout is within a normal voltage range. In the reference power supply device 930, an open-drain transistor 947a is used, and when it is determined that the output voltage Vout is within the normal voltage range, the transistor 947a is turned off, causing the signal Spg to go high, and when it is determined that the output voltage Vout is outside the normal voltage range, the transistor 947a is turned on, causing the signal Spg to go low.

[0048] In the reference power supply device 930, when the reference voltage Vref increases from the designed voltage due to an abnormality in the voltage generation circuit 941, the output voltage Vout also increases from the designed voltage, the feedback voltage Vfb also increases, and as a result, when "Vfb > V_H" is satisfied, the transistor 947a turns on and the signal Spg becomes a low level (the signal Spg becomes an output abnormality signal). Conversely, when the reference voltage Vref decreases from the designed voltage due to an abnormality in the voltage generation circuit 941, the output voltage Vout also decreases from the designed voltage, the feedback voltage Vfb also decreases, and as a result, when "Vfb < V_L" is satisfied, the transistor 947a turns on and the signal Spg becomes a low level (the signal Spg becomes an output abnormality signal). That is, by using the voltage generation circuit 942, an abnormality in the output voltage Vout due to an abnormality in the voltage generation circuit 941 can be correctly detected.

[0049] On the other hand, in the reference power supply device 930, when the voltages Vref_H and Vref_L increase or decrease due to an abnormality in the voltage generation circuit 942, the signal Spg may become a low level even if the output voltage Vout is normal. Therefore, in the reference power supply device 930, when an abnormality occurs in either the voltage generation circuit 941 or 942, it is possible to represent the abnormality by the signal Spg. However, in the reference power supply device 930, it is not possible to determine which of the voltage generation circuits 941 and 942 has an abnormality. If it were possible to determine which of the voltage generation circuits 941 and 942 has an abnormality, it would be possible to hold flag data corresponding to the determination result, output a signal Spg corresponding to the determination result, or notify an external device of the flag data corresponding to the determination result, etc., or it would also be possible to replace the reference voltage used for switching control with another voltage when an abnormality occurs in the voltage generation circuit 941, which is beneficial.

[0050] Hereinafter, in the first to fourth embodiments, details of the power supply device 1 according to the present embodiment (particularly details of the state detection circuit 16), application technologies, modified technologies, etc., configured in consideration of matters related to the reference power supply devices 910 and 930 will be described.

[0051] <<First Embodiment>> The first embodiment will be described. As shown in FIG. 6, comparators 161 to 164 are provided in the state detection circuit 16 according to the first embodiment. The comparators 161 to 164 are two-input comparators respectively.

[0052] Voltage V1a and voltage V3a are input to the non-inverting input terminal and the inverting input terminal of comparator 161 respectively. Comparator 161 compares voltage V1a and V3a and outputs a comparison result signal CMP1 indicating the high / low relationship between voltage V1a and V3a from its output terminal. Comparator 161 outputs a high-level comparison result signal CMP1 when "V1a > V3a" holds, outputs a low-level comparison result signal CMP1 when "V1a < V3a" holds, and outputs a high-level or low-level comparison result signal CMP1 when "V1a = V3a" holds.

[0053] Voltage V3b and voltage V1b are input to the non-inverting input terminal and the inverting input terminal of comparator 162 respectively. Comparator 162 compares voltage V3b and V1b and outputs a comparison result signal CMP2 indicating the high / low relationship between voltage V3b and V1b from its output terminal. Comparator 162 outputs a high-level comparison result signal CMP2 when "V3b > V1b" holds, outputs a low-level comparison result signal CMP2 when "V3b < V1b" holds, and outputs a high-level or low-level comparison result signal CMP2 when "V3b = V1b" holds.

[0054] Voltage V2a and voltage V3c are input to the non-inverting input terminal and the inverting input terminal of comparator 163 respectively. Comparator 163 compares voltage V2a and V3c and outputs a comparison result signal CMP3 indicating the high / low relationship between voltage V2a and V3c from its output terminal. Comparator 163 outputs a high-level comparison result signal CMP3 when "V2a > V3c" holds, outputs a low-level comparison result signal CMP3 when "V2a < V3c" holds, and outputs a high-level or low-level comparison result signal CMP3 when "V2a = V3c" holds.

[0055] The non-inverting input terminal and the inverting input terminal of the comparator 164 are respectively input with the voltage V3d and the voltage V2b. The comparator 164 compares the voltages V3d and V2b and outputs a comparison result signal CMP4 indicating the high / low relationship between the voltages V3d and V2b from its output terminal. When "V3d>V2b" holds, the comparator 164 outputs a high-level comparison result signal CMP4. When "V3d<V2b" holds, the comparator 164 outputs a low-level comparison result signal CMP4. When "V3d = V2b" holds, the comparator 164 outputs a high-level or low-level comparison result signal CMP4.

[0056] The state detection circuit 16 individually detects whether there are abnormalities in the voltage generation circuits 11 to 13 based on the comparison result signals CMP1 to CMP4. That is, the state detection circuit 16 distinguishes and detects the abnormalities of the voltage generation circuits 11 to 13 (detects the normal or abnormal states of the voltage generation circuits 11 to 13 respectively). Specifically, the state detection circuit 16 detects whether there is an abnormality in the voltage generation circuit 11 based on the comparison result signals CMP1 to CMP4 (detects whether the voltage generation circuit 11 is in a normal or abnormal state), detects whether there is an abnormality in the voltage generation circuit 12 (detects whether the voltage generation circuit 12 is in a normal or abnormal state), and detects whether there is an abnormality in the voltage generation circuit 13 (detects whether the voltage generation circuit 13 is in a normal or abnormal state). However, in the state detection circuit 16, the operation of detecting whether there is an abnormality in the voltage generation circuit 13 may be omitted.

[0057] Since the abnormalities of the voltage generation circuits 11 to 13 can be distinguished and detected, the state detection circuit 16 or the control circuit 14 can perform the necessary first processing corresponding to the occurrence of the abnormality of the voltage generation circuit 11 when detecting the abnormality of the voltage generation circuit 11, can perform the necessary second processing corresponding to the occurrence of the abnormality of the voltage generation circuit 12 when detecting the abnormality of the voltage generation circuit 12, and can perform the necessary third processing corresponding to the occurrence of the abnormality of the voltage generation circuit 13 when detecting the abnormality of the voltage generation circuit 13.

[0058] An abnormality in the voltage generation circuit 11 refers to a state in which the error between the actual voltage value of the first voltage under evaluation and the design voltage value (ideal voltage value) of the first voltage under evaluation exceeds a predetermined abnormality threshold TH1. The first voltage under evaluation is the reference voltage Vref. However, the first voltage under evaluation may also be understood to be voltage V1a or V1b, or the output voltage of the DC voltage source 11a. Because the multiple voltages generated by the voltage generation circuit 11 (the output voltage of the DC voltage source 11a, the reference voltage Vref, voltage V1a, and voltage V1b) are proportional to one another, when the voltage value of any one of the multiple generated voltages deviates from the design voltage value, the voltage values ​​of the other generated voltages also deviate from the design voltage value in the same direction. The state detection circuit 16 detects the state of the voltage generation circuit 11 as a binary value. Therefore, if the state detection circuit 16 does not detect an abnormality in the voltage generation circuit 11, it detects the voltage generation circuit 11 as normal.

[0059] An abnormality in the voltage generation circuit 12 refers to a state in which the error between the actual voltage value of the second voltage under evaluation and the design voltage value (ideal voltage value) of the second voltage under evaluation exceeds a predetermined abnormality threshold TH2. The second voltage under evaluation is voltage V_H or V_L. However, the second voltage under evaluation may also be voltage V2a or V2b, or the output voltage of the DC voltage source 12a. Because the multiple voltages generated by the voltage generation circuit 12 (the output voltage of the DC voltage source 12a and voltages V_H, V_L, V2a, and V2b) are proportional to one another, when the voltage value of any one of the multiple generated voltages deviates from the design voltage value, the voltage values ​​of the other generated voltages also deviate from the design voltage value in the same direction. The status detection circuit 16 detects the status of the voltage generation circuit 12 as a binary value. Therefore, if the status detection circuit 16 does not detect an abnormality in the voltage generation circuit 12, it detects the voltage generation circuit 12 as normal.

[0060] An abnormality in the voltage generation circuit 13 refers to a state in which the error between the actual voltage value of the third evaluation target voltage and the design voltage value (ideal voltage value) of the third evaluation target voltage exceeds a predetermined abnormality threshold TH3. The third evaluation target voltage is voltage V3a, V3b, V3c, or V3d. However, the output voltage of the DC voltage source 13a may also be interpreted as the third evaluation target voltage. Because the multiple voltages generated by the voltage generation circuit 13 (the output voltage of the DC voltage source 13a and voltages V3a, V3b, V3c, and V3d) are proportional to each other, when the voltage value of any of the multiple generated voltages deviates from the design voltage value, the voltage values ​​of the other generated voltages also deviate from the design voltage value in the same direction. The status detection circuit 16 detects the status of the voltage generation circuit 13 as a binary value. Therefore, if the status detection circuit 16 does not detect an abnormality in the voltage generation circuit 13, it detects the voltage generation circuit 13 as normal.

[0061] Based on the comparison result signals CMP1 to CMP4, the state detection circuit 16 distinguishes between the following abnormal states: a fully normal state in which the voltage generation circuits 11, 12, and 13 are all normal; a first abnormal state in which the voltage generation circuit 11 is abnormal and the voltage generation circuits 12 and 13 are normal; a second abnormal state in which the voltage generation circuit 12 is abnormal and the voltage generation circuits 11 and 13 are normal; and a third abnormal state in which the voltage generation circuit 13 is abnormal and the voltage generation circuits 11 and 12 are normal. Note that it is unlikely that two or more of the voltage generation circuits 11, 12, and 13 will be abnormal at the same time. Therefore, in this embodiment, it is assumed that a situation in which two or more of the voltage generation circuits 11, 12, and 13 will be abnormal at the same time is not anticipated, and if one of the voltage generation circuits 11, 12, and 13 is abnormal, the voltages generated by the other two voltage generation circuits will have their design voltage values.

[0062] As shown in FIG. 7, the signal group consisting of the comparison result signals CMP1 to CMP4 assumes one of the first to seventh signal states. In the first signal state, the comparison result signals CMP1 to CMP4 are all at low levels. In the second signal state, the comparison result signal CMP1 is at high levels and the comparison result signals CMP2 to CMP4 are at low levels. In the third signal state, the comparison result signal CMP2 is at high levels and the comparison result signals CMP1, CMP3, and CMP4 are at low levels. In the fourth signal state, the comparison result signal CMP3 is at high levels and the comparison result signals CMP1, CMP2, and CMP4 are at low levels. In the fifth signal state, the comparison result signal CMP4 is at high levels and the comparison result signals CMP1 to CMP3 are at low levels. In the sixth signal state, the comparison result signals CMP2 and CMP4 are at high levels and the comparison result signals CMP1 and CMP3 are at low levels. In the seventh signal state, the comparison result signals CMP1 and CMP3 are at high levels and the comparison result signals CMP2 and CMP4 are at low levels.

[0063] When the comparison result signals CMP1 to CMP4 are in the first signal state, the state detection circuit 16 detects and determines that the voltage generation circuits 11, 12, and 13 are all in a normal state.

[0064] When the comparison result signals CMP1 to CMP4 are in the second signal state or the third signal state, the state detection circuit 16 detects and determines that the voltage generation circuits 11, 12, and 13 are in the first abnormal state (detects that there is an abnormality in the voltage generation circuit 11; see FIG. 7). An abnormality in the voltage generation circuit 11 in the second signal state is an abnormality in which the voltage values ​​of the voltages generated by the voltage generation circuit 11 are excessively high compared to the design voltage values, and an abnormality in the voltage generation circuit 11 in the third signal state is an abnormality in which the voltage values ​​of the voltages generated by the voltage generation circuit 11 are excessively low compared to the design voltage values.

[0065] On the premise that the voltage generation circuit 13 is normal (on the premise that each generated voltage of the voltage generation circuit 13 has a designed voltage value), the comparators 161 and 162 form a window comparator that determines whether the generated voltage of the voltage generation circuit 11 is excessive or too small. Specifically, for example, it can be as follows. That is, after setting the voltages V1a and V1b as a common voltage V1_com, the voltage generation circuit 13 generates voltages V3a and V3b that satisfy "V3a > V3b" (see FIG. 8). Then, the comparators 161 and 162 determine whether the voltage V1_com falls within the voltage range from the voltage V3b to the voltage V3a. If each generated voltage of the voltage generation circuits 11 and 13 has a designed voltage value, it is assumed that "V3b < V1a = V1b = V1_com < V3a" holds. Then, on the premise that the voltage generation circuit 13 is normal, if the voltage generation circuit 11 is normal, "V3b < V1a = V1b = V1_com < V3a" holds, so the comparison result signals CMP1 and CMP2 both become low level.

[0066] When an abnormality occurs in the voltage generation circuit where each generated voltage of the voltage generation circuit 11 rises from the designed voltage value, so that "V3b < V3a < V1a = V1b = V1_com" holds, the comparison result signals CMP1 and CMP2 become high level and low level respectively. Conversely, when an abnormality occurs in the voltage generation circuit where each generated voltage of the voltage generation circuit 11 drops from the designed voltage value, so that "V1a = V1b = V1_com < V3b < V3a" holds, the comparison result signals CMP1 and CMP2 become low level and high level respectively.

[0067] When the comparison result signals CMP1 to CMP4 are in the fourth signal state or the fifth signal state, the state detection circuit 16 detects and determines that the voltage generation circuits 11, 12, and 13 are in the second abnormal state (detects that there is an abnormality in the voltage generation circuit 12; see FIG. 7). The abnormality of the voltage generation circuit 12 in the fourth signal state is an abnormality in which the voltage value of each generated voltage of the voltage generation circuit 12 becomes excessive as viewed from the designed voltage value, and the abnormality of the voltage generation circuit 12 in the fifth signal state is an abnormality in which the voltage value of each generated voltage of the voltage generation circuit 12 becomes too small as viewed from the designed voltage value.

[0068] On the premise that the voltage generation circuit 13 is normal (on the premise that each generated voltage of the voltage generation circuit 13 has a designed voltage value), the comparators 163 and 164 form a window comparator for determining whether the generated voltage of the voltage generation circuit 12 is excessive or too small. Specifically, for example, it can be done as follows. That is, after setting the voltages V2a and V2b as a common voltage V2_com, the voltage generation circuit 13 generates voltages V3c and V3d that satisfy "V3c > V3d" (see FIG. 9). Then, the comparators 163 and 164 determine whether the voltage V2_com falls within the voltage range from the voltage V3d to the voltage V3c. If each generated voltage of the voltage generation circuits 12 and 13 has a designed voltage value, it is assumed that "V3d < V2a = V2b = V2_com < V3c" holds. Then, on the premise that the voltage generation circuit 13 is normal, if the voltage generation circuit 12 is normal, "V3d < V2a = V2b = V2_com < V3c" holds, so the comparison result signals CMP3 and CMP4 both become low level.

[0069] When an abnormality occurs in the voltage generation circuit 12 where each generated voltage of the voltage generation circuit 12 rises from the designed voltage value, so that "V3d < V3c < V2a = V2b = V2_com" holds, the comparison result signals CMP3 and CMP4 become high level and low level respectively. Conversely, when an abnormality occurs in the voltage generation circuit 12 where each generated voltage of the voltage generation circuit 12 drops from the designed voltage value, so that "V2a = V2b = V2_com < V3d < V3c" holds, the comparison result signals CMP3 and CMP4 become low level and high level respectively.

[0070] When the comparison result signals CMP1 to CMP4 are in the sixth signal state or the seventh signal state, the state detection circuit 16 detects and determines that the voltage generation circuits 11, 12, and 13 are in the third abnormal state (detects that there is an abnormality in the voltage generation circuit 13; see FIG. 7). The abnormality of the voltage generation circuit 13 in the sixth signal state is an abnormality in which the voltage value of each generated voltage of the voltage generation circuit 13 is excessive as seen from the designed voltage value, and the abnormality of the voltage generation circuit 13 in the seventh signal state is an abnormality in which the voltage value of each generated voltage of the voltage generation circuit 13 is too small as seen from the designed voltage value.

[0071] On the premise that the voltage generation circuits 11 and 12 are normal (on the premise that each generated voltage of the voltage generation circuits 11 and 12 has a designed voltage value), the comparators 161 to 164 form window comparators for determining whether the generated voltage of the voltage generation circuit 13 is excessive or too small. Specifically, for example, it may be as follows. That is, after setting the voltages V1a and V1b as a common voltage V1_com and the voltages V2a and V2b as a common voltage V2_com, the voltage generation circuit 13 generates voltages V3a to V3d that satisfy "V3a > V3b" and "V3c > V3d" (see FIGS. 10 and 11). If each generated voltage of the voltage generation circuits 11 to 13 has a designed voltage value, it is assumed that "V3b < V1a = V1b = V1_com < V3a" and "V3d < V2a = V2b = V2_com < V3c" hold (see FIGS. 10 and 11). Then, on the premise that the voltage generation circuit 11 is normal, if the voltage generation circuit 13 is normal, "V3b < V1a = V1b = V1_com < V3a" holds, so that the comparison result signals CMP1 and CMP2 both become low levels. On the premise that the voltage generation circuit 12 is normal, if the voltage generation circuit 13 is normal, "V3d < V2a = V2b = V2_com < V3c" holds, so that the comparison result signals CMP3 and CMP4 both become low levels.

[0072] When an abnormality occurs in the voltage generation circuit 13 in which each generated voltage of the voltage generation circuit 13 rises from the designed voltage value, "V1a = V1b = V1_com < V3b < V3a" and "V2a = V2b = V2_com < V3d < V3c" hold (see FIGS. 10 and 11). As a result, the comparison result signals CMP2 and CMP4 become high levels while the comparison result signals CMP1 and CMP3 become low levels. Conversely, when an abnormality occurs in the voltage generation circuit 13 in which each generated voltage of the voltage generation circuit 13 drops from the designed voltage value, "V3b < V3a < V1a = V1b = V1_com" and "V3d < V3c < V2a = V2b = V2_com" hold (see FIGS. 10 and 11). As a result, the comparison result signals CMP2 and CMP4 become low levels while the comparison result signals CMP1 and CMP3 become high levels.

[0073] 8 to 11, examples of the relationships between voltages V1a, V1b, V2a, V2b, V3a, V3b, V3c, and V3d for detecting the normality or abnormality of voltage generation circuits 11 to 13 have been described above, but the relationships between these voltages may be set in various ways as long as the normality or abnormality of each of voltage generation circuits 11 to 13 can be detected. For example, even if the design voltage values ​​of voltages V3a and V3b are the same and the design voltage value of voltage V1a is lower than the design voltage value of voltage V1b, the normality or abnormality of voltage generation circuit 11 can be correctly detected from comparison result signals CMP1 and CMP2. The same applies to detecting the normality or abnormality of voltage generation circuits 12 and 13.

[0074] In this way, the state detection circuit 16 can distinguish and detect which of the voltage generation circuits 11 to 13 has an abnormality.

[0075] When the state detection circuit 16 detects that an abnormality exists in any of the voltage generation circuits 11 to 13, the state detection circuit 16 may store abnormality detection flag data indicating that the abnormality has been detected in a memory in the power supply control device 2A. The memory in which the abnormality detection flag data is stored may be a non-volatile memory or a volatile memory. The abnormality detection flag data may include information indicating which of the voltage generation circuits 11 to 13 is the voltage generation circuit that has been detected to have an abnormality. When the state detection circuit 16 detects that an abnormality exists in any of the voltage generation circuits 11 to 13, the state detection circuit 16 may transmit the abnormality detection flag data to the MPU 4. The abnormality detection flag data may be transmitted via an SPI (Serial Peripheral Interface) or an I / O. 2 This may be done using an interface based on C (Inter-Integrated Circuit) or Microwire.

[0076] <<Second Example>> A second embodiment will now be described. The second embodiment is implemented in combination with the first embodiment. When comparison result signals CMP1 to CMP4 of the second signal state or the third signal state are obtained (see FIG. 7), the control circuit 14 according to the second embodiment can perform switching control of the output stage circuit MM using the backup voltage Vbkup generated by the voltage generation circuit 13 instead of the reference voltage Vref. FIG. 12 shows an overview of the operation according to the second embodiment.

[0077] Voltage generating circuit 13 according to the second embodiment generates backup voltage Vbkup as a voltage proportional to the output voltage of DC voltage source 13a (see FIG. 3). Therefore, if the output voltage of reference voltage source 13a is voltage V13a, then "Vbkup=k3e×V13a" holds. k3e is a predetermined positive proportionality coefficient, which may have a value of 1. Any of the above-mentioned voltages V3a to V3d may be backup voltage Vbkup.

[0078] The design voltage value of the backup voltage Vbkup is the same as the design voltage value of the reference voltage Vref. That is, the voltage generation circuit 13 generates the backup voltage Vbkup so that the backup voltage Vbkup has the same voltage value as the design voltage value of the reference voltage Vref. For example, if the design voltage value (ideal voltage value) of the reference voltage Vref is 0.80 V, the voltage generation circuit 13 generates the backup voltage Vbkup so that the backup voltage Vbkup becomes 0.80 V.

[0079] A selector 18 is added to the power supply control device 2A according to the second embodiment. The selector 18 selects either the reference voltage Vref generated by the voltage generation circuit 11 or the backup voltage Vbkup generated by the voltage generation circuit 13, and supplies the selected voltage to the control circuit 14 as the adopted reference voltage Vref2. The control circuit 14 supplies a selection signal SEL to the selector 18. The selection signal SEL is a binary signal having a value of "0" or "1." When the selection signal SEL has a value of "0," the reference voltage Vref is selected by the selector 18, and therefore the adopted reference voltage Vref2 matches the reference voltage Vref. When the selection signal SEL has a value of "1," the backup voltage Vbkup is selected by the selector 18, and therefore the adopted reference voltage Vref2 matches the backup voltage Vbkup.

[0080] The control circuit 14 supplies the selector 18 with a selection signal SEL that has a value of "0" in principle, and maintains the value of the selection signal SEL at "0" unless the comparison result signals CMP1 to CMP4 in the second or third signal state are obtained. After that, when the comparison result signals CMP1 to CMP4 in the second or third signal state are obtained (i.e., when an abnormality in the voltage generating circuit 11 is detected), the state detection circuit 16 outputs a specific abnormality notification signal Sn to the control circuit 14. The specific abnormality notification signal Sn indicates that the voltage generation circuits 11 to 13 are in the first abnormal state (i.e., that an abnormality has been detected in the voltage generation circuit 11). When the control circuit 14 receives the specific abnormality notification signal Sn, it changes the value of the selection signal SEL from "0" to "1." This switches the employed reference voltage Vref2 from the reference voltage Vref to the backup voltage Vbkup. Thereafter, the employed reference voltage Vref2 may be maintained at the backup voltage Vbkup unless a predetermined release condition is met.

[0081] The control circuit 14 according to the second embodiment controls the switching of the output stage circuit MM based on the feedback voltage Vfb and the adopted reference voltage Vref2. Specifically, in controlling the switching of the output stage circuit MM, the control circuit 14 according to the second embodiment controls the on / off states of the transistors MH and ML by controlling the levels of the gate signals GH and GL so that the error between the feedback voltage Vfb and the adopted reference voltage Vref2 approaches zero (ideally, so that it matches zero), thereby stabilizing the output voltage Vout at a predetermined target voltage Vtg. When the error between the feedback voltage Vfb and the adopted reference voltage Vref2 is zero, the output voltage Vout matches the target voltage Vtg (assuming that the voltage value of the adopted reference voltage Vref2 matches the designed voltage value of the reference voltage Vref).

[0082] According to the second embodiment, even if an abnormality occurs in the voltage generating circuit 11, it is possible to properly maintain the operation of the power supply device 1A (the operation of stabilizing the output voltage Vout at the desired target voltage Vtg) by using the voltage generated by the voltage generating circuit 13 provided for detecting abnormalities in the voltage generating circuits 11 and 12.

[0083] When the control circuit 14 receives the specific abnormality notification signal Sn while performing switching control of the output stage circuit MM, the control circuit 14 may immediately switch the value of the selection signal SEL from "0" to "1" while continuing switching control of the output stage circuit MM. Alternatively, when the control circuit 14 receives the specific abnormality notification signal Sn while performing switching control of the output stage circuit MM, the control circuit 14 may store selector flag data corresponding to the reception of the specific abnormality notification signal Sn in its own nonvolatile memory without immediately switching the value of the selection signal SEL from "0" to "1." In this case, when the power supply control device 2A is restarted after stopping its operation (including stopping its switching control) due to, for example, interruption of the input voltage Vin, the control circuit 14 may set the value of the selection signal SEL to "1" based on the selector flag data stored in the nonvolatile memory and then start switching control of the output stage circuit MM.

[0084] <<Third Example>> The third embodiment will be described. The control method for stabilizing the output voltage Vout at the target voltage Vtg is arbitrary. For example, a pulse width modulation method may be adopted in the control method. When the pulse width modulation method is adopted, the switching frequency of the output stage circuit MM (the switching frequency of the transistor MH) is made constant, and then the on-duty ratio of the output stage circuit MM is controlled. At this time, the control circuit 14 performs feedback control to increase the on-duty ratio of the output stage circuit MM if "Vfb < Vref2", and to decrease the on-duty ratio of the output stage circuit MM if "Vfb > Vref2". The voltage Vref2 here is the adoption reference voltage Vref2 described in the second embodiment. When the technology shown in the second embodiment is not used, the adoption reference voltage Vref2 always coincides with the reference voltage Vref. The on-duty ratio of the output stage circuit MM is the ratio of the on-period of the transistor MH to the sum of the on-period and the off-period of the transistor MH.

[0085] In addition, a pulse frequency modulation method or a constant on-time control method may be adopted in the control method for stabilizing the output voltage Vout at the target voltage Vtg.

[0086] <<Fourth Embodiment>> The fourth embodiment will be described.

[0087] The power supply 1A in FIG. 3 shown as an example of the power supply 1 is a step-down switching power supply ((switching regulator)), but the power supply 1 may also be a step-up switching power supply. A step-up switching power supply generates an output voltage Vout higher than the input voltage Vin by stepping up the input voltage Vin. FIG. 13 is a partial configuration diagram of the power supply 1 when the power supply 1 is a step-up switching power supply. When the power supply 1 is a step-up switching power supply, as shown in FIG. 13, a first end of the coil L1 is connected to an application terminal for the input voltage Vin (a terminal to which the input voltage Vin is applied), a second end of the coil L1 is connected to the drain of the transistor MH and the source of the transistor ML, the source of the transistor MH is connected to ground, and the drain of the transistor ML is connected to the output terminal OUT. The power supply device 1 is connected to the feedback terminal MH and is also connected to ground via a capacitor C1. The control circuit 14 alternately turns on and off the transistors MH and ML so that the error between the feedback voltage Vfb and the employed reference voltage Vref2 approaches zero. If the technology described in the second embodiment is not used, the employed reference voltage Vref2 always coincides with the reference voltage Vref. In the configuration of FIG. 13, the transistor ML serving as the rectifying element may be replaced with a synchronous rectifying diode having an anode connected to the drain of the transistor MH and a cathode connected to the output terminal OUT. In either case, the output element (MH) is switched on and off during switching operation of the output stage MM, generating the output voltage Vout based on the current (IL) flowing through the coil L1. The power supply device 1 may be a buck-boost switching power supply.

[0088] The power supply 1 may be a linear regulator (series regulator). FIG. 14 is a partial configuration diagram of the power supply 1 when the power supply 1 is a linear regulator. When the power supply 1 is a linear regulator, as shown in FIG. 14, the output stage circuit MM is composed only of an output transistor M0. While the output transistor M0 in FIG. 14 is an N-channel MOSFET, a P-channel MOSFET or a bipolar transistor may also be used as the output transistor M0. In FIG. 14, the drain of the output transistor M0 is connected to the terminal to which the input voltage Vin is applied, and the source of the output transistor M0 is connected to the output terminal OUT (the source of the output transistor M0 is directly connected to the output terminal OUT without the coil L1 described above). As described above, an output capacitor C1 and a series circuit of feedback resistors R1 and R2 are provided between the output terminal OUT and ground. When the power supply 1 is a linear regulator, the control circuit 14 controls the gate voltage of the output transistor M0 so that the error between the feedback voltage Vfb and the adopted reference voltage Vref2 approaches zero. If the technique shown in the second embodiment is not used, the adopted reference voltage Vref2 always coincides with the reference voltage Vref.

[0089] In addition, the technology disclosed herein can be widely applied to any power supply device that generates an output voltage Vout from an input voltage Vin through power conversion and stabilizes the output voltage Vout through feedback control based on a feedback voltage Vfb corresponding to the output voltage Vout and an adopted reference voltage Vref2 (Vref or Vbkup).

[0090] The system shown in Fig. 1 can be installed in any electrical device, such as an electrical component installed in a vehicle such as an automobile, a computer device, a home appliance, or an industrial device.

[0091] With respect to any signal or voltage, the relationship between the high level and the low level thereof may be reversed without prejudice to the above-mentioned gist.

[0092] The channel types of the FETs (field effect transistors) shown in the above embodiments are merely examples, and the channel type of any FET may be changed between P-channel and N-channel types without departing from the spirit of the above.

[0093] Any of the transistors described above may be any type of transistor, provided that no disadvantages arise. For example, any of the transistors described above as MOSFETs may be replaced with junction field effect transistors (FETs), insulated gate bipolar transistors (IGBTs), or bipolar transistors, provided that no disadvantages arise. Any of the transistors has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate. In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.

[0094] In the present disclosure, any first physical quantity and any second physical quantity being "the same" is understood as a concept that includes errors. In other words, a first physical quantity and a second physical quantity being "the same" means that they are designed or manufactured with the aim of making the first physical quantity and the second physical quantity "the same." Even if there is a slight error between the first and second physical quantities, the first physical quantity and the second physical quantity should be understood as being "the same." This applies not only to physical quantities, but also to expressions similar to "the same" (e.g., "identical" or "matching"), and should be interpreted in the same way.

[0095] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0096] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0097] A power supply control device according to one aspect of the present disclosure is a power supply control device (2, 2A) constituting a power supply device (1, 1A) having an output stage circuit (MM) provided between an input terminal (IN) to which an input voltage (Vin) is applied and an output terminal (OUT) to which an output voltage (Vout) is applied, and configured to generate the output voltage from the input voltage, the power supply control device (2, 2A) comprising a first voltage generation circuit (11), a control circuit (14) configured to stabilize the output voltage to a target voltage by controlling the state of the output stage circuit based on a feedback voltage (Vfb) corresponding to the output voltage and a reference voltage (Vref) generated by the first voltage generation circuit, a second voltage generation circuit (12), and a feedback The configuration (first configuration) includes an output abnormality monitoring circuit (15) configured to monitor abnormalities in the output voltage based on a feedback voltage and output monitoring voltages (V_H, V_L) generated by the second voltage generation circuit, a third voltage generation circuit (13), and a state detection circuit (16) configured to distinguish between and detect abnormalities in the first voltage generation circuit and the second voltage generation circuit based on first determination voltages (V1a, V1b) generated by the first voltage generation circuit, second determination voltages (V2a, V2b) generated by the second voltage generation circuit, and third determination voltages (V3a, V3b, V3c, V3d) generated by the third voltage generation circuit.

[0098] This makes it possible to properly distinguish and detect whether an abnormality has occurred in the first voltage generation circuit or the second voltage generation circuit, which is advantageous because it becomes possible to perform a first process required to deal with the abnormality in the first voltage generation circuit if an abnormality in the first voltage generation circuit is detected, and to perform a second process required to deal with the abnormality in the second voltage generation circuit if an abnormality in the second voltage generation circuit is detected.

[0099] In the power supply control device according to the first configuration, the state detection circuit may be configured (second configuration) to distinguish and detect abnormalities in the first voltage generation circuit, the second voltage generation circuit, and the third voltage generation circuit based on the first judgment voltage, the second judgment voltage, and the third judgment voltage.

[0100] This makes it possible, advantageously, to perform the necessary first processing corresponding to the abnormality of the first voltage generation circuit if an abnormality is detected in the first voltage generation circuit, to perform the necessary second processing corresponding to the abnormality of the second voltage generation circuit if an abnormality is detected in the second voltage generation circuit, and to perform the necessary third processing corresponding to the abnormality of the third voltage generation circuit if an abnormality is detected in the third voltage generation circuit.

[0101] In the power supply control device according to the second configuration, the control circuit may be configured (third configuration) to use a backup voltage (Vbkup) generated by the third voltage generation circuit instead of the reference voltage when an abnormality is detected in the first voltage generation circuit, and control the state of the output stage circuit based on the feedback voltage and the backup voltage.

[0102] As a result, even if an abnormality occurs in the first voltage generation circuit, it is possible to maintain proper operation of the power supply device (operation of stabilizing the output voltage at the target voltage) by using the voltage generated by the third voltage generation circuit provided for detecting abnormalities in the first and second voltage generation circuits.

[0103] In the power supply control device according to the third configuration, the third voltage generating circuit may be configured (fourth configuration) to generate the backup voltage so that the backup voltage has the same voltage value as the design voltage value of the reference voltage.

[0104] This makes it possible to maintain proper operation of the power supply device (operation of stabilizing the output voltage at the target voltage) even if an abnormality occurs in the first voltage generating circuit.

[0105] In the power supply control device according to any of the above first to fourth configurations, the first determination voltage may be proportional to the reference voltage, and the second determination voltage may be proportional to the output monitoring voltage (fifth configuration).

[0106] In the power supply control device according to any one of the first to fourth configurations, the abnormality detection circuit has a first comparator (CMP1) configured to compare a first voltage (V1a) and a second voltage (V3a), a second comparator (CMP2) configured to compare a third voltage (V3b) and a fourth voltage (V1b), a third comparator (CMP3) configured to compare a fifth voltage (V2a) and a sixth voltage (V3c), and a fourth comparator (CMP4) configured to compare a seventh voltage (V3d) and an eighth voltage (V2b), and based on the comparison results of the first to fourth comparators, The configuration may be a sixth configuration in which abnormalities in the first voltage generation circuit, the second voltage generation circuit, and the third voltage generation circuit are distinguished and detected, the first determination voltage includes the first voltage and the fourth voltage, the first voltage, the fourth voltage, and the reference voltage are proportional to each other, the second determination voltage includes the fifth voltage and the eighth voltage, the fifth voltage, the eighth voltage, and the output monitoring voltage are proportional to each other, and the third determination voltage includes the second voltage, the third voltage, the sixth voltage, and the seventh voltage, and the second voltage, the third voltage, the sixth voltage, and the seventh voltage are proportional to each other.

[0107] In the power supply control device according to the sixth configuration, the abnormality detection circuit may be configured (seventh configuration) to distinguish and detect, based on the comparison results of the first comparator to the fourth comparator, a state in which the first voltage generation circuit to the third voltage generation circuit are all normal, a state in which the first voltage generation circuit is abnormal and the second voltage generation circuit and the third voltage generation circuit are normal, a state in which the second voltage generation circuit is abnormal and the first voltage generation circuit and the third voltage generation circuit are normal, and a state in which the third voltage generation circuit is abnormal and the first voltage generation circuit and the second voltage generation circuit are normal.

[0108] In the power supply control device according to any of the above first to seventh configurations, the output monitoring voltage may include a first output monitoring voltage (V_L) and a second output monitoring voltage (V_H) higher than the first output monitoring voltage, and the output abnormality monitoring circuit may be configured to monitor an abnormality in the output voltage by monitoring whether the feedback voltage falls within a voltage range from the first output monitoring voltage to the second output monitoring voltage (eighth configuration).

[0109] In the power supply control device according to any one of the first to eighth configurations, the output stage circuit may be provided in the power supply control device (ninth configuration).

[0110] The power supply control device according to any one of the first to eighth configurations may have a configuration (tenth configuration) in which the output stage circuit provided outside the power supply control device is connected to the power supply control device. [Explanation of symbols]

[0111] 1, 1A power supply 2, 2A power control device 3 Discrete Components 4 MPU CS chassis Vin Input voltage Vout Output voltage L1 coil C1 Output capacitor R1, R2 feedback resistors R3 pull-up resistor LD load IN input terminal OUT output terminal SW Switch terminal GND Ground terminal FB Feedback terminal PG Power Good pin VDD power supply voltage 11, 12, 13 Voltage generation circuit 11a, 12a, 13a DC voltage source 14 Control circuit 15 Output abnormality monitoring circuit 15_H, 15_L Comparator 16 Status detection circuit 17 Signal output circuit 17a Transistor MM output stage circuit MH, ML transistors Vfb Feedback voltage Vref Reference voltage V1a, V1b, V2a, V2b, V3a, V3b, V3c, V3d voltages 161~164 Comparator CMP1~CMP4 comparison result signal 18 Selectors Vref2 Reference voltage Sn Specific abnormality notification signal SEL selection signal M0 output transistor 910, 930 reference power supply unit 820, 940 Power supply control device 921, 941, 942 Voltage generation circuit 924, 944 Control circuit 925, 945 Output abnormality monitoring circuit

Claims

1. A power supply control device constituting a power supply device having an output stage circuit provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and configured to generate the output voltage from the input voltage, a first voltage generating circuit; a control circuit configured to stabilize the output voltage to a target voltage by controlling a state of the output stage circuit based on a feedback voltage corresponding to the output voltage and a reference voltage generated by the first voltage generating circuit; a second voltage generating circuit; an output abnormality monitoring circuit configured to monitor an abnormality in the output voltage based on the feedback voltage and the output monitoring voltage generated by the second voltage generating circuit; a third voltage generating circuit; a state detection circuit configured to distinguish and detect abnormalities in the first voltage generation circuit and the second voltage generation circuit based on a first determination voltage generated by the first voltage generation circuit, a second determination voltage generated by the second voltage generation circuit, and a third determination voltage generated by the third voltage generation circuit. , power control device.

2. The state detection circuit distinguishes and detects abnormalities in the first voltage generation circuit, the second voltage generation circuit, and the third voltage generation circuit based on the first determination voltage, the second determination voltage, and the third determination voltage. The power supply control device according to claim 1 .

3. When an abnormality is detected in the first voltage generating circuit, the control circuit uses a backup voltage generated by the third voltage generating circuit instead of the reference voltage, and controls a state of the output stage circuit based on the feedback voltage and the backup voltage. The power supply control device according to claim 2 .

4. The third voltage generating circuit generates the backup voltage so that the backup voltage has the same voltage value as a design voltage value of the reference voltage. The power supply control device according to claim 3 .

5. The first determination voltage is proportional to the reference voltage, and the second determination voltage is proportional to the output monitoring voltage.

5. The power supply control device according to claim 1.

6. the abnormality detection circuit has a first comparator configured to compare a first voltage with a second voltage, a second comparator configured to compare a third voltage with a fourth voltage, a third comparator configured to compare a fifth voltage with a sixth voltage, and a fourth comparator configured to compare a seventh voltage with an eighth voltage, and distinguishes between and detects abnormalities in the first voltage generation circuit, the second voltage generation circuit, and the third voltage generation circuit based on the comparison results of the first comparator to the fourth comparator; the first determination voltage includes the first voltage and the fourth voltage, and the first voltage, the fourth voltage, and the reference voltage are proportional to each other; the second determination voltage includes the fifth voltage and the eighth voltage, and the fifth voltage, the eighth voltage, and the output monitoring voltage are proportional to each other; The third determination voltage includes the second voltage, the third voltage, the sixth voltage, and the seventh voltage, and the second voltage, the third voltage, the sixth voltage, and the seventh voltage are proportional to each other.

5. The power supply control device according to claim 1.

7. The abnormality detection circuit distinguishes between and detects a state in which the first voltage generation circuit to the third voltage generation circuit are all normal, a state in which the first voltage generation circuit is abnormal and the second voltage generation circuit and the third voltage generation circuit are normal, a state in which the second voltage generation circuit is abnormal and the first voltage generation circuit and the third voltage generation circuit are normal, and a state in which the third voltage generation circuit is abnormal and the first voltage generation circuit and the second voltage generation circuit are normal, based on the comparison results of the first comparator to the fourth comparator. The power supply control device according to claim 6 .

8. the output monitoring voltages include a first output monitoring voltage and a second output monitoring voltage higher than the first output monitoring voltage; The output abnormality monitoring circuit monitors whether the feedback voltage falls within a voltage range from the first output monitoring voltage to the second output monitoring voltage, thereby monitoring the output voltage for abnormalities.

5. The power supply control device according to claim 1.

9. The output stage circuit is provided in the power supply control device.

5. The power supply control device according to claim 1.

10. The output stage circuit provided outside the power supply control device is connected to the power supply control device.

5. The power supply control device according to claim 1.

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