Semiconductor device and manufacturing method thereof

Abstract

To provide a technique capable of improving a trade-off relation when a thickness of a semiconductor region having an impurity concentration is relatively thin.SOLUTION: A semiconductor device includes a first semiconductor region, a second semiconductor region, an insulating film, and a conductive film provided on the second semiconductor region via the insulating film. The second semiconductor region includes an upper region, a middle region provided deeper than the upper region and having a higher impurity concentration than the upper region, and a lower region provided deeper than the middle region, having a lower impurity concentration than the middle region and having a constant impurity concentration at a depth of 0.5 μm or more.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Various technologies have been proposed for MOS (Metal-Oxide-Semiconductor) capacitors that constitute ICs (Integrated Circuits) such as analog integrated circuits. For example, Patent Document 1 proposes a technology that can increase the concentration of impurity diffusion regions that constitute MOS capacitors from the interface toward the inside of the semiconductor substrate, thereby reducing the occupied area and increasing reliability. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 08-097363 Summary of the Invention [Problem to be solved by the invention]

[0004] When the thickness of the semiconductor region having an impurity concentration that constitutes the MOS capacitor is thin, the trade-off relationship between the capacitance value of the MOS capacitor and the gate voltage dependency of the MOS capacitor becomes significant. Therefore, when the thickness of the semiconductor region having an impurity concentration is relatively thin, there is a need to improve the trade-off relationship between the capacitance value of the MOS capacitor and the gate voltage dependency of the MOS capacitor.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a technology that can improve the trade-off relationship when the thickness of a semiconductor region having an impurity concentration is relatively thin. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a first semiconductor region, a second semiconductor region provided on top of the first semiconductor region, at least a portion of which has an impurity concentration higher than the impurity concentration of the first semiconductor region, an insulating film provided on the second semiconductor region, and a conductive film provided on the second semiconductor region via the insulating film, wherein the second semiconductor region includes an upper region, a middle region provided deeper than the upper region and having a higher impurity concentration than the upper region, and a lower region provided deeper than the middle region, having a lower impurity concentration than the middle region and being constant at a depth of 0.5 μm or more. [Effects of the Invention]

[0007] According to the present disclosure, the two semiconductor regions include a middle region that is deeper than the upper region and has a higher impurity concentration than the upper region, and a lower region that is deeper than the middle region and has a lower impurity concentration than the middle region and is constant at a depth of 0.5 μm or more. With this configuration, when the thickness of the second semiconductor region is relatively thin, it is possible to improve the trade-off between the capacitance value of the MOS capacitor and the gate voltage dependence of the MOS capacitance. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a configuration of a MOS capacitor according to a first embodiment. [Figure 2] FIG. 10 is a diagram showing the relationship between the capacitance value of a MOS capacitor and the gate voltage. [Figure 3] 5 is a diagram showing a concentration profile of a second semiconductor region of the MOS capacitor according to the first embodiment. FIG. [Figure 4] FIG. 10 is a diagram showing the relationship between the capacitance value of a MOS capacitor and the gate voltage dependency. [Figure 5] FIG. 10 is a diagram showing a concentration profile of a second semiconductor region of the MOS capacitor according to the second embodiment. [Figure 6] FIG. 10 is a diagram showing the relationship between the capacitance value of a MOS capacitor and the gate voltage dependency. [Figure 7] FIG. 10 is a diagram showing a concentration profile of a second semiconductor region of a MOS capacitor according to the third embodiment. [Figure 8] FIG. 10 is a diagram showing a concentration profile of a second semiconductor region of a MOS capacitor according to the fourth embodiment. [Figure 9] FIG. 13 is a diagram showing a concentration profile of a second semiconductor region of a MOS capacitor according to the fifth embodiment. [Figure 10] FIG. 13 is a cross-sectional view showing the configuration of a MOS capacitor according to a seventh embodiment. [Figure 11] FIG. 13 is a diagram showing a concentration profile of a second semiconductor region of a MOS capacitor according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the accompanying drawings. Features described in each of the following embodiments are exemplary, and not all features are necessarily required. In the following description, similar components in multiple embodiments are denoted by the same or similar reference numerals, and different components will be mainly described. In the following description, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" may not necessarily correspond to the positions and directions in actual implementation. A higher density in one portion than another portion may mean, for example, that the average density of the one portion is higher than the average density of the other portion. Conversely, a lower density in one portion than another portion may mean, for example, that the average density of the one portion is lower than the average density of the other portion.

[0010] <First Embodiment> Fig. 1 is a cross-sectional view showing the configuration of a MOS capacitor, which is a semiconductor device according to Embodiment 1. The MOS capacitor in Fig. 1 includes a first semiconductor region 1, a second semiconductor region 2, a gate insulating film 3 which is an insulating film, a third semiconductor region 4, a field insulating film 5, a conductive film 6, an interlayer insulating film 7, a back gate electrode 8, and a gate electrode 9.

[0011] The first semiconductor region 1, the second semiconductor region 2, and the third semiconductor region 4 are provided in a semiconductor layer. The semiconductor layer may be made of a normal semiconductor wafer or an epitaxially grown layer. The semiconductor layer may be made of normal silicon (Si), or may be made of a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), or diamond. When the semiconductor layer is made of a wide bandgap semiconductor, stable operation under high temperatures and high voltages, and faster switching speeds can be expected. In the following, a configuration in which the conductivity type of the first semiconductor region 1, the second semiconductor region 2, and the third semiconductor region 4 is N-type will be mainly described, but they may also be P-type.

[0012] The second semiconductor region 2 is selectively provided on the upper part of the first semiconductor region 1, for example, by implanting impurities. The N-type impurity concentration of at least a part of the second semiconductor region 2 is higher than the N-type impurity concentration of the first semiconductor region 1. Although a boundary line is shown between the first semiconductor region 1 and the second semiconductor region 2 in FIG. 1, the N-type impurity concentrations of the first semiconductor region 1 and the second semiconductor region 2 near the boundary line may be the same.

[0013] The third semiconductor region 4 is selectively provided on the upper part of the second semiconductor region 2, for example, by implanting impurities. The N-type impurity concentration in at least a part of the third semiconductor region 4 is higher than the N-type impurity concentration of the second semiconductor region 2. Although a boundary line is shown between the second semiconductor region 2 and the third semiconductor region 4 in FIG. 1, the N-type impurity concentrations of the second semiconductor region 2 and the third semiconductor region 4 near the boundary line may be the same.

[0014] The gate insulating film 3 is provided on the second semiconductor region 2. In FIG. 1, the gate insulating film 3 is provided continuously with a field insulating film 5 for electrically isolating elements. The gate insulating film 3 and the field insulating film 5 are formed by, for example, but not limited to, thermal oxidation. The field insulating film 5 is thicker than the gate insulating film 3, and the interface between the second semiconductor region 2 and the gate insulating film 3 is located above the interface between the first semiconductor region 1 and the field insulating film 5.

[0015] The conductive film 6 is provided on a portion of the second semiconductor region 2 where the third semiconductor region 4 is not provided, via the gate insulating film 3. A part of the conductive film 6 is provided on the field insulating film 5. The material of the conductive film 6 is, for example, polysilicon, but is not limited to this.

[0016] The interlayer insulating film 7 is provided on the field insulating film 5 and the conductive film 6. The back gate electrode 8 is connected to the third semiconductor region 4 through a contact hole in the interlayer insulating film 7, and the third semiconductor region 4 reduces the contact resistance between the back gate electrode 8 and the second semiconductor region 2. The gate electrode 9 is connected to the conductive film 6 on the field insulating film 5 through another contact hole in the interlayer insulating film 7. In the following, a configuration in which a gate voltage is applied to the gate electrode 9 as appropriate and the potential of the back gate electrode 8 is a reference potential will be described as an example, but the present invention is not limited to this.

[0017] When a positive gate voltage is applied to the gate electrode 9, positive charges are accumulated in the conductive film 6, and negative charges are accumulated on the surface of the N-type second semiconductor region 2. In this state, almost no depletion layer is formed in the second semiconductor region 2, so the capacitance value C of the MOS capacitance is substantially equal to the gate insulating film capacitance value Cox.

[0018] On the other hand, when a negative gate voltage is applied to the gate electrode 9, negative charges are accumulated in the conductive film 6, and a depletion layer is formed on the surface of the N-type second semiconductor region 2. The width of the depletion layer varies depending on the negative gate voltage, so the depletion layer capacitance Cd of that portion varies depending on the negative gate voltage. This depletion layer capacitance Cd and the gate insulating film capacitance Cox are connected in series, and the capacitance C of the MOS capacitance (composite capacitance C) is expressed by the following equation (1):

[0019] C = 1 / (1 / Cox+1 / Cd) (1) The larger the absolute value of the negative gate voltage, the larger the depletion layer spread and the smaller the depletion layer capacitance Cd. As a result, the depletion layer capacitance Cd has a greater effect on the combined capacitance C, resulting in a greater gate voltage dependency of the combined capacitance C. Increasing the impurity concentration of the second semiconductor region 2 would suppress the spread of the depletion layer, but increasing the impurity concentration would accelerate the oxidation of silicon during thermal oxidation during the formation of the gate insulating film 3, a subsequent process, and would significantly increase the thickness tox of the gate insulating film 3. As the thickness tox increases, the gate insulating film capacitance Cox decreases, resulting in a problem of a smaller combined capacitance C.

[0020] 2 is a diagram showing the relationship between the capacitance value C of the MOS capacitor (composite capacitance value C) and the gate voltage when the N-type second semiconductor region 2 is formed under two implantation conditions with different phosphorus implantation doses. When the phosphorus implantation dose is reduced, the surface concentration of the second semiconductor region 2 decreases, the accelerated oxidation rate during thermal oxidation is suppressed, the thickness tox of the gate insulating film 3 decreases, and the gate insulating film capacitance value Cox increases. Therefore, when the phosphorus implantation dose is small (solid line in FIG. 2), the composite capacitance value C can be made larger than when the phosphorus implantation dose is large (dotted line in FIG. 2).

[0021] However, when the phosphorus concentration in the second semiconductor region 2 decreases, the depletion layer expands as the absolute value of the negative gate voltage increases, and the depletion layer capacitance Cd decreases. As a result, the influence of the depletion layer capacitance Cd on the combined capacitance C when the gate voltage is negative increases, and the gate voltage dependency of the combined capacitance C increases, as shown by the solid line in Figure 2.

[0022] As described above, there is a trade-off between the capacitance value C of the MOS capacitor and the gate voltage dependence of the MOS capacitance with respect to the impurity concentration in the region from the outermost surface of the second semiconductor region 2 to the depth where the depletion layer extends. To improve this trade-off, for example, it is conceivable to increase the impurity concentration to stabilize the gate voltage dependence and compensate for the decrease in the capacitance value of the MOS capacitor by increasing the area of ​​the MOS capacitor. However, this would result in a new problem: the area of ​​the integrated circuit would increase.

[0023] Therefore, in the MOS capacitor according to the first embodiment, in order to improve the above trade-off relationship, the concentration profile of the second semiconductor region 2 is optimized. Fig. 3 is a diagram showing the concentration profile of the second semiconductor region 2 according to the first embodiment.

[0024] The second semiconductor region 2 includes an upper region (the region on the left side of FIG. 3), a middle region (the region in the middle of FIG. 3), and a lower region (the region on the right side of FIG. 3). The middle region is provided deeper than the upper region, and the impurity concentration of the middle region is higher than the impurity concentration of the upper region. The lower region is provided deeper than the middle region, and the impurity concentration of the lower region is lower than the impurity concentration of the middle region, and the impurity concentration of the lower region is constant at a depth of 0.5 μm or more. Here, a constant impurity concentration means, for example, that the local change in the impurity concentration is less than about 10% of the impurity concentration.

[0025] According to the MOS capacitor of the first embodiment, the impurity concentration in the upper region close to the gate insulating film 3 is lower than the impurity concentration in the middle region, thereby suppressing accelerated oxidation. This increases the gate insulating film capacitance Cox, thereby increasing the capacitance C of the MOS capacitor. Meanwhile, the impurity concentration of the entire second semiconductor region 2 can be increased by the impurity concentration in the middle region, thereby suppressing the expansion of the depletion layer and suppressing the gate voltage dependence of the MOS capacitance. This improves the trade-off between the capacitance value of the MOS capacitor and the gate voltage dependence of the MOS capacitance. Note that it is preferable that the concentration of the second semiconductor region 2 is highest in the portion where the depletion layer is formed.

[0026] In the first embodiment, the impurity concentration in the lower region is constant at a depth of 0.5 μm or more. This configuration can improve the trade-off relationship in a configuration in which the thickness of the second semiconductor region 2 is relatively thin, that is, in a configuration in which the trade-off relationship between the capacitance value of the MOS capacitance and the gate voltage dependency of the MOS capacitance becomes particularly pronounced.

[0027] <Embodiment 2> A cross-sectional view showing the configuration of a MOS capacitor, which is a semiconductor device according to the second embodiment, is similar to the cross-sectional view of FIG.

[0028] 4 is a diagram showing the relationship between the capacitance value of the MOS capacitor and the gate voltage dependency. The straight line in FIG. 4 is a line obtained by plotting and connecting values ​​obtained when the impurity concentration (phosphorus concentration) of the second semiconductor region 2, which has a uniform impurity concentration overall, is changed. The trade-off relationship described in the first embodiment holds true on this line.

[0029] Improvement of the trade-off relationship described in the first embodiment corresponds to a progression in the upper left direction in FIG. 4. The triangular points in FIG. 4 are plots of values ​​obtained when the injection acceleration energy is increased relative to the injection acceleration energy used in the MOS capacitor from which the values ​​on the straight line in FIG. 4 were obtained. The triangular points in FIG. 4 are generally located on the upper left side of the straight line, and this result shows that the trade-off relationship can be improved by increasing the injection acceleration energy. The reason for this improvement is thought to be that by increasing the injection acceleration energy, impurities are more easily injected into the middle region of the second semiconductor region 2 than into the upper region, thereby suppressing accelerated oxidation.

[0030] Taking the above into consideration, in the method for manufacturing a MOS capacitor according to the second embodiment, the second semiconductor region 2 is formed by implanting impurities using an implantation acceleration energy with a projected range of 0.2 μm or more and 0.3 μm or less. Also, in the second embodiment, the MOS capacitor is fabricated such that the concentration profile of the second semiconductor region 2 is predominantly determined when the gate insulating film 3 is formed. The fact that the concentration profile of the second semiconductor region 2 is predominantly determined when the gate insulating film 3 is formed means that the concentration profile of the second semiconductor region 2 during the heat treatment included in the process of forming the gate insulating film 3 is substantially the same as the concentration profile when the MOS capacitor is completed. For example, in cases where the MOS capacitor is completed by performing a manufacturing process at a temperature lower than that of the heat treatment after the heat treatment included in the process of forming the gate insulating film 3, the concentration profile of the second semiconductor region 2 is predominantly determined when the gate insulating film 3 is formed.

[0031] 5 is a diagram showing the concentration profile of the second semiconductor region 2 of the MOS capacitor fabricated by the manufacturing method according to the second embodiment. The impurity concentration in the upper part of the upper region is 1.0E17 / cm 3 More than 1.9E19 / cm 3 The impurity concentration of the intermediate region is 1.0E19 / cm 3 at a depth of 0.2 μm or more and 0.3 μm or less from the lower surface of the gate insulating film 3. 3 Higher than 4.0E19 / cm 3The impurity concentration in the lower region is 3.0E15 / cm at a depth of 0.5 μm or more from the lower surface of the gate insulating film 3. 3 More than 1.0E16 / cm 3 With this configuration, it is possible to improve the trade-off between the capacitance value of the MOS capacitor and the gate voltage dependency of the MOS capacitor, as in the first embodiment.

[0032] <Third Embodiment> A cross-sectional view showing the configuration of a MOS capacitor, which is a semiconductor device according to the third embodiment, is similar to the cross-sectional view of FIG.

[0033] 6 is a diagram showing the relationship between the capacitance value of the MOS capacitor and the gate voltage dependency. The straight line in FIG. 6 is a line obtained by plotting and connecting values ​​obtained when the impurity concentration of the second semiconductor region 2, which has a uniform impurity concentration overall, is changed. The trade-off relationship described in the first embodiment also holds true on this line.

[0034] The improvement of the trade-off relationship described in the first embodiment corresponds to moving in the upper left direction in Figure 6. The impurity indicated by the straight line on the lower right side of Figure 6 is phosphorus, and the impurity indicated by the straight line on the upper left side is arsenic. This result shows that when the second semiconductor region 2 is formed by implanting arsenic, which is an impurity with a smaller diffusion coefficient than phosphorus, the trade-off relationship can be improved compared to phosphorus.

[0035] The reason for this improvement is thought to be that arsenic is less likely to diffuse than phosphorus during heat treatment after implantation, making it more difficult for arsenic to reach the upper region of the second semiconductor region 2, thereby suppressing accelerated oxidation. Although not shown, if the conductivity type of the second semiconductor region 2 is p-type, forming the second semiconductor region 2 by implanting BF2, an impurity with a smaller diffusion coefficient than boron, can improve the trade-off relationship compared to boron.

[0036] Taking the above into consideration, in the method for manufacturing a MOS capacitor according to the third embodiment, the second semiconductor region 2 is formed by implanting an impurity having a smaller diffusion coefficient than phosphorus or boron. Also, in the third embodiment, as in the second embodiment, the MOS capacitor is fabricated so that the concentration profile of the second semiconductor region 2 is predominantly determined when the gate insulating film 3 is formed.

[0037] 7 is a diagram showing the concentration profile of the second semiconductor region 2 of the MOS capacitor fabricated by the manufacturing method according to the third embodiment. The impurity concentration in the upper part of the upper region is 1.0E18 / cm 3 More than 1.9E19 / cm 3 The impurity concentration of the intermediate region is 1.0E19 / cm 3 at a depth of 0.2 μm or more and 0.3 μm or less from the lower surface of the gate insulating film 3. 3 Higher than 4.0E19 / cm 3 The impurity concentration in the lower region is 3.0E15 / cm at a depth of 0.5 μm or more from the lower surface of the gate insulating film 3. 3 More than 1.0E16 / cm 3 With this configuration, it is possible to improve the trade-off between the capacitance value of the MOS capacitor and the gate voltage dependency of the MOS capacitor, as in the first embodiment.

[0038] <Fourth Embodiment> A cross-sectional view showing the configuration of a MOS capacitor, which is a semiconductor device according to the fourth embodiment, is similar to the cross-sectional view of FIG.

[0039] The manufacturing method according to the fourth embodiment includes the manufacturing method according to the second embodiment and the manufacturing method according to the third embodiment. That is, in the manufacturing method of the MOS capacitor according to the fourth embodiment, the second semiconductor region 2 is formed by implanting an impurity having a smaller diffusion coefficient than phosphorus or boron, using an implantation acceleration energy with a projected range of 0.2 μm or more and 0.3 μm or less. Also, in the fourth embodiment, as in the second embodiment, the MOS capacitor is fabricated so that the concentration profile of the second semiconductor region 2 is predominantly determined when the gate insulating film 3 is formed.

[0040] 8 is a diagram showing the concentration profile of the second semiconductor region 2 of the MOS capacitor fabricated by the manufacturing method according to the third embodiment. The impurity concentration in the upper part of the upper region is 5.0E16 / cm 3 More than 1.9E19 / cm 3 The impurity concentration of the intermediate region is 1.0E19 / cm 3 at a depth of 0.2 μm or more and 0.3 μm or less from the lower surface of the gate insulating film 3. 3 Higher than 4.0E19 / cm 3 The impurity concentration in the lower region is 3.0E15 / cm at a depth of 0.5 μm or more from the lower surface of the gate insulating film 3. 3 More than 1.0E16 / cm 3 With this configuration, it is possible to improve the trade-off between the capacitance value of the MOS capacitor and the gate voltage dependency of the MOS capacitor, as in the first embodiment.

[0041] <Fifth Embodiment> A cross-sectional view showing the configuration of a MOS capacitor, which is a semiconductor device according to the fifth preferred embodiment, is similar to the cross-sectional view of FIG.

[0042] In the method for manufacturing a MOS capacitor according to the fifth embodiment, the second semiconductor region 2 is formed by implanting impurities with a projected range of 0.2 μm or more and 0.3 μm or less, using different implantation acceleration energies. Also, in the fifth embodiment, as in the second embodiment, the MOS capacitor is fabricated so that the concentration profile of the second semiconductor region 2 is predominantly determined when the gate insulating film 3 is formed.

[0043] 9 is a diagram showing the concentration profile of the second semiconductor region 2 of the MOS capacitor fabricated by the manufacturing method according to the fifth embodiment. The impurity concentration in the upper part of the upper region is 1.0E17 / cm 3 More than 1.9E19 / cm 3 The impurity concentration of the intermediate region is 1.0E19 / cm 3 or less at a depth of 0.05 μm or more and less than 0.5 μm from the lower surface of the gate insulating film 3. 3 Higher than 4.0E19 / cm 3The impurity concentration in the lower region is 3.0E15 / cm at a depth of 0.5 μm or more from the lower surface of the gate insulating film 3. 3 More than 1.0E16 / cm 3 is less than.

[0044] With this configuration, the impurity concentration can be made higher in a relatively deep portion of the second semiconductor region 2 than in the first embodiment. This makes it possible to suppress the expansion of the depletion layer and reduce the gate voltage dependency, thereby further improving the trade-off between the capacitance value of the MOS capacitance and the gate voltage dependency of the MOS capacitance.

[0045] <Sixth Embodiment> A cross-sectional view showing the configuration of a MOS capacitor that is a semiconductor device according to the sixth preferred embodiment is similar to the cross-sectional view of FIG.

[0046] When impurities of different conductivity types are implanted into the same region, the impurity concentrations can be substantially canceled out. Taking advantage of this, in the method for manufacturing a MOS capacitor according to the sixth embodiment, the second semiconductor region 2 is formed by implanting impurities of different conductivity types using an implantation acceleration energy with a projected range of 0.2 μm or more and 0.3 μm or less. For example, after forming an n-type concentration profile with one peak as shown in FIG. 5, p-type impurities are locally implanted into the middle region to form a concentration profile with multiple peaks as shown in FIG. 9.

[0047] Note that if the impurity to be implanted is different, the projected range will be different even if the implantation acceleration energy is the same. Therefore, the implantation acceleration energy may be changed for each impurity to be implanted, or may be constant regardless of the impurity to be implanted. In the sixth embodiment, similar to the second embodiment, the MOS capacitor is fabricated so that the concentration profile of the second semiconductor region 2 is predominantly determined when the gate insulating film 3 is formed.

[0048] According to the sixth embodiment as described above, a concentration profile similar to that of the fifth embodiment can be formed, and therefore, similar to the fifth embodiment, the trade-off between the capacitance value of the MOS capacitance and the gate voltage dependency of the MOS capacitance can be improved.

[0049] <Seventh Embodiment> 10 is a cross-sectional view showing the configuration of a MOS capacitor that is a semiconductor device according to the seventh embodiment. In the seventh embodiment, the gate insulating film 3 is provided on the second semiconductor region 2 via the first semiconductor region 1. The third semiconductor region 4 is also partially provided in the first semiconductor region 1 on the second semiconductor region 2.

[0050] FIG. 11 is a diagram showing a concentration profile of the second semiconductor region 2 of the MOS capacitor according to the seventh embodiment.

[0051] The impurity concentration of the first semiconductor region 1 is 3.0E15 / cm 3 More than 1.0E16 / cm 3 The impurity concentration in the upper part of the upper region of the second semiconductor region 2 is equal to or higher than the impurity concentration in the first semiconductor region 1. The impurity concentration in the middle region is 1.0E19 / cm at a depth of 0.2 μm or more and 0.3 μm or less from the lower surface of the gate insulating film 3. 3 Higher than 4.0E19 / cm 3 The impurity concentration in the lower region is 3.0E15 / cm at a depth of 0.5 μm or more from the lower surface of the gate insulating film 3. 3 More than 1.0E16 / cm 3 is less than.

[0052] According to the seventh embodiment as described above, the capacitance value of the MOS capacitor can be increased by further suppressing the accelerated oxidation, and therefore the trade-off relationship between the capacitance value of the MOS capacitor and the gate voltage dependency of the MOS capacitance can be further improved.

[0053] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more' and 'at least one' can be used interchangeably.

[0054] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0055] Various aspects of the present disclosure are summarized below as appendices.

[0056] (Appendix 1) a first semiconductor region; a second semiconductor region provided above the first semiconductor region, at least a portion of which has an impurity concentration higher than the impurity concentration of the first semiconductor region; an insulating film provided on the second semiconductor region; a conductive film provided on the second semiconductor region via the insulating film; Equipped with The second semiconductor region is The upper region and a middle region that is provided deeper than the upper region and has a higher impurity concentration than the upper region; a lower region that is provided deeper than the middle region, the impurity concentration of which is lower than that of the middle region, and the impurity concentration of which is constant at a depth of 0.5 μm or more; 10. A semiconductor device comprising:

[0057] (Appendix 2) 10. The semiconductor device according to claim 1, The impurity concentration in the upper portion of the upper region is 1.0E17 / cm 3 More than 1.9E19 / cm 3 is as follows: The impurity concentration of the intermediate region is 1.0E19 / cm at a depth of 0.2 μm or more and 0.3 μm or less from the bottom surface of the insulating film. 3 has a peak higher than The impurity concentration in the lower region is 1.0E16 / cm at a depth of 0.5 μm or more from the lower surface of the insulating film. 34. A semiconductor device comprising:

[0058] (Appendix 3) The semiconductor device according to claim 1 or 2, The impurity concentration in the upper portion of the upper region is 1.0E18 / cm 3 More than 1.9E19 / cm 3 is as follows: The impurity concentration of the intermediate region is 1.0E19 / cm at a depth of 0.2 μm or more and 0.3 μm or less from the bottom surface of the insulating film. 3 has a peak higher than The impurity concentration in the lower region is 1.0E16 / cm at a depth of 0.5 μm or more from the lower surface of the insulating film. 3 4. A semiconductor device comprising:

[0059] (Appendix 4) The semiconductor device according to claim 1 or 2, The impurity concentration in the upper portion of the upper region is 1.0E17 / cm 3 More than 1.9E19 / cm 3 is as follows: The impurity concentration of the intermediate region is 1.0E19 / cm at a depth of 0.05 μm or more and less than 0.5 μm from the bottom surface of the insulating film. 3 and having multiple peaks higher than The impurity concentration in the lower region is 1.0E16 / cm at a depth of 0.5 μm or more from the lower surface of the insulating film. 3 4. A semiconductor device comprising:

[0060] (Appendix 5) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 4, The insulating film is The impurity concentration is 1.0E16 / cm 3 provided on the second semiconductor region via the first semiconductor region, the first semiconductor region being less than the impurity concentration in the upper portion of the upper region is equal to or greater than the impurity concentration in the first semiconductor region; The impurity concentration of the intermediate region is 1.0E19 / cm at a depth of 0.2 μm or more and 0.3 μm or less from the bottom surface of the insulating film.3 has a peak higher than The impurity concentration in the lower region is 1.0E16 / cm at a depth of 0.5 μm or more from the lower surface of the insulating film. 3 4. A semiconductor device comprising:

[0061] (Appendix 6) A manufacturing method for manufacturing the semiconductor device according to Supplementary Note 1 or Supplementary Note 2, comprising: forming the second semiconductor region by implanting impurities using an implant acceleration energy having a projected range of 0.2 μm or more and 0.3 μm or less; A method for manufacturing a semiconductor device, wherein the profile of the second semiconductor region is predominantly determined when the insulating film is formed.

[0062] (Appendix 7) A manufacturing method for manufacturing the semiconductor device according to Supplementary Note 1 or Supplementary Note 3, comprising: forming the second semiconductor region by implanting an impurity having a diffusion coefficient smaller than that of phosphorus or boron; A method for manufacturing a semiconductor device, wherein the profile of the second semiconductor region is predominantly determined when the insulating film is formed.

[0063] (Appendix 8) A manufacturing method for manufacturing the semiconductor device according to Supplementary Note 1, comprising: forming the second semiconductor region by implanting an impurity having a diffusion coefficient smaller than that of phosphorus or boron using an implant acceleration energy having a projected range of 0.2 μm or more and 0.3 μm or less; A method for manufacturing a semiconductor device, wherein the profile of the second semiconductor region is predominantly determined when the insulating film is formed.

[0064] (Appendix 9) A manufacturing method for manufacturing the semiconductor device according to Supplementary Note 1 or Supplementary Note 4, comprising: forming the second semiconductor region by implanting impurities with a projected range of 0.2 μm or more and 0.3 μm or less and using different implantation acceleration energies; A method for manufacturing a semiconductor device, wherein the profile of the second semiconductor region is predominantly determined when the insulating film is formed.

[0065] (Appendix 10) A manufacturing method for manufacturing the semiconductor device according to Supplementary Note 1 or Supplementary Note 4, comprising: forming the second semiconductor region by implanting impurities of a different conductivity type using an implant acceleration energy having a projected range of 0.2 μm or more and 0.3 μm or less; A method for manufacturing a semiconductor device, wherein the profile of the second semiconductor region is predominantly determined when the insulating film is formed. [Explanation of symbols]

[0066] 1 first semiconductor region, 2 second semiconductor region, 3 gate insulating film, 6 conductive film.

Claims

1. a first semiconductor region; a second semiconductor region provided above the first semiconductor region, at least a portion of which has an impurity concentration higher than the impurity concentration of the first semiconductor region; an insulating film provided on the second semiconductor region; a conductive film provided on the second semiconductor region via the insulating film; Equipped with The second semiconductor region is The upper region and a middle region that is provided deeper than the upper region and has a higher impurity concentration than the upper region; a lower region that is provided deeper than the middle region, the impurity concentration of which is lower than that of the middle region, and the impurity concentration of which is constant at a depth of 0.5 μm or more; 10. A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, The impurity concentration in the upper portion of the upper region is 1.0E17 / cm ３ More than 1.9E19 / cm ３ is as follows: The impurity concentration of the intermediate region is 1.0E19 / cm at a depth of 0.2 μm or more and 0.3 μm or less from the lower surface of the insulating film. ３ has a peak higher than The impurity concentration in the lower region is 1.0E16 / cm at a depth of 0.5 μm or more from the lower surface of the insulating film. ３ 4. A semiconductor device comprising:

3. 2. The semiconductor device according to claim 1, The impurity concentration in the upper portion of the upper region is 1.0E18 / cm ３ More than 1.9E19 / cm ３ is as follows: The impurity concentration of the intermediate region is 1.0E19 / cm at a depth of 0.2 μm or more and 0.3 μm or less from the lower surface of the insulating film. ３ has a peak higher than The impurity concentration in the lower region is 1.0E16 / cm at a depth of 0.5 μm or more from the lower surface of the insulating film. ３ 4. A semiconductor device comprising:

4. 2. The semiconductor device according to claim 1, The impurity concentration in the upper portion of the upper region is 1.0E17 / cm ３ More than 1.9E19 / cm ３ is as follows: The impurity concentration of the intermediate region is 1.0E19 / cm at a depth of 0.05 μm or more and less than 0.5 μm from the lower surface of the insulating film. ３ and having multiple peaks higher than The impurity concentration in the lower region is 1.0E16 / cm at a depth of 0.5 μm or more from the lower surface of the insulating film. ３ 4. A semiconductor device comprising:

5. 2. The semiconductor device according to claim 1, The insulating film is The impurity concentration is 1.0E16 / cm ３ is provided on the second semiconductor region via the first semiconductor region, the impurity concentration of the upper portion of the upper region is equal to or greater than the impurity concentration of the first semiconductor region; The impurity concentration of the intermediate region is 1.0E19 / cm at a depth of 0.2 μm or more and 0.3 μm or less from the lower surface of the insulating film. ３ has a peak higher than The impurity concentration in the lower region is 1.0E16 / cm at a depth of 0.5 μm or more from the lower surface of the insulating film. ３ 4. A semiconductor device comprising:

6. A method for manufacturing the semiconductor device according to claim 1, comprising: forming the second semiconductor region by implanting impurities using an implantation acceleration energy having a projected range of 0.2 μm or more and 0.3 μm or less; A method for manufacturing a semiconductor device, wherein a profile of the second semiconductor region is predominantly determined when the insulating film is formed.

7. A method for manufacturing the semiconductor device according to claim 1, comprising: forming the second semiconductor region by implanting an impurity having a diffusion coefficient smaller than that of phosphorus or boron; A method for manufacturing a semiconductor device, wherein a profile of the second semiconductor region is predominantly determined when the insulating film is formed.

8. A method for manufacturing the semiconductor device according to claim 1, comprising: forming the second semiconductor region by implanting an impurity having a smaller diffusion coefficient than phosphorus or boron using an implant acceleration energy having a projected range of 0.2 μm or more and 0.3 μm or less; A method for manufacturing a semiconductor device, wherein a profile of the second semiconductor region is predominantly determined when the insulating film is formed.

9. A method for manufacturing the semiconductor device according to claim 1, comprising: forming the second semiconductor region by implanting impurities with a projected range of 0.2 μm or more and 0.3 μm or less and using different implantation acceleration energies; A method for manufacturing a semiconductor device, wherein a profile of the second semiconductor region is predominantly determined when the insulating film is formed.

10. A method for manufacturing the semiconductor device according to claim 1, comprising: forming the second semiconductor region by implanting impurities of a different conductivity type using an implant acceleration energy having a projected range of 0.2 μm or more and 0.3 μm or less; A method for manufacturing a semiconductor device, wherein a profile of the second semiconductor region is predominantly determined when the insulating film is formed.

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