Semiconductor device

Abstract

To obtain a semiconductor device that can be miniaturized.SOLUTION: A semiconductor device according to the present disclosure includes a plurality of semiconductor chips, an IC, a memory, and a plurality of terminals electrically connected to the outside, and the IC includes a drive circuit configured to drive the plurality of semiconductor chips, and a plurality of switches connected to the plurality of terminals and configured to switch the connection destination of the plurality of terminals between the drive circuit and the memory.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent document 1 discloses a semiconductor device that includes a semiconductor chip that is a power chip, an IC (Integrated Circuit) that controls the operation of the semiconductor chip, a control signal terminal that receives a control signal from the semiconductor chip, a recording element, and a communication signal terminal for communicating with the recording element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-57985 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device such as that disclosed in Patent Document 1, it is necessary to provide a communication signal terminal for communicating with the recording element, which may hinder miniaturization of the semiconductor device.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device that can be miniaturized. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a plurality of semiconductor chips, an IC, a memory, and a plurality of terminals electrically connected to the outside, and the IC comprises a drive circuit configured to drive the plurality of semiconductor chips, and a plurality of switches connected to the plurality of terminals and configured to switch the connection destination of the plurality of terminals between the drive circuit and the memory. [Effects of the Invention]

[0007] In the semiconductor device according to the present disclosure, by providing a plurality of switches, it is possible to give two functions to a plurality of terminals, thereby enabling the semiconductor device to be miniaturized. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing a layout of the semiconductor device according to the first embodiment. [Figure 3] FIG. 10 is a circuit diagram of a semiconductor device according to a modification of the first embodiment. [Figure 4] FIG. 10 is a diagram showing a layout of a semiconductor device according to a modification of the first embodiment. [Figure 5] FIG. 10 is a circuit diagram of a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a diagram showing a layout of a semiconductor device according to a second embodiment. [Figure 7] FIG. 10 is a circuit diagram of a semiconductor device according to a third embodiment. [Figure 8] FIG. 10 is a diagram showing a layout of a semiconductor device according to a third embodiment. [Figure 9] FIG. 10 is a circuit diagram of a semiconductor device according to a fourth embodiment. [Figure 10] FIG. 10 is a diagram showing a layout of a semiconductor device according to a fifth embodiment. [Figure 11] FIG. 13 is a circuit diagram of a semiconductor device according to a sixth embodiment. [Figure 12] FIG. 13 is a diagram showing a layout of a semiconductor device according to a sixth embodiment. [Figure 13] FIG. 13 is a plan view of a semiconductor device according to a seventh embodiment. [Figure 14] FIG. 13 is a diagram showing a state in which the semiconductor device according to the seventh embodiment is fixed to a substrate and heat dissipation fins. DETAILED DESCRIPTION OF THE INVENTION

[0009] The semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and the repeated description may be omitted.

[0010] Embodiment 1 FIG. 1 is a circuit diagram of a semiconductor device 100 according to a first embodiment. FIG. 2 is a diagram showing the layout of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 has a P-side high side and an N-side low side. That is, the semiconductor device 100 includes, as the multiple semiconductor chips 10, multiple high-side semiconductor chips 10a and multiple low-side semiconductor chips 10b. The semiconductor chips 10a and 10b are, for example, power chips. In the semiconductor device 100, semiconductor chips 10 corresponding to the U phase, V phase, and W phase are provided on each of the P side and the N side. The semiconductor device 100 is a semiconductor device known as a 6-in-1 or the like.

[0011] The semiconductor device 100 further includes an HVIC 20 configured to drive multiple high-side semiconductor chips 10a, and an LVIC 30 configured to drive multiple low-side semiconductor chips 10b. By dividing the IC into two, the HVIC and the LVIC, the wires connecting the IC to the semiconductor chip 10 can be shortened. Furthermore, the circuit configuration of the semiconductor device 100 can be simplified. The HVIC 20 and the LVIC 30 may be integrated into a single IC. The semiconductor device 100 further includes a memory 40. The memory 40 is, for example, a non-volatile storage element.

[0012] The P terminal is an output power supply terminal 70 for applying power to the semiconductor chips 10a and 10b. The output terminals 72 are outputs of the U-phase, V-phase, and W-phase semiconductor chips 10a and 10b. The output terminals 72 include a U terminal corresponding to the output of the U-phase semiconductor chips 10a and 10b, a V terminal corresponding to the output of the V-phase semiconductor chips 10a and 10b, and a W terminal corresponding to the output of the W-phase semiconductor chips 10a and 10b. The output reference potential terminals 74 are outputs of the U-phase, V-phase, and W-phase semiconductor chips 10a and 10b. The output reference potential terminals 74 include an UN terminal corresponding to the U terminal, a VN terminal corresponding to the V terminal, and a WN terminal corresponding to the W terminal.

[0013] The semiconductor device 100 also includes input signal terminals 50 and 52 for externally inputting input signals that control the drive timing of the semiconductor chips 10a and 10b to the semiconductor device 100. The P-side input signal terminal 50 is provided to correspond to the P-side U-phase, V-phase, and W-phase semiconductor chips 10a and includes a UPIN terminal, a VPIN terminal, and a WPIN terminal that drive and control the semiconductor chip 10a. The input signal terminal 50 corresponds to multiple terminals that are electrically connected to the outside and is configured to receive input signals that drive the multiple semiconductor chips 10a. Similarly, the N-side input signal terminal 52 is provided to correspond to the N-side U-phase, V-phase, and W-phase semiconductor chips 10b and includes a UNIN terminal, a VNIN terminal, and a WNIN terminal that drive and control the semiconductor chip 10b.

[0014] The semiconductor device 100 also includes control power supply terminals 54 and 56 for applying control power necessary to drive the semiconductor chips 10a and 10b. The control power supply terminal 54 includes a VDH terminal for applying power to the HVIC 20, and a UVFB terminal, a VVFB terminal, and a WVFB terminal for applying drive voltages to the P-side U-phase, V-phase, and W-phase semiconductor chips 10a, respectively. The control power supply terminal 56 includes a VDL terminal for applying power to the LVIC 30. The semiconductor device 100 also includes control reference potential terminals 55 and 60 corresponding to the control power supply terminals 54 and 56. The control reference potential terminals 55 and 60 include GND terminals corresponding to the VDH and VDL terminals, a UVFS terminal corresponding to the UVFB terminal, a VVFS terminal corresponding to the VVFB terminal, and a WVFS terminal corresponding to the WVFB terminal. The potential difference between a control power supply terminal and the corresponding control reference potential terminal is defined as a control power supply voltage. For example, the drive voltage of the P-side U-phase semiconductor chip 10a, which is one of the control power supply voltages, is a voltage obtained by subtracting the potential of the UVFS terminal from the potential of the UVFB terminal.

[0015] The semiconductor device 100 also includes a VDM terminal, which is a power supply terminal 58 that applies power to the memory 40. The VDM terminal and a GND terminal are connected to the memory 40. Furthermore, a UPIN terminal, a VPIN terminal, and a WPIN terminal, which are P-side input signal terminals 50, are connected to the memory 40 via a changeover switch 22, which will be described later.

[0016] Next, we will explain the internal configuration of the HVIC 20. The HVIC 20 has a drive circuit 24 configured to drive multiple semiconductor chips 10a. The drive circuit 24 controls the multiple semiconductor chips 10a in response to signals input from an input signal terminal 50 via a selector switch 22.

[0017] The changeover switch 22 has a plurality of switches 22u, 22v, and 22w connected to a plurality of input signal terminals 50. The plurality of switches 22u, 22v, and 22w are provided to correspond to the plurality of input signal terminals 50. The plurality of switches 22u, 22v, and 22w are configured to switch the connection destination of the plurality of input signal terminals 50 between the drive circuit 24 and the memory 40. The HVIC 20 also has a control circuit 26 configured to control the plurality of switches 22u, 22v, and 22w.

[0018] The changeover switch 22 can change over the connection destination of the input signal terminal 50 between the drive circuit 24 and the memory 40 under any condition. The changeover switch 22 is controlled by the control circuit .

[0019] The internal configuration of the LVIC 30 is the same as that of the HVIC 20, except that the selector switch 22 and the control circuit 26 are not provided. The LVIC 30 includes a drive circuit 34 configured to drive the multiple semiconductor chips 10b. The drive circuit 34 controls the multiple semiconductor chips 10b in response to signals input from the input signal terminal 52.

[0020] Next, an example of a condition for switching the connection destination of the input signal terminal 50 will be described. The control circuit 26 may switch the connection destination of the input signal terminal 50 according to the control power supply voltage. Hereinafter, the control power supply voltage used to switch the connection destination of the changeover switch 22 may be referred to as the switching voltage. In other words, the switching voltage may be any voltage at the control power supply terminals 54, 56 configured to input a control power supply voltage for driving one of the multiple semiconductor chips 10a, 10b. Specifically, the voltage at the VDH terminal, VDL terminal, UVFB terminal, VVFB terminal, or WVFB terminal can be used as the switching voltage.

[0021] For example, the switches 22u, 22v, and 22w are connected to the drive circuit 24 when the switching voltage is equal to or higher than a predetermined first voltage, and are connected to the memory 40 when the switching voltage is lower than the first voltage. At this time, the control circuit 26 reads the switching voltage and a first voltage that is predetermined and stored in the control circuit 26, the HVIC 20, the semiconductor device 100, or the like. The control circuit 26 determines whether to connect to the memory 40 or the drive circuit 24 depending on the comparison result between the switching voltage and the first voltage.

[0022] Furthermore, a second voltage lower than the first voltage may be stored in advance in the control circuit 26, the HVIC 20, the semiconductor device 100, or the like. In this case, when the switching voltage is less than the predetermined second voltage, data is read from the memory 40 through one of the plurality of input signal terminals 50. When the switching voltage is less than the first voltage and equal to or greater than the second voltage, data is written to the memory 40 through one of the plurality of input signal terminals 50. In this way, the control circuit 26 may switch the mode of the memory 40 between read and write depending on the result of comparing the switching voltage and the second voltage.

[0023] For example, a case will be described where the first voltage is 5.0V and the second voltage is 3.0V. In this case, when the control power supply voltage is less than 3.0V, the multiple switches 22u, 22v, and 22w are connected to the memory 40, and the memory 40 is in read mode. When the control power supply voltage is 3.0 to 5.0V, the multiple switches 22u, 22v, and 22w are connected to the memory 40, and the memory 40 is in write mode. When the control power supply voltage is 5.0V or higher, the multiple switches 22u, 22v, and 22w are connected to the drive circuit 24.

[0024] The first voltage is preferably lower than the threshold voltage of the semiconductor chips 10a and 10b. It is generally recommended that semiconductor chips be used with a control power supply of around 15V. Therefore, by setting the first and second voltages lower than the threshold voltage, e.g., 5.0V and 3.0V, the connection of the selector switch 22 to the memory 40 when the control power supply voltage is less than 5.0V, at which the semiconductor chips 10a and 10b are not driven. Furthermore, when the control power supply voltage is ≥ 5V, at which the semiconductor chips 10a and 10b may be driven, the connection of the selector switch 22 to the drive circuit 24. This allows the input signal terminal 50 to be used for reading or writing from or to the memory 40 when the semiconductor chips 10a and 10b are not expected to be driven.

[0025] The above-mentioned conditions for switching the connection destination of the input signal terminal 50 are merely examples, and the connection destination of the input signal terminal 50 may be switched under any conditions.

[0026] As described above, according to this embodiment, by providing the changeover switch 22, it is possible to give two functions to the plurality of input signal terminals 50. That is, it is possible to give the input signal terminals 50 the function of controlling the timing of driving the semiconductor chip 10a and the function of functioning as a terminal for communication with the memory 40. Therefore, it is not necessary to provide a terminal dedicated to communication with the memory 40. Therefore, it is possible to miniaturize the semiconductor device 100.

[0027] In this embodiment, the switches 22u, 22v, and 22w for the U, V, and W phases basically operate in conjunction with each other. That is, the state of the changeover switch 22 is either that all of the switches 22u, 22v, and 22w are connected to the drive circuit 24 or that all of the switches 22u, 22v, and 22w are connected to the memory 40.

[0028] On the other hand, nonvolatile memories generally require two communication terminals: a terminal for writing and a terminal for reading. Therefore, if at least two of the input signal terminals 50 are connected to the memory 40, communication with the memory 40 is possible. Therefore, as a modification of this embodiment, two of the input signal terminals 50 may be connected to the memory 40, and one may be connected to the drive circuit 24. For example, the U phase and the V phase may be connected to the memory 40, and the W phase may be connected to the drive circuit 24.

[0029] In this case, too, there is no problem as long as the condition for connecting the changeover switch 22 to the memory 40 is set as a condition for not driving the semiconductor chip 10a. In other words, for example, even if the U-phase and V-phase are connected to the memory 40 and only the W-phase is connected to the drive circuit 24, the W-phase semiconductor chip 10a will not be driven. Therefore, there is no problem even if the memory 40 is connected to only two input signal terminals 50.

[0030] FIG. 3 is a circuit diagram of a semiconductor device 200 according to a modification of the first embodiment. FIG. 4 is a diagram showing a layout of the semiconductor device 200 according to a modification of the first embodiment. The changeover switch 22 may have only two switches 22u and 22v configured to switch the connection destination of the input signal terminal 50 between the drive circuit 24 and the memory 40. In the example of FIGS. 3 and 4, the switches 22u and 22v are provided for the U phase and the V phase, and the input signal terminal 51 of the W phase is directly connected to the drive circuit 24. As described above, even in such a configuration, there is no problem as long as the condition for connecting the changeover switch 22 to the memory 40 is set as the condition for the semiconductor chip 10a not to be driven.

[0031] Furthermore, the terminal connected to the changeover switch 22 is not limited to the input signal terminal 52. Another terminal provided on the semiconductor device 100 may be connected to the changeover switch 22 to have the function of a communication terminal with the memory 40.

[0032] 2 shows an example in which an IGBT (Insulated Gate Bipolar Transistor) 11 and a diode 12 are provided as separate chips as the semiconductor chip 10 for each phase. However, the semiconductor chip 10 is not limited to this, and may be an RC-IGBT (Reverse Conducting IGBT) in which the IGBT and the diode are integrated into the same chip. Note that any semiconductor chip driven by an IC can be used as the semiconductor chip 10.

[0033] Furthermore, the configuration of the semiconductor device 100 is not limited to that described in this embodiment. Any semiconductor device including a semiconductor chip, an IC for driving the semiconductor chip, and a memory can be used as the semiconductor device 100.

[0034] The semiconductor chip 10 may be formed of a wide bandgap semiconductor. The wide bandgap semiconductor may be silicon carbide, a gallium nitride-based material, or diamond. A switching element or diode formed of a wide bandgap semiconductor has high voltage resistance and a high allowable current density. Therefore, the semiconductor device 100 can be further miniaturized.

[0035] The functions of the changeover switch 22, the drive circuit 24, and the control circuit 26 can be realized by one or more arithmetic units. Each arithmetic unit may be dedicated hardware. Alternatively, the arithmetic unit may be a CPU (Central Processing Unit) that executes a program stored in a memory. The CPU may be a central processing unit, processing unit, microprocessor, microcomputer, processor, or DSP (Digital Signal Processor). The memory in which the program is stored may be memory 40, or may be provided separately from memory 40.

[0036] When the arithmetic device is dedicated hardware, the arithmetic device may be, for example, a single circuit, a composite circuit, a programmed processor, or a parallel programmed processor. The arithmetic device may also be an ASIC (Application Specific Integrated Circuit) or an FPGA (Field-Programmable Gate Array). The arithmetic device may also be a combination of these. The functions of each of the selector switch 22, the drive circuit 24, and the control circuit 26 may each be realized by a separate arithmetic device. The functions of each of the parts may also be realized together by a single arithmetic device.

[0037] When the arithmetic unit is a CPU, the functions of the selector switch 22, the drive circuit 24, and the control circuit 26 are realized by software, firmware, or a combination of software and firmware. The software and firmware are written as programs and stored in memory. The arithmetic unit realizes the functions of each part by reading and executing the programs stored in memory.

[0038] That is, the memory stores a program for switching the connection destination of the multiple input signal terminals 50 between the drive circuit 24 and the memory 40, a program for driving the multiple semiconductor chips 10a, and a program for communicating with the memory 40. It can also be said that these programs cause the computer to execute the procedures or methods of the changeover switch 22, the drive circuit 24, and the control circuit 26.

[0039] Here, the memory in which the program is stored may be a non-volatile or volatile semiconductor memory such as RAM, ROM, flash memory, EPROM, or EEPROM. The memory may be a magnetic disk, flexible disk, optical disk, compact disk, minidisk, DVD, or the like. RAM is an abbreviation for Random Access Memory. ROM is an abbreviation for Read Only Memory. EPROM is an abbreviation for Erasable Programmable Read Only Memory. EEPROM is an abbreviation for Electrically Erasable Programmable Read-Only Memory. Multiple memories may be provided.

[0040] It is also possible to realize some of the functions of the selector switch 22, the drive circuit 24, and the control circuit 26 with dedicated hardware and some with software or firmware. In this way, the computing device can realize each of the above-mentioned functions with hardware, software, firmware, or a combination of these.

[0041] The above-described modifications can be applied as appropriate to the semiconductor devices according to the following embodiments. Note that the semiconductor devices according to the following embodiments have many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0042] Embodiment 2 Fig. 5 is a circuit diagram of a semiconductor device 300 according to the second embodiment. Fig. 6 is a diagram showing the layout of the semiconductor device 300 according to the second embodiment. This embodiment differs from the first embodiment in that the memory 40 is configured to receive power from the HVIC 20. Other configurations are the same as those of the first embodiment.

[0043] The HVIC 20 has a VRGH terminal, which is an IC internal power supply terminal 358. The memory 40 is supplied with power from the internal power supply of the HVIC 20 via the IC internal power supply terminal 358. This eliminates the need for a power supply terminal 58 for the memory 40, and allows the memory 40 to be mounted with the existing terminal configuration. In addition, the semiconductor device 300 can be further miniaturized.

[0044] Embodiment 3 Fig. 7 is a circuit diagram of a semiconductor device 400 according to embodiment 3. Fig. 8 is a diagram showing the layout of the semiconductor device 400 according to embodiment 3. This embodiment differs from embodiment 1 in that a changeover switch 432 is mounted on the LVIC 430.

[0045] The changeover switch 432 has a plurality of switches 432u, 432v, and 432w connected to a plurality of input signal terminals 52. The plurality of switches 432u, 432v, and 432w are provided to correspond to the plurality of input signal terminals 52. The plurality of switches 432u, 432v, and 432w are configured to switch the connection destination of the plurality of input signal terminals 52 between the drive circuit 34 and the memory 40. The LVIC 30 also has a control circuit 436 configured to control the plurality of switches 432u, 432v, and 432w.

[0046] The changeover switch 432 can switch the connection destination of the input signal terminal 52 between the drive circuit 34 and the memory 40 under any condition. Such control of the changeover switch 432 is executed by a control circuit 436. The same conditions as those in the first embodiment can be used as the conditions for switching the changeover switch 432. Also in this embodiment, the memory 40 may be supplied with power from the LVIC 430.

[0047] The internal configuration of the HVIC 420 is the same as that of the HVIC 20, except that the changeover switch 22 and the control circuit 26 are not provided.

[0048] In this way, the IC equipped with the changeover switch may be either an HVIC or an LVIC. Note that, in this embodiment, it is sufficient that at least two terminals of the input signal terminals 52 are connected to the memory 40 via the switch.

[0049] Embodiment 4 9 is a circuit diagram of a semiconductor device 500 according to a fourth embodiment. This embodiment differs from the first embodiment in that both the HVIC 20 and the LVIC 430 are equipped with changeover switches 22, 432. The semiconductor device 500 also includes two memories 40. The memories 40 are connected to the HVIC 20 and the LVIC 430, respectively.

[0050] The changeover switch 22 of the HVIC 20 and the changeover switch 432 of the LVIC 430 operate in conjunction with each other. That is, the switches 22u, 22v, 22w, 432u, 432v, and 432w are either all connected to the drive circuits 24 and 34, or all connected to the memory 40. In this embodiment, it is sufficient that at least two of the input signal terminals 50 are connected to the memory 40 via a switch, and it is sufficient that at least two of the input signal terminals 52 are connected to the memory 40 via a switch.

[0051] Also, one memory 40 may be provided that is common to the HVIC 20 and the LVIC 430. Also in this embodiment, the memory 40 may be supplied with power from the corresponding IC.

[0052] Embodiment 5. 10 is a diagram showing the layout of a semiconductor device 600 according to embodiment 5. Multiple memories 40 may be located between the HVIC 20 and the LVIC 430. The same applies to the case where there is only one memory 40 as in embodiments 1 to 3.

[0053] When the terminals for connection to the HVIC 20 or the LVIC 430 are also used as communication terminals for the memory 40, the optimum location for the memory 40 is between the HVIC 20 and the LVIC 430. This allows the semiconductor device 600 to be further miniaturized.

[0054] Embodiment 6 11 is a circuit diagram of a semiconductor device 700 according to a sixth embodiment. FIG. 12 is a diagram showing the layout of the semiconductor device 700 according to the sixth embodiment. This embodiment differs from the fourth embodiment in that a memory 740 is built into the HVIC 720 and the LVIC 730. The configurations of the HVIC 720 and the LVIC 730 are the same as those of the HVIC 20 and the LVIC 430, except that the memory 740 is built into them. This allows the semiconductor device 700 to be further miniaturized.

[0055] In addition, in the first to third embodiments, the memory 40 may be built into a corresponding IC.

[0056] Embodiment 7 Fig. 13 is a plan view of a semiconductor device 800 according to the seventh embodiment. Fig. 14 is a diagram showing a state in which the semiconductor device 800 according to the seventh embodiment is fixed to a substrate 805 and heat dissipation fins 806. The semiconductor device 800 has a printed portion 803 on the back surface of a package 802 on which a product model name and lot information are printed. Terminals 801 are provided on both sides of the package 802. The terminals 801 are terminals of the semiconductor device 100 shown in Fig. 2 etc.

[0057] In an actual use environment, the semiconductor device 800 is attached to a substrate 805 and heat dissipation fins 806 for use. In this case, a printed portion 803 may be provided on the back surface of the package to which the substrate 805 or the heat dissipation fins 806 is in close contact. Therefore, to check the product model name or lot information of the semiconductor device 800 in an actual use environment, it is necessary to remove the semiconductor device 800 from the substrate 805 or the heat dissipation fins 806 and check the printed portion 803. However, the substrate 805 and the heat dissipation fins 806 are often fixed by screws or soldering. Therefore, it is not easy to remove the substrate 805 and the heat dissipation fins 806. This has led to a problem in that it is not easy to check the product model name and lot information in an actual use environment.

[0058] In contrast, the memory 40 of this embodiment stores product information about the semiconductor device 800. The product information includes the product model name, lot information, and final inspection data before shipping. The product information may be any one of these, or a combination thereof. This allows the product information about the semiconductor device 800 to be confirmed from the input signal terminal 50 or the input signal terminal 52. This eliminates the need to remove the semiconductor device 800 from the substrate 805 or the heat dissipation fin 806. This makes it easy to confirm the product information in the actual usage environment of the semiconductor device 800. Furthermore, any product information can be confirmed at the customer's site, improving the convenience of the semiconductor device 800.

[0059] The technical features described in each embodiment may be used in appropriate combination.

[0060] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) a plurality of semiconductor chips; IC and Memory and a plurality of terminals electrically connected to the outside; Equipped with The IC is a drive circuit configured to drive the plurality of semiconductor chips; a plurality of switches connected to the plurality of terminals and configured to switch the connection destinations of the plurality of terminals between the drive circuit and the memory; A semiconductor device comprising: (Appendix 2) 2. The semiconductor device according to claim 1, wherein the plurality of terminals are configured to receive input signals for driving the plurality of semiconductor chips. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the IC includes a control circuit configured to control the plurality of switches. (Appendix 4) a control power supply terminal configured to receive a control power supply voltage for driving any one of the plurality of semiconductor chips; The semiconductor device described in any one of appendixes 1 to 3, characterized in that the plurality of switches are connected to the drive circuit when the voltage of the control power terminal is equal to or higher than a predetermined first voltage, and are connected to the memory when the voltage of the control power terminal is less than the first voltage. (Appendix 5) 5. The semiconductor device according to claim 4, wherein the first voltage is lower than a threshold voltage of the semiconductor chip. (Appendix 6) When the voltage of the control power supply terminal is lower than a predetermined second voltage that is lower than the first voltage, data of the memory is read from any one of the plurality of terminals; The semiconductor device described in Appendix 4 or 5, characterized in that when the voltage of the control power supply terminal is less than the first voltage and greater than or equal to the second voltage, data is written to the memory from any one of the plurality of terminals. (Appendix 7) 7. The semiconductor device according to claim 1, wherein the memory is configured to receive power from the IC. (Appendix 8) A plurality of high-side semiconductor chips; A plurality of low-side semiconductor chips; an HVIC configured to drive the high-side semiconductor chips; an LVIC configured to drive the low-side semiconductor chips; Equipped with 8. The semiconductor device according to claim 1, wherein the IC is either the HVIC or the LVIC. (Appendix 9) the plurality of high-side semiconductor chips; the plurality of low-side semiconductor chips; an HVIC provided as the IC on the high side; an LVIC provided as the IC on the low side; 8. The semiconductor device according to claim 1, further comprising: (Appendix 10) 10. The semiconductor device according to claim 8, wherein the memory is located between the HVIC and the LVIC. (Appendix 11) 10. The semiconductor device according to any one of claims 1 to 9, wherein the memory is built into the IC. (Appendix 12) 12. The semiconductor device according to any one of claims 1 to 11, wherein the memory stores product information of the semiconductor device. (Appendix 13) 13. The semiconductor device according to any one of claims 1 to 12, wherein the semiconductor chip is formed of a wide bandgap semiconductor. (Appendix 14) 14. The semiconductor device according to claim 13, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond. [Explanation of symbols]

[0061] 10, 10a, 10b semiconductor chip, 11 IGBT, 12 diode, 22 changeover switch, 22u, 22v, 22w switch, 24 drive circuit, 26 control circuit, 34 drive circuit, 40 memory, 50, 51, 52 input signal terminal, 54 control power supply terminal, 55 control reference potential terminal, 56 control power supply terminal, 58 power supply terminal, 60 control reference potential terminal, 70 output power supply terminal, 72 output terminal, 74 output reference potential terminal, 100, 200, 300, 358 IC internal power supply terminal, 400 semiconductor device, 432 changeover switch, 432u, 432v, 432w switch, 436 control circuit, 500, 600, 700 semiconductor device, 740 memory, 800 semiconductor device, 801 terminal, 802 package, 803 printed portion, 805 substrate, 806 Heat dissipation fin

Claims

1. a plurality of semiconductor chips; IC and Memory and a plurality of terminals electrically connected to the outside; Equipped with The IC is a drive circuit configured to drive the plurality of semiconductor chips; a plurality of switches connected to the plurality of terminals and configured to switch the connection destinations of the plurality of terminals between the drive circuit and the memory; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the plurality of terminals are configured to receive input signals for driving the plurality of semiconductor chips.

3. 3. The semiconductor device according to claim 1, wherein the IC includes a control circuit configured to control the plurality of switches.

4. a control power supply terminal configured to receive a control power supply voltage for driving any one of the plurality of semiconductor chips; 3. The semiconductor device according to claim 1, wherein the plurality of switches are connected to the drive circuit when the voltage of the control power supply terminal is equal to or higher than a predetermined first voltage, and are connected to the memory when the voltage of the control power supply terminal is less than the first voltage.

5. 5. The semiconductor device according to claim 4, wherein the first voltage is lower than a threshold voltage of the semiconductor chip.

6. When the voltage of the control power supply terminal is lower than a predetermined second voltage that is lower than the first voltage, data of the memory is read from any one of the plurality of terminals; 5. The semiconductor device according to claim 4, wherein when the voltage of the control power supply terminal is lower than the first voltage and higher than or equal to the second voltage, data is written to the memory from any one of the plurality of terminals.

7. 3. The semiconductor device according to claim 1, wherein the memory is configured so that power is supplied from the IC.

8. A plurality of high-side semiconductor chips; A plurality of low-side semiconductor chips; an HVIC configured to drive the high-side semiconductor chips; an LVIC configured to drive the plurality of low-side semiconductor chips; Equipped with 3. The semiconductor device according to claim 1, wherein the IC is either the HVIC or the LVIC.

9. the plurality of high-side semiconductor chips; the plurality of low-side semiconductor chips; an HVIC provided as the IC on the high side; an LVIC provided as the IC on the low side; 3. The semiconductor device according to claim 1, further comprising:

10. 9. The semiconductor device according to claim 8, wherein the memory is located between the HVIC and the LVIC.

11. 10. The semiconductor device according to claim 9, wherein the memory is located between the HVIC and the LVIC.

12. 3. The semiconductor device according to claim 1, wherein the memory is built into the IC.

13. 3. The semiconductor device according to claim 1, wherein the memory stores product information of the semiconductor device.

14. 3. The semiconductor device according to claim 1, wherein the semiconductor chip is made of a wide bandgap semiconductor.

15. 15. The semiconductor device according to claim 14, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

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