Selective alteration of interconnect pads for direct bonding

Abstract

To provide selective alteration of interconnect pads for direct bonding.SOLUTION: A bonded structure and a method of forming such a bonded structure are disclosed. The bonded structure can include a first element and a second element. The first element has a first bonding surface, which includes a first nonconductive material and a plurality of first contact pads. The first contact pads are electrically connected to one or more first microelectronic devices in the first element. The second element has a second bonding surface, which includes a second nonconductive material and a plurality of second contact pads. The second contact pads are electrically connected to one or more second microelectronic devices in the second element. The second bonding surface is directly bonded to the first bonding surface without an intervening adhesive to form a bonding interface, and one or more first contact pads are omitted from the first microelectronic element to alter the functionality of the bonded structure.SELECTED DRAWING: Figure 3B

Description

[Technical Field]

[0001] [Incorporation by reference to any priority application] This application claims priority to U.S. Provisional Patent Application No. 62 / 970,458, filed February 5, 2020, the entire contents of which are hereby incorporated by reference in their entirety and for all purposes.

[0002] The field of the invention relates to bonded semiconductor devices and methods for forming same. [Background technology]

[0003] Semiconductor elements, such as integrated device dies, can be stacked on top of each other to perform specific functions. For example, contact pads on each of two integrated device dies can be electrically connected to each other by solder balls. The contact pads can be connected to active circuitry within the respective integrated device die. In each of the integrated device dies, the contact pads can be positioned to make electrical connections between selected active circuitry within the die to perform specific functions. That is, in a stacked and electrically connected structure, connections between the contact pads can enable desired functionality of the electronic device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 9,564,414 [Patent Document 2] U.S. Patent No. 9,391,143 [Patent Document 3] U.S. Patent No. 10,434,749 [Patent Document 4] U.S. Patent No. 9,716,033 [Patent Document 5] U.S. Patent No. 9,852,988 [Patent Document 6] US Patent Application Publication No. 2019 / 0096741 Summary of the Invention [Means for solving the problem]

[0005] A bonding structure is disclosed in one embodiment, comprising: a first element having a first bonding surface comprising a first non-conductive material and a plurality of first contact pads, the first contact pads electrically connected to one or more first microelectronic devices within the first element; and a second element having a second bonding surface comprising a second non-conductive material and a plurality of second contact pads, the second contact pads electrically connected to one or more second microelectronic devices within the second element, the second bonding surface bonded directly to the first bonding surface without an intervening adhesive to form a bonding interface, and one or more of the first contact pads being removed from the first microelectronic element to modify the functionality of the bonding structure.

[0006] In some embodiments, the joining structure further includes a deletion contactpad region where one or more first contact pads are deleted, and traces extending between the at least one first microelectronic device and the deletion contactpad region. In some embodiments, the deletion contactpad region includes one or more voids within the first non-conductive material. In some embodiments, the deletion contactpad region includes a solid non-conductive filler material disposed in the one or more voids, with an interface disposed between the solid non-conductive filler material and the first non-conductive material. In some embodiments, the deletion contactpad region includes a complete deletion contactpad region lacking a contact pad. In some embodiments, the first non-conductive material extends continuously within the deletion contactpad region. In some embodiments, the deletion contactpad region includes a partial deletion contactpad region including a remaining portion of the deletion contact pad and a void above the remaining portion. In some embodiments, the joining structure further includes a solid non-conductive filler material in the voids. In some embodiments, the plurality of first contact pads are directly bonded to a second plurality of second contact pads, and the bonding structure includes a plurality of traces extending between the plurality of first microelectronic devices and the plurality of first contact pads. In some embodiments, the traces have termination ends that terminate in the removed contact pad areas. In some embodiments, the first element includes a bulk semiconductor portion and a die bond pad formed in or on the semiconductor portion, a first non-conductive material is disposed on the bulk semiconductor portion, and the termination ends of the traces include the die bond pad of the first element. In some embodiments, the first element includes a bulk semiconductor portion, a first non-conductive material is disposed on the bulk semiconductor portion, and the termination ends of the traces extend into the first non-conductive material. In some embodiments, the bonding structure further includes redistribution metallization extending laterally within the first non-conductive material, and the termination ends of the traces include ends of the redistribution metallization. In some embodiments, the traces are connected to electrical ground. In some embodiments, one or more second contact pads are deleted from the second microelectronic element, and the deleted second contact pads are aligned with the deleted first contact pads.In some embodiments, the plurality of first contact pads are arranged in a regular pattern when viewed from a bottom perspective, apart from one or more removed first contact pads. In some embodiments, the removed contact pad area includes a barrier layer disposed on the first non-conductive material, with rounded or angled surfaces of the first non-conductive material extending between the barrier layer and the bonding interface.

[0007] In another embodiment, the bonding structure includes a first element having a first bonding surface including a first non-conductive material and a plurality of first contact pads, the first contact pads electrically connected to one or more first microelectronic devices within the first element by one or more first traces; and a second element having a second bonding surface including a second non-conductive material and a plurality of second contact pads, the second contact pads electrically connected to one or more second microelectronic devices within the second element by one or more second traces, the second bonding surface bonded directly to the first bonding surface without an intervening adhesive to form a bonding interface, and at least one first trace extending between the at least one first microelectronic device and a removed contact pad area at the bonding interface.

[0008] In some embodiments, the deletion contact pad region includes one or more voids within the first non-conductive material. In some embodiments, the deletion contact pad region includes a solid non-conductive filler material disposed in the one or more voids, with an interface disposed between the solid non-conductive filler material and the first non-conductive material. In some embodiments, the deletion contact pad region includes a complete deletion contact pad region lacking a contact pad. In some embodiments, the first non-conductive material extends continuously within the deletion contact pad region.

[0009] Also disclosed is a method of forming a bonding structure. In one embodiment, the method includes the steps of: directly bonding a first bonding material of a first element to a second non-conductive material of a second element without an intervening adhesive to form a bonding interface; directly contacting a plurality of first contact pads of the first element to a plurality of second contact pads of the second element, wherein the first conductive contact pads are electrically connected to one or more first microelectronic devices within the first element and the second contact pads are electrically connected to one or more second microelectronic devices within the second element; and removing one or more of the first contact pads from the first microelectronic element to modify the functionality of the bonding structure.

[0010] In some embodiments, removing one or more first contact pads comprises forming one or more first contact pads and at least partially removing one or more first contact pads prior to the direct bonding step. In some embodiments, at least partially removing comprises completely removing one or more first contact pads. In some embodiments, at least partially removing comprises partially removing one or more first contact pads. In some embodiments, the method further comprises providing a solid filler material to voids formed by the at least partially removing step. In some embodiments, removing one or more first contact pads comprises selectively forming a plurality of first contact pads to remove one or more first contact pads to modify functionality of the bonded first and second elements. In some embodiments, directly bonding comprises directly bonding a first wafer including the first elements to a second wafer including the second elements. In some embodiments, the directly bonding step includes directly bonding a first die including the first element to a second die including the second element. In some embodiments, the directly bonding step includes directly bonding a die including the first element to a wafer including the second element. In some embodiments, the method further includes removing the barrier layer in deleted contact pad areas where one or more first contact pads have been deleted. In some embodiments, removing the barrier layer includes forming a rounded or angled surface in the first non-conductive material between the barrier layer and the bonding interface. In some embodiments, the one or more deleted first contact pads are varied based on test data.

[0011] In yet another embodiment, the bonding structure includes a bonding surface having a plurality of wafer test pad locations, and all or a portion of the metallization at the wafer test pad locations is removed to recess the portions from the bonding surface. In some embodiments, the bonding surface includes a non-conductive material, and the portions of the metallization at the wafer test pad locations are recessed from a top surface of the non-conductive material.

[0012] Specific implementations will now be described with reference to the following drawings, which are provided by way of example and not limitation. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional side view of semiconductor elements to be bonded directly to one another without an intervening adhesive. [Figure 2] 1 is a schematic cross-sectional side view of a semiconductor device including contact pads that have been modified or removed prior to being directly bonded to one another in accordance with an embodiment. [Figure 3A] 1A-1C are schematic cross-sectional side views of various configurations of a bonding structure including two directly bonded semiconductor elements. [Figure 3B] 1A-1C are schematic cross-sectional side views of various configurations of a bonding structure including two directly bonded semiconductor elements. [Figure 3C] 1A-1C are schematic cross-sectional side views of various configurations of a bonding structure including two directly bonded semiconductor elements. [Figure 3D] 1A-1C are schematic cross-sectional side views of various configurations of a bonding structure including two directly bonded semiconductor elements. [Figure 4] 1 is a schematic cross-sectional side view of a portion of a semiconductor device according to an embodiment. [Figure 5A] 1 is a schematic cross-sectional side view of a semiconductor element that can be directly bonded according to an embodiment. [Figure 5B] 1 is a schematic cross-sectional side view of a semiconductor element that can be directly bonded according to an embodiment. [Figure 6A] 1A-1D are schematic cross-sectional side views of various embodiments of bonding structures including two directly bonded semiconductor elements. [Figure 6B] 1A-1D are schematic cross-sectional side views of various embodiments of bonding structures including two directly bonded semiconductor elements. [Figure 6C] 1A-1D are schematic cross-sectional side views of various embodiments of bonding structures including two directly bonded semiconductor elements. [Figure 6D] 1A-1D are schematic cross-sectional side views of various embodiments of bonding structures including two directly bonded semiconductor elements. [Figure 7A]1A-1C are schematic bottom views of semiconductor devices having different contact pad patterns. [Figure 7B] 1A-1C are schematic bottom views of semiconductor devices having different contact pad patterns. [Figure 7C] 1A-1C are schematic bottom views of semiconductor devices having different contact pad patterns. [Figure 8] FIG. 1 is a schematic system diagram illustrating an electronic system that can include one or more junction structures according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0014] Microelectronic devices, such as active circuits on semiconductor elements, can have many different functionalities depending on which components of the circuit are enabled. As described herein, two or more elements (e.g., semiconductor elements) can be directly bonded to each other and stacked without an intervening adhesive. For example, the non-conductive bonding surfaces of each of the elements can be directly bonded to each other without adhesive. Similarly, corresponding conductive contact pads can be directly bonded to each other without adhesive to provide electrical communication between the two elements. The bonded two elements communicate with each other through the contact pads and can perform one or more functions. In conventional applications, when different functions are desired for a bonded structure, implementing such different functions often requires a new tapeout for one or both of the bonded semiconductor elements, e.g., a new design for the circuit layout and construction of the semiconductor elements, which can consume a significant amount of resources and time. Each tapeout or fabrication of an integrated circuit die (e.g., a semiconductor chip) is an expensive and time-consuming process.

[0015] Thus, it can be beneficial to perform different functions on a bonding structure or repair errors or defects in a bonding structure (or individual elements) without completing an entirely new tapeout for each element, especially when similar or identical chips can be utilized with different components and / or different electrical connections enabled. In various embodiments disclosed herein, adjusting the interconnections between opposing contact pads in a bonding structure can enable an assembler or manufacturer to achieve different functions and / or repair errors in a bonding structure or individual elements.

[0016] 1 is a schematic cross-sectional side view of a first element 10 and a second element 12 (which may comprise semiconductor elements) to be directly bonded together. Each of the first element 10 and the second element 12 includes a device portion 14 (e.g., a bulk semiconductor portion), a non-conductive bonding layer 16 disposed on the device portion 14 and defining a bonding surface 18, a plurality of microelectronic devices comprising integrated devices or circuits 20 (which may include active devices (e.g., transistors, logic devices, etc.) and / or passive devices (e.g., capacitors, etc.)), a plurality of conductive contact pads 22 exposed to (e.g., recessed relative to or flush with) the bonding surface 18, and a plurality of traces 24 connecting each integrated circuit 20 to a corresponding conductive contact pad 22. In some embodiments, each of the first element 10 and / or the second element 12 may be in wafer form, such as a wafer, a reconstituted wafer, or an interposer. In other embodiments, the first element 10 and / or the second element 12 may comprise singulated elements, such as integrated device dies (such as processor dies, microelectromechanical systems (MEMS) dies, sensor dies, memory dies, etc.), reconfiguration dies, singulated interposer elements, etc. In some embodiments, the first element 10 may be in wafer form and the second element 12 may be singulated (e.g., in die form), or vice versa. The device portion 14 may comprise a bulk semiconductor portion, such as silicon. Furthermore, the device portion 14 may include, for example, one or more patterned device layers, which may include many integrated circuit layers having logic gates, local interconnects, and other devices such as capacitors. Furthermore, although not shown, the device portion 14 may further comprise a metallization layer (e.g., back-end-of-line (BEOL)) to provide routing on the top surface. The bonding layer 16 and pads 22 may be provided on the device portion 14, including on any metallization or BEOL layers on the top surface of the device portion 14.

[0017] As shown, the microelectronic device may include an integrated circuit 20 that may be disposed within the device portion 14 and may include various electronic components, such as, for example, transistors and other types of circuit elements. The integrated circuit 20 shown in FIG. 2 is an example of a microelectronic device that may be provided within the device portion 14. While the integrated circuit 20 is shown in a highly schematic block diagram, those skilled in the art will understand that the integrated circuit 20 may be patterned within the device portion 14, on the surface of the device portion 14, or in any other suitable location. One or more conductive traces 24 may electrically connect the integrated circuit 20 with corresponding conductive contact pads 22 that may be configured to electrically connect (e.g., be directly bonded to) corresponding contact pads on another device. In various embodiments, the traces 24 may terminate at die bond pads (not shown) of the device 10, 12 (e.g., die), which may communicate with the contact pads 22 in the bonding layer 16. In some embodiments, the contact pads 22 of the bonding layer 16 are deposited directly on the die bond pads of the device 10, 12. In other embodiments, additional conductive material may be provided within bonding layer 16 to extend trace 24 laterally and / or vertically to connect to contact pad 22. For example, in some embodiments, trace 24 may be part of a redistribution metallization in a redistribution layer (RDL) (not shown) that is routed laterally relative to device portion 14 from a die bond pad to contact pad 22. It should be appreciated that while trace 24 is shown very schematically in the figures as extending within bonding layer 16 (e.g., as part of additional routing in the bonding layer or as a bond pad extension), it may terminate at a die bond pad (not shown) on the side of device portion 14.

[0018] After direct bonding, the contact pads 22 of the first component 10 can be electrically connected to the contact pads of the second component 12 to form an electrical connection between the integrated circuit 20 on the first component 10 and the integrated circuit 20 on the second component 12. Direct bonding between the components 10, 12 can include direct bonding as described in detail herein. It should be appreciated that the components 10, 12 in FIG. 1 are shown schematically, and the relative proportions of various structural features may be exaggerated for ease of illustration. Furthermore, FIG. 1 may show only a subset of the integrated circuits 20; in fact, additional integrated circuits 20 may be provided and electrically connected to the contact pads 22.

[0019] The non-conductive bonding layer may comprise one or more dielectric layers in various embodiments. For example, the non-conductive layer may comprise a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride layer, or any other suitable non-conductive material. The contact pads 22 may comprise any suitable type of electrical conductor, such as a metal, e.g., copper. Similarly, the traces 24 may comprise a suitable conductor, such as copper. In some embodiments, a single non-conductive layer 16 is provided. In other embodiments, multiple non-conductive layers 16 (and multiple vertical and / or lateral metallizations) may be provided (e.g., deposited or plated) within the multiple layers 16.

[0020] Various embodiments disclosed herein relate to a bonding structure 1 (e.g., as shown in FIGS. 3A-3D and 6A-6D). As discussed above, first and second elements 10 and 12 can be fabricated at the wafer level with devices configured to perform various functions. For example, in FIG. 1, a non-conductive bonding layer 16 can be deposited over device portion 14 and patterned to expose openings into which conductive material for contact pads 22 (and / or traces 24 or other routing metallization extensions) will be deposited. As described below, the non-conductive bonding layer 16 can be prepared for direct bonding, allowing the two elements 10, 12 (including both the non-conductive layer 16 and the contact pads 22) to be directly bonded to one another without an intervening adhesive. In FIG. 1, all integrated circuits 20 designed to connect to a contact pad 22 are connected to that contact pad 22 through one or more traces 24. As used herein, traces 24 may electrically connect contact pads 22 directly to integrated circuit 20, or may electrically connect contact pads 22 indirectly to integrated circuit 20 through intervening die bond pads and / or bonding layer 16 and / or additional routing metallization in other layers provided on devices 10, 12. Thus, after bonding, the structure of FIG. 1 includes an electrical connection between integrated circuit 20 and contact pads 22, with traces 24 connecting pads 22 and integrated circuit 20 based on the original circuit design for devices 10, 12 and the bonding structure.

[0021] Thus, in FIG. 1 , the layout of integrated circuit 20, corresponding contact pads 22, and corresponding connecting traces 24 are designed to perform a specific function. In some embodiments, it may be desirable to change the functionality of the bonding structure without redesigning the individual components 10, 12. In some embodiments, it may be desirable to correct errors or address defects within one or more components 10, 12 or the bonding structure. In various embodiments, the bonding layer of a chip similar or identical to that of FIG. 1 can be modified to affect the performance of the bonding structure 1 or to adjust the configuration of a given microelectronic device within the chip of the bonding structure 1. For example, the contact pad design for one or both components 10, 12 can be modified to change the functionality of the bonding structure. Beneficially, such modifications allow manufacturers to offer custom bonding products using the same basic chip without creating new tapeouts for the individual components 10, 12. This further allows manufacturers to more easily customize products for different markets using the same or similar chips while controlling price points, functionality, frequency / frequency range (which can reduce power and errors), etc.

[0022] In embodiments disclosed herein, including forming and / or modifying the bonding layer 16 and pads 22, photoresist exposure can be performed at the wafer level using mask and lithography techniques to expose and pattern areas for the contact pads 22. Alternatively, methods that allow for greater flexibility, such as laser writing to actively remove interconnects or resist exposure to selectively etch interconnect locations, can be used to pattern the bonding layer 16 and pads 22. The laser writing process can utilize test information for wafer sorting or from process monitor data.

[0023] Test interconnect pad locations used for wafer sorting can have their probe marks removed by selectively etching those locations. Probe marks can have features that cause them to extend beyond the bonding interface, limiting bonding of the surfaces. Removing this material can prevent material from exceeding a height that would prevent bonding. Thus, in some embodiments, a bonding surface can have multiple wafer test pad locations. All or a portion of the metallization at the wafer test pad locations can be removed and recessed from the partial bonding surface, thereby recessing that portion of the metallization at the wafer test pad locations from the top surface of the non-conductive material, thereby disabling interconnection at those locations when the devices 10 and 12 are bonded. This recessing can be achieved by patterning with photoresist and selectively etching the metal (e.g., copper) through the openings at those locations.

[0024] FIG. 2 is a schematic cross-sectional side view of semiconductor devices 10 and 12 that can be directly bonded to one another according to embodiments. Unless otherwise noted, components in FIG. 2 can be the same as or substantially similar to similarly numbered components in FIG. 1 . Unlike devices 10 and 12 of FIG. 1 , the bonding surface 18 and / or bonding layer 16 can be modified to provide different functionality for the bonding structure. For example, bonding layer 16 can include at least one deleted pad region, such as a fully deleted pad region 32 lacking a contact pad and / or a partially deleted pad region 33. The fully deleted pad region 32 can include a void 26, and the partially deleted pad region 33 can include a partial void 28 and a remaining pad portion 29. Each of these voids 26 and 28 can be filled with a non-conductive material, such as a gas, e.g., air, or a solid non-conductive material (e.g., a solid dielectric material such as silicon oxide). The remaining pad portion 29 can be present in the partially deleted pad region 33.

[0025] To allow for customization of the bonding system and to alter or restore functionality described herein, in one embodiment, one or more of the conductive contact pads 22 may be at least partially removed, as shown, for example, in fully deleted pad region 32 (which may consist of pads 22 completely removed) and / or in partially deleted pad region 33. The at least partial removal of one or more conductive contact pads 22 may affect or even disable one or more functionality of the bonding structure 1.

[0026] For example, removal of one or more conductive contact pads 22 can correct problems with the conductive contact pads 22 and / or bonding interface 34 (shown in FIGS. 3A-3D and 6A-6D ), which may be performed at the manufacturing factory. Additionally or alternatively, the conductive contact pads 22 can be modified at a later stage to perform “dip switch”-type programming to set chip parameters and / or to change the functionality of the bonding structure. Such functional modifications can serve as hard programming steps that can occur at the manufacturing factory to set chip functionality before singulation, at the facility where devices 10 and 12 are bonded, at a test facility that uses test results to set dip switch settings, or at any other suitable location or stage in the assembly or manufacturing process. As one example, such functional modifications can be useful in various situations for post-manufacturing adjustment of integrated devices that currently utilize fuses, antifuses, or resistor trimming (e.g., in field programmable gate arrays (FPGAs)). As another example, such functional modifications can salvage defective parts based on test results. That is, for example, the operating speed of a processor can be set based on performance testing, or a faulty or shorted subcircuit can be shut off by such a change.

[0027] One or more conductive contact pads 22 to be removed (partially or completely) can be at least partially removed by masking and patterning with photoresist and wet etching the conductive contact pads 22, which can be partially or completely removed from the bonding surface 18. In some embodiments, laser writing lithography with a certain level of precision (e.g., sub-micron linewidths, such as 300 nm linewidths) can be used, allowing for maskless patterning.

[0028] Thus, in the embodiment of FIG. 2 , one or more conductive contact pads 22 can be at least partially removed from or modified on the first element 10 and / or the second element 12 after initial formation. For example, the conductive contact pads 22 can be formed according to a predetermined pattern on the first element 10 or the second element 12. Trenches or openings can be formed in the bonding layer 16, and a barrier layer (e.g., a metal or dielectric barrier layer) can be provided to line the openings. A seed layer can be provided on the barrier layer, and the openings can be provided with conductive material for the contact pads 22. A material removal process, such as chemical mechanical polishing (CMP), can be performed to remove overburden (not shown) on the conductive contact pads 22 and substantially establish the bonding surface 18. Subsequently, one or more conductive contact pads 22 can be selectively reduced or removed to prevent interconnections to these conductive contact pads 22 between the first element 10 and the second element 12. This process can be customized on a die-by-die or wafer-by-wafer basis to customize the functionality of the final bonding structure 1.

[0029] The bonding surface 18 can be prepared for direct bonding (e.g., by removing barrier materials, such as metal, from the bonding surface 18 and by planarization), and parameters (e.g., recess depth) for the conductive contact pads 22 can be set to achieve hybrid direct bonding. As described above herein, the fully deleted pad regions 32 and / or the partially deleted pad regions 33 resulting from the previous step can be filled with a gas, e.g., air or a solid non-conductive material (e.g., a solid dielectric material, such as silicon oxide). Remaining portions 29 of the conductive contact pads 22 can be present in the partially deleted pad regions 33.

[0030] The bonding of the bonding surfaces 18 between the first element 10 and the second element 12 can be achieved using wafer-to-wafer, die-to-die, or die-to-wafer hybrid bonding techniques such that interconnections are disabled between the first element 10 and the second element 12 at locations corresponding to the deleted pad regions 32 and / or the partially deleted pad regions 33. The hybrid bonding between the first element 10 and the second element 12 can be associated with two chips (e.g., two integrated device dies) or a chip and a wafer. For example, in the case of a die-to-wafer implementation, a single type of die can be configured for various functions by implementing the above-described connection variants on the host wafer, which are achieved by partially or completely removing or deleting one or more conductive contact pads 22 on the wafer. Conversely, a single type of host wafer can be configured for various functions by implementing the above-described connection variants on the die, which are achieved by partially or completely removing or deleting one or more conductive contact pads 22 on selected dies.

[0031] 3A-3D are schematic cross-sectional side views of various arrangements of bonded structures. As shown and described in more detail below, a first element 10 and a second element 12 (e.g., as shown in FIGS. 1 and 2) can be directly bonded without an intervening adhesive to form a bonded structure 1, which includes a bonded interface 34 formed by bonding surfaces 18 of the first element 10 and the second element 12.

[0032] 3A shows a bonding structure 1 including the first element 10 and second element 12 of FIG. 1 without the deleted pad area 32 or the partially deleted pad area 33. Thus, all of the interconnections between the pads 22 of the first element 10 and second element 12 are provided, and none of the functionality is altered or disabled.

[0033] 3B-3D, in contrast, illustrate bonding structures having various combinations of deleted pad regions 32 and / or partially deleted pad regions 33 on the first element 10 and / or second element 12. In these embodiments, the interconnections between the first element 10 and the second element 12 are not available at locations corresponding to the deleted pad regions 32 and / or partially deleted pad regions 33, thereby altering or disabling one or more functions of the bonding structure.

[0034] For example, in FIG. 3B , the bonding layer 16 can include a fully deleted pad region 32 and a partially deleted pad region 33. In the direct bond structure 1, the voids 26, 29 can remain filled with a gas (e.g., air) without the use of a solid fill material. The voids 26, 28 of the opposing elements 10, 12 can be aligned with one another and remain in the bonded structure as gas-filled voids 26, 28. The presence of the non-conductive fill gas in the fully deleted and partially deleted regions 32, 33 can prevent electrical connection between the opposing integrated circuits 20 in the elements 10, 12. As shown in FIG. 3B , the remaining pad portions 29 in the partially deleted pad region 33 can be spaced apart by voids 28 in the bonded structure 1, electrically isolating the opposing remaining pad portions 29. In the fully deleted pad region 32, the termination ends 23 of the opposing traces 24 can be electrically isolated from one another by the gas-filled voids 26. As noted above, it should be appreciated that in some embodiments, terminating end 23 of trace 24 may include a die bond pad (not shown) of device 10 or 12. In other embodiments, terminating end 23 of trace 24 may include a conductive extension into bonding layer 16 that connects to contact pad 22 prior to at least partial removal of pad 22. For example, as noted above, RDL or other metallization may extend laterally and / or vertically into bonding layer 16 to connect to pad 22 prior to at least partial removal. Thus, as shown, for a removed (e.g., fully or partially removed) contact pad, the associated trace 24 may extend between integrated circuit 20 (an example of a microelectronic device) and the removed contact pad region (e.g., fully removed region 32 or partially removed region 33).

[0035] The bonding structure of FIG. 3C includes fully and partially removed pad regions 32, 33 with opposing gaps 26, 28, as in FIG. 3B. FIG. 3C further illustrates a solid fill material 25, in which a solid non-conductive material (e.g., a solid dielectric material such as silicon oxide) is provided in the opposing gaps 26, 28. The solid fill material 25 may be provided on the remaining pad portions 29 in the partially removed pad region 33. In some arrangements, the solid fill material 25 may be provided on the termination ends 23 of the traces 24 that terminate in the gaps 26 in the removed pad region 32. Because the solid fill material 25 may be provided after at least partial removal of selected pads, an interface may exist between the solid fill material 25 and the surrounding non-conductive material of the bonding layer 16. In some embodiments, the removed pad region 32 or 33 may be provided in the bonding layer 16 of both the first and second elements 10, 12. In some embodiments, the removed pad region 32 or 33 may be provided on only one side of the bonding interface 34, for example, only in the bonding layer 16 of either the first or second element 10, 12. FIG. 3D illustrates additional combinations of fully removed and partially removed pad region 32, 33 arrangements on the first and / or second elements 10, 12. As shown, in some arrangements, filler material 25 may be provided on the bonding layer 16 of one element 10, which may face the unmodified contact pad 22 on the opposing element 12. In some areas, the partially removed pad portion 32 may include a void 28 adjacent to the unmodified contact pad 22. In some areas, the partially removed pad portion 33 may face the fully removed pad portion 32, so that the voids 26, 28 are located adjacent to each other. In some areas, the void 26 from the fully removed pad region 32 may be located adjacent to the conductive material of the unmodified contact pad 22. Those skilled in the art will appreciate that other combinations of opposing modified pad areas may be suitable.

[0036] 3B-3D, selected contact pads 22 can be modified to disable electrical connection between first and second components 10, 12, selectively preventing electrical communication between integrated circuits 20 connected to those selected contact pads 22. In various regions, gas voids can electrically isolate a remaining pad portion 29 (in the case of a partially removed pad portion 33 and an opposing fully removed pad portion 32), two remaining pad portions (in the case of two opposing partially removed pad portions 33), and / or two opposing termination ends 23 of traces 24 (in the case of two opposing fully removed pad portions 32) from the termination end 23 of trace 24. In various regions, solid fill material 25 can be provided in voids 26, 28 to isolate the remaining pad portion, two remaining pad portions 29, two opposing termination ends 23 of traces, and / or gas voids located over the remaining pad portion 29 or termination ends 23 of traces 24 from the termination end 23 of trace 24.

[0037] Advantageously, as described above, modifications to the bonding layer 16 and contact pads 22 can be used to change the functionality of the bonding structure without redesigning the chip patterns of the elements 10 and 12. Thus, in some applications, the individual elements 10 and 12 of FIGS. 3B-3D can be functionally similar or identical to the elements 10 and 12 of FIG. 3A. For example, in some embodiments, the same type of chip can be used for the elements 10 and 12 of FIGS. 3A-3D, so that the basic design of the integrated circuit 20 is functionally the same. Modifying the contact pads 22 as described herein to selectively disable connections between selected opposing pads can change the overall functionality of the bonding structure. As shown, even if the contact pads 22 are completely or partially removed, the underlying traces 24 and integrated circuit 20 can remain unchanged. Thus, partially or completely removed pads can be identified by the presence of traces 24 extending from the integrated circuit 20 to electrically inactive pad portions, such as gas voids 26 and 28, solid non-conductive fill material 25, or remaining pad portions 29 electrically isolated from the opposing pads on the opposing elements. Traces 24 connected to the interrupt circuitry may therefore terminate in an inactive pad, an inactive remaining pad portion 29, or a non-conductive material (such as a gas void or fill material 25). It should be appreciated that in any of the embodiments disclosed herein, for each element 10 or 12, all of the deleted pad areas may comprise full deleted pad areas 32, all of the deleted pad areas may comprise partial deleted pad areas 33, or the deleted pad areas may comprise a mixture of full deleted pad areas 32 and partial deleted pad areas 33. In some embodiments, traces 24 terminating in deleted pad areas 32, 33 may be electrically grounded to prevent stray electrical contacts.

[0038] FIG. 4 is a schematic cross-sectional side view of a portion of semiconductor device 10 or 12 according to an embodiment. For example, FIG. 4 shows a removal pad region 32 including a barrier layer 30 and a rounded or angled surface 31 extending between barrier layer 30 and bonding surface 18. As described above, barrier layer 30 can be provided in the opening before the conductive material of contact pad 22 is deposited. Barrier layer 30 can prevent the conductive material (e.g., copper) of conductive contact pad 22 from diffusing into non-conductive bonding layer 16 (which can be made of silicon oxide, for example). Barrier layer 30 can comprise a conductive layer such as titanium nitride, tantalum nitride, or the like.

[0039] In some arrangements, at least partial removal of pad 22, for example by etching, can leave at least a portion of barrier layer 30 behind to line bonding layer 16 within gap 26. In various embodiments, removed pad region 32 and / or partially removed pad region 33 may undergo oxide and / or barrier edge rounding or other removal to ensure that any remaining metal from barrier layer 30 does not electrically connect circuits intended to be electrically isolated. Barrier layer 30 can be removed by etching at least at bonding surface 18, or can be removed as part of preparation of bonding surface 18 (e.g., by polishing), thereby resulting in a rounding effect and removal of barrier material at bonding surface 18. The barrier removal process can form rounded or angled surfaces 31. The rounded or angled surfaces 31 can extend between the remaining portions of barrier layer 30 within the gap and bonding surface 18. Advantageously, such oxide rounding can also prevent unintended interconnections, for example, through the often conductive barrier layer 30, in the deleted pad regions 32 and / or partially deleted pad regions 33 between the conductive contact pads 22 on the opposing elements 10, 12.

[0040] Additionally, there may be conductive contact pads 22 that do not connect to any active circuitry for fully deleted pad regions 32 and / or partially deleted pad regions 33 in bonding structure 1. In some embodiments, the blocked or modified pads may be connected to electrical ground so that none of the conductive contact pads 22 corresponding to deleted pad regions 32 and / or partially deleted pad regions 33 are left electrically floating.

[0041] 5A-5B are schematic cross-sectional side views of semiconductor devices that can be directly bonded according to other embodiments. Unless otherwise noted, components in FIGS. 5A-5B can be the same or substantially similar to similarly numbered components in FIGS. 1-4. Similar to the embodiment of FIGS. 3B-3D, devices 10 and 12 can also include one or more deleted pad regions 36, which represent areas where conductive contact pads 22 are absent (e.g., deleted) from the pad layout pattern stage used to form the conductive contact pads 22. Unlike the embodiment of FIGS. 3B-3D, in which contact pads 22 are at least partially removed at selected interconnection locations, in FIGS. 5A-6D, the interconnection between devices can be altered by changing the contact pad pattern, thereby providing a non-through interconnection by deleting pads from bonding layer 16 during patterning. In such an embodiment, forming deleted pad regions 36 does not require forming and then at least partially removing pads.

[0042] In one embodiment, the pad layout pattern used to form the conductive contact pads 22 can be modified such that at least one conductive contact pad 22 is deleted from the pad layout pattern, resulting in one or more regions 36 lacking a conductive contact pad 22. The deleted pad regions 36 can be formed during masking and lithography so that the regions that would typically contain contact pads instead contain a non-conductive bonding material, such as silicon oxide. Thus, certain dies, chips, wafers, or portions thereof will not have conductive contact pads 22 formed in those locations corresponding to one or more regions 36 to effect a functional change of the die (or wafer), program the die (or wafer), or otherwise change the characteristics of the bonding structure 1. In this embodiment, once the hybrid interconnects are formed according to direct bonding techniques, there is no need to modify the conductive contact pads 22. In this embodiment, functional changes of the die, wafer, or portions thereof can be achieved by modifying the pattern of interconnects at the bonding interface 34 rather than modifying the die or wafer itself. In other embodiments, some pads can be patterned away, as shown in Figures 5A-5B, and portions of other contact pads 22 can be at least partially removed, as illustrated in Figures 3B-3D, if additional modifications are desired.

[0043] In this embodiment, one or more conductive contact pads 22 can be omitted from formation on the first element 10 and / or the second element 12. For example, to customize the final bonded product, the layout of the conductive contact pads 22 can be customized on a die-by-die or wafer-by-wafer location basis through modifications to the pad layout pattern used to form the bonding layer 16 and the conductive contact pads 22. A material removal process, such as chemical mechanical polishing (CMP), can be performed to remove overburden (not shown) around the to-be-formed conductive contact pads 22 and establish the bonding surface 18. Subsequently, the bonding surface 18 can be finished for bonding (e.g., by removing a barrier material, such as a metal, from the bonding surface 18, e.g., comprising an oxide), and parameters (e.g., recession) for the conductive contact pads 22 can be set to perform hybrid direct bonding.

[0044] 6A-6D are schematic cross-sectional side views of various embodiments of a bonding structure including two directly bonded semiconductor elements. As shown, a first element 10 and a second element 12 can be directly bonded to form a bonding structure 1, which includes a bonding interface 34 formed by bonding surfaces 18 of the first element 10 and the second element 12.

[0045] 6A shows an illustration of the first element 10 and the second element 12 without the deleted pad region 36. Thus, all of the interconnections between the pads 22 of the first element 10 and the second element 12 are considered available without any functionality being affected or disabled.

[0046] In contrast, Figures 6B-6D illustrate various combinations of deletion contact pad regions 36 on the first element 10 and / or the second element 12, showing that conductive contact pads 22 are not patterned and formed in these regions 36. Instead of conductive pad material, a non-conductive bonding material (a solid dielectric, such as silicon oxide) of the bonding layer 16 can be applied to the deletion contact pad regions 36. In these scenarios, the interconnects typically connected between the first element 10 and the second element 12 are no longer available in the locations corresponding to the regions 36, thereby altering or disabling one or more functions without modifying the individual elements 10, 12. As shown in Figures 6B-6D, the non-conductive material in the deletion pad regions 36 can extend between the device portions 14 of the respective elements 10, 12, or between the device portions 14 of one element 10, 12 and the contact pads 22 of the other element 10, 12. As a result, the non-conductive material in the removal pad region 36 selectively electrically isolates the integrated circuits 20 on opposing elements 10, 12 that would typically be electrically connected by the original design. As noted above, the termination ends 23 of the traces 24 (which may include die bond pads, dangling ends of the traces, or trace extensions or other metallization that extend into bonding layer 16) that would normally connect the integrated circuits 20 with the active contact pads 22 can instead terminate in the non-conductive material in the removal contact pad region 36, so that no electrical connection is made between the selected integrated circuits 20 and the opposing contact pads and / or integrated circuits 20 on the opposing elements.

[0047] 7A-7C are schematic bottom views of semiconductor devices 10 with different contact pad patterns. FIG. 7A shows device 10 or 12 with contact pads 22 arranged in a regular two-dimensional array. In FIG. 7A, none of the contact pads 22 are removed (as in FIGS. 3A and 6A), so all available connections between the bonded devices 10 and 12 are made. In contrast, FIGS. 7B and 7C show removed contact pad regions 32, 33, and 36, in which all or portions of selected contact pads 22 may be removed at selected locations on the devices 10 and 12. For example, in FIG. 7B, removed contact pad regions 32, 33, and 36 may be interspersed within this array to selectively disable electrical interconnections at specifically identified contact pads 22. In FIG. 7C, removed contact pad regions 32, 33, and 36 may comprise multiple rows of pads 22, for example, in the central regions of the devices 10 and 12. For example, in some embodiments, contact pads 22 in a common area may have similar functionality, and thus functionality can be changed by deleting contact pads in that area (e.g., the two rows shown in FIG. 7C ). Those skilled in the art will recognize that many other patterns for deleted pads may be suitable. It should be appreciated that deleted contact pad areas 32, 33, 36 may be provided in any portion of elements 10, 12 to change the interconnections at particular isolated portions of elements 10, 12 or to change areas of elements 10, 12. Thus, as can be seen from the bottom view, multiple contact pads may be arranged in a regular pattern, with one or more deleted contact pads.

[0048] FIG. 8 is a schematic diagram of a system 38 incorporating one or more bonding structures 1 according to various embodiments. The system 38 can comprise any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, a tablet computing device, a laptop computer, etc.), a desktop computer, an automobile or component thereof, a stereo system, a medical device, a camera, or any other suitable type of system. In some embodiments, the electronic device can comprise a microprocessor, a graphics processor, an electronic recording device, or a digital memory. The system 80 can include one or more device packages 40 mechanically and electrically connected to the system 38, for example, through one or more motherboards. Each package 40 can include one or more bonding structures 1. The bonding structure 1 shown in FIG. 8 can comprise any of the bonding structures disclosed herein. The bonding structure 1 can include one or more integrated device dies that perform various functions related to the system 38.

[0049] Examples of direct bonding and direct bonding structures Various embodiments disclosed herein relate to direct bond structures that allow two elements to be directly bonded to one another without an intervening adhesive. Two or more semiconductor elements (integrated device dies, wafers, etc.) can be stacked or bonded to one another to form the bond structure. The conductive contact pads of one element can be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements can be stacked within the bond structure.

[0050] In some embodiments, the elements are directly bonded to one another without adhesive. In various embodiments, the non-conductive or dielectric material of a bonding layer of a first element can be directly bonded to a corresponding non-conductive or dielectric field region of a bonding layer of a second element without adhesive. This non-conductive material may be referred to as a non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to a corresponding non-conductive material of the second element using a non-conductor-to-conductor (e.g., dielectric-to-dielectric) bonding technique. For example, a dielectric-to-dielectric bond can be formed without adhesive using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0051] In various embodiments, a direct hybrid bond can be formed without an intervening adhesive. For example, the dielectric bonding surfaces can be polished to increase smoothness. The bonding surfaces can be cleaned and then exposed to a plasma and / or an etchant to activate the bonding surfaces. In some embodiments, after or during activation (e.g., during a plasma and / or etch process), the surfaces can be terminated with chemical species. Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces, and the termination can provide additional chemical species at the bonding surfaces that improve bond energy during direct bonding. In some embodiments, activation and termination are provided in the same step that activates and terminates the bonding surfaces, e.g., with a plasma or wet etchant. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination species can comprise nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, one or more fluorine peaks can be present near the layers and / or bonding interface. Thus, in a direct bond structure, the bond interface between the two dielectric materials can have a very smooth interface with a higher nitrogen content and / or fluorine peak at the bond interface. Further examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0052] In various embodiments, conductive contact pads of a first element can be directly bonded to corresponding conductive contact pads of a second element. For example, hybrid bonding techniques can be used to provide conductor-to-conductor direct bonds along bonding interfaces that include covalently directly bonded dielectric-to-dielectric surfaces prepared as described above. In various embodiments, conductor-to-conductor (e.g., contact pad-to-contact pad) direct bonds and dielectric-to-dielectric hybrid bonds can be formed using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0053] For example, as described above, dielectric bonding surfaces can be prepared and bonded directly to one another without an intervening adhesive. Conductive contact pads (which may be surrounded by a non-conductive dielectric field region) can also be bonded directly to one another without an intervening adhesive. In some embodiments, each contact pad can be recessed relative to the outer (e.g., upper) surface of the dielectric field or non-conductive bonding region, e.g., by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. In some embodiments, non-conductive bonding regions can be bonded directly to one another without an adhesive at room temperature, after which the bonded structure can be annealed. Upon annealing, the contact pads can expand and contact one another, forming a metal-to-metal direct bond. Beneficially, direct bond interconnect or DBI® technology, commercially available from Xperi, Inc. of San Jose, California, can be used to connect high density pads (e.g., small or fine pitch for a regular array) across the direct bond interface. In some embodiments, the pitch of the bond pads, or the conductive traces embedded in the bonding surface of one of the bonding elements, can be less than 40 microns, or less than 10 microns, or even less than 2 microns. In some applications, it is desirable for the ratio of the bond pad pitch to one of the bond pad dimensions to be less than 5, or less than 3, and sometimes less than 2. In other applications, the width of the conductive trace embedded in the bonding surface of one of the bonding elements can be in the range of 0.3 to 3 microns. In various embodiments, the contact pads and / or traces can comprise copper, although other metals may be suitable.

[0054] That is, in a direct bonding process, a first element can be bonded directly to a second element without an intervening adhesive. In some arrangements, the first element can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element can comprise a carrier or substrate (e.g., a wafer).

[0055] As described herein, the first and second elements can be directly bonded to each other without adhesive, which differs from a deposition process. In one application, the width of the first element at the bonded structure is similar to the width of the second element. In some other embodiments, the width of the first element at the bonded structure differs from the width of the second element. Similarly, the width or area of ​​the larger element at the bonded structure may be at least 10% greater than the width or area of ​​the smaller element. The first and second elements can accordingly comprise non-deposited elements. Furthermore, unlike deposited layers, direct bonded structures can include defect regions in which nanovoids exist along the bonded interface. The nanovoids can form due to activation (e.g., exposure to plasma) of the bonded surfaces. As described above, the bonded interface can include material enrichment due to activation and / or final chemical treatment steps. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak can be formed at the bonded interface. In embodiments utilizing oxygen plasma for activation, an oxygen peak can be formed at the bonded interface. In some embodiments, the bonded interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond can comprise a covalent bond that is stronger than a van der Waals bond. The bonding layer can also comprise a polished surface that has been planarized to a high degree of smoothness.

[0056] In various embodiments, the metal-to-metal bond between the contact pads can be bonded such that the copper grains grow into each other across the bond interface. In some embodiments, the copper can have grains oriented along crystal planes to improve diffusion of the copper across the bond interface. The bond interface can extend substantially all the way to at least a portion of the bonded contact pads, so that there are substantially no gaps between the non-conductive bond regions at or near the bonded contact pads. In some embodiments, a barrier layer can be provided (e.g., can include copper) below the contact pads. However, in other embodiments, there may be no barrier layer below the contact pads, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated herein by reference in its entirety for all purposes.

[0057] Unless the context clearly indicates otherwise, the words "comprises," "comprising," "includes," "including," and the like throughout this specification and claims shall be construed in an inclusive sense, i.e., "including but not limited to," as opposed to a restrictive or exhaustive sense. The word "coupled," as used generally herein, refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Similarly, the word "connected," as used generally herein, refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Furthermore, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as being "on" or "on" a second element, the first element can be directly on or on the second element, such that the first and second elements are in direct contact, or the first element can be indirectly on or on the second element, such that there are one or more intervening elements between the first and second elements. Where the context permits, words using the singular or plural in the above Detailed Description can also include the plural or singular, respectively. The word "or" referring to a list of two or more items shall have the following interpretations for that word: any of the items in the list, all of the items in the list, and all of any and all combinations of the items in the list are encompassed.

[0058] Furthermore, conditional language used herein, such as, among others, "may," "could," "might," "may," "e.g.," "for example," and "such as," is generally intended to convey that certain embodiments include certain features, elements, and / or conditions, while other embodiments do not, unless specifically stated otherwise or understood otherwise within the context in which it is used. Thus, such conditional language is generally not intended to imply that a feature, element, and / or condition is required in any way for one or more embodiments.

[0059] While disclosed in connection with certain embodiments and examples, those skilled in the art will recognize that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses, and obvious modifications and equivalents thereof. Furthermore, unless otherwise specified, elements in an illustrative drawing may be the same or substantially similar to elements with similar numbering in one or more different illustrative drawings. In addition, while certain variations have been shown and described in detail, other modifications falling within the scope of the present disclosure will be readily apparent to those skilled in the art based on this disclosure. It is contemplated that various combinations or subcombinations of specific features and aspects of the embodiments are possible and still fall within the scope of the present disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another to form varying modes of the disclosed invention. Thus, it is intended that the scope of the invention disclosed herein should not be limited by the specific embodiments disclosed above, but should be determined solely by a fair reading of the following embodiments. [Explanation of symbols]

[0060] 1 Joint structure 10 First element 16 Non-conductive bonding layer 22 conductive contact pads 24 Trace

Claims

1. A joining structure, a first element having a first bonding surface comprising a first non-conductive material and a plurality of first contact pads at least partially embedded in the first non-conductive material, the first contact pads being electrically connected to one or more first microelectronic devices within the first element; a second element having a second bonding surface including a second non-conductive material and a plurality of second contact pads at least partially embedded in the second non-conductive material, the second contact pads electrically connecting to one or more second microelectronic devices within the second element; Equipped with the second mating surface is bonded directly to the first mating surface without an intervening adhesive to form a mating interface; the first element includes a removal contact pad area including an insulating material, a trace terminating in the removal contact pad area extending to at least one of the one or more first microelectronic devices, the trace being electrically isolated from any contact pads; A joining structure characterized by:

2. 10. The bonding structure of claim 1, wherein the removable contact pad area comprises one or more voids within the first non-conductive material.

3. 2. The joining structure of claim 1, wherein the insulating material in the removal contact pad region is a solid non-conductive filler material disposed in the first non-conductive material, and an interface is disposed between the solid non-conductive filler material and the first non-conductive material.

4. The joining structure of claim 1 , wherein the deleted contact pad area comprises a completely deleted contact pad area that is devoid of a contact pad.

5. 5. The joint structure of claim 4, wherein the first non-conductive material extends continuously within the removal contact pad area.

6. 2. The joining structure of claim 1, wherein the deleted contact pad area comprises a partially deleted contact pad area including a remaining portion of one of the plurality of first contact pads and a void above the remaining portion.

7. The joint structure of claim 6 further comprising a solid non-conductive filler material within the void.

8. 2. The bonding structure of claim 1, wherein the plurality of first contact pads are directly bonded to the plurality of second contact pads, and the bonding structure comprises a plurality of traces extending between the one or more first microelectronic devices and the plurality of first contact pads.

9. 2. The joint structure of claim 1, wherein the traces have terminal ends that terminate in the removal contact pad areas.

10. 10. The junction structure of claim 9, wherein the first element comprises a bulk semiconductor portion, the first non-conductive material is disposed on the bulk semiconductor portion, and the termination end of the trace extends into the first non-conductive material.

11. The joint structure of claim 1 , wherein the trace is connected to an electrical ground.

12. 2. The bonding structure of claim 1, wherein the second element comprises a second deletion contact pad area, the second deletion contact pad area being aligned with the deletion contact pad area.

13. 2. The joining structure of claim 1, wherein the plurality of first contact pads are arranged in a regular pattern when viewed from a bottom view, apart from the first contact pads with the removed contact pad area.

14. 2. The bonding structure of claim 1, wherein the removal contact pad area comprises a barrier layer disposed on the first non-conductive material, with rounded or angled surfaces of the first non-conductive material extending between the barrier layer and the bonding interface.

15. The splice structure of claim 1 , wherein the traces terminate below the splice interface.

16. A joining structure, a first element having a first bonding surface comprising a first non-conductive material and a plurality of first contact pads at least partially embedded in the first non-conductive material, the first contact pads being electrically connected to one or more first microelectronic devices within the first element by one or more first traces; a second element having a second bonding surface comprising a second non-conductive material and a plurality of second contact pads at least partially embedded in the second non-conductive material, the second contact pads being electrically connected to one or more second microelectronic devices within the second element by one or more second traces; Equipped with the second bonding surface is bonded directly to the first bonding surface without an intervening adhesive to form a bonding interface, at least one of the first traces extending between at least one of the one or more first microelectronic devices and a removal contact pad area at the bonding interface, the removal contact pad area comprising an insulating material, and the at least one trace terminating in the removal contact pad area and being electrically isolated from any contact pads; A joining structure characterized by:

17. 17. The joint structure of claim 16, wherein the removable contact pad area comprises one or more voids within the first non-conductive material.

18. 20. The joining structure of claim 17, wherein the insulating material in the removal contact pad region is a solid non-conductive filler material disposed in the one or more voids, and an interface is disposed between the solid non-conductive filler material and the first non-conductive material.

19. The joining structure of claim 16 , wherein the deleted contact pad area comprises a completely deleted contact pad area devoid of a contact pad.

20. 20. The joint structure of claim 19, wherein the first non-conductive material extends continuously within the removal contact pad area.

21. The splice structure of claim 16 , wherein the at least one trace terminates below the splice interface.

22. 1. A method of forming a bonded structure, comprising: directly bonding a first non-conductive material of a first element to a second non-conductive material of a second element without an intervening adhesive to form a bonding interface; directly contacting a plurality of first contact pads of the first element with a plurality of second contact pads of the second element, the first contact pads being electrically connected to one or more first microelectronic devices within the first element and the second contact pads being electrically connected to one or more second microelectronic devices within the second element; providing the first element with a removal contact pad area disposed at the bonding interface, the removal contact pad area comprising an insulating material, at least one trace connected to an electronic device terminating in the removal contact pad area, the at least one trace being electrically isolated from any contact pads; A method comprising:

23. 23. The method of claim 22, wherein providing the first element with the removed contact pad region comprises at least partially removing one of the first contact pads prior to the directly bonding step.

24. 24. The method of claim 23, wherein the at least partially removing comprises completely removing the first contact pad.

25. 24. The method of claim 23, wherein the at least partially removing step comprises partially removing the first contact pad.

26. 24. The method of claim 23, further comprising providing a solid filler material in the void created by the at least partially removing step.

27. 23. The method of claim 22, wherein providing the first element with the deleted contact pad region comprises selectively forming the plurality of first contact pads to delete one of the first contact pads.

28. 23. The method of claim 22, wherein the directly bonding step comprises directly bonding a first wafer comprising the first elements to a second wafer comprising the second elements.

29. 23. The method of claim 22, wherein the directly bonding step comprises directly bonding a first die comprising the first element to a second die comprising the second element.

30. 23. The method of claim 22, wherein the directly bonding step comprises directly bonding a die comprising the first device to a wafer comprising the second device.

31. 23. The method of claim 22, further comprising removing a barrier layer in the removal contact pad area.

32. 32. The method of claim 31 , wherein removing the barrier layer comprises forming a rounded or angled surface in the first non-conductive material between the barrier layer and the bonding interface.

33. 23. The method of claim 22, wherein the removal contact pad area is provided based on test data.

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