Imaging device

Abstract

To provide an imaging device that generates in a pixel, a potential that is higher than a potential to be supplied to the pixel.SOLUTION: An imaging device includes a pixel having a first circuit and a second circuit. The second circuit includes a photoelectric conversion device. The first circuit and the second circuit are electrically connected to each other. The first circuit has a function of adding up a first potential and a second potential to generate a third potential. The second circuit has a function of generating data in the photoelectric conversion device to which the third potential is applied, and a function of outputting the data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] The technology of constructing transistors using oxide semiconductor thin films formed on substrates has been attracting attention. For example, a transistor having an oxide semiconductor and extremely low off-state current is used in a pixel circuit. An imaging device having such a configuration is disclosed in Patent Document 1.

[0005] In addition, a memory device having a structure in which a transistor with extremely low off-state current is used as a memory cell is disclosed in a patent document. This is disclosed in reference 2. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119711 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-119674 Summary of the Invention [Problem to be solved by the invention]

[0007] To increase the resolution of an image sensor, it is necessary to reduce the area per pixel and increase the pixel density. Since the reduction in pixel area is accompanied by a reduction in the light-receiving area of ​​the photoelectric conversion device, the light sensitivity Especially when capturing images under low light, the S / N ratio of the captured data drops significantly. In other words, in image sensors with conventional configurations, the resolution and light sensitivity are not consistent. There is a problem in that they are in a do-off relationship.

[0008] To address the above issues, we developed a photoelectric conversion device that utilizes the highly photosensitive avalanche multiplication effect. However, to utilize the avalanche multiplication effect, A relatively high voltage must be applied to the photoelectric conversion device, and a dedicated power supply circuit must be used. It must be.

[0009] Therefore, in one aspect of the present invention, it is possible to generate a voltage higher than the voltage supplied to the pixel. Another object of the present invention is to provide an imaging device that can provide two potentials to a pixel. It is an object of the present invention to provide an imaging device capable of adding An object of the present invention is to provide an imaging device capable of generating a reset potential.

[0010] Another object is to provide an imaging device with low power consumption. It is one of the objects to provide an imaging device that can perform the above. One of the objects is to provide a novel imaging device. Another object is to provide a method for operating the imaging device. One of the objects is to provide a novel semiconductor device and the like.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention relates to an imaging device that generates a potential higher than a potential supplied to a pixel within the pixel. do.

[0013] One embodiment of the present invention is an imaging device having a pixel including a first circuit and a second circuit. The second circuit has a photoelectric conversion device, and the first circuit and the second circuit are electrically connected. The first circuit has a function of generating a third potential by adding the first potential and the second potential. The second circuit has a function of generating data from a photoelectric conversion device to which a third potential is applied. It is an imaging device that has the function of capturing and outputting the image data.

[0014] The first circuit includes a first transistor, a second transistor, and a first capacitor. One of the source and drain of the first transistor is connected to one of the first capacitors. The other electrode of the first capacitor is electrically connected to the source of the second transistor. the source or drain of the first transistor, One of the terminals can be connected to a second circuit.

[0015] The second circuit further includes a third transistor, a fourth transistor, and a fifth transistor. a second capacitor, and one electrode of the photoelectric conversion device is connected to a third transistor. the source or drain of the third transistor; Alternatively, the other of the drains is electrically connected to one electrode of the second capacitor. One electrode of the capacitor is electrically connected to the gate of the fourth transistor. One of the source or drain of the fifth transistor is connected to the source or drain of the fifth transistor. The second electrode can be electrically connected to one of the first electrode and the second electrode.

[0016] One of the source and drain of the third transistor of the second circuit is connected to the first circuit. Alternatively, the source or drain of the third transistor of the second circuit may be connected to the other terminal. The first circuit can be connected to the second circuit.

[0017] As a different configuration from the above, the second circuit further includes a third transistor and a fourth transistor. a fifth transistor, a second capacitor, and a third transistor; The electrode of the second capacitor is electrically connected to one electrode of the second capacitor. The other electrode is electrically connected to the gate of the fourth transistor, and the other electrode is electrically connected to the source of the fourth transistor. One of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the fifth transistor. The other electrode of the photoelectric conversion device is connected to the source or drain of the third transistor. One electrode of the photoelectric conversion device is electrically connected to one of the drains, and one electrode of the photoelectric conversion device is connected to the first circuit. It may also be used.

[0018] At least one of the transistors included in the imaging device has a channel formation region formed of a metal oxide. The metal oxide is In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, It is preferable that the alloy contains at least one of the following elements: La, Ce, Nd, or Hf.

[0019] It is preferable to use an avalanche photodiode as the photoelectric conversion device. [Effects of the Invention]

[0020] By using one embodiment of the present invention, a voltage higher than the voltage supplied to a pixel can be generated. Alternatively, it is possible to provide an imaging device that can add two potentials supplied to a pixel. Alternatively, a reset potential can be generated in the pixel. It is possible to provide an imaging device that can

[0021] Alternatively, it is possible to provide an imaging device with low power consumption. Alternatively, a highly reliable imaging device can be provided. Alternatively, a novel imaging device can be provided. Alternatively, a method for operating the imaging device can be provided. Alternatively, a novel semiconductor device or the like can be provided. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 1 is a diagram illustrating a pixel circuit. [Figure 2] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 3] FIG. 3 is a diagram illustrating a pixel circuit. [Figure 4] 4A and 4B are diagrams illustrating a pixel circuit. [Figure 5] 5A and 5B are timing charts illustrating the operation of the pixel circuit. [Figure 6] 6A and 6B are diagrams illustrating a pixel circuit. [Figure 7] 7A and 7B are diagrams illustrating a pixel circuit. [Figure 8] FIG. 8 is a diagram illustrating a pixel circuit. [Figure 9] FIG. 9 is a timing chart illustrating the operation of the pixel circuit. [Figure 10] FIG. 10 is a diagram illustrating a pixel circuit. [Figure 11] FIG. 11 is a diagram illustrating a pixel circuit. [Figure 12] FIG. 12 is a timing chart illustrating the operation of the pixel circuit. [Figure 13] FIG. 13 is a block diagram illustrating the imaging device. [Figure 14] 14A and 14B are diagrams illustrating the simulation results. [Figure 15] 15(A) to 15(E) are diagrams illustrating the configuration of pixels in an imaging device. [Figure 16] 16A and 16B are diagrams illustrating the configuration of a pixel in an imaging device. [Figure 17] 17(A) to 17(C) are diagrams illustrating a transistor. [Figure 18] 18A and 18B are diagrams illustrating the configuration of a pixel in an imaging device. [Figure 19] 19(A) to 19(D) are diagrams illustrating a transistor. [Figure 20] 20(A) to 20(C) are diagrams illustrating the configuration of a pixel in an imaging device. [Figure 21]21(A1) to 21(B3) are perspective views of a package and a module that house an imaging device. [Figure 22] 22(A) to 22(F) are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0024] In addition, even if a circuit diagram shows a single element, there may be functional problems. If there is no need for a single element, the element may be composed of multiple elements. For example, a transistor that operates as a switch may be used. In some cases, multiple resistors may be connected in series or in parallel. In some cases, the sensor may be divided and placed in multiple positions.

[0025] In addition, when one conductor has multiple functions such as wiring, electrode, and terminal, In this specification, the same element may be referred to by multiple names. Even if the circuit diagram shows direct connections between elements, In some cases, the elements are connected via multiple conductors, and in this specification, Even configurations such as this are included in the category of direct connection.

[0026] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0027] One embodiment of the present invention is an imaging device in which a boosting operation can be performed in a pixel. By generating a voltage, it is possible to operate an avalanche photodiode without using a high-voltage power supply. Therefore, it is possible to provide a low-power, high-sensitivity imaging device. Cut.

[0028] <Configuration example 1> FIG. 1 is a diagram illustrating a pixel 10a that can be used in an imaging device according to one embodiment of the present invention. The pixel 10 a can be configured to include a circuit 11 and a circuit 12 .

[0029] Circuit 11 is a circuit that generates a reset potential, and it is possible to generate a reset potential by adding two potentials supplied. Therefore, a higher voltage can be generated.

[0030] The circuit 12 has a photoelectric conversion device and performs photoelectric conversion using the reset potential generated by the circuit 11. The device can be operated to generate and store image data.

[0031] It is preferable to use an avalanche photodiode as the photoelectric conversion device. Since a high voltage (reset potential) can be generated in the circuit 11, it is possible to achieve an average voltage without using a high voltage power supply. A Ranche photodiode can be operated.

[0032] The circuit 11 includes a transistor 102, a transistor 103, and a capacitor 107. One of the source and drain of the transistor 102 is connected to the capacitor 107. The other electrode of the capacitor 107 is electrically connected to one electrode of the transistor 1. The source of the transistor 102 is electrically connected to one of the source and drain of the transistor 103. Alternatively, one of the drains can be connected to the circuit 12 .

[0033] The circuit 12 includes a photoelectric conversion device 101, a transistor 104, a transistor 105, and , a transistor 106, and a capacitor 108. It is also possible to configure the system without providing 08.

[0034] One electrode (cathode) of the photoelectric conversion device 101 is connected to the source or is electrically connected to one of the source and drain of the transistor 104. The other end is electrically connected to one electrode of the capacitor 108. The electrode of the transistor 105 is electrically connected to the gate of the transistor 105. One of the source and drain of the transistor 106 is electrically connected to one of the source and drain of the transistor 106. One of the source and drain of the transistor 104 is electrically connected to the circuit 11. can be effectively connected.

[0035] Here, the other of the source or drain of the transistor 104 and one of the capacitors 108 The wiring connecting the electrode and the gate of the transistor 105 is referred to as a node FD. It can function as a load storage section.

[0036] The other electrode (anode) of the photoelectric conversion device 101 is electrically connected to the wiring 122. The gate of the transistor 102 is electrically connected to the wiring 125. The other of the source and the drain of transistor 2 is electrically connected to a wiring 123. The gate of the transistor 103 is electrically connected to the wiring 126. The other drain is electrically connected to a wiring 124. The gate of the transistor 104 is The other electrode of the capacitor 108 is electrically connected to the wiring 127. The source or drain of the transistor 105 is electrically connected to a reference potential line such as The other end is electrically connected to a wiring 121. The gate of the transistor 106 is electrically connected to a wiring 128. The other of the source and the drain of the transistor 106 is electrically connected to the wiring 12. 9 and electrically connected to each other.

[0037] The wirings 121 and 122 can function as power supply lines. The wiring 123 can have a function of supplying a potential for generating a reset potential. The potential of the electrodes 124 varies depending on the direction of connection of the photoelectric conversion device 101. In this configuration, the cathode side of the photoelectric conversion device 101 is electrically connected to the transistor 102. The node FD is reset to a high potential to operate. The wiring 124 is at a high potential (a higher potential than the wiring 122). When the direction is opposite to that of FIG. 1, the wirings 123 and 124 are at a low potential (a lower potential than the wiring 122). This can be done as follows.

[0038] Wirings 125, 126, 127, and 128 are used as signal lines to control the conduction of each transistor. The wiring 129 can function as an output line.

[0039] A photodiode can be used as the photoelectric conversion device 101. In a preferred embodiment, an avalanche photodiode is used.

[0040] The transistors 102 and 103 have a function of generating a reset potential. The transistor 104 has a function of controlling the potential of the node FD. The potential of the node FD can be output to the wiring 129 as image data. The transistor 106 has a function of selecting a pixel to output image data.

[0041] When an avalanche photodiode is used as the photoelectric conversion device 101, a relatively high current is generated. In order to apply a voltage, the transistor connected to the photoelectric conversion device 101 is a transistor with a high withstand voltage. For example, a high-voltage transistor is preferably used. Transistors using metal oxide (hereinafter referred to as OS transistors) can be used in the Specifically, OS transistors can be used for the transistors 102 and 104. In addition, it is preferable to use OS transistors as the transistors 103, 105, and 106. Good too.

[0042] The OS transistor also has an extremely low off-state current. By using an OS transistor in 104, the period during which the charge can be held at the node FD can be shortened. Therefore, the total length can be increased without complicating the circuit configuration or operation method. A global shutter system can be applied in which charge accumulation is performed simultaneously in pixels.

[0043] In addition to the above, OS transistors and transistors using Si in the channel formation region may also be used. Any combination of Si transistors may be used. The transistor may be an OS transistor or a Si transistor. As examples, transistors with amorphous silicon, crystalline silicon (typically , low-temperature polysilicon, single-crystal silicon, etc.) and the like.

[0044] <Configuration example 2> The imaging device of one embodiment of the present invention may have the configuration of the pixel 10b shown in FIG. In pixel 10a, the connection position of circuit 11 and circuit 12 is different from that of pixel 10a, and circuit 11 is connected to node FD. In this configuration, the other of the source or drain of the transistor 104 is connected to the capacitor. One electrode of the bottom electrode 108, the gate of the transistor 105, the source of the transistor 102 The wiring connecting one of the drains and one of the electrodes of the capacitor 107 is a node FD. The configurations of the circuit 11, the circuit 12, and the wiring connecting them are the same as those of the pixel 10a. do.

[0045] <Configuration example 3> The imaging device of one embodiment of the present invention may have the configuration of the pixel 10c shown in FIG. In the pixel 10a shown in FIG. 1, the connection position of the transistor 104 in the circuit 12 is different from that of the pixel 10a shown in FIG. One of the source and drain of the transistor 104 is connected to the other of the photoelectric conversion device 101. the source or drain of the transistor 104. The other end is electrically connected to a wiring 122. The other configuration is the same as that of the pixel 10a.

[0046] In this configuration, node FD is connected to either the source or drain of transistor 102, One electrode of the capacitor 107, one electrode of the capacitor 108, and the gate of the transistor 105. This serves as a wiring for connecting the photoelectric conversion device 101 and one electrode (cathode) of the photoelectric conversion device 101. The potential of the node FD is distributed to the other electrode (anode) of the photoelectric conversion device 101. The potential is determined including the potential.

[0047] The transistor 104 has a function of controlling the potential of the node FD. It is used to initialize and maintain the potential of the FD. By making the node FD non-conductive, the conduction between the photoelectric conversion device 101 and the node FD is cut off. The potential of the FD is determined.

[0048] In the pixel 10c, the transistor 104 is turned off, and the photoelectric conversion device 101 The other electrode (anode) is disconnected from the wiring 122. The transistor 104 is turned off. Then, the potential of the anode of the photoelectric conversion device 101 rises and the potential of the cathode and anode When the difference approaches the forward voltage (Vf), the photoelectric conversion device 101 stops operating. Thus, the potential of the node FD can be determined.

[0049] <Modification of Circuit 12> The above-described pixels 10a, 10b, and 10c are configured such that the reset potential of the node FD is applied to the photoelectric conversion device The photoelectric conversion device 10 is set to a voltage higher than the anode of 101, and a reverse bias is applied to the photoelectric conversion device 10 This is a configuration in which 1 is connected.

[0050] As another configuration, as shown in the modified example of the circuit 12 in FIGS. 4(A) and 4(B), the node FD The reset potential is set to a voltage lower than the cathode of the photoelectric conversion device 101, and the reverse bias is The photoelectric conversion device 101 may be connected in such a direction. The circuit 12 can be applied as a modification of the pixels 10a and 10b, and is shown in FIG. The circuit 12 can be applied as a modification of the pixel 10c.

[0051] In the configurations shown in FIGS. 4A and 4B, the node FD is operated to have a negative potential. Therefore, at least the transistor 105 is preferably a p-ch transistor. It is preferable to use a

[0052] <Operation of Circuit 11> Taking the connection configuration of the circuit 11 and the circuit 12 shown in FIG. 2 as an example, the voltage addition operation in the circuit 11 First, the transistor 102 is turned on, and the potential of the wiring 123 is applied to the node FD. V RS1 ” (reset potential 1) is written. Also, the transistor 103 is made conductive, and the The other electrode of the capacitor 107 is connected to the potential “V REF This supplies a reference potential. At this time, the capacitor 107 has a potential “V RS1 -V REF " is held. Then, the node FD is set to a floating state, and the other electrode of the capacitor 107 is connected to the potential “V RS 2” (reset potential 2).

[0053] At this time, the capacitance value of the capacitor 107 is C 107 , the capacitance value of node FD is C FD So, , the potential of node FD is "V RS1 +(C 107 / (C 107 +C FD ))×(V RS2 -V REF )" where C 107 The value of CFD is sufficiently larger than C FD The value of If this can be neglected, the potential of node FD will be "V RS1 +V RS2 -V REF " becomes .

[0054] Therefore, “V RS1 ”=“V RS2 ", "V REF "=0V, and C 107 C FD If the potential of node FD is sufficiently large compared to RS1 ". In other words, A voltage approximately twice the voltage that can be supplied to the element can be supplied to node FD as a reset potential. This becomes the case.

[0055] The high voltage reset potential supplied to the node FD is supplied to the photoelectric conversion device 101. "V RS1 ", "V RS2 By supplying the appropriate voltage as The avalanche photodiode can be operated without using a voltage power supply.

[0056] <Configuration Example 1 Operation> Next, an example of the operation of the pixel 10a will be described with reference to the timing chart of FIG. In the explanation of the timing charts in this specification, high potential is referred to as "HH" or " H” (“HH”>“H”), low potential is “L”, reset potential is “V RS1 " or "V R S2 " and the reference potential is "V REF ". "H" is always supplied to the wiring 121, and "H" is always supplied to the wiring 1 22 is always supplied with "L".

[0057] In addition, in the distribution, coupling or loss of potential, the circuit configuration and operation timing, etc. The detailed changes due to the capacitance coupling using a capacitor are not taken into account. The capacitance of the capacitor depends on the capacitance ratio between the capacitor and the element to which it is connected. Therefore, the capacitance value of the element is assumed to be sufficiently small.

[0058] During the period T1, the potential of the wiring 123 is set to “V RS1 ”, and the potential of the wiring 124 is set to “V REF ” , the potential of the wiring 125 is set to "H", the potential of the wiring 126 is set to "H", the potential of the wiring 127 is set to "H", When the potential of the wiring 128 is set to "L", the transistors 102 and 104 are turned on, and the node FD The potential of the wiring 123 is "V RS1 " is supplied. Also, transistor 103 is turned on, The other electrode of the capacitor 107 is connected to the potential “V REF " is supplied. In this case, the capacitor 107 has a "V RS1 -V REF " is retained.

[0059] During the period T2, the potential of the wiring 123 is set to “V RS1 ”, and the potential of the wiring 124 is set to “V RS2 ” , the potential of the wiring 125 is set to "L", the potential of the wiring 126 is set to "H", the potential of the wiring 127 is set to "H", When the potential of the wiring 128 is set to "L", the other electrode of the capacitor 107 is connected to the wiring 124. Potential “V” RS2 At this time, due to the capacitive coupling of the capacitor 107, the node The potential of FD is "V RS1 +V RS2 '" (reset operation).

[0060] As explained in the operation of circuit 11, C 107 The value of C FDis sufficiently larger than the value of C FD If the value of can be ignored, the potential of node FD becomes "V RS1 +V RS2 -V REF ” Here, "V REF " is 0V, and C FD actually has a non-negligible value Assuming that the potential of node FD is “V RS1 +V RS2 It can be represented as ' Cut.

[0061] “V RS1 " and "V RS2 " is "V RS1 +V RS2 '" Photoelectric conversion device 10 It is preferable to set the voltage at which 1 reaches the voltage at which the avalanche multiplication characteristic is exhibited. For example, “V RS1 " and "V RS2 " indicates that the photoelectric conversion device 101 has an avalanche multiplication characteristic. The voltage shall be higher than half the voltage shown.

[0062] During the period T2, the potential of the node FD decreases in response to the operation of the photoelectric conversion device 101. (accumulation operation).

[0063] During the period T3, the potential of the wiring 123 is set to “V RS1 ”, and the potential of the wiring 124 is set to “V RS2 ” , the potential of the wiring 125 is set to "L", the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", When the potential of the wiring 128 is set to "L", the potential of the node FD is determined and maintained (maintenance operation). ).

[0064] During the period T4, the potential of the wiring 123 is set to “V RS1 ”, and the potential of the wiring 124 is set to “V RS2 ” , the potential of the wiring 125 is set to "L", the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", When the potential of the wiring 128 is set to "H", the transistor 106 is turned on and the transistor 105 The potential of the node FD is read out to the wiring 129 by the source follower operation (read out operation). made).

[0065] The above is an example of the operation of the pixel 10a shown in Fig. 1. Note that when the circuit 12 shown in Fig. 4(A) is used, If you use RS1 " and "V RS2 " can be made to have a negative potential.

[0066] <Operation of configuration examples 2 and 3> Next, an example of the operation of the pixels 10b and 10c will be explained using the timing chart of FIG. 5(B). Although the pixels 10b and 10c have different circuit element connection configurations, they are connected to the same timing circuit. It can work with the cart.

[0067] During the period T1, the potential of the wiring 123 is set to “V RS1 ”, and the potential of the wiring 124 is set to “V REF ” , the potential of the wiring 125 is set to "H", the potential of the wiring 126 is set to "H", the potential of the wiring 127 is set to "L", When the potential of the wiring 128 is set to "L", the transistor 102 is turned on, and the wiring 123V potential RS1 " is supplied. Also, the transistor 103 is turned on, and the capacitor The other electrode of the capacitor 107 is connected to the potential "V REF " is supplied. In the above operation, , and capacitor 107 is “V RS1 -V REF " is retained.

[0068] During the period T2, the potential of the wiring 123 is set to “V RS1 ”, and the potential of the wiring 124 is set to “V RS2 ” , the potential of the wiring 125 is set to "L", the potential of the wiring 126 is set to "H", the potential of the wiring 127 is set to "L", When the potential of the wiring 128 is set to "L", the other electrode of the capacitor 107 is connected to the wiring 124. Potential “V” RS2 At this time, due to the capacitive coupling of the capacitor 107, the node The potential of FD is "V RS1 +V RS2 '" (reset operation).

[0069] As explained in the operation of circuit 11, C 107 The value of C FD is sufficiently larger than the value of C FD If the value of can be ignored, the potential of node FD becomes "V RS1 +V RS2 -V REF ” Here, "V REF " is 0V, and C FD actually has a non-negligible value Assuming that the potential of node FD is “V RS1 +V RS2 It can be represented as ' Cut.

[0070] During the period T3, the potential of the wiring 123 is set to “V RS1 ”, and the potential of the wiring 124 is set to “V RS2 ” , the potential of the wiring 125 is set to "L", the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "H", When the potential of the wiring 128 is set to "L", the node FD The potential of the capacitor decreases (storage operation).

[0071] During the period T4, the potential of the wiring 123 is set to “V RS1 ”, and the potential of the wiring 124 is set to “V RS2 ” , the potential of the wiring 125 is set to "L", the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", When the potential of the wiring 128 is set to "L", the potential of the node FD is determined and maintained (maintenance operation). ).

[0072] During the period T5, the potential of the wiring 123 is set to “V RS1 ”, and the potential of the wiring 124 is set to “V RS2 ” , the potential of the wiring 125 is set to "L", the potential of the wiring 126 is set to "L", the potential of the wiring 127 is set to "L", When the potential of the wiring 128 is set to "H", the transistor 106 is turned on and the transistor 105 The potential of the node FD is read out to the wiring 129 by the source follower operation (read out operation). made).

[0073] The above is an example of the operation of the pixel 10b shown in FIG. 2 and the pixel 10c shown in FIG. When the circuit 12 shown in FIG. 4(A) is applied to the pixel 10b, and when the circuit 12 shown in FIG. 4(B) is applied to the pixel 10c, When applying the circuit 12 shown in RS1 " and "V RS2 If a negative potential is used for good.

[0074] <Modifications of Configuration Examples 1, 2, and 3> In one embodiment of the present invention, as illustrated in FIGS. 6(A) and 6(B), a buffer is attached to a transistor. FIG. 6(A) shows a configuration in which a back gate is electrically connected to the front gate. This shows a configuration in which the transistors are electrically connected, which has the effect of increasing the on-state current. The gate of the transistor is electrically connected to a wiring that can supply a constant potential. The threshold voltage of the transistor can be controlled.

[0075] Also, by combining Figure 6(A) and (B), each transistor can be operated appropriately. In addition, a transistor without a back gate may be used as a pixel transistor. Note that the structure in which a back gate is provided in a transistor is not the same as that in the pixel 10. This can be applied to all of 10a to 10c.

[0076] As a modification of the pixels 10a and 10b, the circuit 11 may be configured as shown in FIGS. The source or drain of the transistor 102 and the voltage of one of the capacitors 107 are connected to each other. The electrodes may be electrically connected via the transistor 104.

[0077] In addition, the pixels 10a, 10b, and 10c are deformed to form a source follower circuit in a plurality of pixels. For example, the configuration shown in FIG. 8 is used. FIG. 8 shows a pixel 10a as a basic structure. As a result, it is a configuration that includes more appropriate elements and is also compatible with the global shutter method. By sharing a source follower circuit among multiple pixels, the number of transistors per pixel can be reduced. The number of transistors can be reduced.

[0078] FIG. 8 shows the reset circuit (transistor 111) and source follower for four pixels in the vertical direction. The pixel 10a has a shared circuit (transistor 105) and a common pixel circuit. '(pixel 10a'[1] to [4]) has the elements of pixel 10a, as well as capacitor 10 9, and has a transistor 110.

[0079] One electrode of the capacitor 109 is connected to the other of the source or drain of the transistor 104. The other of the source and drain of the transistor 104 is electrically connected to the The source or drain of the transistor 110 is electrically connected to the The other of the source and drain is electrically connected to the source or drain of the transistor 111. The source or drain of the transistor 111 is connected to the It is electrically connected to the gate of 05.

[0080] The other electrode of the capacitor 109 and the other of the source or drain of the transistor 111 The other end is electrically connected to a reference potential line such as a GND line. The gate of the transistor 111 is electrically connected to a wiring 130. 1. The wiring 130 (wirings 130[1] to [4]) and wiring 131 can function as a signal line that controls the conduction of each transistor.

[0081] The source or drain of the transistor 110 in each of the pixels 10a'[1] to [4] the other of the drain of the transistor 111, the source or drain of the transistor 112, and the The wiring to which the gate of the transistor 105 is connected is the node FD. The other of the source or drain of the capacitor 109 and the The wiring that connects either the source or the drain is called a node AD. It has the function of storing the captured data.

[0082] The operation of the shared pixel circuit shown in FIG. 8 will be described with reference to the timing chart shown in FIG. This operation is a global shutter method in which accumulation operations are performed simultaneously in all pixels.

[0083] For the operation of the periods T1 to T3, the description of the operation of the pixel 10a can be referred to. The data acquired by the accumulation operation is stored in nodes AD[1] to [4].

[0084] In the period T4, when the potential of the wiring 131 is set to “H”, the transistor 111 is turned on, and the node F The potential of D is reset. The reset potential can be, for example, GND or 0V. It is possible.

[0085] During the period T5, the potential of the wiring 131 is set to "L", the potential of the wiring 130[1] is set to "H", and the potential of the wiring 128 is set to "H". When the potential of the node AD[1] is set to "H", the transistor 110 is turned on, and the potential of the node AD[1] becomes Also, the source follower operation of the transistor 105 and the transistor When the transistor 106 is turned on, a potential according to the potential of the node FD is read out to the wiring 129.

[0086] Since data is held in nodes AD[2] to [4], from period T6 to T12 By repeating the above operation, data can be read from the pixels 10a'[1] to [4]. can.

[0087] As in the above description, the pixel 10b and the pixel 10c can also be configured as a shared pixel circuit. FIG. 10 shows a configuration in which pixel 10b is applied to a shared pixel circuit of four pixels in the vertical direction (pixel 1 0b'[1] to [4]). FIG. 11 shows the shared pixel circuit of four pixels in the vertical direction. The configuration in which the pixel 10c is applied (pixels 10c'[1] to [4]) is shown. The pixel circuit can also be operated according to the timing chart shown in FIG.

[0088] FIG. 13 is an example of a block diagram illustrating a circuit configuration of an imaging device according to one embodiment of the present invention. The imaging device includes a pixel array 21 having pixels 10 arranged in a matrix, and a A circuit 22 (row driver) having a function of selecting a row of the pixel 21, and a circuit 23 (row driver) for receiving data from the pixel 10 The pixel 10 includes a circuit 23 having a read function and a circuit 28 for supplying a power supply potential. , pixels 10a, 10b, 10c and any of their variations can be used.

[0089] The circuit 23 is connected to a circuit 24 (column driver) having a function of selecting a column of the pixel array 21. a circuit 25 (CD S circuit) and the function of converting analog data output from circuit 25 into digital data. The circuit 26 includes an A / D conversion circuit and the like.

[0090] The circuit 23 is electrically connected to the wiring 129 and converts the data output from the pixel 10 into digital data. For example, neural networks, memory The output destination can be a device, a display device, a communication device, or the like.

[0091] Next, the results of a simulation of the operation of the pixel circuit will be described. Assuming the pixel 10a shown in FIG. 1 and the pixel 10b shown in FIG. 2, the potential of the node FD is calculated as follows: went.

[0092] The parameters used in the simulation are as follows, and the transistor size is L / W. = 3 μm / 10 μm (transistors 102, 103, 104), L / W = 3 μm / 50 μ m (transistors 105 and 106), the capacitance of the capacitor 107 is 200 fF, The capacitance of the photoelectric conversion device 101 is 100 fF (not set for the pixel 10a). The value is 20 fF, and the reset potential is 1 (V RS1 ) is 20V, reset potential 2 (V RS2 ) is 2 The voltage applied to the gate of the transistor is set to +26V or is set to +46V and "L" to 0V. PICE was used.

[0093] FIG. 14A shows the state when the pixel 10a is operated according to the timing chart of FIG. 5A. The horizontal axis is time, and the vertical axis (left) is the gate wiring (GL1, GL2 ) and the vertical axis (right) shows the voltage at node FD. 25 and GL2 correspond to wiring 126.

[0094] V to node FD RS1 After writing, V is set according to the capacitance ratio. RS2 is added, and high voltage ( V RS1 +V RS2 It was confirmed that ') can be generated.

[0095] FIG. 14B shows the state when the pixel 10b is operated according to the timing chart of FIG. 5B. Similar to the pixel 10a, the node FD is connected to V RS1 Written by After that, V is RS2 is added, and a high voltage (V RS1 +V RS2 ') is generated It was confirmed that this was possible.

[0096] The above simulation results show that a high-voltage power supply circuit can be realized by using one embodiment of the present invention. High voltage can be generated within the pixel without using a photodiode, enabling avalanche photodiode operation It was confirmed that this was the case.

[0097] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0098] (Embodiment 2) In this embodiment, a structural example of an imaging device according to one embodiment of the present invention will be described.

[0099] 15(A) and (B) show examples of pixel structures of an imaging device. The pixel is an example of a stacked structure of a layer 561 and a layer 562 .

[0100] The layer 561 includes the photoelectric conversion device 101. The photoelectric conversion device 101 is shown in FIG. 5), the layer 565a, the layer 565b, and the layer 565c may be stacked.

[0101] The photoelectric conversion device 101 shown in FIG. 15(C) is a pn junction photodiode, for example. If so, layer 565a + layer 565b is an n-type semiconductor, layer 565c is an n-type semiconductor + type semiconductor Alternatively, layer 565a may be + layer 565b is a p-type semiconductor; 565c to p + Alternatively, the layer 565b may be an i-type semiconductor. It may also be a junction photodiode.

[0102] The pn junction photodiode or pin junction photodiode is made of single crystal silicon. The pin junction photodiode can be formed using an amorphous silicon. It can also be formed using a thin film of crystalline silicon, microcrystalline silicon, polycrystalline silicon, etc. .

[0103] 15(D), the photoelectric conversion device 101 included in the layer 561 is Alternatively, the layer 6a, the layer 566b, the layer 566c, and the layer 566d may be stacked. The photoelectric conversion device 101 shown is an example of an avalanche photodiode, and is shown in FIG. The layer 566a and the layer 566d correspond to electrodes, and the layers 566b and 566c correspond to photoelectric conversion parts.

[0104] The layer 566a is preferably made of a low-resistance metal layer, such as aluminum. Titanium, tungsten, tantalum, silver or laminates thereof can be used.

[0105] The layer 566d is preferably formed using a conductive layer that has high transparency to visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide oxide, indium-gallium-zinc oxide, or graphene can be used. The layer 566d may be omitted.

[0106] The layers 566b and 566c of the photoelectric conversion section are pn junctions in which a selenium-based material is used as the photoelectric conversion layer. The layer 566b can be a p-type semiconductor. A gallium oxide or the like, which is an n-type semiconductor, is used for the layer 566c. It is preferable that:

[0107] Photoelectric conversion devices using selenium-based materials have the characteristic of high external quantum efficiency for visible light. In this photoelectric conversion device, the incident light is multiplied by using avalanche multiplication. It is possible to increase the electron amplification relative to the amount of light. Also, selenium-based materials The material has a high light absorption coefficient, which offers advantages in terms of production, such as the ability to fabricate a thin film photoelectric conversion layer. Thin films of selenium-based materials can be formed using vacuum deposition or sputtering. do.

[0108] Selenium-based materials include crystalline selenium such as single crystal selenium and polycrystalline selenium, and amorphous selenium. , copper, indium, selenium compounds (CIS), or copper, indium, gallium, selenium Compounds of CIGS and the like can be used.

[0109] The n-type semiconductor is formed from a material that has a wide band gap and is transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or These materials can be used for hole injection. It also functions as a blocking layer and can reduce dark current.

[0110] 15(E), the photoelectric conversion device 101 included in the layer 561 is 7a, layer 567b, layer 567c, layer 567d, and layer 567e may be laminated. The photoelectric conversion device 101 shown in FIG. 15(E) is an example of an organic photoconductive film, and the layer 567a The layer 567e corresponds to an electrode, and the layers 567b, 567c, and 567d correspond to a photoelectric conversion section. .

[0111] One of the layers 567b and 567d of the photoelectric conversion portion is a hole transport layer, and the other is an electron transport layer. The layer 567c can be a photoelectric conversion layer.

[0112] The hole transport layer may be made of, for example, molybdenum oxide. For example, fullerenes such as C60 and C70, or derivatives thereof, are used. It is possible.

[0113] The photoelectric conversion layer is a mixed layer of n-type organic semiconductor and p-type organic semiconductor (bulk heterojunction). structure) can be used.

[0114] The layer 562 shown in FIG. 15(A) can be, for example, a silicon substrate. The silicon substrate has Si transistors and the like. The Si transistors are used to form pixel circuits. In addition to the circuit, a circuit for driving the pixel circuit, a circuit for reading out the image signal, an image processing circuit, etc. are provided. Specifically, the pixel circuit and peripheral circuits (pixel 1) described in the first embodiment can be 0, circuits 22, 23, 28, etc.) are provided in layer 562. It can be done.

[0115] As shown in FIG. 15(B), the pixel has a laminated structure of a layer 561, a layer 563, and a layer 562. may have

[0116] Layer 563 is a layer for forming an OS transistor (e.g., transistors 102, 103, and 104 of pixel 10a). 04, etc.) where layer 562 may have a Si transistor (e.g., The pixel 10a may have transistors 105, 106, etc. Some of the transistors included in the peripheral circuits described in 1 may be provided in the layer 563.

[0117] By adopting this configuration, the elements constituting the pixel circuit and the peripheral circuits are distributed across multiple layers, The elements can be overlapped with each other or with the peripheral circuit, so that the imaging device In the configuration of FIG. 15(B), the area of ​​the supporting layer 562 can be reduced. The substrate may be used, and the pixel 10 and peripheral circuits may be provided on the layer 561 and the layer 563 .

[0118] The semiconductor material used for the OS transistor has an energy gap of 2 eV or more. Metal oxides having a specific resistance of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAAC -OS(C-Axis Aligned Crystalline Oxide Sem iconductor) or CAC (Cloud-Aligned Compositor e)-OS, etc. can be used. CAAC-OS has stable atoms that make up the crystal. CAC-OS is suitable for transistors where reliability is important. Therefore, it is suitable for transistors that operate at high speed.

[0119] Since the energy gap of the semiconductor layer of an OS transistor is large, the current is several yA / μm (channel The OS transistor exhibits extremely low off-state current characteristics (current value per 1 μm of transistor width). The stan- dard is free from impact ionization, avalanche breakdown, and short channel effects. These features differ from Si transistors, allowing for the creation of highly reliable circuits with high voltage resistance. In addition, the electrical characteristics caused by the non-uniformity of the crystallinity, which is a problem in Si transistors, can be improved. OS transistors are also less likely to experience variations in performance.

[0120] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn oxides containing metals such as tin, neodymium, or hafnium The film can be made of a material such as a silicon dioxide film.

[0121] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form a film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratios were In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5: The atomic ratio of the semiconductor layers to be formed is preferably 1:8 or the like. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0122] The semiconductor layer is made of an oxide semiconductor with a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Further details are as follows: Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Below, further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a highly pure intrinsic or This oxide semiconductor has a low density of defect states and is stable. It can be said that this oxide semiconductor has stable characteristics.

[0123] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be carefully considered. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0124] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase, causing the semiconductor layer to become n-type. The concentrations of phosphate and carbon (obtained by secondary ion mass spectrometry) were measured at 2 × 10 18 atom s / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0125] In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0126] In addition, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons, which are carriers, This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0127] In addition, if hydrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, the oxide that bonds with the metal atoms Since the oxygen reacts with oxygen to form water, oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the conductor contains oxygen vacancies, the transistor will be normally on. Furthermore, defects in which hydrogen has entered the oxygen vacancies act as donors, In addition, some of the hydrogen atoms bond with the metal atoms, resulting in the generation of carrier electrons. It may combine with hydrogen to generate electrons, which are carriers. A transistor including an oxide semiconductor having such a structure tends to be normally on.

[0128] A defect in which hydrogen is inserted into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, the acid As a parameter of the compound semiconductor, we assume a state in which no electric field is applied, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "donor concentration."

[0129] Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor be reduced as much as possible. In oxide semiconductors, secondary ion mass spectrometry (SIMS) The hydrogen concentration obtained by mass spectrometry was calculated as 1×10 20 a toms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than, more preferably is 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / c m 3 The oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used as the transistor chip. By using it in the channel forming region, stable electrical characteristics can be imparted.

[0130] The semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure may have a c-axis orientation. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystalline structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0131] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide semiconductor film may have a completely amorphous structure and may have a crystalline portion. No.

[0132] The semiconductor layer may have an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a CAAC structure. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0133] Hereinafter, we will discuss CAC (Cloud-Aligned C), which is one type of non-single-crystal semiconductor layer. This section explains the structure of the .NET composite OS.

[0134] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0135] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0136] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (Ga X4 Zn Y4 OZ4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0137] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0138] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0139] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0140] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0141] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0142] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0143] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will The nanoparticle-like regions are observed in the region where the metal element is the main component, and the region where In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0144] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0145] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction measurement, It can be seen that the orientation of the regions in the ab plane direction and the c axis direction is not observed.

[0146] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped area of ​​high brightness (phosphor) is formed. The electron diffraction pattern is Therefore, the crystal structure of CAC-OS does not have orientation in the planar direction and the cross-sectional direction. It can be seen that it has a nano-crystal structure.

[0147] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The main ingredients are Area and In X2 Zn Y2 OZ2 , or InO X1 The area where the main component is unevenly distributed, It can be seen that it has a mixed structure.

[0148] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0149] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or In O X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for a high electric field. Effective mobility (μ) can be achieved.

[0150] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0151] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, In X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) This can be done.

[0152] Furthermore, semiconductor devices using CAC-OS have high reliability. , and is suitable as a constituent material for various semiconductor devices.

[0153] 16A is a diagram illustrating an example of a cross section of the pixel shown in FIG. The photoelectric conversion device 101 is a pn junction photodiode with a silicon photoelectric conversion layer. The layer 562 has a Si transistor, and in FIG. 16(A), the pixel 10b is taken as an example. Illustrated here are transistors 102 and 104 that form the pixel circuit.

[0154] In the photoelectric conversion device 101, the layer 565a is p + layer 565b is an n-type region, layer 565c is n + The layer 565b can be a mold region. The layer 565c can be a power line. For example, the region 536 is provided to connect the p + The type area This can be done.

[0155] The Si transistor shown in FIG. 16(A) has a channel forming region in a silicon substrate 540. The Si transistor is a fin type, and its cross section in the channel width direction is shown in FIG. It may also be of a planar type as shown in 17(B).

[0156] Alternatively, as shown in FIG. 17(C), a transistor having a semiconductor layer 545 of a silicon thin film may be used. The semiconductor layer 545 may be, for example, a silicon substrate 540 on an insulating layer 546. Single crystal silicon (SOI (Silicon on Insulator)) It can be said that:

[0157] In FIG. 16(A), the elements of the layer 561 and the elements of the layer 562 are electrically connected. An example of a configuration obtained by the combination technique is shown.

[0158] The layer 561 is provided with an insulating layer 542, a conductive layer 533, and a conductive layer 534. 33 and conductive layer 534 have regions buried in insulating layer 542. Conductive layer 533 has The conductive layer 534 is electrically connected to the region 536. The surfaces of the insulating layer 542, the conductive layer 533, and the conductive layer 534 are at the same height. It has been flattened to resemble a square.

[0159] The layer 562 is provided with an insulating layer 541, a conductive layer 531, and a conductive layer 532. 31 and conductive layer 532 have regions buried in insulating layer 541. Conductive layer 532 has The conductive layer 531 is electrically connected to the source or drain of the transistor 104. In addition, the surfaces of the insulating layer 541, the conductive layer 531, and the conductive layer 532 are electrically connected to each other. The surfaces are flattened to have the same height.

[0160] Here, the conductive layer 531 and the conductive layer 533 preferably contain the same metal element as a main component. It is preferable that the conductive layer 532 and the conductive layer 534 have the same metal element as a main component. In addition, it is preferable that the insulating layer 541 and the insulating layer 542 are made of the same component. It's nice.

[0161] For example, the conductive layers 531, 532, 533, and 534 may be made of Cu, Al, Sn, Zn, W, or A. For ease of bonding, Cu, Pt, Au, etc. can be used. The insulating layers 541 and 542 are made of Al, W, or Au. Silicon nitride, silicon oxynitride, silicon nitride, titanium nitride, etc. can be used .

[0162] That is, the combination of the conductive layer 531 and the conductive layer 533 and the combination of the conductive layer 532 and the conductive layer 533 are It is preferable to use the same metal material as shown above for each of the 34 combinations. In addition, the insulating layer 541 and the insulating layer 542 are made of the same insulating material as described above. By adopting this configuration, it is possible to bond the layer 561 and the layer 562 at the boundary between them. Combinations can be made.

[0163] By this bonding, a combination of the conductive layer 531 and the conductive layer 533 and the conductive layer 53 2 and the conductive layer 534. As a result, a connection having mechanical strength between the insulating layers 541 and 542 can be obtained.

[0164] To bond metal layers together, the oxide film on the surface and the adsorption layer of impurities are removed by sputtering or other methods. The surface activated bonding method is used to bond the cleaned and activated surfaces together. Alternatively, a diffusion bonding method can be used, which uses a combination of temperature and pressure to bond surfaces together. Both of these bond at the atomic level, so they can be used not only electrically but also mechanically. Mechanically excellent bonding can also be obtained.

[0165] In addition, to bond the insulating layers together, after obtaining high flatness by polishing, etc., oxygen plasma etc. The hydrophilic treated surfaces are brought into contact with each other to temporarily bond them together, and then the final bonding is performed by dehydrating them through heat treatment. Aqueous bonding methods can be used. Hydrophilic bonding also occurs at the atomic level, so , and mechanically excellent bonding can be obtained.

[0166] When the layer 561 and the layer 562 are bonded together, the bonding surfaces are made up of a mixture of insulating and metal layers. To achieve this, for example, a surface activated bonding method and a hydrophilic bonding method may be combined.

[0167] For example, after polishing, the surface is cleaned, and the surface of the metal layer is subjected to an anti-oxidation treatment and then to a hydrophilic treatment. Alternatively, the surface of the metal layer may be treated with a hard metal such as Au. It is also possible to use an oxidized metal and then subject it to hydrophilic treatment. That's fine.

[0168] FIG. 16B shows a pixel layer 561 shown in FIG. 15A in which a selenium-based material is used as a photoelectric conversion layer. A cross-sectional view of a pn junction photodiode is shown. The second electrode includes layers 566b and 566c as photoelectric conversion layers, and a layer 566d as the other electrode.

[0169] In this case, layer 561 can be formed directly on layer 562. Layer 566a is a The layer 566d is electrically connected to the source or drain of the transistor 104. 7, the layer 561 is electrically connected to the power supply line. The connection with the transistor is similar.

[0170] 18(A) is a diagram illustrating an example of a cross section of the pixel shown in FIG. 15(B). The photoelectric conversion device 101 is a pn junction photodiode with a silicon photoelectric conversion layer. The layer 562 has a Si transistor, and in FIG. 18(A), the pixel 10b is taken as an example. The layer 563 is an OS transistor. The transistors 102 and 104 that constitute the pixel circuit are shown as examples. The layer 563 shows a configuration example in which electrical connection is achieved by bonding.

[0171] FIG. 19A shows details of an OS transistor. The OS transistor shown in FIG. an insulating layer is provided over a stack of an oxide semiconductor layer and a conductive layer; and a groove reaching the oxide semiconductor layer is formed. A self-aligned type in which the source electrode 205 and the drain electrode 206 are formed by providing The structure is as follows.

[0172] The OS transistor has a channel formation region and a source region 203 formed in an oxide semiconductor layer. and a drain region 204, a gate electrode 201, and a gate insulating film 202. The trench can be formed with at least a gate insulating film 202 and a gate electrode 201. An oxide semiconductor layer 207 may be further provided in the groove.

[0173] As shown in FIG. 19B, the OS transistor is formed by oxidizing the gate electrode 201 as a mask. It can also be used as a self-aligned structure in which source and drain regions are formed in the compound semiconductor layer. good.

[0174] Alternatively, as shown in FIG. 19(C), the source electrode 205 or the drain electrode 206 and the gate electrode A non-self-aligned top-gate transistor having an area where the top electrode 201 overlaps with the It may also be a

[0175] The transistors 102 and 104 are shown with a back gate 535. The back gate 535 may be a gate-less structure. As shown in the cross section of the channel width direction of the transistor, The gate of the transistor shown in FIG. The same applies to transistors with other structures. The gate 535 may be configured to be supplied with a fixed potential different from that of the front gate. stomach.

[0176] Between the region where the OS transistor is formed and the region where the Si transistor is formed, An insulating layer 543 having a function of preventing diffusion of elements is provided. The hydrogen in the insulating layer provided near the channel forming region 6 acts as a dangling bond of silicon. On the other hand, a gate is provided near the channel forming region of the transistors 102 and 104. Hydrogen in the insulating layer is one of the factors that generate carriers in the oxide semiconductor layer.

[0177] The insulating layer 543 confines hydrogen to one layer, thereby forming the transistors 105 and 106. This improves reliability. In addition, the diffusion of hydrogen from one layer to another is suppressed. This also improves the reliability of the transistors 102 and 104.

[0178] The insulating layer 543 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0179] FIG. 18(B) shows a case where a selenium-based material is used as a photoelectric conversion layer in the layer 561 of the pixel shown in FIG. 15(B). 5 is a cross-sectional view of a case where a pn junction photodiode is used. For details of the layers 561, 562, and 563, please refer to the above description. In addition, even if an organic photoconductive film is used for the layer 561, the connection with the transistor will be the same. .

[0180] FIG. 20A illustrates an example in which a color filter or the like is added to a pixel of an imaging device according to one embodiment of the present invention. In this perspective view, cross sections of a plurality of pixels are also shown. An insulating layer 580 is formed on the layer 561 on which the device 101 is formed. For the passive layer, a silicon oxide film or the like having high transparency to visible light can be used. A silicon nitride film may be laminated as the reflection preventing film. A dielectric film such as fluorine may be laminated.

[0181] A light-shielding layer 581 may be formed on the insulating layer 580. The light-shielding layer 581 may be formed on the upper color The light-shielding layer 581 has a function of preventing the color mixing of light passing through the filter. A metal layer such as tungsten can be used. A dielectric film having a function may be laminated.

[0182] An organic resin layer 582 is provided as a planarization film on the insulating layer 580 and the light-shielding layer 581. In addition, a color filter 583 (color filters 583a, 583b, For example, R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By applying the light, a color image can be obtained.

[0183] An insulating layer 586 or the like having a light-transmitting property to visible light is provided on the color filter 583. It is possible.

[0184] As shown in FIG. 20(B), an optical conversion layer 585 is provided instead of the color filter 583. By using such a configuration, it is possible to obtain images in various wavelength regions. The imaging device may be an imaging device.

[0185] For example, if a filter that blocks light having wavelengths shorter than visible light is used for the optical conversion layer 585, infrared In addition, the optical conversion layer 585 can be used to block light having a wavelength shorter than that of near-infrared rays. If a filter is used, it can be used as a far-infrared imaging device. By using a filter that blocks light with wavelengths greater than that of visible light, it can be used as an ultraviolet imaging device. .

[0186] In addition, if a scintillator is used for the optical conversion layer 585, the radiation used in X-ray imaging devices, etc. It can be used as an imaging device to obtain an image that visualizes the intensity of radiation such as X-rays that has passed through the subject. When radiation is incident on the scintillator, it emits visible and ultraviolet light due to the photoluminescence phenomenon. The light is converted into light (fluorescence) such as rays. The light is then detected by the photoelectric conversion device 101. In addition, image data is acquired by using an imaging device with this configuration in a radiation detector or the like. That's fine.

[0187] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. These include materials that emit visible and ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C Use materials such as eF3, LiF, LiI, and ZnO dispersed in resin or ceramics. can be done.

[0188] In the photoelectric conversion device 101 using a selenium-based material, radiation such as X-rays is converted into electric charges. Since the light can be directly converted into the scintillator, a configuration can be made in which a scintillator is not required.

[0189] Also, as shown in FIG. 20(C), a microlens array 58 is formed on the color filter 583. 4 may be provided. The light passing through each lens of the microlens array 584 is incident on the The light passes through the color filter 583 and is irradiated onto the photoelectric conversion device 101. A microlens array 584 may be provided on the optical conversion layer 585 shown in FIG. 20(B).

[0190] Below we will introduce an example of a package containing an image sensor chip and a camera module. The image sensor chip can use the configuration of the imaging device described above. do.

[0191] FIG. 21(A1) is a perspective view of the top surface of a package containing an image sensor chip. The package fixes the image sensor chip 450 (see FIG. 21(A3)). The package includes a package substrate 410, a cover glass 420, and an adhesive 430 for bonding the two together. do.

[0192] FIG. 21(A2) is a perspective view of the bottom surface of the package. , and has a BGA (Ball grid array) with solder balls as bumps 440. In addition to BGA, LGA (Land grid array) and PGA (Pin Grid Array) may also be included.

[0193] FIG. 21(A3) shows a package in which the cover glass 420 and the adhesive 430 are partially omitted. Electrode pads 460 are formed on the package substrate 410. The pad 460 and the bump 440 are electrically connected via a through hole. The pads 460 are electrically connected to the image sensor chip 450 by wires 470. are.

[0194] Also, Figure 21(B1) shows a camera in which an image sensor chip is housed in a lens-integrated package. 1 is a perspective view of the top surface of a camera module. A package substrate 411 for fixing a chip 451, a lens cover 421, and a lens 43 5, etc. Also, a package substrate 411 and an image sensor chip 451 (FIG. 21 (See (B3)) is an IC that has functions such as a drive circuit for the imaging device and a signal conversion circuit. A chip 490 (see FIG. 21(B3)) is also provided, and a SiP (System in Package) is also provided. It is structured as a package.

[0195] 21(B2) is a perspective view of the appearance of the lower surface side of the camera module. The bottom and side surfaces of the package 411 are provided with lands 441 for mounting. It has a structure of a lattice no-lead package. Note that this structure is just an example. QFP (Quad flat package) and the BGA mentioned above are provided. Good too.

[0196] FIG. 21(B3) shows a model in which the lens cover 421 and the lens 435 are partially omitted. The land 441 is electrically connected to the electrode pad 461. The wire 461 is connected to the image sensor chip 451 or IC chip 490 by wire 471. are electrically connected.

[0197] By housing the image sensor chip in the package of the above type, it is possible to This makes it easier to mount image sensor chips on various semiconductor devices and electronic equipment. It is possible.

[0198] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0199] (Embodiment 3) Examples of electronic devices that can use the imaging device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproduction device equipped with a recording medium, a mobile phone, a mobile phone Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines, etc. Specific examples of these electronic devices are shown in Figures 22(A) to 22(F).

[0200] FIG. 22A shows an example of a mobile phone, which includes a housing 981, a display unit 982, and an operation button 983. , an external connection port 984, a speaker 985, a microphone 986, a camera 987, etc. The mobile phone has a touch sensor on the display unit 982. All operations, such as inputting, can be performed by touching the display 982 with a finger or a stylus. The imaging device according to one embodiment of the present invention can be used as an element for acquiring an image in the mobile phone. can be applied.

[0201] FIG. 22B shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, a camera, and the like. The display unit 912 has a touch panel function for inputting and outputting information. In addition, characters and the like can be recognized from the image acquired by the camera 919 and output from the speaker 91 3. The character can be output as voice. For image acquisition on the mobile data terminal The imaging device of one embodiment of the present invention can be applied to the above elements.

[0202] FIG. 22(C) shows a surveillance camera, which includes a support base 951, a camera unit 952, and a protective cover 9 The camera unit 952 is provided with a rotation mechanism and can be installed on the ceiling. This enables the camera unit to capture images of the entire surroundings. The imaging device according to one aspect of the invention can be applied. For example, a device with a surveillance camera function is a camera. It is also called a camera or video camera.

[0203] FIG. 22D shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, It has operation keys 974, a lens 975, a connection part 976, a speaker 977, a microphone 978, etc. The operation keys 974 and the lens 975 are provided on the first housing 971, and the display unit 97 3 is provided in the second housing 972. Elements for image acquisition in the video camera The imaging device of one embodiment of the present invention can be applied to the above.

[0204] FIG. 22(E) shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, and a microphone 964. 63, a light emitting unit 967, a lens 965, etc. The imaging device according to one embodiment of the present invention can be applied to an element for this purpose.

[0205] FIG. 22(F) shows a wristwatch-type information terminal, which includes a display unit 932, a housing / wristband 933, The display unit 932 has a touch panel for operating the information terminal. The display unit 932 and the housing / wristband 933 are flexible and can be easily attached to the body. The imaging device according to one embodiment of the present invention is used as an element for acquiring images in the information terminal. can be applied.

[0206] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. [Explanation of symbols]

[0207] 10: pixel, 10a: pixel, 10b: pixel, 10c: pixel, 11: circuit, 12: circuit, 2 1: pixel array, 22: circuit, 23: circuit, 24: circuit, 25: circuit, 26: circuit, 28 : circuit, 101: photoelectric conversion device, 102: transistor, 103: transistor, 1 04:Transistor, 105:Transistor, 106:Transistor, 107:Capacitor 108: capacitor, 109: capacitor, 110: transistor, 111: transistor Register, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 1 26: Wiring, 127: Wiring, 128: Wiring, 129: Wiring, 130: Wiring, 131: Wiring 201: gate electrode, 202: gate insulating film, 203: source region, 204: drain region, 205: source electrode, 206: drain electrode, 207: oxide semiconductor layer, 410: Package substrate, 411: package substrate, 420: cover glass, 421: lens cover 430: Adhesive, 435: Lens, 440: Bump, 441: Land, 450: Image image sensor chip, 451: image sensor chip, 460: electrode pad, 461: electrode Pad, 470: Wire, 471: Wire, 490: IC chip, 531: Conductive layer, 53 2: conductive layer, 533: conductive layer, 534: conductive layer, 535: back gate, 536: region, 537: Conductive layer, 540: Silicon substrate, 541: Insulating layer, 542: Insulating layer, 543: Insulating layer Edge layer, 545: Semiconductor layer, 546: Insulating layer, 561: Layer, 562: Layer, 563: Layer, 56 5a: layer, 565b: layer, 565c: layer, 566a: layer, 566b: layer, 566c: layer, 566d: layer, 567a: layer, 567b: layer, 567c: layer, 567d: layer, 567e: layer, 580: insulating layer, 581: light-shielding layer, 582: organic resin layer, 583: color filter, 583a: color filter, 583b: color filter, 583c: color filter, 5 84: Microlens array, 585: Optical conversion layer, 586: Insulation layer, 911: Housing, 9 12: Display unit, 913: Speaker, 919: Camera, 932: Display unit, 933: Housing and relay Strut band, 939: camera, 951: support stand, 952: camera unit, 953: protection Cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens, 967: light emitting unit, 971: housing, 972: housing, 973: display unit, 974: operation keys, 9 75: Lens, 976: Connection part, 977: Speaker, 978: Microphone, 981: Housing, 9 82: Display unit, 983: Operation buttons, 984: External connection port, 985: Speaker, 98 6: Microphone, 987: Camera

Claims

[Claim 1] a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a photoelectric conversion device, a first capacitor, and a second capacitor; the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor each have a metal oxide in a channel formation region; one of a source and a drain of the first transistor is electrically connected to one electrode of the first capacitor; one of a source and a drain of the second transistor is electrically connected to one electrode of the photoelectric conversion device; one of a source and a drain of the third transistor is electrically connected to one electrode of the photoelectric conversion device; the other of the source and the drain of the third transistor is electrically connected to the other electrode of the first capacitor, electrically connected to one electrode of the second capacitor, and electrically connected to the gate of the fourth transistor; One of the source and the drain of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor.

Images