Semiconductor device

Abstract

To provide a highly-reliable semiconductor device using an oxide semiconductor.SOLUTION: There is provided a semiconductor device that includes an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, a gate electrode layer overlapping with the oxide semiconductor layer, and a source electrode layer and a drain electrode layer which are electrically connected to the oxide semiconductor layer, where the oxide semiconductor layer includes a first region having crystal of size of 10 nm or less, and a second region overlapping the insulating layer with the first region interposed therebetween and having a crystal portion in which a c axis is aligned in a direction parallel to a normal vector of a surface of the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The invention disclosed herein relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter In particular, the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, and a drive circuit for these devices. For example, the present invention relates to a semiconductor device having an oxide semiconductor. The present invention relates to a semiconductor device, a display device, or a light-emitting device.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to all devices, including electro-optical devices, semiconductor circuits, display devices, light-emitting devices, and electronic equipment. It is a body device. [Background technology]

[0003] The technology of constructing a transistor using a semiconductor film formed on a substrate with an insulating surface is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (also known simply as display devices). It is widely applied to electronic devices such as transistors. Silicon-based semiconductor materials are widely known as the body film, but other materials with semiconductor properties are also available. Metal oxides (oxide semiconductors) that exhibit this property are attracting attention.

[0004] For example, amorphous oxides containing In, Zn, Ga, Sn, etc. are used as oxide semiconductors. A technique for fabricating a transistor is disclosed in Patent Document 1.

[0005] Although transistors using oxide semiconductors can be obtained with relative ease, However, since the oxide semiconductor film is easily amorphous and has unstable physical properties, it is difficult to ensure reliability. do.

[0006] On the other hand, a transistor using a crystalline oxide semiconductor film has a higher resistance than a transistor using an amorphous oxide semiconductor film. It has been reported that it has superior electrical properties and reliability compared to transistors (Non-patented (See Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165529 [Non-patent literature]

[0008] [Non-Patent Document 1] Shunpei Yamazaki, Jun Koyama, Yoshitaka Yamamoto and Kenji Okamoto, “Research, Development, and Application of Crystalline Oxide Semiconductor” SID 2012 DIGEST pp183-186 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a highly reliable semiconductor device that includes an oxide semiconductor. It shall be one of the following.

[0010] Another object of one embodiment of the present invention is to provide a transistor or the like with low off-state current. Another embodiment of the present invention provides a normally-off transistor or the like. Another object of one embodiment of the present invention is to provide a semiconductor device that can suppress fluctuations in threshold voltage and degradation. Another object of the present invention is to provide a transistor or the like with a small number of transistors. Another object of the present invention is to provide a semiconductor device or the like with low power consumption. Another object of the present invention is to provide a display device or the like that is easy on the eyes. Another object of the present invention is to provide a semiconductor device or the like using a transparent semiconductor layer. An object of the present invention is to provide a novel semiconductor device and the like.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0012] One embodiment of the disclosed invention is a semiconductor device including an oxide semiconductor layer and an insulating layer in contact with the oxide semiconductor layer. The oxide semiconductor layer has a first region having crystals of 10 nm or less in size, and The c-axis of the oxide semiconductor layer is aligned parallel to the normal vector of the surface of the oxide semiconductor layer. and a second region having a crystal portion. The semiconductor device has the following configuration.

[0013] One embodiment of the present invention is a semiconductor device including an oxide semiconductor layer, an insulating layer in contact with the oxide semiconductor layer, and an insulating layer including an oxide semiconductor layer. a gate electrode layer overlapping the oxide semiconductor layer; and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. and an oxide semiconductor layer having a first region having crystals of a size of 10 nm or less. The oxide semiconductor layer has a c-axis that is a normal vector of the surface of the oxide semiconductor layer. and a second region having crystal portions aligned in a direction parallel to the first region.

[0014] In the above, the first region and the second region have oxide semiconductors with different compositions. Good too.

[0015] In one embodiment of the present invention, a first insulating layer, an oxide semiconductor layer over the first insulating layer, and an oxide semiconductor layer a second insulating layer above the oxide semiconductor layer; a gate electrode layer overlapping the oxide semiconductor layer; a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer; The layer has a first region having crystals of 10 nm or less in size and a first insulating layer sandwiching the first region. The crystal part overlapping with the edge layer and whose c-axis is aligned parallel to the normal vector of the surface of the oxide semiconductor layer. a second region having a size of 10 nm or less, located between the second region and the second insulating layer; and a third region having a silicon crystal.

[0016] In the above, the first region and the second region have oxide semiconductors with different compositions. The second region and the third region may have oxide semiconductors with different compositions. Good too.

[0017] In the semiconductor device, the third region has a beam diameter of the electron beam of 1 nmφ or more and 10 nmφ or less. By focusing the electron beam at the micro-beam, multiple spots distributed circumferentially were observed. and a limited field of view using a transmission electron microscope with an electron beam diameter of 300 nm or more. Halo patterns are sometimes observed in electron diffraction.

[0018] In the semiconductor device, the first region has a beam diameter of the electron beam of 1 nmφ or more and 10 By using ultrafine electron diffraction focused to less than 100 nmφ, multiple spots distributed circumferentially were observed. It is observed that the electron beam diameter is 300 nm or more. In limited-area electron diffraction, halo patterns can sometimes be observed.

[0019] In the semiconductor device, the film density of the second region is higher than the film density of the first region. It is preferable that

[0020] In the above semiconductor device, a channel is preferably formed in the second region. [Effects of the Invention]

[0021] According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. [Brief explanation of the drawings]

[0022] [Figure 1] 1A and 1B are schematic diagrams illustrating examples of stacked layer structures included in a semiconductor device of one embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram showing the state of sputtering particles peeling off from a sputtering target. [Figure 3] FIG. 1 is a diagram illustrating a discharge state during sputtering using an AC power supply. [Figure 4] Schematic diagram showing how sputtered particles reach the deposition surface when the substrate is heated. [Figure 5] Schematic diagram showing how sputtered particles reach the deposition surface during film deposition at room temperature. [Figure 6] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 7] FIG. 1 is a flow diagram showing an example of a method for producing a sputtering target. [Figure 8]1A and 1B are schematic diagrams illustrating an example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention, and diagrams illustrating its band structure. [Figure 9] 1A to 1C illustrate structural examples of transistors according to an embodiment. [Figure 10] 1A to 1C illustrate an example of a method for manufacturing a transistor according to an embodiment. [Figure 11] 1A to 1C illustrate structural examples of transistors according to an embodiment. [Figure 12] FIG. 1 is a circuit diagram of a semiconductor device of one embodiment of the present invention. [Figure 13] 1A and 1B are a circuit diagram and a conceptual diagram of a semiconductor device of one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a structure of a display panel according to an embodiment. [Figure 15] 1A to 1C are block diagrams illustrating electronic devices according to embodiments of the present invention. [Figure 16] 1A to 1C are diagrams illustrating external views of electronic devices according to embodiments. [Figure 17] 1A and 1B are diagrams showing a cross-sectional TEM image and a microelectron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 18] 1A and 1B are diagrams showing a planar TEM image and a selected area electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 19] Schematic diagram of electron diffraction intensity distribution. [Figure 20] FIG. 2 is a diagram showing an electron microbeam diffraction pattern of a quartz glass substrate. [Figure 21] 1 shows a micro-electron diffraction pattern of a nanocrystalline oxide semiconductor layer. [Figure 22] FIG. 2 shows a cross-sectional TEM image of a nanocrystalline oxide semiconductor layer. [Figure 23] FIG. 10 shows the results of X-ray diffraction analysis of a nanocrystalline oxide semiconductor layer. [Figure 24] 10A and 10B show crystal structures of oxide semiconductor layers used in calculations. [Figure 25] Calculation results showing the effect of hydrogen addition on the crystalline state. [Figure 26] Calculation results using radial distribution functions. [Figure 27]10A and 10B are diagrams showing electron microbeam diffraction patterns of oxide semiconductor layers obtained by using an electron microbeam; [Figure 28] 10A and 10B show the results of CPM measurement of an oxide semiconductor layer. [Figure 29] 10A and 10B show the results of CPM measurement of an oxide semiconductor layer. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and those skilled in the art will recognize that the present invention can be modified in various ways. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that is done.

[0024] In each drawing described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale.

[0025] In this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking layers. It does not indicate a specific name for the purpose of

[0026] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it also includes the case where the angle is between -5° and 5°. "Perpendicular" refers to two straight lines that form an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°.

[0027] In this specification and the like, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0028] (Embodiment 1) In this embodiment, the oxide semiconductor layer included in the semiconductor device of one embodiment of the present invention will be described as follows: This will be explained with reference to FIG.

[0029] <Stacked structure of oxide semiconductor layers> FIG. 1A is a schematic diagram illustrating an example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the oxide semiconductor layer 104 is provided on and in contact with the insulating layer 102. Has.

[0030] The oxide semiconductor layer 104 has a first region 104a and an insulating layer 104b sandwiching the first region 104a. 02 and a second region 104b overlapping the first region 104a.

[0031] In the oxide semiconductor layer 104, the first region 104a and the second region 104b are bonded together. The second regions have different crystallinity. The region 104b has higher crystallinity than the first region 104a.

[0032] Examples of crystalline oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS (CA xis Aligned Crystalline Oxide Semiconductor tor), oxide semiconductors containing polycrystals (hereinafter referred to as polycrystalline oxide semiconductors), microcrystals (nanocrystals Examples of oxide semiconductors include those containing nanocrystalline oxide semiconductors (hereinafter referred to as nanocrystalline oxide semiconductors).

[0033] In the oxide semiconductor layer 104 of this embodiment, the first region 104a has a thickness of, for example, 1 nm. It contains nanocrystals (nc) with a size of 10 nm or less. It is preferable to do so.

[0034] Nanocrystalline oxide semiconductor films are denser and more compact than amorphous oxide semiconductor films. Therefore, the first region 104a of the oxide semiconductor layer 104 containing nanocrystals is an amorphous oxide. This is a region where the defect level density is reduced compared to the nitride semiconductor film.

[0035] In this specification, an amorphous oxide semiconductor film is a film in which the atomic arrangement is disordered. The oxide semiconductor film does not have a crystalline component even in a microscopic region. A typical example is an oxide semiconductor film that has a completely amorphous structure.

[0036] The c-axis of the second region 104b is a normal vector of the surface where the oxide semiconductor layer 104 is to be formed or a vector of the surface of the oxide semiconductor layer 104. It is preferable that the crystal portions are aligned in a direction parallel to the normal vector of the surface. An example of an oxide semiconductor film is a CAAC-OS film.

[0037] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is so small that it fits inside a cube with a side length of less than 100 nm. The crystal parts contained in the OS film are in the form of cubes with sides of less than 10 nm, less than 5 nm, or less than 3 nm. In addition, the CAAC-OS film was observed under a transmission electron microscope (TEM). Observed using a Transmission Electron Microscope Then, clear boundaries between the crystals, that is, grain boundaries, were confirmed. Therefore, the CAAC-OS film is susceptible to the decrease in electron mobility due to grain boundaries. It can be said that it is unlikely to occur.

[0038] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). ) It can be confirmed that the metal atoms are arranged in layers in the crystalline portion. Each layer of metal atoms is formed on the surface on which the CAAC-OS film is to be formed (the surface on which the film is to be formed) or on the unevenness of the upper surface. The CAAC-OS film has a shape reflecting this, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0039] On the other hand, the CAAC-OS film was observed by TEM from a direction approximately perpendicular to the sample surface (planar TEM). When observed, metal atoms are arranged in triangular or hexagonal shapes in the crystals. However, there is no regularity in the arrangement of metal atoms between different crystal parts. .

[0040] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It turns out that there are.

[0041] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, it is considered that the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0042] On the other hand, in-pl X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the analysis by the ane method, a peak may appear at 2θ around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. In the case of a semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is set as the axis (φ axis). When the sample is rotated and analyzed (φ scan), the crystal plane is returned to the (110) plane. In contrast, in the case of the CAAC-OS film, the 2θ is set to 56 Even when φ is fixed at around 10° and scanned, no clear peak appears.

[0043] From the above, it is concluded that the orientation of the a-axis and b-axis is irregular between different crystal regions in the CAAC-OS film. However, the c-axis is oriented and parallel to the normal vector of the surface to be formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is a plane parallel to the ab plane of the crystal.

[0044] The crystalline part is formed when the CAAC-OS film is formed or when a crystallization process such as a heat treatment is performed. As described above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed or The orientation of the CAAC-OS film is parallel to the normal vector of the top surface. When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the normal vector of the face or top surface.

[0045] The crystallinity of the CAAC-OS film may not be uniform. When the crystalline part of the CAAC-OS film is formed by crystal growth from the vicinity of the top surface, The area adjacent to the surface may have a higher degree of crystallinity than the area adjacent to the surface on which the CAAC is formed. When impurities are added to the -OS film, the crystallinity of the region where the impurities are added changes, resulting in partial In some cases, regions of different crystallinity may be formed.

[0046] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the c-axis orientation in part of the CAAC-OS film. The CAAC-OS film has a peak at 2θ around 31°. It is preferable that the chromaticity of ...

[0047] The CAAC-OS film is denser and has a higher film density than nanocrystalline oxide semiconductor films. Therefore, the second region 104b of the oxide semiconductor layer 104 containing the CAAC-OS is composed of nanocrystals. This is a region in which the defect state density is further reduced compared to the first region 104a containing crystals.

[0048] The oxide semiconductor layer 104 described in this embodiment is an oxide semiconductor layer with a reduced density of defect states. The first region 104a includes a nanocrystal, and the second region 104b includes a nanocrystal oxide semiconductor having a defect level higher than that of the nanocrystal oxide semiconductor. a second region 104b including a CAAC-OS which is a reduced-density oxide semiconductor; do.

[0049] In a semiconductor device using an oxide semiconductor layer, in order to improve reliability, a layer that functions as a channel must be formed. It is necessary to reduce defect levels in the oxide semiconductor layer and its interface. The negative shift in threshold voltage of a transistor using a conductor layer is due to the This is thought to be due to defect levels resulting from oxygen vacancies in the oxide semiconductor layer and its interface. can be done.

[0050] Therefore, as shown in this embodiment, an oxide semiconductor layer 1 including a region where defect levels are reduced is formed. By using 04 in a transistor, the transistor can be illuminated with visible light or ultraviolet light. Fluctuations in electrical characteristics can be reduced, thereby improving the reliability of the transistor. It can be done.

[0051] In addition, when the oxide semiconductor layer 104 is used in a transistor, the defect level is further reduced. The second region 104b containing the AAC-OS is applied to the main current path (channel) of the transistor. It is preferable to use the second region 104b as the main current path of the transistor. When the insulating layer 102 functions as a first region 104b, the first region 104b is formed at the interface between the insulating layer 102 and the second region 104b. By including a, the formation of a defect level at the interface between the channel and the insulating layer 102 is suppressed. It also has the effect of

[0052] In addition, in the oxide semiconductor layer 104, the second region 104b functions as a main current path. Even if the first region 104a is not connected to the first region 104b, a certain amount of current may still flow through the first region 104a. The oxide semiconductor layer 104 shown in FIG. 1 has a low density of defect states even in the first region 104a. Since the first region 104a contains the reduced nanocrystalline oxide semiconductor, In this case, reliability can be improved compared to other cases.

[0053] Note that the stacked layer structure included in the semiconductor device of one embodiment of the present invention is not limited to the structure shown in FIG. For example, as shown in FIG. 1B, This may also be configured as follows.

[0054] In FIG. 1B, the oxide semiconductor layer 114 located under the insulating layer 106 is The first region 114a containing nanocrystals is located on the second region 114b containing OS. In other words, in FIG. 1B, as in FIG. 1A, the first region 114a and the first region The insulating layer 106 has a second region 114b that overlaps the insulating layer 106 with the region 114a sandwiched therebetween.

[0055] Alternatively, as shown in FIG. 1C, the oxide semiconductor layer 124 over the insulating layer 102 and the oxide semiconductor layer 125 In the structure having the insulating layer 106 on the conductor layer 124, the oxide semiconductor layer 124 is A first region 124a including silicon crystals and a layer overlapping the insulating layer 102 with the first region 124a sandwiched therebetween. , a second region 124b including the CAAC-OS, and a layer between the second region 124b and the insulating layer 106. and a third region 124c located therebetween and including nanocrystals.

[0056] The oxide semiconductor layer 114 illustrated in FIG. 1B and the oxide semiconductor layer 124 illustrated in FIG. 1C are Similar to Fig. 1(A), it has a region containing nanocrystals and a region containing CAAC-OS, and the defect quasi-crystalline structure is Therefore, such an oxide semiconductor layer is used as a transistor. By applying this to transistors, the fluctuations in electrical characteristics can be reduced, resulting in highly reliable transistors. This can be done.

[0057] In addition, similar to FIG. 1(A), the stacked structure shown in FIG. 1(B) contains a CAAC-OS. A first region 114a containing nanocrystals is provided between a second region 114b containing nanocrystals and the insulating layer 106. In addition, in the stacked structure shown in FIG. 1(C), the second region containing CAAC-OS a first region 124a containing nanocrystals between the region 124b and the insulating layer 102; a third region including nanocrystals between the second region 124b including AC-OS and the insulating layer 106; With this structure, the oxide semiconductor layer 114 is In the transistor, when the second region 114b functions as a channel, the oxide It is possible to prevent the insulating layer 106 in contact with the semiconductor layer 114 from directly contacting the channel. In addition, in the transistor including the oxide semiconductor layer 124, the second region 124b When the insulating layer 102 or the insulating layer 103 in contact with the oxide semiconductor layer 124 functions as a channel, This can prevent the insulating layer 106 from coming into direct contact with the channel. Therefore, the formation of defect levels at the interface of the channel can be prevented. Reliability can be improved.

[0058] Note that the oxide semiconductor layers 104, 114, and 124 shown in FIG. 1 may include single crystal regions. Alternatively, it may contain amorphous regions.

[0059] For example, in FIG. 1A, the oxide semiconductor layer 104 has an amorphous layer on the second region 104b. Alternatively, in FIG. 1B, the oxide semiconductor layer 114 may include a second The layer below the region 114b may include an amorphous region.

[0060] In addition, the first region 104a and the second region 104b included in the oxide semiconductor layer 104 shown in FIG. The region 104b may include regions of different crystallinity in a single layer film, or may be a region of different crystallinity. It may also be configured by laminating different films. Unless otherwise specified, the term "region" can be read as "layer." For example, an oxide semiconductor The layer 104 is a first oxide semiconductor layer containing nanocrystals and a second oxide semiconductor layer containing CAAC-OS. It may also have a laminated structure with a compound semiconductor layer.

[0061] The oxide semiconductor layer 104 is made of a first oxide semiconductor layer containing nanocrystals and a CAAC-O In the case of a stacked structure with a second oxide semiconductor layer containing S, the first oxide semiconductor layer and the second oxide semiconductor layer The metal elements constituting the oxide semiconductor layer may be the same or different. In addition, when the same metal element is contained, the composition may be the same or different. The same applies to the oxide semiconductor layer 114 and the oxide semiconductor layer 124.

[0062] The oxide semiconductor layer described in this embodiment has a CAAC-OS layer which functions as a main current path. The oxide semiconductor has a region containing nanocrystals at the interface between the region containing nanocrystals and the insulating layer. The reliability of a transistor including the layer can be improved.

[0063] Note that the oxide semiconductor layer described in this embodiment is used as, for example, an active layer of a transistor. However, the embodiment of the present invention is not limited to this. The oxide semiconductor layer can be configured as a part of various elements. The oxide semiconductor layer shown in the embodiment can be formed as a part of a resistor element. A protection circuit can be formed using the element. The oxide semiconductor layer can also be configured as a part of the electrode of the capacitor. The capacitor can be configured as a storage capacitor in the pixel, or as a capacitive element in the driver circuit. The oxide semiconductor layer described in this embodiment can be used as a transistor When the semiconductor device is configured as a capacitor or resistor, the oxide semiconductor contained in the device In this case, the number of process steps can be reduced, which is preferable. Note that the oxide semiconductor layer described in this embodiment can be used as a capacitor or a resistor. In this case, hydrogen or the like can be introduced into the film to reduce the resistance. Therefore, when a film containing hydrogen, such as a silicon nitride film, is placed in contact with the oxide semiconductor layer described in this embodiment, In this way, the resistance value of the oxide semiconductor layer described in this embodiment can be reduced.

[0064] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0065] (Embodiment 2) In this embodiment, with respect to the formation of the crystal portion included in the oxide semiconductor layer described in Embodiment 1, 2 to 6. However, the film formation model described below is merely a consideration. It should be noted that the embodiments of the present invention are not limited to the following models. .

[0066] <Crystalline film formation model> FIG. 2(A) shows a sputtering target 1000 used in the formation of an oxide semiconductor layer. This is a schematic diagram showing how ions 1001 collide and sputtering particles 1002 peel off. In FIG. 2, the sputtering particle 1002 is a hexagonal columnar particle, and the hexagonal faces are ab When the sputtering particle is a triangular prism, the triangular surface is parallel to the a -b plane is parallel to the hexagonal surface. The direction is the c-axis (see Figure 2(B)). The same applies to the triangular prism. The grains 1002 are parallel to the ab plane, although this differs depending on the type of oxide semiconductor used. The diameter of the surface (equivalent circle diameter) is 1 nm or more and 30 nm or less, or 1 nm or more and 10 nm or less. The ions 1001 are oxygen cations. In place of the argon cation, other rare earth ions may be used. Positive ions of a gas may also be used.

[0067] By using oxygen cations as ions 1001, plasma damage during film formation is reduced. Therefore, the ions 1001 can be projected onto the surface of the sputtering target 1000. When the target 1000 collides with the surface, the crystallinity of the target 1000 decreases. can suppress the amorphization.

[0068] The detached sputtered particles 1002 are preferably positively charged. The timing at which the sputtering particles 1002 are positively charged is not particularly important. The sputtering particles 1002 may become positively charged due to exposure to the plasma, or ions 1001 may become positively charged by receiving a charge when they collide with the acid. The positive ions 1001 are charged to the side, top or bottom of the sputtered particles 1002. It may become positively charged by binding to a surface.

[0069] The sputtered particles 1002 have positive charges at the corners of the polygonal faces. By having positive charges at the corners of the shaped surface, the positive charges repel each other, maintaining the flat shape. It can be held.

[0070] In order for the corners of the polygonal faces of the sputtering particle 1002 to have a positive charge, It is preferable to use a direct current (DC) power supply. Note that a radio frequency (RF) power supply, an alternating current (AC) power supply, etc. However, RF power supplies are not suitable for sputtering, which can deposit films on large-area substrates. In addition, DC power is preferable to AC power for the following reasons: It is considered desirable.

[0071] When an AC power supply is used, adjacent targets alternately switch between cathode and anode potentials. In the period A shown in FIG. 3(A), the target 1 is turned to the cathode as shown in FIG. 3(B1). The target 2 functions as an anode. In this case, target 1 acts as the anode and target 2 acts as the cathode, as shown in Figure 3(B2). The sum of period A and period B is 20 to 50 μsec. Periods A and B are repeated at regular intervals.

[0072] When the sputtering particles 1002 are positively charged, they repel each other, However, when an AC power source is used, the electric field may momentarily Since there is a time when the charge on the sputtering particle 1002 is not applied, the charge on the sputtering particle 1002 disappears. As a result, the structure of the sputtered particles may be destroyed (see Figure 3(C)). It can be seen that using a DC power supply is preferable to using an AC power supply.

[0073] <CAAC-OS film formation> The manner in which sputtered particles are deposited on a film-forming surface will be described below with reference to FIG. FIG. 4 shows the case where the film was formed while the substrate was heated.

[0074] As shown in FIG. 4, when the substrate is heated, sputtering particles 1002 are deposited on the surface 1003 on which the film is to be formed. In this case, other sputtering particles 1002 move to an area where they are not deposited, and migration occurs. By joining the particles, they bond with the particles already deposited and accumulate. The sputtering particles 1002 are laid out with the flat surface facing upward. The c-axes of the tar- ing particles 1002 are aligned in the direction perpendicular to the deposition surface 1003, and the CAA The oxide film obtained by deposition has a uniform thickness and a uniform crystal orientation. This becomes an oxide semiconductor layer.

[0075] The CAAC-OS obtained by this mechanism has an amorphous surface, an amorphous insulating surface, and an amorphous Even the surface of a porous oxide film has high crystallinity.

[0076] <<Deposition of nanocrystalline oxide semiconductor films>> Figure 5 shows how sputtered particles accumulate on the surface of a film when the film is formed without heating the substrate. Indicates a child.

[0077] From Figure 5, when the substrate is not heated (for example, the substrate temperature is room temperature plus or minus 50°C, (or room temperature plus or minus 10°C), the sputtering particles 1002 are deposited on the surface 10 03. Therefore, the sputtering particles 1002 are already falling on the other sputtering particles. The particles 1002 are deposited in a disorderly manner. The oxide semiconductor layer thus formed will not have a uniform thickness and will have a different crystal orientation. The obtained oxide semiconductor layer has the crystallinity of the plate-like sputtered particles 1002. Since the crystal structure is maintained to a certain extent, the oxide semiconductor layer has a crystal part.

[0078] As described above, the sputtering particles 1002 are, for example, perpendicular to the plane parallel to the ab plane. The diameter is about 1 nm to 30 nm or 1 nm to 10 nm, and the film is The crystal portion contained in the compound semiconductor layer may be smaller than the sputtering particle 1002. For example, nanocrystalline oxide semiconductors having crystal portions of 10 nm or less, or 5 nm or less. It may be layered.

[0079] A nanocrystalline oxide semiconductor layer is equivalent to a film having a disordered atomic arrangement from a macroscopic perspective. Therefore, it has a wide measurement range (for example, a beam diameter larger than the sputtering particle 1002). X-ray diffraction (XRD) analysis can be used to determine the orientation. In addition, the peaks shown by the sputtering particles 1002 may not be detected. In the diffraction pattern of an electron beam with a beam diameter, a halo pattern may be observed. In this case, for example, the beam diameter of the electron beam is set to be sufficiently smaller than the sputtering particles 1002. The electron diffraction pattern obtained by measuring the nanocrystalline oxide semiconductor layer as a small diameter You can observe spots (bright points) here.

[0080] It is preferable that the film-forming surface 1003 has an insulating surface. By having this, a positive charge is generated from the sputtering particles 1002 deposited on the surface 1003 to be film-formed. However, the deposition rate of the sputtering particles 1002 is slower than the dissipation rate of the positive charge. If the rate of dissipation is slower than that of the film formation surface 1003, the film formation surface 1003 may be conductive. Surface 1003 is preferably an amorphous surface, an amorphous insulating surface.

[0081] Figure 6(A) shows the crystal structure of In-Ga-Zn oxide when viewed parallel to the ab plane of the crystal. The crystal structure after ion collision during sputtering is shown in Figure 6(B).

[0082] For example, the crystals contained in the In-Ga-Zn oxide are composed of gallium atoms or and a layer having zinc atoms and oxygen atoms, and a layer having gallium atoms or / and zinc atoms and The cleavage occurs between the layer with oxygen atoms in the negative charge and the layer with oxygen atoms in the negative charge. This is because the oxygen atoms are close to each other. This becomes:

[0083] That is, ions are deposited on the surface of a sputtering target containing In-Ga-Zn oxide crystal grains. When the electrons collide, the crystals in the In-Ga-Zn oxide are split into planes parallel to the ab plane of the crystal. A plate-shaped sputtered particle cleaved along the ab plane and having upper and lower surfaces parallel to the ab plane. peels off.

[0084] In addition, the In-Ga-Zn oxide crystal shown in Figure 6 has the following structure when viewed from the direction perpendicular to the ab plane: Since metal atoms are arranged in an equilateral triangle or hexagon, the aforementioned flat crystal grains have an internal angle of 12 It tends to become a hexagonal prism with regular hexagonal faces at 0°.

[0085] <Method for producing sputtering targets>

[0086] A method for producing the above-mentioned sputtering target will be described with reference to FIG.

[0087] In FIG. 7(A), oxide powder containing multiple metal elements is used as a sputtering target. First, in step S101, oxide powder is weighed.

[0088] Here, the oxide powder containing multiple metal elements is an oxide powder containing In, M, and Zn. The following describes the preparation of In-M-Zn oxide powder. is InO as a raw material. X Oxide powder, MO Y Oxide powder and ZnO Z Prepare oxide powder Note that X, Y, and Z are any positive numbers. For example, X is 1.5, Y is 1.5, and Z is Of course, the oxide powders mentioned above are only examples, and any suitable powders can be used to obtain the desired composition. The oxide powder can be selected appropriately. M can be Ga, Sn, Hf, Al, La, Ce, or P. r, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu. In this embodiment, an example using three kinds of oxide powders is shown, but the present invention is not limited to this. For example, This embodiment may be applied to the case where four or more kinds of oxide powders are used, or one or more kinds of oxide powders may be used. This may also be applied when two types of oxide powders are used.

[0089] Next, InO X Oxide powder, MO Y Oxide powder and ZnO Z The oxide powder is added to a predetermined mole Mix in numerical ratios.

[0090] The predetermined molar ratio is, for example, InO X Oxide powder, MO Y Oxide powder and Zn O Z The oxide powders were 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 1 :1:2, 3:1:4 or 3:1:2. By using such a molar ratio, This makes it easier to obtain a sputtering target containing a highly crystalline polycrystalline oxide.

[0091] Next, in step S102, InO mixed at a predetermined molar ratio is X Oxide powder, MO Y oxidation Powder and ZnO Z The oxide powder is subjected to the first firing to obtain In-M-Zn oxide. obtain.

[0092] The first firing is carried out in an inert atmosphere, an oxidizing atmosphere, or a reduced pressure atmosphere, and the temperature is 40 The temperature is 0°C or higher and 1700°C or lower, preferably 900°C or higher and 1500°C or lower. The time is, for example, 3 minutes or more and 24 hours or less, preferably 30 minutes or more and 17 hours or less, and more preferably The first firing may be carried out for 30 minutes or more and 5 hours or less. This suppresses unnecessary reactions other than the intended reaction, and the impurity concentration in the In-M-Zn oxide powder is Therefore, it is possible to improve the crystallinity of the In-M-Zn oxide powder. can.

[0093] The first baking may be carried out multiple times by changing the temperature and / or atmosphere. The In-M-Zn oxide powder was maintained at a first temperature in a first atmosphere, and then heated in a second atmosphere. The second temperature may be maintained. Specifically, the first atmosphere may be an inert atmosphere or a reduced pressure atmosphere. It is preferable that the second atmosphere is an oxidizing atmosphere. When reducing the impurities contained in the In-M-Zn oxide powder, This is because oxygen deficiency may occur. Therefore, the In-M obtained in the second atmosphere It is preferable to reduce oxygen vacancies in the In-M-Zn oxide. By reducing the concentration and reducing oxygen vacancies, the crystallinity of the In-M-Zn oxide powder was improved. can be increased.

[0094] Next, in step S103, the In-M-Zn oxide is crushed to obtain an In-M-Zn oxide. A powder is obtained.

[0095] The In-M-Zn oxide contains many surface structures parallel to the ab plane. The In-M-Zn oxide powder is a plate-like crystal with upper and lower surfaces parallel to the ab plane. In addition, the crystal structure of In-M-Zn oxide is hexagonal or trigonal (rhombohedral). Since the aforementioned flat crystal grains are often formed as hexagonal crystals, the internal angles of the grains are approximately 120°. They are often hexagonal prisms with square faces.

[0096] Next, the particle size of the obtained In-M-Zn oxide powder is confirmed in step S104. The average particle size of the In-M-Zn oxide powder is 3 μm or less, preferably 2.5 μm or less, and It is preferable to confirm that the particle size is 2 μm or less. Using a diameter filter, the particle size is 3 μm or less, preferably 2.5 μm or less, and more preferably Alternatively, only In-M-Zn oxide powders with a particle size of 2 μm or less may be selected. The oxide powder has a particle size of 3 μm or less, preferably 2.5 μm or less, and more preferably 2 μm or less. By selecting the following, it is possible to ensure that the average particle size of the In-M-Zn oxide powder is 3 μm or less, and It is preferably 2.5 μm or less, and more preferably 2 μm or less.

[0097] In step S104, if the average particle size of the In-M-Zn oxide powder exceeds a predetermined value, Returning to S103, the In-M-Zn oxide powder is pulverized again.

[0098] In this way, the average particle size is 3 μm or less, preferably 2.5 μm or less, and more preferably In-M-Zn oxide powder with an average particle size of 3 μm or less can be obtained. μm or less, preferably 2.5 μm or less, and more preferably 2 μm or less. By obtaining n-oxide powder, the crystal grains contained in the sputtering target to be produced later can be The particle size can be reduced.

[0099] Next, in FIG. 7(B), the In-M-Zn oxide obtained by the flowchart shown in FIG. 7(A) is The material powder is used to prepare a sputtering target.

[0100] In step S111, the In-M-Zn oxide powder is spread in a mold and molded. This means that the In-M-Zn oxide is spread evenly in the mold. Powder can be introduced and molded by applying external vibration. The oxide powder is introduced and formed into a uniform thickness using a roller or the like. In S111, a slurry of In-M-Zn oxide powder mixed with water, a dispersant, and a binder was prepared. In this case, the slurry is poured into a mold and then suctioned from the bottom of the mold. After that, the molded body after suction is subjected to a drying process. Air drying is preferable because it is less likely to cause cracks in the molded body. By heating at temperatures below 00°C, residual moisture that could not be removed by natural drying can be removed. Remove.

[0101] In-M-Zn oxide containing many plate-like grains with upper and lower surfaces parallel to the ab plane By spreading the powder in a mold and molding it, the crystal grains are aligned with the ab plane facing upwards. Therefore, by spreading and molding the obtained In-M-Zn oxide powder, a- The ratio of the surface structure of the plane parallel to the b plane can be increased. It may be made of oxide and have a rectangular or round top surface.

[0102] Next, in step S112, the In-M-Zn oxide powder is subjected to a second firing. In step S113, the In-M-Zn oxide powder that has been subjected to the second firing is subjected to the first pressure treatment. The second firing is carried out under the same conditions and conditions as the first firing to obtain plate-like In-M-Zn oxide. The second baking step can be performed by the following method. It is possible.

[0103] The first pressure treatment is sufficient if it can compress and compact the In-M-Zn oxide powder. For example, this can be done by using a weight of the same type as the mold. Alternatively, the first pressure treatment may be carried out using various known techniques. The first pressure treatment may be carried out simultaneously with the second baking.

[0104] A planarization process may be performed after the first pressure application. The planarization process may be performed by chemical mechanical polishing (CMP). Chemical Mechanical Polishing (CMP) treatment can be used. good.

[0105] The plate-like In-M-Zn oxide thus obtained becomes a highly crystalline polycrystalline oxide.

[0106] Next, in step S114, the thickness of the obtained plate-shaped In-M-Zn oxide is confirmed. If the thickness of the In-M-Zn oxide is thinner than the desired thickness, the process returns to step S111. In-M-Zn oxide powder is spread on Zn oxide and molded. When the oxide has the desired thickness, the plate-shaped In-M-Zn oxide is sputtered. The following is the case when the plate-shaped In-M-Zn oxide is thinner than the desired thickness. This article explains:

[0107] Next, in step S112, a plate-shaped In-M-Zn oxide and a plate-shaped In-M-Zn oxide are prepared. The In-M-Zn oxide powder is then subjected to a third firing. The plate-shaped In-M-Zn oxides calcined in step 3 and the I-type In-M-Zn oxides The In-M-Zn oxide powder was subjected to a second pressure treatment to obtain the In-M-Zn oxide powder. The thicker plate-like In-M-Zn oxide was obtained. The material is obtained by crystal growth using plate-shaped In-M-Zn oxide as a seed crystal, so the crystalline This results in a highly polycrystalline oxide.

[0108] The third baking may be carried out under the same conditions and by the same method as the second baking. The treatment may be carried out under the same conditions and by the same method as the first pressure treatment. This may be done simultaneously with firing.

[0109] In step S114, the thickness of the obtained plate-like In-M-Zn oxide is checked again.

[0110] Through the above process, the crystal orientation is improved and the thickness of the plate-like In-M-Zn oxide is gradually increased. It is possible.

[0111] By repeating this process of thickening the plate-like In-M-Zn oxide n times (n is a natural number), The desired thickness (t) is, for example, 2 mm or more and 20 mm or less, preferably 3 mm or more and 20 mm or less. Plate-like In-M-Zn oxide can be obtained. Used as a sputtering target.

[0112] After that, a planarization process may be performed.

[0113] The sputtering target thus obtained may be subjected to a fourth firing. The fourth firing may be carried out under the same conditions and by the same method as the first firing. Furthermore, it is possible to obtain a sputtering target containing a highly crystalline polycrystalline oxide. .

[0114] In this way, a polycrystalline oxide having a cleavage plane parallel to the ab plane and a plurality of crystal grains is obtained. and a sputtering target having a small average grain size of a plurality of crystal grains can be produced. can.

[0115] The sputtering target thus produced can be made high density. The high density of the sputtering target allows the density of the deposited film to be high. Specifically, the relative density of the sputtering target is 90% or more, 95% or more, or 9 It can be 9% or more.

[0116] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0117] (Embodiment 3) In this embodiment, another example of a stacked layer structure included in a semiconductor device of one embodiment of the present invention will be described. 8. Specifically, in this embodiment, the oxide semiconductor shown in Embodiment 1 The conductive layer includes a first oxide semiconductor layer containing nanocrystals and a second oxide semiconductor layer containing CAAC-OS. The case where an oxide semiconductor layer and a third oxide semiconductor layer containing nanocrystals are stacked will be shown as an example. vinegar.

[0118] FIG. 8A is a cross-sectional view of an oxide semiconductor layer located between insulating layers. 8(A) is a diagram showing the band structure in X1-Y1.

[0119] In the stacked structure of this embodiment, an oxide semiconductor layer 404 is provided between an insulating layer 402 and an insulating layer 410. The oxide semiconductor layer 404 includes a first oxide semiconductor layer 404a, a second oxide semiconductor layer The oxide semiconductor layer 404b and the third oxide semiconductor layer 404c are included.

[0120] The second oxide semiconductor layer 404b included in the oxide semiconductor layer 404 is a CAAC-OS The second oxide semiconductor layer 404b is an oxide semiconductor layer containing the first oxide The oxide semiconductor layer 404a and the third oxide semiconductor layer 404c have a higher electron affinity than the oxide semiconductor layer 404a and the third oxide semiconductor layer 404c. For example, the second oxide semiconductor layer 404b is made of a first oxide semiconductor. The difference is 0.07 eV or more and 1.3 eV or less than that of the oxide semiconductor layer 404a and the third oxide semiconductor layer 404c. , preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less. An oxide semiconductor layer having a large electron affinity of 0.1 eV or less is used.

[0121] The electron affinity is the energy difference between the vacuum level and the bottom of the conduction band. The energy of the conduction band minimum of the first oxide semiconductor layer 404a is Ec1, and the energy of the conduction band minimum of the second oxide semiconductor layer 404b is Ec2. The energy of the conduction band minimum of the semiconductor layer 404b is Ec2, and the energy of the conduction band minimum of the third oxide semiconductor layer 404c is Ec3. The energy of the conduction band minimum is denoted as Ec3. The energy of the upper end of the electron band is Ev1, and the energy of the upper end of the valence band of the second oxide semiconductor layer 404b is The energy of the upper end of the valence band of the third oxide semiconductor layer 404c is Ev2, and the energy of the upper end of the valence band of the third oxide semiconductor layer 404c is Ev3. Write.

[0122] In addition, the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404b included in the oxide semiconductor layer 404 At least one of the semiconductor layers 404c is an oxide semiconductor layer containing nanocrystals. In this embodiment, the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c Both of them use an oxide semiconductor layer containing nanocrystals.

[0123] The first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c are formed by adding a second oxide The oxide semiconductor layer 404b has an energy gap larger than the energy gap Eg2 of the oxide semiconductor layer 404b. For example, the energy gap E g1 and the energy gap Eg3 of the third oxide semiconductor layer 404c are 2.7 eV or more. 4.9 eV or less, preferably 3 eV or more and 4.7 eV or less, more preferably 3.2 eV or more The energy gap E g2 is smaller than Eg1 and Eg3, for example, 2.5 eV or more and 4.2 eV or less, and is preferably Preferably, the voltage is 2.8 eV or more and 3.8 eV or less, and more preferably, 3 eV or more and 3.5 eV or less. do.

[0124] In such a structure, when an electric field is applied to the gate electrode layer, the oxide semiconductor layer 404 That is, the second oxide semiconductor layer 404b, which has the smallest energy at the bottom of the conduction band, is the main path of the current. That is, the first oxide semiconductor layer 404b is formed between the second oxide semiconductor layer 404b and the insulating layer 402. The oxide semiconductor layer 404a is formed between the second oxide semiconductor layer 404b and the insulating layer 410. The third oxide semiconductor layer 404c is formed, and thus the channel of the transistor is formed. A structure in which the gate insulating layer is not in contact with the gate insulating layer can be used.

[0125] The second oxide semiconductor layer 404b is a layer formed by arranging the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404b. It is an oxide semiconductor layer having a higher film density and a lower defect state density than the oxide layer 404c. When a channel is formed in the second oxide semiconductor layer 404b, the This suppresses fluctuations in the electrical characteristics of transistors, resulting in highly reliable transistors. It can be said that:

[0126] The second oxide semiconductor layer 404b is an oxide semiconductor layer with low carrier density. For example, the second oxide semiconductor layer 404b has a carrier density of 1×10 17 pieces / cm 3 below , preferably 1 x 10 15 pieces / cm 3 or less, more preferably 1 × 10 13 pieces / cm 3 Below or less, more preferably 1 x 10 11 pieces / cm 3 The following oxide semiconductor layer is used.

[0127] The second oxide semiconductor layer 404b is an oxide semiconductor layer containing at least indium. When the second oxide semiconductor layer 404b contains at least indium, the carrier mobility (electron In addition to indium, the element M (aluminum, Preferably, the metal oxide contains gallium, yttrium, zirconium or tin.

[0128] The first oxide semiconductor layer 404a contains at least one element constituting the second oxide semiconductor layer 404b. The second oxide semiconductor layer 404 is an oxide semiconductor layer composed of two or more kinds of oxide semiconductors. The first oxide semiconductor layer 404a is formed of one or more elements constituting b. Therefore, at the interface between the second oxide semiconductor layer 404b and the first oxide semiconductor layer 404a, Therefore, the movement of carriers is not hindered at the interface. Therefore, the field effect mobility of the transistor is increased.

[0129] The first oxide semiconductor layer 404a is made of, for example, aluminum, titanium, silicon, or gallium. , germanium, yttrium, zirconium, tin, lanthanum, cerium or hafnium The oxide semiconductor layer may contain sium at a higher atomic ratio than indium. The first oxide semiconductor layer 404a preferably contains 1.5 times or more of any of the above elements as compared with indium. Preferably, an oxide semiconductor layer containing at least two times, more preferably at least three times as many, atoms as high as the oxide semiconductor layer is used. The above-mentioned elements may have a function of increasing the energy gap of the oxide semiconductor layer. In addition, since the above-mentioned elements are contained in the oxide semiconductor layer at a high atomic ratio, the oxide In some cases, the element has the function of reducing the electron affinity of the semiconductor layer. It binds more strongly to oxygen than silicon, preventing oxygen vacancies from occurring in the oxide semiconductor layer. In addition, the above-described elements have a function of shielding impurities from the oxide semiconductor layer or a function of blocking impurities from the oxide semiconductor layer. The first oxide semiconductor layer 404a may have a function of reducing the diffusion coefficient of a pure material. an oxide semiconductor layer containing the above elements at a higher atomic ratio than the second oxide semiconductor layer 404b; is.

[0130] The third oxide semiconductor layer 404c contains at least one element contained in the second oxide semiconductor layer 404b. The second oxide semiconductor layer 404 is an oxide semiconductor layer composed of two or more kinds of oxide semiconductors. The third oxide semiconductor layer 404c is formed of one or more elements constituting the oxide semiconductor layer 404b. Therefore, at the interface between the second oxide semiconductor layer 404b and the third oxide semiconductor layer 404c, Therefore, the movement of carriers is not hindered at the interface. Therefore, the field effect mobility of the transistor is increased.

[0131] The third oxide semiconductor layer 404c is formed of, for example, aluminum, titanium, silicon, or gallium. , germanium, yttrium, zirconium, tin, lanthanum, cerium or hafnium The oxide semiconductor layer may contain sium at a higher atomic ratio than indium. The third oxide semiconductor layer 404c preferably contains 1.5 times or more of any of the above elements as compared with indium. Preferably, an oxide semiconductor layer containing at least two times, more preferably at least three times as many, atoms as high as the oxide semiconductor layer is used. Note that the third oxide semiconductor layer 404c contains the above-mentioned elements. The oxide semiconductor layer contains a higher atomic ratio than b.

[0132] Note that the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c have different physical properties. Alternatively, an oxide semiconductor layer having the same physical properties as the oxide semiconductor layer may be used. good.

[0133] When the first oxide semiconductor layer 404a is an In-M-Zn oxide, Zn and oxygen are The atomic ratio of the excluded In and M is preferably less than 50 atomic % for In and less than 50 atomic % for M. more preferably, In is less than 25 atomic % and M is 75 atomic % The second oxide semiconductor layer 404b is an In-M-Zn oxide. When the atomic ratio of In and M is 25 atomic % excluding Zn and oxygen, In is preferably 25 atomic % or more, M is less than 75 atomic %, and more preferably In is 34 atomic % or more, In addition, the third oxide semiconductor layer 404c contains In-M- When it is a Zn oxide, the atomic ratio of In and M excluding Zn and oxygen is preferably 5: 0 atomic %, M is 50 atomic % or more, and more preferably In is 25 atomic % or more. omic% or less, and M is 75 atomic% or more.

[0134] The thickness of the first oxide semiconductor layer 404a is greater than or equal to 5 nm and less than or equal to 100 nm, preferably The thickness of the second oxide semiconductor layer 404b is 5 nm to 50 nm. or more and 200 nm or less, preferably 5 nm or more and 100 nm or less, and more preferably 5 nm or less The thickness of the third oxide semiconductor layer 404c is 5 nm to 10 nm. 0 nm or less, preferably 5 nm or more and 50 nm or less.

[0135] The first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c are formed by the second oxide semiconductor layer 404a. Since the oxide semiconductor layer 404b is an oxide semiconductor layer containing one or more metal elements, The compound semiconductor layer 404 can be said to be a stack of oxides that share the same main component. The oxide stack is not simply a stack of layers, but a continuous junction (here, particularly A U-shaped well structure is formed in which the energy of the conduction band edge changes continuously between layers. This is because the interface between each layer is made to have defect levels such as trap centers and recombination centers. When impurities that form junctions are present, the continuity of the energy bands is lost and the crystal structure is This is because the carriers disappear due to trapping or recombination.

[0136] To form continuous junctions, a multi-chamber deposition system equipped with a load lock chamber is required. (sputtering equipment) to continuously stack each layer without exposing it to the air. Each chamber in the sputtering equipment must contain impurities for oxide semiconductors. In order to remove as much water as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to Alternatively, a turbomolecular pump and cold trap can be combined to evacuate the chamber from the exhaust system. It is preferable to prevent gas from flowing back into the chamber.

[0137] In addition, hydrogen and oxygen vacancies that cause defect states in the oxide semiconductor layer are reduced, and oxidation In order to obtain a highly purified intrinsic semiconductor layer, it is not enough to evacuate the chamber to a high vacuum. It is also necessary to increase the purity of the sputtering gas. The gas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using gases that are highly purified up to 1000 times, it is possible to incorporate moisture and other substances into the oxide semiconductor. It can be prevented as much as possible.

[0138] The first oxide semiconductor layer 404b is provided above or below the second oxide semiconductor layer 404b. The oxide semiconductor layer 404a and the third oxide semiconductor layer 404c function as a barrier layer. The influence of defect states formed at the interface between the insulating layer and the oxide semiconductor layer 404 is The second oxide semiconductor layer 404b serves as a main carrier path for the diode. It is possible to prevent the spread of

[0139] For example, oxygen vacancies in an oxide semiconductor layer are formed within the energy gap of the oxide semiconductor. This appears as a localized level at a deep energy position. The reliability of the transistor is reduced when the ions are trapped in the oxide semiconductor layer. It is necessary to reduce oxygen vacancies in the oxide semiconductor layer 404. The oxide semiconductor layer 404b has a composition that is less likely to cause oxygen vacancies than the oxide semiconductor layer 404b. By providing the second oxide semiconductor layer 404b above and below, the second oxide semiconductor layer 404b The oxygen vacancies in 4b can be reduced.

[0140] In addition, the second oxide semiconductor layer 404b may be formed by an insulating layer having a different constituent element (for example, silicon oxide). When the semiconductor contacts a silicon film (underlying insulating layer including silicon film), an interface state is formed at the interface between the two layers. In this case, a second transistor with a different threshold voltage may be formed. However, this can cause transistors to appear and the apparent threshold voltage of the transistor to fluctuate. However, in the oxide semiconductor layer 404, the metal element constituting the second oxide semiconductor layer 404b Since the first oxide semiconductor layer 404a contains one or more elements, Therefore, an interface state is less likely to be formed at the interface between the oxide semiconductor layer 404a and the second oxide semiconductor layer 404b. By providing the first oxide semiconductor layer 404a, the threshold voltage of the transistor can be reduced. This can reduce variations in electrical characteristics.

[0141] Also, the gate insulating layer (here, assumed to be the insulating layer 410) and the second oxide semiconductor layer 40 When a channel is formed at the interface with 4b, interface scattering occurs at the interface, and the However, in the oxide semiconductor layer 404, the second oxide The third oxide semiconductor layer 404b contains one or more metal elements constituting the oxide semiconductor layer 404. Therefore, the second oxide semiconductor layer 404b and the third oxide semiconductor layer 404c are formed. At the interface, carrier scattering is unlikely to occur, which increases the field-effect mobility of the transistor. This can be done.

[0142] The first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c are oxide semiconductors. The constituent elements of the insulating layer in contact with the oxide semiconductor layer 404 are mixed into the second oxide semiconductor layer 404b, causing insulators. It also functions as a barrier layer to prevent the formation of levels due to impurities.

[0143] For example, the insulating layers 402 and 410 in contact with the oxide semiconductor layer 404 may be formed of an insulating material containing silicon. When an insulating layer is used, silicon in the insulating layer or carbon that may be incorporated into the insulating layer may be present in the first The oxide semiconductor layer 404a or the third oxide semiconductor layer 404c is formed to a depth of about several nm from the interface. When impurities such as silicon and carbon enter the oxide semiconductor layer, they can be mixed into the impurity level. The impurity level acts as a donor and generates electrons, making the material n-type.

[0144] However, the thicknesses of the first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c However, if the thickness is more than a few nm, impurities such as silicon and carbon may be mixed into the second oxide semiconductor layer. Since the impurity level does not reach 404b, the influence of the impurity level is reduced.

[0145] Here, the concentration of silicon contained in the oxide semiconductor layer is 3×10 18 / cm 3 The following is preferred: Kuha 3 x 10 17 / cm 3 The concentration of carbon in the oxide semiconductor layer is 3 or less. x10 18 / cm 3 Less than or equal to 3 x 10 17 / cm 3 The following applies. In particular, the second oxidation In order to prevent a large amount of silicon or carbon, which are group 14 elements, from being mixed into the compound semiconductor layer 404b, The first oxide semiconductor layer 404a and the third oxide semiconductor layer 404c form a carrier path. It is preferable that the second oxide semiconductor layer 404b be sandwiched or surrounded by the second oxide semiconductor layer 404b. The concentrations of silicon and carbon in the second oxide semiconductor layer 404b are higher than those in the first oxide semiconductor layer 404b. The concentrations of silicon and carbon contained in the conductor layer 404a and the third oxide semiconductor layer 404c are higher than those of the It is preferable that the temperature is lower than that.

[0146] The impurity concentration in the oxide semiconductor layer was measured using secondary ion mass spectrometry (SIMS). It can be measured by ion mass spectrometry (Ion Mass Spectrometry).

[0147] In addition, when hydrogen or moisture is included in the oxide semiconductor layer as an impurity, it creates donors and becomes n-type. Therefore, hydrogen and moisture are prevented from entering above the oxide semiconductor layer 404 from the outside. Providing a protective insulating layer (such as a silicon nitride layer) is useful for realizing a well structure. do.

[0148] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0149] (Fourth embodiment) In this embodiment, the transistor including the oxide semiconductor layer described in Embodiment 1 or 3 An example of the configuration of the transistor will be described with reference to the drawings.

[0150] <Transistor configuration example> FIG. 9A is a schematic cross-sectional view of a transistor 300. The transistor 300 is a bottom gate type transistor.

[0151] The transistor 300 includes a gate electrode layer 302 provided on a substrate 301 and a gate electrode layer 303 formed on the substrate 301 and a gate electrode layer 304 formed on the substrate 301 and a gate electrode layer 305 formed on the substrate 301 and a gate electrode layer 306 formed on the substrate 301 and a gate electrode layer 307 formed on the substrate 301 and a gate electrode layer 308 formed on the substrate 301 and a An insulating layer 303 is provided on the gate electrode layer 302, and a gate electrode layer 303 is provided on the insulating layer 303. 02, and an oxide semiconductor layer 314 provided on the top surface of the oxide semiconductor layer 314. The insulating layer 305 includes a source electrode layer 305a and a drain electrode layer 305b that are in contact with each other. 3. An insulating film covering the oxide semiconductor layer 314, the source electrode layer 305a, and the drain electrode layer 305b. An edge layer 306 and an insulating layer 307 are provided on the insulating layer 306 .

[0152] The oxide semiconductor layer 314 included in the transistor 300 is a semiconductor layer including an oxide semiconductor layer 314a and an oxide semiconductor layer 314b. The oxide semiconductor layer 314a and the oxide semiconductor layer 314b are stacked together. The boundaries of the conductor layer 314b may be unclear, so they are not shown in the drawings such as FIG. 9(A). The boundary is shown by a dashed line.

[0153] The oxide semiconductor layer 314a and the oxide semiconductor layer 314b are both crystalline oxide semiconductors. In this embodiment, the oxide semiconductor layer 314a is an oxide semiconductor layer. The oxide semiconductor layer 314b has a higher film density and a reduced defect state density. The oxide semiconductor layer 314a is preferably a CAAC-OS film. The semiconductor layer 314b is a nanocrystalline oxide semiconductor layer. In the transistor 300, the oxide semiconductor layer 314 is the same as that shown in FIG. The insulating layer 306 in the transistor 300 corresponds to the oxide semiconductor layer 114. This corresponds to the insulating layer 106 shown in FIG. 1B in Embodiment Mode 1.

[0154] The oxide semiconductor layer 314a is typically made of In-Ga oxide, In-Zn oxide, or In-M -Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) When the oxide semiconductor layer 314a is an In-M-Zn oxide, Zn and oxygen are The atomic ratio of the excluded In and M is preferably 25 atomic % or more of In and 75 atomic % or more of M. atomic %, more preferably, In is 34 atomic % or more and M is 66 atomic % or more. For example, the oxide semiconductor layer 314a has an energy gap of A material having a potential of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more is used. .

[0155] In this embodiment, the oxide semiconductor layer 314b is formed by forming the oxide semiconductor layer 314a. For example, an oxide semiconductor layer containing one or more metal elements such as In-M-Zn oxide is used. (metals such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or Hf) The oxide semiconductor layer has a higher atomic ratio of M than the oxide semiconductor layer 314a. The amount of element M is 1.5 times or more, preferably 2 times or more, than that of the oxide semiconductor layer 314a. It is preferable to use an oxide semiconductor containing the element M at an atomic ratio three times or more higher. It binds more strongly to oxygen than indium, so it has the function of suppressing oxygen deficiency. Therefore, oxygen vacancies are less likely to occur in the oxide semiconductor layer 314b than in the oxide semiconductor layer 314a. The insulating layer may be an oxide semiconductor layer.

[0156] The oxide semiconductor layer 314b is formed of In-M-Zn oxide (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd or Hf) and is more conductive than the oxide semiconductor layer 314a. It is preferable to use an oxide semiconductor whose conduction band minimum energy is close to the vacuum level. For example, the energy of the bottom of the conduction band of the oxide semiconductor layer 314b is The difference in energy from the bottom of the conduction band is 0.05 eV or more, 0.07 eV or more, or 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or It is preferable to set it to 0.4 eV or less.

[0157] For example, when the oxide semiconductor layer 314b is an In-M-Zn oxide, the components other than Zn and oxygen are The atomic ratio of In to M is preferably less than 50 atomic % for In and less than 50 atomic % for M. omic% or more, more preferably, In is less than 25 atomic% and M is 75 atomic% ic% or more.

[0158] For example, the oxide semiconductor layer 314a may have a composition of In:Ga:Zn=1:1:1 or 3:1:2. In-Ga-Zn oxide having the atomic ratio of 1000 to 10000 can be used. 4b: In:Ga:Zn=1:3:2, 1:6:4, or 1:9:6 atomic ratio In-Ga-Zn oxide can be used. The atomic ratio of the compound semiconductor layer 314b is plus or minus the above atomic ratio as an error. Includes a 20% variation.

[0159] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of the transistor, the oxide semiconductor layer 314a and the oxide semiconductor layer 31 4b carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, It is preferable to make the density and the like appropriate.

[0160] Note that in the above description, the oxide semiconductor layer 314 has a structure in which two oxide semiconductor layers are stacked. Although this is an example, a structure in which three or more oxide semiconductor layers are stacked may also be used.

[0161] "Board 301" There is no particular restriction on the material of the substrate 301, but it should be strong enough to withstand the subsequent heat treatment. Use heat-resistant materials, such as glass substrates, ceramic substrates, quartz substrates, and sapphire substrates. A ceramic substrate, a YSZ (yttria stabilized zirconia) substrate, or the like may be used as the substrate 301. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a silicon It is also possible to use a compound semiconductor substrate such as a congermanium substrate, an SOI substrate, or the like. Moreover, a substrate having a semiconductor element provided thereon may be used as the substrate 301. .

[0162] In addition, a flexible substrate such as plastic is used as the substrate 301, and the substrate is directly formed on the flexible substrate. Alternatively, the transistor 300 may be formed between the substrate 301 and the transistor 300. The peeling layer may be provided on the upper layer of the transistor. After that, it can be separated from the substrate 301 and used for transferring to another substrate. Therefore, the transistor 300 can be mounted on a substrate with low heat resistance or a flexible substrate.

[0163] <Gate electrode layer 302> The gate electrode layer 302 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above metals, or It can be formed by using a combination of alloys, etc. Also, manganese, zirconium, etc. The gate electrode layer 302 may be made of one or more metals selected from the following: It may have a single layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon single-layer structure of the film, two-layer structure with titanium film laminated on aluminum film, titanium on titanium nitride film Two-layer structure with a tungsten film laminated on a titanium nitride film, two-layer structure with a tungsten film laminated on a titanium nitride film, Two-layer structure in which a tungsten film is laminated on a titanium film or a tungsten nitride film, A three-layer structure is formed in which an aluminum film is laminated on the titanium film, and a titanium film is further formed on the aluminum film. In addition, aluminum is also used in combination with titanium, tantalum, tungsten, molybdenum, and chromium. an alloy film combining one or more metals selected from chromium, neodymium, and scandium; Alternatively, nitride films of these may be used.

[0164] The gate electrode layer 302 may be formed of indium tin oxide or indium tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide A light-transmitting conductive material such as indium tin oxide may also be used. Alternatively, the light-transmitting conductive material and the metal may be laminated together.

[0165] In addition, an In-Ga-Zn-based oxynitride semiconductor is formed between the gate electrode layer 302 and the insulating layer 303. film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride nitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN These films have a voltage of 5 eV or more, preferably 5.5 eV or more. Since the work function is larger than the electron affinity of the oxide semiconductor, The threshold voltage of the transistor used can be shifted to the positive side, For example, an In-Ga-Zn oxynitride semiconductor film can be used. When using the oxide semiconductor layer 314, the nitrogen concentration is at least higher than that of the oxide semiconductor layer 314, specifically, 7 atomic %. The above-mentioned In-Ga-Zn-based oxynitride semiconductor film is used.

[0166] <Insulating layer 303> The insulating layer 303 functions as a gate insulating film. The edge layer 303 is preferably an amorphous film.

[0167] The insulating layer 303 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Copper, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide The above may be used, and the layer may be a laminate or a single layer.

[0168] The insulating layer 303 is made of hafnium silicate (HfSiOx ), nitrogen added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide By using this, the gate leakage of the transistor can be reduced.

[0169] <<Source Electrode Layer 305a and Drain Electrode Layer 305b>> The source electrode layer 305a and the drain electrode layer 305b are formed using a conductive material such as aluminum, Titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum Single layer structure of tungsten or tungsten alloy as the main component. For example, a single layer of aluminum film containing silicon can be used. A two-layer structure in which a titanium film is laminated on an aluminum film, and a titanium film is laminated on a tungsten film Two-layer structure: a copper film laminated on a copper-magnesium-aluminum alloy film , a titanium film or a titanium nitride film, and an aluminum film overlaid on the titanium film or the titanium nitride film. A three-layer structure in which an aluminum or copper film is laminated and a titanium or titanium nitride film is formed on top of that. Structure, molybdenum film or molybdenum nitride film, and the molybdenum film or molybdenum nitride film An aluminum film or copper film is laminated on top of the film, and a molybdenum film or a nitride film is then laminated on top of that. There are three-layer structures that form a molybdenum oxide film. A transparent conductive material containing zinc may also be used.

[0170] In addition, at least the oxide semiconductor layer of the source electrode layer 305a and the drain electrode layer 305b The oxide semiconductor layer 314 is in contact with the oxide semiconductor layer 314, and oxygen vacancies are generated by removing oxygen from the oxide semiconductor layer 314. It is preferable to use a material that can form an oxide semiconductor layer 314. The carrier concentration in the affected region increases, the region becomes n-type, and the n-type region (n + layer). Therefore, the regions can act as source and drain regions. Examples of materials that can remove oxygen from the compound semiconductor layer 314 and cause oxygen vacancies include: , tungsten, titanium, etc.

[0171] Furthermore, depending on the material and thickness of the oxide semiconductor layer 314, The entire region overlapping with the source electrode layer 305a and the drain electrode layer 305b is a source region. It can also be the drain region.

[0172] The source and drain regions are formed in the oxide semiconductor layer 314, whereby the source and drain regions are formed. The contact resistance between the electrode layer 305a and the drain electrode layer 305b and the oxide semiconductor layer 314 is reduced. Therefore, the electrical characteristics of the transistor, such as the field effect mobility and the threshold voltage, can be improved. The properties can be improved.

[0173] Insulating layers 306 and 307 The insulating layer 306 is formed using an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. It is preferable that the oxide insulating film contains more oxygen than the oxygen required for the stoichiometric composition. When heated, some oxygen is released. The oxide insulating film containing the On Spectroscopy analysis showed that the amount of oxygen released, converted to oxygen atoms, was 1. 0×10 18 atoms / cm 3 or more, preferably 3.0 × 10 20 atoms / cm 3 The oxide insulating film is as described above.

[0174] The insulating layer 306 can be an insulating layer containing silicon oxide, silicon oxynitride, or the like. Cut.

[0175] The insulating layer 306 is formed to prevent the oxide semiconductor layer 31 from being damaged when the insulating layer 307 is formed later. It also functions as a membrane to mitigate damage to 4.

[0176] Alternatively, an oxide film that transmits oxygen may be provided between the insulating layer 306 and the oxide semiconductor layer 314. good.

[0177] As the oxide film that transmits oxygen, an insulating layer containing silicon oxide, silicon oxynitride, or the like is used. In this specification, the silicon oxynitride film has a composition of A silicon nitride oxide film is a film that contains more oxygen than nitrogen. This refers to a film that contains more nitrogen than oxygen.

[0178] The insulating layer 307 can be made of an insulating film having a blocking effect against oxygen, hydrogen, water, etc. By providing the insulating layer 307 over the insulating layer 306, oxygen from the oxide semiconductor layer 314 can be prevented. Therefore, the diffusion of hydrogen, water, and the like to the outside and the intrusion of hydrogen, water, and the like into the oxide semiconductor layer 314 from the outside can be prevented. Examples of insulating films that have a blocking effect against oxygen, hydrogen, water, etc. include silicon nitride, Silicon oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride Sodium, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride There is an insulating layer containing silicon etc.

[0179] Note that a channel protective film may be provided over a channel formation region of the oxide semiconductor layer 314. The channel protective film may be formed between the source electrode layer 305a and the oxide semiconductor layer 314 or between the source electrode layer 305a and the oxide semiconductor layer 314. It is also provided between the drain electrode layer 305b and the oxide semiconductor layer 314. When a channel protection film is provided, the transistor becomes a channel protection type. The protective film may be, for example, a silicon oxide film or a silicon oxynitride film. When forming a silicon oxide film or a silicon oxynitride film, the source gas is silicon. It is preferable to use a deposition gas containing silicon and an oxidizing gas. Typical examples of oxidizing gases include silane, disilane, trisilane, and fluorinated silane. Examples include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0180] <Modifications of the Transistor 300> An example of the structure of a transistor that is partially different from the transistor 300 will be described below.

[0181] Variation 1 9B is a schematic cross-sectional view of the transistor 310. The transistor 310 is an oxide It differs from the transistor 300 in the configuration of the semiconductor layers.

[0182] In the transistor 310, the oxide semiconductor layer 304 is an oxide semiconductor layer 304a. The oxide semiconductor layer 304a includes an oxide semiconductor layer 304b containing nanocrystals. In addition, the oxide semiconductor layer 304b has a film density higher than that of the oxide semiconductor layer 304a. An oxide semiconductor layer having a high conductivity and a low density of defect states is preferably used. 04b, the CAAC-OS is applied. That is, the transistor 31 of this embodiment In this example, the oxide semiconductor layer 304 is the oxide semiconductor layer 304 shown in FIG. The insulating layer 303 in the transistor 310 corresponds to the conductor layer 104. 1 corresponds to the insulating layer 102 shown in FIG. 1(A).

[0183] Note that the components of the transistor 310 other than the oxide semiconductor layer 304 are the same as those of the transistor 300 can be taken into consideration.

[0184] Variation 2 9C is a schematic cross-sectional view of the transistor 320. The transistor 320 is an oxide The transistor 300 differs from the transistor 310 in the configuration of the semiconductor layer. do.

[0185] The oxide semiconductor layer 324 included in the transistor 320 includes an oxide semiconductor layer 324a, an oxide semiconductor layer 324b, an oxide semiconductor layer 324c, an oxide semiconductor layer 324d, an oxide semiconductor layer 324e, an oxide semiconductor layer 324f, an oxide semiconductor layer 324g, an oxide semiconductor layer 324h ... The semiconductor layer 324b and the oxide semiconductor layer 324c are stacked in this order.

[0186] The oxide semiconductor layer 324a and the oxide semiconductor layer 324b are stacked over the insulating layer 303. The oxide semiconductor layer 324c is formed on the top surface of the oxide semiconductor layer 324b and on the source The insulating film 304 is provided in contact with the top surfaces and side surfaces of the electrode layer 305a and the drain electrode layer 305b.

[0187] The oxide semiconductor layer 324a and the oxide semiconductor layer 324c are oxide semiconductor layers containing nanocrystals. In addition, the oxide semiconductor layer 324b can be formed by the method described above. and an oxide semiconductor layer having a higher film density and a lower density of defect states than the oxide semiconductor layer 324c. Preferably, CAAC-OS is used for the oxide semiconductor layer 324b.

[0188] <Example of transistor manufacturing method> Next, an example of a method for manufacturing the transistor 300 illustrated in FIG. 9A will be described.

[0189] First, as shown in FIG. 10(A), a gate electrode layer 302 is formed on a substrate 301. An insulating layer 303 is formed on the electrode layer 302 .

[0190] Here, a glass substrate is used as the substrate 301 .

[0191] <<Formation of gate electrode layer>> The gate electrode layer 302 is formed by the following methods. First, a sputtering method, a CVD method, A conductive film is formed by a vapor deposition method or the like, and a photolithography is performed on the conductive film using a first photomask. A resist mask is formed by a photolithography process. The portion is etched to form a gate electrode layer 302. After that, the resist mask is removed. do.

[0192] The gate electrode layer 302 may be formed by electrolytic plating, printing, ink, or the like instead of the above-mentioned method. It may also be formed by a jet method or the like.

[0193] <<Formation of gate insulating layer>> The insulating layer 303 that functions as a gate insulating layer is formed by a sputtering method, a CVD method, a vapor deposition method, or the like. Form.

[0194] The insulating layer 303 is a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film. When forming the silicon-containing film, a deposition gas containing silicon and an oxidizing gas are used as the source gas. Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and the like. Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen dioxide.

[0195] In addition, when forming a silicon nitride film as the insulating layer 303, a two-stage formation method is used. First, a mixed gas of silane, nitrogen, and ammonia is used as a raw material gas. A first silicon nitride film with few defects is formed by the plasma CVD method using the original material. The fuel gas was changed to a mixture of silane and nitrogen, and the hydrogen concentration was low and hydrogen was not blown. By this method, a second silicon nitride film is formed. As the insulating layer 303, a silicon nitride film having few defects and a hydrogen blocking property is used. can be formed.

[0196] When a gallium oxide film is formed as the insulating layer 303, MOCVD (Metal O Formed using the Organic Chemical Vapor Deposition method It is possible.

[0197] <<Formation of oxide semiconductor layer>> Next, as shown in FIG. 10B, an oxide semiconductor layer 304 is formed over the insulating layer 303.

[0198] The oxide semiconductor layer 314 can be formed by the method described in Embodiment 2. In the embodiment, first, an oxide semiconductor containing CAAC-OS is formed on the substrate 301 while the substrate 301 is heated. The conductor layer 314a is formed, and then the substrate temperature is set to room temperature to form the oxide semiconductor layer 314b. Then, a photolithography process is performed on the oxide semiconductor layer 314b using a photomask. Next, a resist mask is formed by the process of forming an island-shaped oxide semiconductor film using the resist mask. A dielectric layer 314 is formed, and then the resist mask is removed.

[0199] When the oxide semiconductor layer 314a is formed, the substrate 301 is heated to a temperature of 150°C. The substrate temperature is preferably 200°C or higher and 350°C or lower. Note that forming the oxide semiconductor layer while the substrate 301 is kept at a high temperature is an oxidation reaction. This is effective in reducing the concentration of impurities that may be contained in the oxide semiconductor layer.

[0200] After the oxide semiconductor layer 314 is formed, excess hydrogen (including water and a hydroxyl group) contained in the film is removed. It is preferable to perform a heat treatment to remove (dehydrate or dehydrogenate) the The temperature is 300°C or higher and 700°C or lower, or lower than the distortion point of the substrate. This heat treatment can be carried out under atmospheric conditions. Some hydrogen can be removed.

[0201] Note that the heat treatment for dehydration or dehydrogenation can be performed after the formation of the oxide semiconductor layer. This may be carried out at any time during the manufacturing process of the star. The heat treatment for this purpose may be carried out multiple times, or may be carried out in combination with other heat treatments.

[0202] In heat treatment, nitrogen or rare gases such as helium, neon, and argon are mixed with water, hydrogen, etc. It is preferable that nitrogen, helium, or neon introduced into the heat treatment device is not included. The purity of the rare gas such as argon is 6N (99.9999%) or more, preferably 7N (99. 99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm or less) It is preferable to do so.

[0203] After the oxide semiconductor layer 314 is heated by the heat treatment, the heating temperature is maintained or the heating temperature is increased. While slowly cooling from the beginning, high purity oxygen gas, high purity dinitrogen monoxide gas, or ultra-dry air is added to the same furnace. The dew point was measured using a CRDS (cavity ring-down laser spectroscopy) method. In this case, the moisture content should be 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, more preferably Preferably, air (10 ppb or less) may be introduced. It is preferable that the gas does not contain oxygen, water, hydrogen, etc. The purity of the dinitrogen monoxide gas is 6N or more, preferably 7N or more (i.e., oxygen gas or dinitrogen monoxide It is preferable to keep the impurity concentration in the nitrogen gas at 1 ppm or less, preferably 0.1 ppm or less. The action of oxygen gas or nitrous oxide gas is effective in eliminating the unwanted effects of dehydration or dehydrogenation treatment. The main component material of the oxide semiconductor, which was also reduced during the process of removing the impurities, By supplying oxygen, the oxide semiconductor layer is highly purified and made into an i-type (intrinsic) oxide semiconductor layer. can be done.

[0204] In order to obtain a high-purity intrinsic oxide semiconductor, it is not enough to simply evacuate the chamber to a high vacuum. It is also necessary to increase the purity of the sputtering gas. The gas has a dew point of -40°C or less, preferably -80°C or less, more preferably -100°C or less. By using gases that are highly purified up to 1000 times, it is possible to incorporate moisture and other substances into the oxide semiconductor. It can be prevented as much as possible.

[0205] Furthermore, the dehydration or dehydrogenation treatment can remove oxygen, which is a main component material of the oxide semiconductor. Since there is a risk that the amount of The oxide semiconductor layer is doped with oxygen (at least one of oxygen radicals, oxygen atoms, and oxygen ions). ) may be introduced to supply oxygen into the film.

[0206] Oxygen is introduced into the oxide semiconductor layer that has been subjected to dehydration or dehydrogenation treatment to supply oxygen into the film. By this, the oxide semiconductor layer can be highly purified and made to be i-type (intrinsic). A transistor having a purified i-type (intrinsic) oxide semiconductor has low fluctuations in electrical characteristics. It is controlled and electrically stable.

[0207] <<Formation of Source Electrode Layer and Drain Electrode Layer>> Next, as shown in FIG. 10C, the source electrode layer 305a and the drain electrode layer 305b are Form.

[0208] A method for forming the source electrode layer 305a and the drain electrode layer 305b will be described below. A conductive film is formed by a sputtering method, a CVD method, a vapor deposition method, etc. Next, a third conductive film is formed on the conductive film. A resist mask is formed by a photolithography process using a photomask. The conductive film is partly etched using the resist mask to form the source electrode layer 305a and the The rain electrode layer 305b is formed, and then the resist mask is removed.

[0209] Note that as shown in FIG. 10C, when the conductive film is etched, the top of the oxide semiconductor layer 304 is Part of the surface may be etched and thinned.

[0210] <<Formation of insulating layer>> Next, as shown in FIG. 10D, the oxide semiconductor layer 304, the source electrode layer 305a, and the drain electrode layer 305b are An insulating layer 306 is formed on the drain electrode layer 305b, and then an insulating layer 306 is formed on the insulating layer 306. Form 7.

[0211] When a silicon oxide film or a silicon oxynitride film is formed as the insulating layer 306, the source gas As the gas, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silane include silane, disilane, trisilane, and fluorinated silane. Oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0212] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180°C or higher. The temperature is kept at 260°C or less, more preferably 200°C to 240°C, and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less, more preferably 1 The pressure is between 0.00 Pa and 200 Pa, and the electrode installed in the processing chamber is set to 0.17 W / cm 2 End 0.5W / cm 2 or less, more preferably 0.25 W / cm 2 More than 0.35W / cm 2 Below Silicon oxide film or silicon oxynitride film is formed depending on the conditions for supplying high frequency power as follows: do.

[0213] As a film formation condition, high frequency power with the above power density is supplied in a processing chamber with the above pressure. This increases the decomposition efficiency of the source gas in the plasma, increasing the number of oxygen radicals and oxidizing the source gas. As a result, the oxygen content in the oxide insulating film becomes higher than the stoichiometric ratio. However, when the substrate temperature is above this level, the bonding strength between silicon and oxygen is weak, so heating A portion of the oxygen is released, resulting in a mixture containing more oxygen than the stoichiometric composition. In this case, an oxide insulating film from which part of oxygen is released by heating can be formed.

[0214] In addition, when an oxide insulating film is provided between the oxide semiconductor layer 304 and the insulating layer 306, In the step of forming the layer 306 , the oxide insulating film serves as a protective film for the oxide semiconductor layer 304 . As a result, damage to the oxide semiconductor layer 304 is reduced while a high-frequency voltage with a high power density is applied. A force can be used to form the insulating layer 306 .

[0215] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180°C or higher. The temperature is kept at 400°C or less, more preferably 200°C to 370°C, and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is set to 20 Pa or more and 250 Pa or less, more preferably 10 The pressure is between 0 Pa and 250 Pa, and high-frequency power is supplied to the electrode installed in the processing chamber. As a result, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film. In addition, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the oxide insulation can be When the insulating layer is formed, damage to the oxide semiconductor layer 304 can be reduced.

[0216] As a source gas for the oxide insulating film, a deposition gas containing silicon and an oxidizing gas are used. Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and the like. Examples of oxidizing gases include oxygen, ozone, nitrous oxide, and dioxygen. Examples include nitrogen dioxide.

[0217] The insulating layer 307 can be formed by a sputtering method, a CVD method, or the like.

[0218] When a silicon nitride film or a silicon nitride oxide film is formed as the insulating layer 307, the raw material gas The gas used may be a deposition gas containing silicon, an oxidizing gas, or a gas containing nitrogen. Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and the like. Oxidizing gases include oxygen, ozone, nitrous oxide, and fluorinated silane. Nitrogen, etc. Nitrogen-containing gases include nitrogen and ammonia.

[0219] Through the above steps, the transistor 300 can be formed.

[0220] <Other examples of transistor configurations> Hereinafter, a top-gate transistor to which the oxide semiconductor layer of one embodiment of the present invention can be applied will be described. An example of the configuration of the data will be described below.

[0221] In the following, components having the same configuration or function as those described above will be referred to as the same. Each component is given a single reference numeral, and duplicated explanations will be omitted.

[0222] <Configuration example> FIG. 11A is a schematic cross-sectional view of a top-gate transistor 360.

[0223] The transistor 360 is an oxide semiconductor provided on a substrate 301 on which an insulating layer 351 is provided. the oxide semiconductor layer 364, the source electrode layer 305a and the drain electrode layer 305b in contact with the top surface of the oxide semiconductor layer 364, The electrode layer 305b, the oxide semiconductor layer 364, the source electrode layer 305a, and the drain electrode layer 305b The insulating layer 303 is provided over the insulating layer 303. The oxide semiconductor layer 364 is provided over the insulating layer 303. The insulating layer 303 and the gate electrode layer 302 are formed in such a manner as to form a gate electrode layer 302. An insulating layer 352 is provided over 302 .

[0224] The oxide semiconductor layer of one embodiment of the present invention is applied to the oxide semiconductor layer 364 of the transistor 360. It is possible.

[0225] For example, the oxide semiconductor layer 364 includes an oxide semiconductor layer 364a and an oxide semiconductor layer 364b. Here, the oxide semiconductor layer 364a and the oxide semiconductor layer 364c are The layer 364c is an oxide semiconductor layer containing nanocrystals. The oxide semiconductor layer 364b has a higher film density than the oxide semiconductor layer 364a and the oxide semiconductor layer 364c, and has a higher defect density than the oxide semiconductor layer 364b. An oxide semiconductor layer with a low density of states is preferably used as the oxide semiconductor layer 364b. , and CAAC-OS is applied.

[0226] The insulating layer 351 has a function of suppressing diffusion of impurities from the substrate 301 to the oxide semiconductor layer 364. For example, the insulating layer 307 may have the same structure as the insulating layer 307. 351 may not be provided if it is not necessary.

[0227] The insulating layer 352 has a blocking effect against oxygen, hydrogen, water, etc., similar to the insulating layer 307. The insulating layer 307 may be omitted if not necessary. stomach.

[0228] <<Variation>> An example of the structure of a transistor that is partially different from the transistor 360 will be described below.

[0229] FIG. 11B is a schematic cross-sectional view of the transistor 370. The transistor 370 is a source The transistor 360 differs from the transistor 360 in the configuration of the source electrode layer and the drain electrode layer. More specifically, in the transistor 370, the source electrode layer 31 is formed on the source electrode layer 305a. 6a is formed, and the drain electrode layer 316b is formed on the drain electrode layer 305b. The points are different.

[0230] As described above, the source electrode layer 305a and the drain electrode layer 305b are formed of an oxide semiconductor. When a material capable of generating oxygen vacancies in the oxide semiconductor layer is used, Oxygen vacancies occur in the areas near the contact points of the source electrode layer 305a and the drain electrode layer 305b. The region becomes n-type and acts as a source region or drain region of a transistor. It is possible.

[0231] However, when a transistor having an extremely short channel length is formed, the occurrence of the oxygen vacancies is The n-type region may extend in the direction of the transistor channel length due to the formation of In this case, the electrical characteristics of the transistor include variations in the threshold voltage and the The on-region becomes conductive, and the on-state and off-state cannot be controlled. Therefore, when forming a transistor with an extremely short channel length, the source electrode layer and the drain electrode layer It is not preferable to use a conductive material that easily bonds with oxygen for the electrode layer.

[0232] Therefore, the source electrode layer 305a and the drain electrode layer 305b shown as L1 in FIG. The distance between the first and second electrodes 5b is 0.8 μm or more, preferably 1.0 μm or more. If it is smaller, the influence of oxygen vacancies occurring in the channel formation region cannot be eliminated. The electrical characteristics of the transistor may be degraded. From the end of the source electrode layer 305a to the end of the drain electrode layer 305b, which are in contact with and face each other In Figure 11(B), the n-type region is shown schematically by a dotted line. Illustrated.

[0233] Therefore, in the transistor 370, a conductive material that is not easily bonded to oxygen is used to form the source electrode layer. The source electrode layer 316a is formed in contact with the oxide semiconductor layer 305a and the oxide semiconductor layer 364. The drain electrode layer 305b and the oxide semiconductor layer 364 are connected to each other using a conductive material that is difficult to bond with other materials. This forms the drain electrode layer 316b.

[0234] The source electrode layer 316a is formed by insulating the end of the source electrode layer 305a which is in contact with the oxide semiconductor layer 364. The drain electrode layer 316b extends in the direction of L1 beyond the oxide semiconductor layer 364. It extends in the direction L1 beyond the end of the drain electrode layer 305b.

[0235] The extending portion of the source electrode layer 316a and the extending portion of the drain electrode layer 316b are oxidized. The oxide semiconductor layer 364 is in contact with the compound semiconductor layer 364 (particularly, the oxide semiconductor layer 364c). In the transistor 370 shown in FIG. 1, the oxide semiconductor of the extension portion of the source electrode layer 316a is The oxide semiconductor of the extending portion of the drain electrode layer 316b is The distance from the tip of the electrode to the body layer 364 is the channel length, and is shown in FIG. 11(B) as L2. show.

[0236] The oxygen that is hardly bonded to the source electrode layer 316a and the drain electrode layer 316b is used to form the The conductive material may be, for example, a conductive nitride such as tantalum nitride or titanium nitride, or ruthenium. It is preferable to use ammonium or the like. In addition, conductive materials that are difficult to bond with oxygen have a tendency to diffuse oxygen. The thickness of the conductive material is preferably 5 nm or more and 500 nm or less. , more preferably 10 nm or more and 300 nm or less, and further preferably 10 nm or more and 100 nm or less. m or less.

[0237] The conductive material that is difficult to bond with oxygen is used as the source electrode layer 316a and the drain electrode layer 316b. By using the oxide semiconductor layer 364, oxygen vacancies are formed in a channel formation region of the oxide semiconductor layer 364. It is possible to suppress the formation of n-type in the channel formation region. Therefore, even a transistor with an extremely short channel length can have good electrical characteristics. That is, it is possible to set L2 to a value smaller than L1. For example, Even if 2 is 30 nm or less, it is possible to obtain good transistor electrical characteristics. When the single-crystal region included in the oxide semiconductor layer 364 has a width of 30 nm or more, In the cross section in the channel length direction, the entire region of the channel formation region is a single-crystal oxide semiconductor layer. Possible.

[0238] It should be noted that conductive nitrides such as tantalum nitride and titanium nitride may store hydrogen. Therefore, by providing a conductive nitride in contact with the oxide semiconductor layer 364, the oxide semiconductor layer 3 The hydrogen concentration in 64 can be reduced.

[0239] When forming a transistor with an extremely short channel length, fine etching such as electron beam exposure is used. A resist mask is formed using a method suitable for line processing, and etching is performed. The source electrode layer 316a and the drain electrode layer 316b may be formed by this method. If a positive resist is used as the resist mask, the exposed area can be minimized. By using this method, the channel length can be increased to 3 It is possible to fabricate transistors with a thickness of 0 nm or less.

[0240] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. can be done.

[0241] (Embodiment 5) As an example of a semiconductor device according to one embodiment of the present invention, a circuit diagram of a NOR circuit, which is a logic circuit, is shown in FIG. An example is shown in Figure 12(A), and Figure 12(B) is a circuit diagram of a NAND type circuit.

[0242] In the NOR circuit shown in FIG. 12(A), the transistor is a p-channel transistor. The transistors 801 and 802 have a channel formation region made of a semiconductor material other than an oxide semiconductor (for example, silicon The transistor is an n-channel transistor (e.g., a capacitor). The transistors 03 and 804 include an oxide semiconductor and have a structure similar to that of the transistor described in Embodiment 4. A transistor that

[0243] Transistors made of semiconductor materials such as silicon can easily operate at high speeds. A transistor using a semiconductor can retain charge for a long period of time due to its characteristics.

[0244] To miniaturize the logic circuit, n-channel transistors 803 and 8 04 is stacked on p-channel transistors 801 and 802. For example, it is preferable to form the transistors 801 and 802 using a single crystal silicon substrate. Transistors 803 and 804 are formed on the transistors 801 and 802 via an insulating layer. It is possible to achieve this.

[0245] In the NAND circuit shown in FIG. 12(B), the transistor is a p-channel transistor. The transistors 811 and 814 have channel formation regions formed of a semiconductor material other than an oxide semiconductor (for example, The transistor is an n-channel transistor, and the transistor is made of silicon. The transistors 812 and 813 include an oxide semiconductor layer and are the same as those in the transistors described in Embodiment 4. A transistor having a different structure is used.

[0246] In the NAND circuit shown in FIG. 12B, the transistors 812 and 813 are The transistor 360 has a similar configuration to the transistor 360, and the potential of the second gate electrode is controlled. For example, by connecting it to GND, the threshold voltage of the transistors 812 and 813 becomes more positive. Furthermore, the transistor can be a normally-off transistor.

[0247] In addition, similar to the NOR circuit shown in FIG. 12(A), in order to reduce the size of the logic circuit, The transistors 812 and 813 are p-channel transistors. It is preferable that it is stacked on certain transistors 811 and 812 .

[0248] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using transistors with extremely low power consumption, power consumption can be reduced sufficiently.

[0249] In addition, stacking semiconductor elements using different semiconductor materials allows for miniaturization and high integration. A semiconductor device that realizes the above and is provided with stable and high electrical characteristics, and manufacturing method of the semiconductor device A method can be provided.

[0250] Furthermore, by applying the structure of a transistor including an oxide semiconductor layer according to one embodiment of the present invention, This allows us to provide NOR and NAND circuits that are highly reliable and exhibit stable characteristics. Cut.

[0251] In this embodiment, a NOR circuit using the transistor described in Embodiment 3 and an NOR circuit using the transistor described in Embodiment 3 are used. Although an example of an AND circuit is shown, the present invention is not limited to this. The transistors shown in Embodiment 3 may be used. It is also possible to form AND circuits, OR circuits, etc.

[0252] Alternatively, the transistor described in this embodiment or another embodiment may be combined with a display element. For example, a display device can be configured by combining a display element and a device having a display element. Display devices, light emitting devices, and light emitting devices having light emitting elements are available in various forms. It can be used or have various elements. An example of a light-emitting device is an EL (electroluminescence) element (organic or inorganic material). EL elements, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green color LEDs, blue LEDs, etc.), transistors (transistors that emit light according to the current), electron emission element, liquid crystal element, electronic ink, electrophoretic element, grating light valve (GL V), plasma display (PDP), digital micromirror device (DMD), Piezoelectric ceramic displays, carbon nanotubes, etc., are made by electromagnetic interactions. Some have display media that change contrast, brightness, reflectance, transmittance, etc. An example of a display device using electron-emitting devices is an EL display. An example of such a display device is a field emission display (FED) or SED. Flat panel display (SED: Surface-conduction Elect Examples of display devices using liquid crystal elements include: LCD displays (transmissive LCDs, semi-transmissive LCDs, reflective LCDs) LCD displays include projection LCDs, direct-view LCDs, and projection LCDs. An example of a display device using electronic ink or an electrophoretic element is electronic paper. do.

[0253] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0254] (Embodiment 6) In this embodiment, the transistor described in Embodiment 3 is used, and the transistor is used in a situation where power is not supplied. However, it is possible to retain memory contents and there is no limit to the number of times it can be written. An example of this will be explained with reference to the drawings.

[0255] FIG. 13A is a circuit diagram showing the semiconductor device of this embodiment.

[0256] The transistor 260 shown in FIG. 13A is made of a semiconductor material other than an oxide semiconductor (for example, It is possible to apply transistors using silicon or the like, which makes high-speed operation easy. The transistor 262 includes an oxide semiconductor layer of one embodiment of the present invention, and is the same as the transistor described in Embodiment 4. A transistor having a structure similar to that of a transistor can be applied, and its characteristics allow for long-term This allows for charge retention over time.

[0257] It should be noted that the above transistors are all n-channel transistors. However, the transistor used in the semiconductor device described in this embodiment is a p-channel transistor. A transistor can also be used.

[0258] In FIG. 13A, the first wiring (1st Line) and the source of the transistor 260 The electrode layer is electrically connected to the second wiring (2nd Line) and the transistor 260. The drain electrode layer is electrically connected to the third wiring (3rd Line ) is electrically connected to one of the source electrode layer and the drain electrode layer of the transistor 262. The fourth line and the gate electrode layer of the transistor 262 are electrically connected to each other. The gate electrode layer of the transistor 260 and the gate electrode layer of the transistor 26 The other of the source electrode layer and the drain electrode layer is electrically connected to one of the electrodes of the capacitor 264. The fifth wiring (5th Line) and the other electrode of the capacitor 264 are electrically connected. is connected.

[0259] In the semiconductor device illustrated in FIG. 13A, the potential of the gate electrode layer of the transistor 260 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0260] The writing and retention of data will be explained. First, the potential of the fourth wiring is applied to the transistor 262 is set to a potential at which the transistor 262 is turned on, thereby turning the transistor 262 on. The potential of the third wiring is applied to the gate electrode layer of the transistor 260 and the capacitor 264. That is, a predetermined charge is applied to the gate electrode layer of the transistor 260. (Write). Here, charges that give two different potential levels (hereinafter referred to as Low-level charges) , High level charge) is given. Then, the fourth wiring The potential of the transistor 262 is set to a potential at which the transistor 262 is turned off. By setting the transistor 260 in this state, the charge applied to the gate electrode layer of the transistor 260 is held. (hold).

[0261] Since the off-state current of the transistor 262 is extremely low, the gate electrode layer of the transistor 260 The charge is retained for a long time.

[0262] Next, we will explain how to read information. When a predetermined potential (constant potential) is applied to the first wiring, Then, when an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 260 The second wiring has a different potential depending on the amount of charge held in the electrode layer. If the transistor 260 is an n-channel type, a high level is applied to the gate electrode layer of the transistor 260. The apparent threshold voltage V for a given charge th_H is the gate of transistor 260. The apparent threshold voltage V when a low-level charge is applied to the gate electrode layer th_L twist Here, the apparent threshold voltage is the voltage at which the transistor 260 is turned on. This refers to the potential of the fifth wiring required to achieve the "state." The potential of V th_H and V th_L By setting the potential V0 between the For example, in writing, High When a level charge is applied, the potential of the fifth wire is V0 (>V th_H ) and If a low level charge is applied, the transistor 260 is in the "on state." The potential of the fifth wire is V0( <V th_L ), transistor 260 remains "ON" Therefore, by observing the potential of the second wiring, the stored information can be read out.

[0263] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode layer The potential at which transistor 260 is in the "off state" regardless of V th_H Alternatively, a smaller potential may be applied to the fifth wiring. The potential at which transistor 260 is in the "on" state, i.e., V th_L Larger potential is given to the fifth wire.

[0264] FIG. 13B shows an example of a structure of a different memory device. 13(C) is a conceptual diagram showing an example of a semiconductor device. The semiconductor device shown in FIG. 13(B) will be described first, followed by the semiconductor device shown in FIG. 13(C). The location will be explained below.

[0265] In the semiconductor device shown in FIG. 13B, the bit line BL and the source voltage of the transistor 262 The gate or drain electrode of the transistor 262 is electrically connected to the word line WL. The source electrode layer is electrically connected to the source electrode or drain electrode of the transistor 262. The first terminal of the capacitor 254 is electrically connected.

[0266] The transistor 262 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 262 is turned off, the first The potential of the terminal (or the charge stored in the capacitor element 254) can be maintained for an extremely long period of time. It is possible to have it.

[0267] Next, data is written and stored in the semiconductor device (memory cell 250) shown in FIG. This section explains how to do this.

[0268] First, the potential of the word line WL is set to a potential at which the transistor 262 is turned on. The transistor 262 is turned on. As a result, the potential of the bit line BL is changed to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal (write). By setting the potential at which the transistor 262 is turned off, the capacitance The potential of the first terminal of the capacitance element 254 is held (held).

[0269] Since the off-state current of the transistor 262 is extremely low, the potential of the first terminal of the capacitor 254 ( Alternatively, the charge stored in the capacitor element 254 can be held for a long period of time.

[0270] Next, the reading of information will be described. When the transistor 262 is turned on, the floating The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0271] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, and the capacitance before charge redistribution is If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB×VB0+C×V) / (CB+C). Therefore, the state of memory cell 250 is Therefore, if the potential of the first terminal of the capacitance element 254 takes two states, V1 and V0 (V1>V0), Then, the potential of the bit line BL when the potential V1 is maintained is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained (=(CB× VB0+C×V0) / (CB+C)).

[0272] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0273] As described above, in the semiconductor device illustrated in FIG. 13B, the off-state current of the transistor 262 is extremely low. Since the capacitance is low, the charge stored in the capacitor element 254 can be maintained for a long time. In other words, refresh operations are not required, or the frequency of refresh operations can be reduced. Since it is possible to make the power consumption extremely low, it is possible to reduce the power consumption sufficiently. Even if there is no power supply, the memory contents can be retained for a long period of time. do.

[0274] Next, the semiconductor device shown in FIG. 13C will be described.

[0275] The semiconductor device shown in FIG. 13C has a memory cell shown in FIG. 13B as a memory circuit thereon. A memory cell array 251 (including a memory cell array 251a and a memory cell The peripheral circuit necessary for operating the memory cell array 251 is provided below the memory cell array 251b. The peripheral circuit 253 is electrically connected to the memory cell array 251. It continues.

[0276] By using the configuration shown in FIG. 13C, the peripheral circuit 253 is connected to the memory cell array 251. (memory cell array 251a and memory cell array 251b) Therefore, the semiconductor device can be made smaller.

[0277] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 262. It is more preferable to use silicon, germanium, silicon germanium, Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can also be used. Alternatively, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, drive circuits, etc.) that require high-speed operation. be.

[0278] In the semiconductor device shown in FIG. 13(C), two memory cell arrays 251 (memory cells In the illustrated example, a stacked memory cell array 251a and a stacked memory cell array 251b are used. The number of memory cell arrays to be stacked is not limited to this. It may also be configured as follows.

[0279] The transistor 262 includes an oxide semiconductor layer of one embodiment of the present invention in a channel formation region. By using transistors with this property, it is possible to retain memory contents for a long period of time. In other words, refresh operations are not required, or the frequency of refresh operations is extremely low. Since it is possible to make a semiconductor memory device with the smallest possible power consumption, power consumption can be reduced sufficiently. can be done.

[0280] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0281] (Embodiment 7) In this embodiment, a structure of a display panel of one embodiment of the present invention will be described with reference to FIGS. explain.

[0282] FIG. 14A is a top view of a display panel according to one embodiment of the present invention, and FIG. 14B is a top view of a display panel according to one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention is 14C is a circuit diagram for explaining a display panel according to one embodiment of the present invention. A circuit diagram for explaining a pixel circuit that can be used when an organic EL element is used as the substrate. is.

[0283] The transistor disposed in the pixel portion can be formed according to Embodiment 3. Since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be configured with transistors of the same substrate as the transistors in the pixel section. In this way, the transistor described in Embodiment 3 is used in the pixel portion and the driver circuit. This makes it possible to provide a highly reliable display device.

[0284] An example of a block diagram of an active matrix display device is shown in FIG. On a substrate 500, a pixel section 501, a first scanning line driving circuit 502, a second scanning line driving circuit The pixel portion 501 has a signal line driver circuit 503 and a signal line driver circuit 504. A plurality of scanning lines are arranged extending from the first scanning line driving circuit 502, and The scanning line driving circuit 503 is arranged to extend from the scanning line driving circuit 503. In the display area, pixels each having a display element are arranged in a matrix. The substrate 500 is a connection board for FPC (Flexible Printed Circuit) etc. It is connected to a timing control circuit (also called a controller or control IC) via .

[0285] In FIG. 14A, a first scanning line driver circuit 502, a second scanning line driver circuit 503, a signal line The driver circuit 504 is formed on the same substrate 500 as the pixel portion 501. This reduces the number of components, such as the drive circuit, that are required on the substrate 5, thereby reducing costs. 00When an external drive circuit is provided, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driving circuit is provided on the same substrate 500, the number of connections between the wirings can be reduced. Therefore, it is possible to improve reliability or yield.

[0286] <LCD panel> An example of the circuit configuration of a pixel is shown in Figure 14(B). 1 shows a pixel circuit that can be applied to the pixel.

[0287] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels in a multi-domain design to The signals applied to the electrode layers can be controlled independently.

[0288] The gate wiring 512 of the transistor 516 and the gate wiring 513 of the transistor 517 are , are separated so that different gate signals can be applied. The functional source or drain electrode layer 514 is connected to the transistor 516 and the transistor The transistors 516 and 517 are used in common. The transistors described in Section 3 can be used appropriately. This allows for a highly reliable liquid crystal display. A display panel can be provided.

[0289] A first pixel electrode layer electrically connected to the transistor 516 and a second pixel electrode layer electrically connected to the transistor 517 The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The electrode layers are separated by slits. The first pixel electrode layer extends in a V-shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0290] The gate electrode layer of the transistor 516 is connected to the gate wiring 512, and the gate electrode layer of the transistor 517 is connected to the gate wiring 512. The gate electrode layer of this gate electrode is connected to the gate wiring 513. 13, different gate signals are applied to transistors 516 and 517. By varying the orientation, the orientation of the liquid crystal can be controlled.

[0291] Also, the capacitor wiring 510, the gate insulating layer which functions as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0292] The multi-domain structure has a first liquid crystal element 518 and a second liquid crystal element 519 in one pixel. The first liquid crystal element 518 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 519 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. do.

[0293] Note that the pixel circuit shown in FIG. 14(B) is not limited to this. For example, The pixel is newly equipped with a switch, a resistor, a capacitor, a transistor, a sensor, or a logic circuit. Any of these may be added.

[0294] <Organic EL panel> Another example of the circuit configuration of a pixel is shown in FIG. 14(C). 1 shows the pixel structure of the display panel.

[0295] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are released from one of the pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, which This mechanism is what causes this type of luminescence. The element is called a current-excited light-emitting element.

[0296] FIG. 14(C) is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. can be used for the channel formation region of an n-channel transistor. The pixel circuit can be applied with digital time gray scale driving.

[0297] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, I will explain.

[0298] The pixel 520 includes a switching transistor 521, a driving transistor 522, and a light-emitting element The switching transistor 521 has a gate electrode 524 and a capacitance element 523. The source electrode layer is connected to the scanning line 526, and the first electrode (one of the source electrode layer and the drain electrode layer) is connected to the scanning line 526. ) is connected to a signal line 525, and the second electrode (the other of the source electrode layer and the drain electrode layer) is The driving transistor 522 is connected to the gate electrode layer of the driving transistor 522. The gate electrode layer is connected to a power supply line 527 via a capacitor element 523, and the first electrode is connected to the power supply line 527. 27, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 524. The second electrode of the light emitting element 524 corresponds to a common electrode 528. The common electrode 528 is formed on the same substrate. The common potential line is electrically connected to the common potential line formed on the substrate.

[0299] The switching transistor 521 and the driving transistor 522 are the same as those described in the third embodiment. This allows for the use of transistors that illuminate the display, thereby enabling highly reliable organic EL displays. A panel can be provided.

[0300] The potential of the second electrode (common electrode 528) of the light emitting element 524 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential set on the power supply line 527, for example, GND , 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 524, a current flows through the light emitting element 524, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and is at least the forward threshold. Includes low voltages.

[0301] The capacitance element 523 can be reduced by substituting the gate capacitance of the driving transistor 522. The gate capacitance of the driving transistor 522 can be omitted. A capacitance may be formed between the electrode layer and the insulating layer.

[0302] Next, a description will be given of the signal input to the driving transistor 522. In this case, the driving transistor 522 is either fully on or fully off. A video signal such as this is input to the driving transistor 522. In order to operate the drive transistor 522 in the linear region, a voltage higher than the voltage of the power supply line 527 is applied to the drive transistor 522. A signal line 525 is connected to the gate electrode layer of the transistor 522. A voltage equal to or greater than the threshold voltage Vth of the power transistor 522 is applied.

[0303] When analog gradation driving is performed, the gate electrode layer of the driving transistor 522 is connected to the light emitting element 52 A voltage equal to or greater than the sum of the forward voltage of the transistor 4 and the threshold voltage Vth of the driving transistor 522 is applied. In addition, a video signal is input so that the driving transistor 522 operates in the saturation region. A current flows through the light emitting element 524. In addition, the driving transistor 522 is operated in a saturation region. In order to achieve this, the potential of the power supply line 527 is set higher than the gate potential of the driving transistor 522. By converting the video signal into an analog signal, a current corresponding to the video signal is passed through the light emitting element 524. , analog gray scale driving can be performed.

[0304] The configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. (C) The pixel circuit includes a switch, a resistor, a capacitor, a sensor, a transistor, or a logic Circuits etc. may be added.

[0305] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0306] (Embodiment 8) In this embodiment, a semiconductor device and an electronic device including an oxide semiconductor layer according to one embodiment of the present invention will be described. The configuration will be described with reference to FIGS.

[0307] FIG. 15 shows a block diagram of an electronic device including a semiconductor device to which an oxide semiconductor layer of one embodiment of the present invention is applied. This is a block diagram.

[0308] FIG. 16 illustrates an external view of an electronic device including a semiconductor device including an oxide semiconductor layer of one embodiment of the present invention. Figure.

[0309] The electronic device shown in FIG. 15 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, and a A baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, flash memory 910, display controller 911, memory circuit 91 2. Display 913, touch sensor 919, audio circuit 917, keyboard 918, etc. It is composed of:

[0310] The application processor 906 includes a CPU 907, a DSP 908, and an interface ( The memory circuit 912 is configured by an SRAM or a DRAM. It is possible.

[0311] By applying the transistor described in Embodiment 3 to the memory circuit 912, Therefore, it is possible to provide a highly reliable electronic device capable of writing and reading data.

[0312] Furthermore, the transistor described in the third embodiment may be included in the CPU 907 or the DSP 908. By applying this to registers, etc., it is possible to write and read information with high reliability. It is possible to provide high-quality electronic equipment.

[0313] Note that when the off-leak current of the transistor described in Embodiment 3 is extremely low, A memory circuit 912 capable of retaining stored contents for a long time and having sufficiently reduced power consumption is provided. Also, during the power gating period, the state before power gating can be reviewed. It is possible to provide a CPU 907 or a DSP 908 that can store data in a register or the like. do.

[0314] The display 913 includes a display unit 914, a source driver 915, a gate driver 91 It consists of 6.

[0315] The display unit 914 has a plurality of pixels arranged in a matrix. Each pixel includes a pixel circuit. The pixel circuit is electrically connected to a gate driver 916 .

[0316] The transistor described in Embodiment 3 is used as appropriate in the pixel circuit or the gate driver 916. This makes it possible to provide a highly reliable display.

[0317] Examples of electronic devices include television sets (also known as televisions or television receivers). (hereinafter referred to as "computer monitors"), cameras such as digital cameras and digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0318] FIG. 16A shows a portable information terminal, which includes a main body 1101, a housing 1102, a display unit 110 The display unit 1103b is a touch panel. The screen can be operated by touching keyboard buttons 1104 displayed on the display unit 1103b. Of course, the display unit 1103a can be configured as a touch panel. The transistor described in Embodiment 3 may be used as a switching element in a liquid crystal panel or By fabricating an organic light-emitting panel and applying it to the display units 1103a and 1103b, reliability can be improved. It can be a highly portable information terminal.

[0319] The portable information terminal shown in FIG. 16(A) displays various information (still images, videos, text images, etc.). ), calendar, date or time display function, The ability to manipulate or edit the displayed information, and to process it using various software (programs) It can also have external connection terminals ( It may also be configured to include an earphone terminal, a USB terminal, a recording medium insertion portion, etc.

[0320] The portable information terminal shown in FIG. 16(A) can also be configured to transmit and receive information wirelessly. You can purchase and download desired book data from an electronic book server wirelessly. It is also possible to configure it in this way.

[0321] FIG. 16(B) shows a portable music player, and the main body 1021 has a display unit 1023 and an earphone. A fixing part 1022 for mounting, a speaker, an operation button 1024, an external memory slot The transistor shown in the third embodiment is used as a switching element. By manufacturing a liquid crystal panel or an organic light-emitting panel as a display unit 1023, This makes it possible to make a more reliable portable music player.

[0322] Furthermore, the portable music player shown in FIG. 16(B) has an antenna, a microphone function, and a wireless function. In addition, if you connect it to a mobile phone, you can enjoy wireless hands-free driving while driving a passenger car. Conversations are also possible via the internet.

[0323] FIG. 16C shows a mobile phone, which is composed of two housings, a housing 1030 and a housing 1031. The housing 1031 is provided with a display panel 1032, a speaker 1033, a microphone, and the like. 1034, pointing device 1036, camera lens 1037, external connection terminal The housing 1030 also includes a solar cell for charging the mobile phone. The housing 10 is provided with an antenna. The transistor described in Embodiment 3 is built in the display panel 1032. By applying this technology, a highly reliable mobile phone can be achieved.

[0324] The display panel 1032 is equipped with a touch panel, and the image displayed on the display panel 1032 is shown in FIG. The operation keys 1035 are indicated by dotted lines. It also has a boost circuit to boost the voltage required for each circuit.

[0325] For example, the power transistor used in a power supply circuit such as a booster circuit is also described in the third embodiment. The thickness of the oxide semiconductor layer of the transistor is set to 2 μm to 50 μm. It is possible.

[0326] The display direction of the display panel 1032 changes appropriately depending on the usage mode. The camera lens 1037 is located on the same surface as the camera 1032, so video calls are possible. The speaker 1033 and microphone 1034 are not limited to voice calls, but also to video calls, Recording and playback are possible. Furthermore, the housing 1030 and the housing 1031 can be slid apart. As shown in 16(C), it can be folded from the unfolded state to the overlapped state, making it suitable for carrying. This makes it possible to miniaturize the device.

[0327] The external connection terminal 1038 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. A recording medium can be inserted into the memory slot 1041 to accommodate the storage and transfer of larger amounts of data. do.

[0328] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0329] FIG. 16(D) shows an example of a television device. The television device 1050 includes: A display unit 1053 is built into the housing 1051. The display unit 1053 displays images. In addition, the CPU is built into the stand 1055 that supports the housing 1051. The transistor described in the third embodiment is applied to the display unit 1053 and the CPU. This makes it possible to provide television device 1050 with high reliability.

[0330] The television device 1050 can be operated using an operation switch provided on the housing 1051 or a separate remote control. This can be done by a remote control operator. A display unit for displaying the output information may be provided.

[0331] The television device 1050 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0332] The television device 1050 also includes an external connection terminal 1054 and a storage medium playback / recording unit 10 52, an external memory slot. An external connection terminal 1054 is provided for connecting a USB cable or the like. It can be connected to various cables, enabling data communication with a personal computer, etc. The storage medium playback / recording unit 1052 receives a disc-shaped recording medium and records the data on the recording medium. It is possible to read data stored in the external memory and write data to the recording medium. Displays images and videos stored in the external memory 1056 inserted into the slot. It is also possible to display it on the display unit 1053.

[0333] Furthermore, when the off-leak current of the transistor described in the third embodiment is extremely low, By applying transistors to external memory 1056 and CPU, power consumption is sufficiently low. This can result in a television device 1050 with reduced reliability. [Example]

[0334] In this example, nanocrystals contained in an oxide semiconductor layer according to one embodiment of the present invention were The following description will be given using the electron diffraction pattern of a crystalline oxide semiconductor film.

[0335] The nanocrystalline oxide semiconductor film was analyzed by electron diffraction (ultrafine electron diffraction) with a beam diameter of 10 nm or less. In the electron diffraction pattern using the diffractometer, a halo pattern indicating an amorphous state was observed, and a specific Unlike regular spots that show a crystalline state oriented in the plane, spots that have no directionality This is an oxide semiconductor film in which pots are observed.

[0336] Figure 17(A) shows a cross-sectional TEM (Transmission Electrical Transmission Electron Microscopy) image of the nanocrystalline oxide semiconductor film. Transmission electron microscopy (TEM) images are shown in Fig. 17( B) shows the electron diffraction pattern measured by using the electron microdiffraction at point 1 in Figure 17(A). The turn is shown in FIG. 17(C) as measured by microelectron diffraction at point 2 in FIG. 17(A). The electron diffraction pattern measured at point 3 in Figure 17(A) is shown in Figure 17(D). The electron diffraction patterns measured using sagittal beam diffraction are shown.

[0337] In FIG. 17, an In-Ga-Zn oxide film is used as an example of a nanocrystalline oxide semiconductor film. A sample was prepared by depositing a film with a thickness of 50 nm on a glass substrate. The deposition conditions for the thin film were an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. Using this, the experiment was carried out in an oxygen atmosphere (flow rate 45sccm), with a pressure of 0.4Pa and a direct current (DC) power supply of 0. The power was 5 kW and the substrate temperature was room temperature. The specimen is sliced ​​to a width of 40 nm or less (for example, 40 nm plus or minus 10 nm), and cross-sectional TEM images and polarimetry are taken. Electron diffraction patterns were obtained by microelectron diffraction.

[0338] In Figure 17(A), a transmission electron microscope (Hitachi High-Technologies Corporation, H-9000NAR Nanocrystalline oxide semiconductors photographed using a microscope with an accelerating voltage of 300 kV and a magnification of 2 million times. 17(B) to 17(D) are cross-sectional TEM images of the membrane. (Hitachi High-Technologies Corporation "HF-2000") was used, and the accelerating voltage was 200 kV. The electron diffraction pattern was obtained by ultrafine electron diffraction with a diameter of approximately 1 nm. The measurement range for ultrafine electron diffraction with a beam diameter of approximately 1 nm is 5 nm or more. It is less than 0 nmφ.

[0339] As shown in FIG. 17(B), the nanocrystalline oxide semiconductor film was analyzed by electron beam diffraction using ultrafine electron beam diffraction. In the diffraction pattern, multiple spots (bright points) arranged circumferentially are observed. Then, in the nanocrystalline oxide semiconductor film, multiple spots distributed in a circumferential (concentric) pattern were observed. Alternatively, multiple spots distributed circumferentially form multiple concentric circles. It can also be said that...

[0340] In addition, the vicinity of the interface with the quartz glass substrate in FIG. 17(D) and the nanocrystalline oxide semiconductor film In the center of the film thickness direction in Fig. 17(C), multiple circumferentially distributed In FIG. 17(C), the radius to the first circumference (main spot) The interplanar spacing (distance from the surface) was 3.88 / nm to 4.93 / nm. 0.203nm to 0.257nm.

[0341] From the ultrafine electron diffraction pattern in FIG. 17, it is clear that the nanocrystalline oxide semiconductor film has irregular plane orientation. It is also clear that the film contains a mixture of crystal parts of different sizes.

[0342] Next, Fig. 18(A) shows a planar TEM image of the nanocrystalline oxide semiconductor film. B) shows the electron diffraction pattern of the circled area in Figure 18(A) measured by selected area electron diffraction. The sagittal diffraction pattern is shown.

[0343] In FIG. 18, an In-Ga-Zn oxide film is used as an example of a nanocrystalline oxide semiconductor film. A sample was prepared by depositing a film with a thickness of 30 nm on a glass substrate. The deposition conditions for the thin film were an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. Using this, the experiment was carried out in an oxygen atmosphere (flow rate 45sccm), with a pressure of 0.4Pa and a direct current (DC) power supply of 0. The power was 5 kW and the substrate temperature was room temperature. Then, the sample was thinned and the flatness of the nanocrystalline oxide semiconductor film was measured. Area TEM images and electron diffraction patterns were obtained by electron diffraction.

[0344] In Figure 18(A), a transmission electron microscope (Hitachi High-Technologies Corporation, H-9000NAR Nanocrystalline oxide semiconductor photographed using a microscope with an accelerating voltage of 300 kV and a magnification of 500,000 times. The planar TEM photograph of the film is shown in Fig. 18(B). This is an electron beam diffraction pattern obtained by X-ray diffraction. The measurement range is 300 nmφ or more.

[0345] As shown in FIG. 18(B), in the nanocrystalline oxide semiconductor film, the measurement range was larger than that of the ultrafine electron diffraction. In the electron diffraction pattern using the selected area electron diffraction with a wide range, The observed multiple spots are absent and a halo pattern is observed.

[0346] Next, FIG. 19 shows the concept of the distribution of diffraction intensity in the electron beam diffraction patterns of FIGS. 17 and 18. FIG. 19(A) shows the electron microbeam diffraction patterns shown in FIGS. 17(B) to 17(D). 19(B) is a conceptual diagram of the distribution of diffraction intensity in the 19(C) is a schematic diagram of the distribution of diffraction intensity in a selected area electron diffraction pattern. ) is a conceptual diagram of the distribution of diffraction intensities in the electron diffraction pattern of a single crystal structure or polycrystalline structure. is.

[0347] In Figure 19, the vertical axis is the electron beam diffraction intensity (arbitrary unit) that shows the distribution of spots, etc., and the horizontal axis is Indicates the distance from the main spot.

[0348] In the single crystal structure or polycrystalline structure shown in FIG. 19(C), the interplanar orientation of the crystal part is Peaks are observed at specific distances from the main spot depending on the spacing (d value).

[0349] On the other hand, as shown in Figure 17, the electron diffraction pattern of the nanocrystalline oxide semiconductor film is The circumferential area formed by the multiple spots has a relatively large width. 19(A) shows a discrete distribution. Also, in the electron microbeam diffraction pattern, concentric circles It can be seen that there are areas of high brightness between the shaped areas, although they are not clear spots.

[0350] In addition, as shown in FIG. 19(B), the selected area electron diffraction pattern of the nanocrystalline oxide semiconductor film was The electron beam diffraction intensity distribution in the graph shows a continuous intensity distribution. A) shows the electron diffraction intensity distribution, which can be approximated by the results of a wide-area observation. It can be considered that the pots overlap and connect, resulting in a continuous intensity distribution.

[0351] As shown in FIGS. 19A to 19C, the nanocrystalline oxide semiconductor film has irregular plane orientation. The film is a film having a mixture of crystal parts of different sizes, and the crystal parts are The particles are so small that no spots are observed in the selected area electron diffraction pattern. This suggests that...

[0352] In Figure 17, where multiple spots were observed, the nanocrystalline oxide semiconductor film was 50 nm or less. The electron beam diameter is focused to 1 nm, so the measurement range is The range is 5 nm to 10 nm. is estimated to be 50 nm or less, for example, 10 nm or less, or 5 nm or less. can be.

[0353] Here, FIG. 20 shows the electron microbeam diffraction pattern on the quartz glass substrate. The measurement conditions were the same as those for the electron beam diffraction patterns shown in FIGS. 17(B) to 17(D).

[0354] As shown in FIG. 20, the quartz glass substrate having an amorphous structure does not have a specific spot. A halo pattern with continuously changing brightness is observed from the main spot. In the case of a film having an amorphous structure, even if electron diffraction is performed on a very small area, The multiple spots distributed circumferentially, which are observed in a crystalline oxide semiconductor film, are not observed. Therefore, the multiple spots distributed circumferentially as observed in Figures 17(B) to 17(D) It is confirmed that this is unique to nanocrystalline oxide semiconductor films.

[0355] Also, in FIG. 21, the beam diameter is focused to about 1 nmφ at point 2 shown in FIG. 17(A). The electron diffraction pattern is shown, which was measured after irradiating the sample with a sagittal beam for 1 minute.

[0356] The electron beam diffraction pattern shown in FIG. 21 is similar to the electron beam diffraction pattern shown in FIG. 17(C). Multiple spots distributed circumferentially were observed, and no significant differences were found between the two measurement results. This is because the crystalline portion confirmed by the electron diffraction pattern in FIG. 17(C) is an oxide semiconductor. This means that the particles have been present since the formation of the membrane, and were formed by irradiating the membrane with a focused electron beam. This means that no crystal parts are formed.

[0357] Next, Fig. 22 shows a partially enlarged view of the cross-sectional TEM image shown in Fig. 17(A). , the vicinity of point 1 (surface of nanocrystalline oxide semiconductor film) in Figure 17(A) was photographed at a magnification of 8 million times. 22(B) shows the cross-sectional TEM image observed near point 2 in FIG. 17(A) ( Cross-sectional TEM image of the central part of the nanocrystalline oxide semiconductor film in the thickness direction, observed at 8 million times magnification. is.

[0358] The cross-sectional TEM image shown in Figure 22 does not clearly show the crystal structure of the nanocrystalline oxide semiconductor film. Cannot be confirmed.

[0359] 17 and 18, the nanocrystalline acid film of the present embodiment was formed on the quartz glass substrate. The sample on which the semiconductor film was formed was analyzed by X-ray diffraction (XRD). n) was used for the analysis. Figure 23 shows the XRD spectrum obtained using the out-of-plane method. The measurement results are shown below.

[0360] In FIG. 23, the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the diffraction angle 2θ (deg. The XRD spectrum was measured using an X-ray diffractometer manufactured by Bruker AXS. -8 ADVANCE was used.

[0361] As shown in FIG. 23, a peak due to quartz is observed in the vicinity of 2θ=20 to 23°. However, no peaks due to the crystalline portions contained in the nanocrystalline oxide semiconductor film can be confirmed.

[0362] From the results of Figures 22 and 23, it can be seen that the crystalline parts contained in the nanocrystalline oxide semiconductor film are extremely fine. This suggests that it is a crystalline part.

[0363] As described above, the nanocrystalline oxide semiconductor film of this example exhibits a wide measurement range of X-ray diffraction ( XRD (X-ray diffraction) analysis detects peaks indicating orientation The electron diffraction pattern obtained by selected area electron diffraction with a wide measurement range is Therefore, the nanocrystalline oxide semiconductor film of this example has a large Visually, it can be said to be equivalent to a film with a disordered atomic arrangement. Nanocrystals can be identified by ultrafine electron diffraction with sufficiently small diameters (for example, 10 nm or less). By measuring the oxide semiconductor film, the electron microbeam diffraction pattern obtained shows spots (bright spots). ) can be observed. Therefore, the nanocrystalline oxide semiconductor film of this example has no misalignment of the plane orientation. Regular ultrafine crystal parts (for example, grain size is 10 nm or less, or 5 nm or less, or 3 nm or less) It can be assumed that the film is formed by the aggregation of nanoparticles (crystals below). The nanocrystalline region is included in the entire region of the nanocrystalline oxide semiconductor film in the thickness direction. [Example]

[0364] In this example, the influence of impurities in an oxide semiconductor layer on the crystallinity of the oxide semiconductor layer was measured. I calculated.

[0365] In this example, hydrogen is assumed as an impurity contained in the oxide semiconductor layer. The correlation between the amount of hydrogen added to the conductor layer and the order of the oxide semiconductor layer to which the hydrogen has been added was investigated. This was investigated using first-principles calculations.

[0366] The oxide semiconductor layer is In-Ga-Zn with an atomic ratio of In:Ga:Zn=1:1:1. First, the structure of 28 atoms shown in Figure 24 was optimized, and then the a-axis and The b axis was doubled to create a lattice containing 112 atoms. The structure with hydrogen (H) added to the molecule and the structure without hydrogen (H) added to the lattice containing 112 atoms. The temperature is changed for each, and the movement of each atom is calculated, and the structure with and without hydrogen added is calculated. We investigated the differences between the two.

[0367] In this example, the hydrogenated structure has an atomic ratio of In:Ga:Zn=1:1:1. In the lattice of In-Ga-Zn oxide containing 112 atoms, four hydrogen atoms (hydrogen concentration 3.45a % or 8 hydrogen atoms (hydrogen concentration 6.67 atom%) were added. The added hydrogen atoms were arranged within the lattice of a perfect crystal.

[0368] Molecular dynamics was performed on three structures: no hydrogen addition, four hydrogen atoms added, and eight hydrogen atoms added. We performed calculations to investigate the change in bonding strength and structural disorder in the In-Ga-Zn oxide due to hydrogen addition. To investigate this, an analysis was carried out using the radial distribution function. The calculation conditions are shown in Table 1. ”VASP (Vienna Ab-initio Simulation Packag) e)" was used.

[0369] [Table 1]

[0370] The calculation results are shown in Figure 25. Figure 25(A) shows the crystal structure of the In-Ga-Zn oxide in the initial state. Fig. 25(B) shows the structure of In-Ga-Zn oxide without hydrogen addition at a temperature of 2 The crystal structure after 5 psec at 500K is shown in Figure 25(C). In the In-Ga-Zn oxide with hydrogen (3.45 atom%), the temperature was increased to 25 25(D) shows the crystal structure after 5 psec at 00K. In the In-Ga-Zn oxide with 8 doped atoms (hydrogen concentration 6.67 atom%), This is the crystal structure after 5 psec when the temperature is set to 2500K.

[0371] As can be seen from Figure 25, the hydrogen-added structure has a crystal structure that is different from the structure without hydrogen addition. This indicates that the bonds in the In-Ga-Zn oxide are disordered by hydrogenation. This suggests that it is weakening.

[0372] To quantitatively evaluate the effect of hydrogen addition on the bond strength in In-Ga-Zn oxide, For the structure of psec to 5psec, elements other than hydrogen, such as In, Ga, Zn, and O, The radial distribution function was calculated for only the ion beam. The calculation results are shown in Figure 26.

[0373] As shown by the arrow in FIG. 26, the more hydrogen added, the lower the first peak becomes, and It can be seen that the valley between the first and second peaks is shallower. r) represents the probability density of another atom being present at a distance r from a certain atom. As the correlation between atoms decreases, g(r) approaches 1. Therefore, as shown in Figure 2 The results of 6 show that the addition of hydrogen weakens the bonds within the In-Ga-Zn oxide, causing the structure to collapse. This indicates that the system is becoming more susceptible to breakdown (disorder).

[0374] As described above, when the impurity (here, hydrogen) concentration in the oxide semiconductor layer increases, the oxide semiconductor It was confirmed that the order of the layers was disrupted and the crystallinity was reduced. The layer can be described as a film that contains a large amount of impurities (here, hydrogen). [Example]

[0375] In this example, oxide semiconductor layers with different crystal states were measured and compared using various methods. The results will be explained.

[0376] First, the method for preparing the measurement samples used in this example will be described below.

[0377] <Measurement sample A> The CAAC-OS layer was applied to measurement sample A. In measurement sample A, an In-Ga-Zn oxide layer was applied. The target is In:Ga:Zn=1:1:1 [atomic ratio], and the deposition gas is Argon gas was used at 30 sccm and oxygen gas at 15 sccm, and the pressure was set at 0.4 Pa. Sputtering was performed under the conditions of a substrate temperature of 400°C and a DC power of 0.5 kW. An oxide semiconductor layer was formed by a method. Note that a glass substrate was used as the substrate. After heating for 1 hour in a nitrogen atmosphere at 0°C, the oxide was formed by heating for 1 hour in an oxygen atmosphere at 450°C. A process for desorbing hydrogen contained in the semiconductor layer and a process for supplying oxygen to the oxide semiconductor layer are performed. In this manner, a measurement sample A including an oxide semiconductor layer that is a CAAC-OS layer was obtained.

[0378] Regarding measurement sample A, X-ray reflectometry (XRR) was used. The film density was measured using the sintered body, and the film density was 6.3 g / cm. 3 It was. That is, the CAAC-OS film has a high film density.

[0379] <Measurement sample B1, measurement sample B2> A nanocrystalline oxide semiconductor layer was applied to measurement samples B1 and B2. The substrate is an In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]) A target was used, and the deposition gases were argon gas at 30 sccm and oxygen gas at 15 sccm. The conditions were: pressure 0.4 Pa, substrate temperature room temperature, and DC power 0.5 kW. The oxide semiconductor layer was formed by a sputtering method using a glass substrate. As a result of the above, measurement sample B containing an oxide semiconductor layer, which is a nanocrystalline oxide semiconductor layer, I got 1.

[0380] Measurement sample B2 was prepared by heating an oxide semiconductor layer prepared in the same manner as measurement sample B1 to nitrogen at 450°C. After heating for 1 hour in a nitrogen atmosphere, the oxide semiconductor was formed by heating for 1 hour in an oxygen atmosphere at 450°C. A process for desorbing hydrogen contained in the conductor layer and a process for supplying oxygen to the oxide semiconductor layer are performed. In this way, measurement sample B2 was obtained.

[0381] The film density of measurement samples B1 and B2 was measured using X-ray reflectivity. The film density of measurement sample B1 was 5.9 g / cm3 The film density of measurement sample B2 is 6.1 g / cm 3 It was.

[0382] Therefore, it was confirmed that the film density of the oxide semiconductor film can be increased by heat treatment. Ta.

[0383] <Measurement sample C> Measurement sample C is a nanocrystalline oxide semiconductor layer, and is thinner than measurement samples B1 and B2. As described in Example 2, an oxide semiconductor layer containing a large amount of hydrogen was used. Addition of hydrogen to the oxide semiconductor layer disrupts the order of the oxide semiconductor layer, resulting in a decrease in crystallinity. Measurement sample C is a nanocrystal with even lower crystallinity than measurement samples B1 and B2. It can be said to be an oxide semiconductor layer.

[0384] Measurement sample C is In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]) The target was a mixture of argon gas and hydrogen gas (Ar:H2 = The gas pressure was set to 2.0 Pa and the substrate temperature was set to room temperature. Then, an oxide semiconductor layer was formed by sputtering under the condition of applying a DC power of 200 W. Thus, measurement sample C was obtained.

[0385] The film density of measurement sample C was measured using X-ray reflectivity. The density is 5.0 g / cm 3 It was confirmed that the film density decreased when hydrogen was added. It was.

[0386] The obtained electron microbeam diffraction patterns of measurement samples A, B1, and C are shown in FIG. FIG. 27(A) is the electron microbeam diffraction pattern of measurement sample A, and FIG. 27(B) is 27(B) is the electron microbeam diffraction pattern of the measurement sample B1, and FIG. 27(C) is the electron microbeam diffraction pattern of the measurement sample C. In the electron microbeam diffraction pattern shown in FIG. The beam diameter was converged to 1 nmφ for observation.

[0387] As shown in Figure 27, the spots in sample A, which is a high-density CAAC-OS layer, are due to the crystallinity. On the other hand, in the measurement sample C, which is a low-density nanocrystalline oxide semiconductor layer, The electron beam spot appears as a halo pattern, but some of the particles are nanocrystals. In addition, in the measurement sample B1, which is a medium-density nanocrystalline oxide semiconductor layer, The pot-shaped pattern is more clearly visible.

[0388] Therefore, it was shown that the higher the film density, the higher the crystallinity. It was shown that the lower the value, the more highly crystalline the film obtained.

[0389] In addition, the localized levels (defect levels) of the obtained measurement samples A, B1, and B2 are Here, the oxide semiconductor layer was subjected to CPM (Constant Photocurrent Measuring The results of the evaluation using the ent method are explained below.

[0390] In the CPM measurement, a photoelectric conversion was performed while a voltage was applied between a pair of electrodes placed in contact with the oxide semiconductor layer. The amount of light irradiated onto the sample surface between the terminals is adjusted so that the current value is constant, and the desired wavelength range is obtained. The extinction coefficient was derived from the amount of irradiated light.

[0391] The absorption coefficient due to the band tail was removed from the absorption coefficient obtained by CPM measurement of sample A. The absorption coefficient, i.e., the absorption coefficient due to defects, is shown in Figure 28. The absorption coefficient obtained by measuring the band tail is subtracted from the absorption coefficient due to defects. The resulting absorption coefficient is shown in Figure 29(A). The absorption coefficient obtained by subtracting the absorption coefficient due to the band tail from the absorption coefficient, i.e., the absorption coefficient due to defects The numbers are shown in Figure 29(B).

[0392] 28 and 29, the horizontal axis represents the absorption coefficient, and the vertical axis represents the light energy. 28 and 29, the lower end of the conduction band of the oxide semiconductor layer is set to 0 eV, and the The upper end of the band is set to 3.15 eV. In Figures 28 and 29, the curves represent the relationship between the absorption coefficient and the photon energy. This curve shows the relationship between energy and corresponds to the defect level.

[0393] In the curve shown in Figure 28, the absorption coefficient due to the defect level is 5.86 × 10 -4 cm -1 in That is, the CAAC-OS film has an absorption coefficient due to defect levels of 1×10 -3 / cm , preferably 1 x 10 -4 / cm, which means that the film has a low defect level density.

[0394] From Figure 29(A), the absorption coefficient due to the defect level of the measurement sample B1 is 5.28 × 10 -1 cm -1 From FIG. 29(B), the absorption coefficient due to the defect level of the measurement sample B2 was 1.75 x10 -2 cm -1 Therefore, the defects contained in the oxide semiconductor layer were removed by the heat treatment. can be reduced.

[0395] Based on the results obtained above, we have classified the crystalline state of oxide semiconductors (referred to as OS) and A comparison with silicon (denoted as Si) is shown in Table 2.

[0396] [Table 2]

[0397] As shown in Table 2, the crystalline state of oxide semiconductors includes, for example, amorphous oxide semiconductors (aO S, a-OS:H), microcrystalline oxide semiconductors (nc-OS, μc-OS), polycrystalline oxide semiconductors Conductor (polycrystalline OS), continuous crystalline oxide semiconductor (CAAC-OS), single crystal oxide semiconductor ( The crystalline state of silicon can be classified into the following types: As such, amorphous silicon (a-Si and a-Si:H), microcrystalline silicon (nc-Si, μ c-Si), polycrystalline silicon (polycrystalline Si), continuous crystalline silicon (CG (Continu Examples include single grain silicon, and single crystal silicon (single crystal Si).

[0398] For oxide semiconductors in each crystalline state, electron beams were focused to a beam diameter of 10 nm or less. When electron beam diffraction (ultrafine electron beam diffraction) is performed using In amorphous oxide semiconductors, a halo pattern (halo In the case of a microcrystalline oxide semiconductor, spots are observed. In the polycrystalline oxide semiconductor, spots and / or ring patterns are observed. In the case of a continuous crystal oxide semiconductor, spots are observed. In the case of a single crystal oxide semiconductor, , a spot is observed.

[0399] In addition, from the ultrafine electron diffraction pattern, the crystal part of the microcrystalline oxide semiconductor is nanometer (n The diameter of the polycrystalline oxide semiconductor is in the range of 1000 to 1500 μm. It can be seen that there are grain boundaries between the crystalline parts, and the boundaries are discontinuous. It can be seen that the conductor has no observable boundaries between the crystalline regions, and is continuously connected.

[0400] The density of an oxide semiconductor in each crystalline state will be described. The density of an amorphous oxide semiconductor is The density of a microcrystalline oxide semiconductor is low. The density of a continuous crystalline oxide semiconductor is medium. That is, the density of the continuous crystal oxide semiconductor is higher than that of the microcrystalline oxide semiconductor. The density of the semiconductor is higher than that of an amorphous oxide semiconductor.

[0401] In addition, the defect density (DOS) present in the oxide semiconductor in each crystalline state is The characteristics of amorphous oxide semiconductors are explained below. Amorphous oxide semiconductors have a high DOS. Oxide semiconductors have a slightly higher DOS. Continuous crystal oxide semiconductors have a lower DOS. Single crystal oxide Semiconductors have extremely low DOS. That is, single-crystal oxide semiconductors have a lower DOS than continuous-crystal oxide semiconductors. The OS is low, and continuous crystalline oxide semiconductors have a lower DOS than microcrystalline oxide semiconductors. The DOS of amorphous semiconductors is lower than that of amorphous oxide semiconductors.

[0402] In the oxide semiconductor layer according to one embodiment of the present invention, a continuous crystalline oxide semiconductor having a low DOS is used as the main current source. The interface between the insulating layer and the channel contains a DO layer rather than an amorphous layer. Therefore, a transistor including the oxide semiconductor layer This makes it possible to make the transistor highly reliable. [Explanation of symbols]

[0403] 102 Insulating layer 104 Oxide semiconductor layer 104a area 104b area 106 Insulating layer 114 Oxide semiconductor layer 114a area 114b area 124 Oxide semiconductor layer 124a area 124b area 124c area 250 memory cells 251 Memory Cell Array 251a Memory Cell Array 251b memory cell array 253 Peripheral Circuits 254 Capacitor 260 transistors 262 transistors 264 Capacitive Element 300 transistors 301 Substrate 302 gate electrode layer 303 Insulation Layer 304 Oxide semiconductor layer 304a Oxide semiconductor layer 304b Oxide semiconductor layer 305a Source electrode layer 305b Drain electrode layer 306 Insulation Layer 307 Insulation Layer 310 Transistor 314 Oxide semiconductor layer 314a Oxide semiconductor layer 314b Oxide semiconductor layer 316a Source electrode layer 316b Drain electrode layer 320 transistors 324 Oxide semiconductor layer 324a Oxide semiconductor layer 324b Oxide semiconductor layer 324c Oxide semiconductor layer 351 Insulating Layer 352 Insulation Layer 360 Transistor 364 Oxide semiconductor layer 364a Oxide semiconductor layer 364b Oxide semiconductor layer 364c Oxide semiconductor layer 370 transistors 402 Insulating layer 404 Oxide semiconductor layer 404a Oxide semiconductor layer 404b Oxide semiconductor layer 404c Oxide semiconductor layer 410 Insulating layer 500 boards 501 Pixel unit 502 Scanning line driving circuit 503 Scanning line driving circuit 504 Signal line driver circuit 510 Capacitance wiring 512 Gate wiring 513 Gate wiring 514 Drain electrode layer 516 Transistor 517 Transistor 518 Liquid crystal element 519 Liquid crystal element 520 pixels 521 Switching Transistor 522 Drive transistor 523 Capacitor 524 Light-emitting element 525 signal line 526 scan lines 527 Power line 528 Common electrode 801 transistors 802 transistors 803 Transistor 804 transistor 811 Transistor 812 transistors 813 Transistor 814 transistors 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 Memory Circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Voice Circuit 918 keyboard 919 Touch Sensor 1000 Sputtering Targets 1001 AEON 1002 Sputtering particles 1003 Film-forming surface 1021 Main Unit 1022 Fixed part 1023 Display section 1024 operation buttons 1025 external memory slots 1030 Case 1031 Case 1032 Display Panel 1033 Speaker 1034 Microphone 1035 Operation Key 1036 Pointing Device 1037 Camera Lenses 1038 External connection terminal 1040 solar cell 1041 External memory slot 1050 Television Equipment 1051 Case 1052 Storage media playback and recording unit 1053 Display section 1054 External connection terminal 1055 Stand 1056 external memory 1101 Main unit 1102 Case 1103a Display section 1103b Display section 1104 Keyboard Buttons

Claims

1. a first conductive layer that functions as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region in contact with a top surface of the first insulating layer and a region overlapping with the first conductive layer with the first insulating layer interposed therebetween; a second conductive layer having a region located over the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region located over the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor; a second insulating layer having a region located on the second conductive layer and a region located on the third conductive layer; the first insulating layer comprises silicon oxide; the second insulating layer comprises silicon oxide; the oxide semiconductor layer has a stacked structure of a first oxide semiconductor layer having a region in contact with an upper surface of the first insulating layer and a second oxide semiconductor layer having a region located above the first oxide semiconductor layer; the first oxide semiconductor layer has a region in which a plurality of circumferentially distributed spots are observed in electron beam diffraction using an electron beam having a diameter of 10 nmφ or less; the second oxide semiconductor layer has a crystal part having a c-axis orientation, the oxide semiconductor layer has a region in which the hydrogen concentration of the second oxide semiconductor layer is lower than the hydrogen concentration of the first oxide semiconductor layer; the first oxide semiconductor layer contains indium and gallium; the second oxide semiconductor layer contains indium and gallium, an atomic ratio of gallium to indium in the first oxide semiconductor layer and an atomic ratio of gallium to indium in the second oxide semiconductor layer are different from each other.

2. a first conductive layer that functions as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region in contact with a top surface of the first insulating layer and a region overlapping with the first conductive layer with the first insulating layer interposed therebetween; a second conductive layer having a region located over the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region located over the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor; a second insulating layer having a region located on the second conductive layer, a region located on the third conductive layer, and a region in contact with a top surface of the oxide semiconductor layer; the first insulating layer comprises silicon oxide; the second insulating layer comprises silicon oxide; the oxide semiconductor layer has a stacked structure of a first oxide semiconductor layer having a region in contact with an upper surface of the first insulating layer and a second oxide semiconductor layer having a region located above the first oxide semiconductor layer; the first oxide semiconductor layer has a region in which a plurality of circumferentially distributed spots are observed in electron beam diffraction using an electron beam having a diameter of 10 nmφ or less; the second oxide semiconductor layer has a crystal part having a c-axis orientation, the oxide semiconductor layer has a region in which the silicon concentration of the second oxide semiconductor layer is lower than the silicon concentration of the first oxide semiconductor layer; the first oxide semiconductor layer contains indium and gallium; the second oxide semiconductor layer contains indium and gallium, an atomic ratio of gallium to indium in the first oxide semiconductor layer and an atomic ratio of gallium to indium in the second oxide semiconductor layer are different from each other.

3. a first conductive layer that functions as a gate electrode of a transistor; a first insulating layer having a region overlying the first conductive layer; an oxide semiconductor layer having a region in contact with a top surface of the first insulating layer and a region overlapping with the first conductive layer with the first insulating layer interposed therebetween; a second conductive layer having a region located over the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; a third conductive layer having a region located over the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor; a second insulating layer having a region located on the second conductive layer, a region located on the third conductive layer, and a region in contact with a top surface of the oxide semiconductor layer; the first insulating layer comprises silicon oxide; the second insulating layer comprises silicon oxide; the oxide semiconductor layer has a stacked structure of a first oxide semiconductor layer having a region in contact with an upper surface of the first insulating layer and a second oxide semiconductor layer having a region located above the first oxide semiconductor layer; the first oxide semiconductor layer has a region in which a plurality of circumferentially distributed spots are observed in electron beam diffraction using an electron beam having a diameter of 10 nmφ or less; the second oxide semiconductor layer has a crystal part having a c-axis orientation, the oxide semiconductor layer has a region in which the hydrogen concentration of the second oxide semiconductor layer is lower than the hydrogen concentration of the first oxide semiconductor layer and the silicon concentration of the second oxide semiconductor layer is lower than the silicon concentration of the first oxide semiconductor layer; the first oxide semiconductor layer contains indium and gallium; the second oxide semiconductor layer contains indium and gallium, an atomic ratio of gallium to indium in the first oxide semiconductor layer and an atomic ratio of gallium to indium in the second oxide semiconductor layer are different from each other.

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