Metal film and metal film manufacturing method

Abstract

To provide a metal film that is scratch-resistant and has good shielding properties, and a metal film manufacturing method.SOLUTION: A metal film is provided on a resin, the metal film includes a first metal layer, a second metal layer provided on the first metal layer, a third metal layer provided on the second metal layer, and a fourth metal layer provided between the resin and the first metal layer. The first metal layer and the second metal layer contain copper. The grain size of the second metal layer is smaller than that of the first metal layer, and the resistivity of the second metal layer is greater than that of the first metal layer. The fourth metal layer contains stainless steel.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to metal films and methods for making metal films. [Background technology]

[0002] In order to suppress EMI (Electro Magnetic Interference) generated by a semiconductor device, multiple metal films are sometimes formed on the surface of the semiconductor device as electromagnetic shields. During characteristic tests of the semiconductor device, the outer metal films of the multiple metal films may be scraped off, exposing the inner metal films. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-170416 A (US Patent Publication No. 2018 / 0286817) [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-243122 [Patent Document 3] U.S. Patent No. 7,989,928 Summary of the Invention [Problem to be solved by the invention]

[0004] The present embodiment provides a metal film that is scratch-resistant and has good shielding properties, and a method for manufacturing the metal film. [Means for solving the problem]

[0005] The metal film according to this embodiment is provided on a resin and includes a first metal layer, a second metal layer provided on the first metal layer, a third metal layer provided on the second metal layer, and a fourth metal layer provided between the resin and the first metal layer. The first metal layer and the second metal layer contain copper. The grain size of the second metal layer is smaller than that of the first metal layer, and the resistivity of the second metal layer is greater than that of the first metal layer. The fourth metal layer contains stainless steel. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is an enlarged cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is an enlarged cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Figure 5] FIG. 2 is an enlarged cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Figure 6A] FIG. 2 is a characteristic diagram of the semiconductor device according to the first embodiment. [Figure 6B] FIG. 2 is a characteristic diagram of the semiconductor device according to the first embodiment. [Figure 7] Flowchart of the semiconductor device manufacturing method according to the first embodiment [Figure 8] Flowchart of the semiconductor device manufacturing method according to the first embodiment [Figure 9] 1 is a flowchart of another method for manufacturing a semiconductor device according to the first embodiment; [Figure 10] FIG. 10 is an enlarged cross-sectional view of a portion of a semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to these embodiments. In the following embodiments, the up-down direction indicates the relative direction when the surface of a wiring substrate on which a semiconductor chip is mounted is considered to be up, and may differ from the up-down direction according to gravitational acceleration. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those in reality. In the specification and drawings, elements similar to those previously described with reference to the drawings are designated by the same reference numerals, and detailed descriptions are omitted. When a cross-section of a metal layer is photographed using an X-ray or optical microscope, etc., and the cross-sectional area of ​​a crystal grain appearing in the cross-section is determined, the cross-sectional area may be assumed to be the area of ​​a circle, and the diameter of the circle may be used as the grain size of the crystal grain. Here, when there are multiple crystal grains in the cross-section, the average value of all crystal grains within the measurement range may be used as the grain size.

[0008] (First embodiment) Fig. 1 is a top view showing an example of the configuration of a semiconductor device according to a first embodiment, and Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1.

[0009] The semiconductor device 1 includes a wiring substrate 10, semiconductor chips 50 and 52, bonding wires 30, a resin layer 70, and a metal film 90. The wiring substrate 10 has a first surface 10A, a second surface 10B opposite the first surface 10A, and a side surface 10C between the first surface 10A and the second surface 10B. The wiring substrate 10 includes wiring layers 13 to 16 (see FIG. 3) and an interlayer insulating film 17 (see FIG. 3) that insulates the wiring layers. The interlayer insulating film 17 may be made of glass epoxy resin or ceramics. The wiring substrate 10 may be, for example, a printed circuit board or an interposer made of glass epoxy resin. The wiring substrate 10 has pads 12 electrically connected to one of its internal wirings. The first surface 10A of the wiring substrate 10, excluding the pads 12, may be covered with an insulating film such as a solder resist (not shown). The pads 12 include aluminum, gold, copper, or a composite material thereof.

[0010] The semiconductor chip 50 is provided on the first surface 10A of the wiring substrate 10. The semiconductor chip 50 is adhered to the first surface 10A of the wiring substrate 10 by an adhesive layer 40. The semiconductor chip 52 is adhered onto the semiconductor chip 50 by the adhesive layer 40. The adhesive layer 40 may be a paste or film-like resin such as NCP (Non Conductive Paste) or DAF (Die Attach Film). The number of stacked semiconductor chips may be more than two. Only the semiconductor chip 50 may be provided without stacking. A controller chip that controls the other semiconductor chips 50 and 52 may be stacked. The controller chip may be provided separately on the first surface 10A.

[0011] The semiconductor chip 50 has a pad 54 electrically connected to one of the semiconductor elements formed on its surface. The semiconductor chip 52 has a pad 56 electrically connected to one of the semiconductor elements formed on its surface. The pads 54, 56 include aluminum, gold, copper, or a composite material thereof.

[0012] The bonding wire 30 connects between the pads 12 and 54. The bonding wire 30 connects between the pads 54 and 56. The bonding wire 30 is a metal wire such as an Au wire, a Cu wire, an Ag wire, or a Pd-coated Cu wire.

[0013] The resin layer 70 encapsulates and protects the semiconductor chips 50, 52 and the bonding wires 30 on the wiring substrate 10. The resin layer 70 does not necessarily have to be provided on the side surface 10C of the wiring substrate 10. The resin layer 70 is a thermosetting resin, such as an epoxy resin or an acrylic resin. The resin layer 70 may be a resin material containing an inorganic filler (not shown). The inorganic filler may be, for example, silica, i.e., silicon oxide. In addition to silica, the inorganic filler may also include, for example, aluminum hydroxide, calcium carbonate, aluminum oxide, boron nitride, titanium oxide, barium titanate, or the like.

[0014] Metal film 90 covers the surface and side surfaces of resin layer 70. Metal film 90 covers up to side surface 10C of wiring board 10 and is electrically connected to part of the wiring of wiring board 10 at side surface 10C.

[0015] FIG. 3 is a cross-sectional view showing the configuration of frame III in FIG. 2 in more detail. Wiring substrate 10 includes wiring layers 13 to 16 as part of the wiring layer. Wiring layer 16 is provided on the second surface 10B side. Wiring layer 15 is provided above wiring layer 16. Wiring layers 13 and 14 are provided above wiring layer 15. Wiring substrate 10 may further include other wiring layers. An interlayer insulating film 17 is provided between wiring layers 13 to 16. Wiring layer 13 may be connected to pad 12 or may function as pad 12. Wiring layer 16 may also function as a pad on the second surface 10B side, and a Cu pillar or the like may be provided on wiring layer 16 to connect to an external terminal (not shown).

[0016] At the side surface 10C of the wiring substrate 10, a portion of the wiring layers 14, 15 is exposed from the interlayer insulating film 17. The wiring layers 14, 15 exposed from the interlayer insulating film 17 are connected to, for example, a predetermined voltage (for example, a ground voltage). The metal film 90 covers the side surface 10C of the wiring substrate 10 and is electrically connected to the wiring layers 14, 15. Therefore, the metal film 90 is grounded via the wiring layers 14, 15. This allows the metal film 90 to function as an electromagnetic shield.

[0017] Fig. 4 is a cross-sectional view showing in more detail the configuration of box IV in Fig. 2. Note that Fig. 4 shows only the upper part of the semiconductor device 1. The metal film 90 covering the surface and side surfaces of the resin layer 70 includes a stacked film of metal layers 91, 92, 93, and 94.

[0018] The metal layer 91 covers the surface and side surfaces of the resin layer 70 and the side surface 10C of the wiring substrate 10. A metal material containing, for example, stainless steel, nickel, or titanium is used for the metal layer 91. The film thickness of the metal layer 91 is, for example, approximately 100 nm to 300 nm.

[0019] The metal layer 92 is provided on the metal layer 91 and covers the surface and side surface of the resin layer 70 and the side surface 10C of the wiring board 10 via the metal layer 91. The metal layer 92 is made of a different material from the metal layers 91 and 94 and has a lower resistance than the metal layers 91, 93, and 94. The metal layer 92 is made of a metal material such as copper or a compound containing copper. The film thickness of the metal layer 92 is, for example, approximately 1.5 μm to 2.5 μm. The average particle size is approximately 0.15 μm to 0.5 μm. The metal layer 92 has a resistivity of less than 2.0 μΩ·cm.

[0020] The metal layer 93 is provided on the metal layer 92 and covers the surface and side surface of the resin layer 70 and the side surface 10C of the wiring board 10 via the metal layers 91 and 92. The metal layer 93 is made of a metal material, such as copper or a copper-containing compound, and is the same material as the metal layer 92. As shown in FIG. 5, the grain size of the metal layer 93 is smaller than the grain size of the metal layer 92. The film thickness of the metal layer 93 is, for example, approximately 0.3 μm to 1.5 μm. The average grain size is less than 0.15 μm. The metal layer 93 has a resistivity of 2.0 μΩ·cm or more. The total film thickness of the metal layers 92 and 93 is, for example, 1.7 μm to 4.0 μm. A range of 1.7 μm to 3.0 μm is more preferable.

[0021] The metal layer 94 is provided on the metal layer 93, and covers the surface and side surface of the resin layer 70 and the side surface 10C of the wiring substrate 10 via the metal layers 91, 92, and 93. The metal layer 94 covers the metal layer 93 and is the outermost layer of the semiconductor device 1. The metal layer 94 is made of a metal material containing, for example, stainless steel, nickel, or titanium. The metal layer 94 may be made of the same material as the metal layer 91. The film thickness of the metal layer 94 is, for example, approximately 300 nm to 900 nm.

[0022] (effect) FIG. 6A is an explanatory diagram showing the relationship between the particle size of metal layer 93 and the adhesion strength with metal layer 94. The vertical axis of FIG. 6A indicates the amount of force required to expose metal layer 93 from metal layer 94. The horizontal axis indicates the particle size of metal layer 93. As shown in FIG. 6A, if the standard value of the force required to prevent peeling is CmN, then small particle size A meets the standard, but large particle size B does not meet the standard. Thus, by reducing the particle size of metal layer 93, the adhesion between metal layer 93 and metal layer 94 improves, making metal layer 94 less likely to peel from metal layer 93. In other words, metal layer 94 can more reliably protect metal layer 93.

[0023] Figure 6B shows the dependence of the resistance of metal layer 93 on particle size. For a larger particle size (line B) in Figure 6B, the resistivity can be reduced for the same film thickness, resulting in a sufficient electromagnetic shielding effect. On the other hand, for a smaller particle size (line A) in Figure 6B, the resistivity increases. In this case, a sufficient electromagnetic shielding effect cannot be achieved. For example, if the resistivity standard is CmΩ / Sq, a larger particle size (X1 μm) is sufficient, but a smaller particle size (X2 μm) is required. Therefore, if metal film 90 is formed using only metal layers 91, 93, and 94 without metal layer 92, and the required adhesion and resistivity are to be met, metal layer 93 must be sufficiently thick. However, if metal layer 93 is made sufficiently thick, the film formation process takes time, resulting in increased costs.

[0024] (a) Therefore, a metal layer 92 with a large grain size is sandwiched between metal layer 91 and metal layer 93. Metal layer 92 can reduce resistivity even when it is thin. Therefore, sufficient adhesion and electromagnetic shielding effect can be obtained at a lower cost than if metal layer 93 were made sufficiently thick. (b) Furthermore, by using the same material for metal layer 92 and metal layer 93, the adhesion between metal layer 92 and metal layer 93 can be made stronger than if different materials were used.

[0025] (Method for manufacturing the semiconductor device according to the first embodiment) Next, a method for manufacturing the semiconductor package 1 according to the first embodiment will be described. Figures 7 and 8 are flow charts showing an example of the method for manufacturing the semiconductor package according to the first embodiment.

[0026] A description will be given of a manufacturing method of a semiconductor device before performing step 1 in Fig. 7. A semiconductor chip 50 is provided on a first surface 10A of a wiring substrate 10 via an adhesive layer 40. A semiconductor chip 52 is provided on the semiconductor chip 50 via the adhesive layer 40. At this time, the multiple wiring substrates 10 are still connected together and have not yet been separated into individual semiconductor packages.

[0027] Next, after the wiring substrate 10 is plasma cleaned, the pads 12 of the wiring substrate 10, the pads 54 of the semiconductor chip 50, and the pads 56 of the semiconductor chip 52 are connected by bonding wires 30.

[0028] Although the semiconductor chips 50 and 52 are stacked in a direction substantially perpendicular to the first surface 10A, the semiconductor chips may also be arranged side by side on the first surface 10A.

[0029] Next, in step S1, a resin layer 70 is provided on the wiring substrate 10 to seal the semiconductor chips 50, 52 and the bonding wires 30.

[0030] In step S2, the wiring substrate 10 is divided into individual semiconductor devices using a blade, thereby forming the semiconductor devices 1.

[0031] In step S3, marking is performed on the upper surface of the resin layer 70 of the individual semiconductor device 1. The marking is performed by engraving the product name, manufacturer, lot number, etc. using a laser marker.

[0032] In step S4, the semiconductor device 1 is placed in an oven and baked. The baking is performed at a temperature between 100°C and 260°C, for example. The baking evaporates the moisture contained in the resin layer 70, improving the adhesion of the metal film 90, which will be described later. Furthermore, baking at a temperature below the melting point of the solder, for example, below 260°C, suppresses deterioration in the reliability of the bonding portions, wiring, transistors, etc. Furthermore, a vacuum may be created to release gas contained in the resin layer 70 and the wiring substrate 10.

[0033] In step S5, a plurality of semiconductor devices 1 are placed on a tray (not shown) made of metal, heat-resistant plastic, or the like, which can withstand temperatures of 200° C. or higher.

[0034] In step S6, the semiconductor devices 1 are placed on a tray and then carried into a decompression chamber where the pressure is lower than atmospheric pressure.

[0035] In step S7, the semiconductor device 1 is transferred to an etching chamber, where the resin layer 70 is etched. The resin layer 70 is etched (sputter-etched) using, for example, plasma containing argon (Ar) and nitrogen (N). The flow rate ratio of argon to nitrogen can be, for example, 3:7 to 7:3. Outside this range, the adhesion between the resin layer 70 and the metal film 90 may be reduced. This etching selectively etches the resin layer 75 by approximately 1 to 100 nm relative to the inorganic filler. Because the inorganic filler has high adhesion to the metal film 90, exposing the inorganic filler improves the adhesion between the resin layer 70 and the metal film 90.

[0036] In step S8, the semiconductor device 1 is introduced into a film-forming chamber, and a metal film 90 is formed on the upper and side surfaces of the resin layer 70 and on the side surface 10C of the semiconductor device 1. The metal film 90 is formed, for example, by using a sputtering method, with a plurality of semiconductor devices 1 placed on a tray. Here, the etching chamber and the film-forming chamber may be the same chamber.

[0037] As described above, the metal film 90 is a laminated film of metal layers 91 to 94. The metal layers 91 to 94 are successively formed in the same decompression chamber while changing the sputtering material source. As shown in FIG. 5, first, the metal layer 91 is formed on the resin layer 70 (S81). For example, when stainless steel is used as the metal layer 91, the metal layer 91 is formed by sputtering using a stainless steel source. The thickness of the stainless steel film is, for example, 100 nm to 300 nm.

[0038] Next, a metal layer 92 is formed on the metal layer 91 at approximately 200°C (S82). At this time, the tray and the semiconductor device 1 may be heated by a heater or the like. The metal layer 92 is formed by sputtering using copper or an alloy containing copper as a source. The temperature of the semiconductor device 1 during film formation is approximately 200°C. As shown in FIG. 6B, the grain size of the metal layer 92 is larger than the grain size of copper formed at 150°C, and the metal layer 92 has a relatively low resistance. The film thickness of the metal layer 92 is, for example, approximately 1.5 μm to 2.5 μm. The average grain size is approximately 0.20 μm to 0.5 μm.

[0039] Next, metal layer 93 is formed on metal layer 92 at approximately 150°C (S83). At this time, heating such as by a heater may be stopped to allow the temperature of semiconductor device 1 to drop. Metal layer 93 is formed by sputtering using the same material as metal layer 92 as a source. At this time, as shown in FIG. 6A, the grain size of the copper alloy in metal layer 93 is relatively small. As shown in FIG. 6B, metal layer 93 has a higher resistance than metal layer 92. The film thickness of metal layer 93 is, for example, approximately 0.3 μm to 1.5 μm. The average grain size is 0.15 μm or less.

[0040] Next, a metal layer 94 is formed on the metal layer 93 (S84). For example, when stainless steel is used as the metal layer 94, the metal layer 94 is formed by sputtering using a stainless steel source. The thickness of the stainless steel film is, for example, 300 nm to 900 nm. At this time, in accordance with the underlying metal layer 93, the metal layer 94 also becomes a relatively flat film with a small grain size. The temperatures during the formation of the metal layers 91, 93, and 94 may be approximately the same.

[0041] The metal layers 91 to 94 may be formed by a CVD (Chemical Vapor Deposition) method, a vacuum deposition method, or an ion plating method.

[0042] Through the above manufacturing method, the semiconductor device 1 is completed. (effect) (a) If sputtering is performed on a semiconductor device 1 mounted on, for example, a resin tape that cannot withstand temperatures above 150°C, the metal films 92 and 93 must be deposited at temperatures below 150°C. Therefore, the grain size of the metal films 92 and 93 becomes small, resulting in relatively high resistance. In contrast, in this embodiment, the wiring substrate 10 is mounted on a tray that can withstand higher temperatures than the resin tape and the sputtering process is performed. Therefore, the metal layer 92 can be deposited at 200°C, which is above 150°C, and the grain size can be increased. As a result, the metal layer 92 has relatively low resistance. By depositing the metal layer 92 at a high temperature of approximately 200°C and the metal layer 93 at a low temperature of 150°C, the metal layer 92, which has low resistance but low adhesion to the metal layer 94, and the metal layer 93, which has high resistance but high adhesion to the metal layer 94, can be combined, achieving both electromagnetic shielding properties and adhesion. (b) Since the metal layers 92 and 93 are made of the same material, they can be deposited using the same source, thereby reducing costs. (c) Since the metal layers 92 and 93 are deposited in the same chamber, the number of deposition chambers can be reduced, thereby reducing costs.

[0043] (Other manufacturing methods) 9 shows another method for manufacturing the semiconductor device 1. The metal film 90 is a laminated film of metal layers 91 to 94. The film thicknesses, film formation methods, film formation temperatures, etc. of the metal layers 91 to 94 are substantially the same as those in the method for manufacturing the semiconductor device 1 in the first embodiment. The metal layers 91 to 94 are formed in different decompression chambers.

[0044] A metal layer 91 is formed on the resin layer 70 (S181).

[0045] The semiconductor device 1 is carried out from the film forming apparatus in which the metal layer 91 is formed (S182).

[0046] The semiconductor device 1 is carried into a high temperature film forming apparatus different from the first chamber (S183).

[0047] The stage of the high-temperature film formation apparatus has already been preheated to the target film formation temperature, so the semiconductor device 1 carried into the high-temperature film formation apparatus does not have to wait long for the temperature to rise, and the metal layer 92 is formed (S184).

[0048] The semiconductor device 1 is carried out from the high-temperature film-forming apparatus (S185).

[0049] The semiconductor device 1 is carried into a film forming apparatus (S186). At this time, the film forming apparatus may be an apparatus that has formed another metal layer 91, or may be a film forming apparatus serving as a "third chamber" different from the first and second chambers.

[0050] The stage of the film forming apparatus is at the target film forming temperature, so the semiconductor device 1 carried into the film forming apparatus does not need to wait long for the temperature to drop, and the metal layer 93 is formed (S187).

[0051] After the metal layer 93 is formed, the metal layer 94 is formed (S188).

[0052] By the above manufacturing method, the semiconductor device 1 is completed by another manufacturing method.

[0053] (effect) (d) Metal layer 92 and metal layer 93 are formed in different chambers. This reduces the waiting time for the chambers to heat up and cool down. As a result, in addition to the effects (a) and (b) of the semiconductor device manufacturing method of the first embodiment, semiconductor device 1 can be processed in a shorter time.

[0054] (Other embodiments) (a) In the above embodiment, the same source is used to form metal layer 92 and metal layer 93. However, a metallic copper source with a purity of 4N (99.99%) or higher may be used only for metal layer 92, and a copper source with a purity lower than 4N may be used for metal layer 93. This results in metal layer 92 with a purity of 99.99% or higher, thereby enabling lower resistance. Furthermore, a source with a lower purity may be used for metal layer 93, which does not require low resistance, thereby reducing costs. For example, when forming a film by sputtering, a copper sputtering target with a purity of 4N or higher is used for metal layer 92. A copper sputtering target with a purity of 4N or lower is used for metal layer 93. In this case, even if the purity of the copper in metal layer 93 is slightly lower, the adhesion between metal layer 92 and metal layer 93 can be maintained because copper is the main constituent material. (b) In the above embodiment, the deposition temperature of the metal layer 93 is 150° C., but it may be below 150° C., preferably below 120° C., and more preferably below 100° C. In this case, the grain size of the third metal layer 93 can be further reduced, thereby improving the adhesion with the fourth metal layer. (c) In the above embodiment, the deposition temperature for the metal layer 92 is 200°C, but the effect of increasing the grain size can be obtained even at temperatures below 200°C as long as the temperature is higher than 150°C. The deposition temperature may be 200°C or higher, preferably 200°C to 230°C, and more preferably 230°C to 250°C. In this case, the grain size of the metal layer 92 can be further increased, thereby reducing the resistivity of the metal layer 92. (d) As shown in Figure 10, a metal layer 95 containing the same material as metal layer 92 and having a smaller particle size than metal layer 92 may be provided between metal layer 91 and metal layer 92. The film thickness of metal layer 95 may be thinner than that of metal layer 93. The adhesion between metal layer 91 and metal layer 95 is strengthened. Furthermore, since metal layer 92 and metal layer 95 contain the same material, the adhesion between metal layer 92 and metal layer 95 can also be strengthened. In this case, metal layer 95 may be formed at 150°C or less, similar to metal layer 93. (e) In the above embodiment, the film formation temperature is the set temperature of the stage of the film formation apparatus, etc. However, it is also possible to attach a temperature sensor or the like to the semiconductor device to measure the temperature while forming the film, and use the temperature actually measured at that time as the film formation temperature.

[0055] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as the inventions described in the claims and their equivalents. [Explanation of symbols]

[0056] 1 semiconductor package, 10 wiring substrate, 40 adhesive layer, 50, 52 semiconductor chip, 12, 54, 56 pad, 60 bonding wire, 70 resin layer, 90 metal film, 91 to 94 metal layers, 13 to 16 wiring layer, 17 insulating layer

Claims

1. A metal film provided on a resin, the metal film has a first metal layer provided on the resin, a second metal layer provided on the first metal layer, and a third metal layer provided on the second metal layer; the first metal layer and the second metal layer contain copper, the grain size of the second metal layer is smaller than the grain size of the first metal layer, and the resistivity of the second metal layer is larger than the resistivity of the first metal layer; The metal film further comprises a fourth metal layer between the first metal layer and the resin, the fourth metal layer including stainless steel.

2. A metal film provided on a resin, the metal film has a first metal layer provided on the resin, a second metal layer provided on the first metal layer, and a third metal layer provided on the second metal layer; the first metal layer and the second metal layer contain copper, the grain size of the second metal layer is smaller than the grain size of the first metal layer, and the resistivity of the second metal layer is larger than the resistivity of the first metal layer; A metal film, wherein the purity of copper in the first metal layer is different from the purity of copper in the second metal layer.

3. 3. The metal film according to claim 1, wherein the third metal layer has a thickness of 300 nm to 900 nm.

4. The metal film according to claim 1 , wherein the first metal layer has a resistivity of less than 2.0 μΩ·cm.

5. 5. The metal film according to claim 1, wherein the grain size of the first metal layer is 0.20 μm to 0.5 μm, and the grain size of the second metal layer is 0.15 μm or less.

6. 6. The metal film according to claim 1, wherein the first metal layer has a thickness of 1.5 μm to 2.5 μm, and the second metal layer has a thickness of 0.3 μm to 1.5 μm.

7. Resin is provided, providing a first metal layer on the resin at a first temperature; providing a second metal layer on the first metal layer at a second temperature lower than the first temperature; providing a third metal layer on the second metal layer; A method for manufacturing a metal film, wherein the first metal layer and the second metal layer contain copper, the grain size of the second metal layer is smaller than the grain size of the first metal layer, and the resistivity of the second metal layer is greater than the resistivity of the first metal layer.

8. The method for manufacturing a metal film according to claim 7, further comprising providing a fourth metal layer between the resin and the first metal layer at a temperature of 150°C or less.

9. 9. The method for manufacturing a metal film according to claim 7, wherein the first metal layer and the second metal layer are provided in different chambers.

10. 10. The method for manufacturing a metal film according to claim 7, wherein the third metal layer has a thickness of 300 nm to 900 nm.

11. The method for manufacturing a metal film according to claim 7 , wherein the first metal layer, the second metal layer, and the third metal layer are formed by sputtering.

12. 12. The method for manufacturing a metal film according to claim 7, wherein copper having a purity of 99.99% or more is used to form the first metal layer, and copper having a purity of less than 99.99% is used to form the second metal layer.

Images