Thermoelectric cooling of die packages

Abstract

In some aspects, the disclosed technology provides thermoelectric devices capable of efficiently dissipating heat and methods of making the disclosed thermoelectric devices. In some embodiments, the disclosed devices can include a first integrated device die. The disclosed devices can further include a thermoelectric element bonded to the first integrated device die. The disclosed devices can further include a heat sink attached to at least the thermoelectric element. The thermoelectric element can be configured to transfer heat from the first integrated device die to the heat sink. The thermoelectric element can be directly bonded to the first integrated device die without adhesive.

Description

[Technical field]

[0001] The technical field relates to microelectronics, and in particular to the dissipation of heat in microelectronic devices containing direct bonded components.

[0002] [Citation to Related Applications] This application claims priority to U.S. Provisional Patent Application No. 63 / 265,765 (title: THERMOELECTRIC COOLING FOR DIE PACKAGES), filed on December 20, 2021, which is incorporated by reference in its entirety. [Background technology]

[0003] The miniaturization and high density integration of electronic components increases the heat flux density in microelectronics. Microelectronic components typically operate below a certain rated motion to ensure optimal operation. A heat spreader or heat sink may be attached on top of a high temperature microelectronic component or semiconductor die using a thermally conductive material (TIM), thereby drawing heat away from the top of the semiconductor die. If the heat generated during the operation of the microelectronics is not sufficiently dissipated or drawn away, the microelectronics may not be able to operate reliably, its performance may be adversely affected, or even the microelectronics may shut down or burn out. In particular, heat dissipation and drawing is a serious challenge in high power devices, and this challenge becomes more difficult with chip stacking. Summary of the Invention

[0004] According to one aspect of the present invention, there is provided a microelectronic device having a first integrated device die, a thermoelectric element bonded to the first integrated device die, and a heat sink attached to at least the thermoelectric element, the thermoelectric element configured to transfer heat from the first integrated device die to the heat sink, and the thermoelectric element being directly bonded to the first integrated device die without an adhesive.

[0005] Specific embodiments will now be described with reference to the following drawings, which are provided by way of illustration and not by way of limitation. [Brief description of the drawings]

[0006] [Figure 1A] 1 is a schematic cross-sectional view of an exemplary microelectronic system. [Figure 1B] FIG. 1B is a schematic plan view of the example microelectronic system shown in FIG. 1A. [Figure 2A] 1 is a schematic diagram illustrating a method of fabricating a thermoelectric element in a die stack in accordance with one embodiment of the disclosed technology. [Figure 2B] 1 is a schematic diagram illustrating a method of fabricating a thermoelectric element in a die stack in accordance with one embodiment of the disclosed technology. [Figure 2C] 1 is a schematic diagram illustrating a method of fabricating a thermoelectric element in a die stack in accordance with one embodiment of the disclosed technology. [Figure 2D] 1 is a schematic diagram illustrating a method of fabricating a thermoelectric element in a die stack in accordance with one embodiment of the disclosed technology. [Figure 2E] 1 is a schematic diagram illustrating a method of fabricating a thermoelectric element in a die stack in accordance with one embodiment of the disclosed technology. [Figure 2F] 1 is a schematic diagram illustrating a method of fabricating a thermoelectric element in a die stack in accordance with one embodiment of the disclosed technology. [Figure 3A] 13 is a schematic diagram of a portion of another method for fabricating thermoelectric elements in a die stack in accordance with an embodiment of the disclosed technology. [Figure 3B]13 is a schematic diagram of a portion of another method for fabricating thermoelectric elements in a die stack in accordance with an embodiment of the disclosed technology. [Figure 3C] 13 is a schematic diagram of a portion of another method for fabricating thermoelectric elements in a die stack in accordance with an embodiment of the disclosed technology. [Figure 4A] 13 is a schematic diagram of yet another method of fabricating a thermoelectric element in a die stack in accordance with a disclosed embodiment. [Figure 4B] 13 is a schematic diagram of yet another method of fabricating a thermoelectric element in a die stack in accordance with a disclosed embodiment. [Figure 4C] 13 is a schematic diagram of yet another method of fabricating a thermoelectric element in a die stack in accordance with a disclosed embodiment. [Figure 4D] 13 is a schematic diagram of yet another method of fabricating a thermoelectric element in a die stack in accordance with a disclosed embodiment. [Figure 5A] 13 is a schematic diagram of yet another method of fabricating thermoelectric elements in a die stack in accordance with an embodiment of the disclosed technology. [Figure 5B] 13 is a schematic diagram of yet another method of fabricating thermoelectric elements in a die stack in accordance with an embodiment of the disclosed technology. [Figure 5C] 13 is a schematic diagram of yet another method of fabricating thermoelectric elements in a die stack in accordance with an embodiment of the disclosed technology. [Figure 6A] 1 is a schematic cross-sectional view of another exemplary microelectronic system. [Figure 6A-2] FIG. 6B is a schematic plan view of the example microelectronic system shown in FIG. 6A. [Figure 6B] 1 is a schematic cross-sectional view of yet another exemplary microelectronic system. [Figure 7A] 1 is a schematic cross-sectional view of yet another exemplary microelectronic system. [Figure 7B] 1 is a schematic cross-sectional view of yet another exemplary microelectronic system. [Figure 8A] 1 is a schematic cross-sectional view of yet another exemplary microelectronic system. [Figure 8B] FIG. 8B is a schematic plan view of the example microelectronic system shown in FIG. 8A. [Figure 9] 1 is a schematic cross-sectional view of yet another exemplary microelectronic system. [Figure 10] 1 is a schematic cross-sectional view of yet another exemplary microelectronic system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Microelectronic elements (e.g., dies / chips) can be stacked and bonded together to create a device. It becomes difficult to dissipate heat from device dies with chip stacking, especially as the chips become thinner. The use of chip attachment techniques, such as adhesive bonding, flip chip interconnection, etc., can slow down the efficiency of heat dissipation or heat transfer toward the heat spreader and ultimately heat extraction within the device, because the adhesive can reduce or insulate the heat transfer from one die to another or from the bottom die to the top die (towards the heat spreader). Furthermore, it is difficult to specifically lower the temperature within a desired portion of the device. For example, when packaging a stack of dies, heat dissipation is typically aided by a heat sink at the top of the stack, but efficiently extracting heat from the lower die in the die stack (especially the die located at the bottom of the stack) is a challenge. Thus, there is a continuing need for improved techniques to dissipate heat within microelectronic devices.

[0008] Methods and structures are provided for redirecting heat flow in a die stack, for example, from a lower die in the stack to an upper heat dissipation structure (e.g., heat sink / heat pipe). Also provided is a process for making such structures. In one aspect, as shown in FIG. 1A, a microelectronic device 100 can have a thermoelectric element 103 that helps remove heat from the device 100 and can actively redirect heat flow in the device 100, for example, to actively reduce the temperature of a chip, a location on the chip, or a hot spot in the chip. The thermoelectric element 103 can be a Peltier element that includes two materials with different Peltier coefficients joined together at a junction. The Peltier element utilizes the Peltier effect and can create a net heat flow rate at the junction of two different materials through which electrical energy (e.g., DC current) is delivered due to an imbalance of Peltier heat flowing into and out of the junction. In some embodiments, the Peltier elements may include pairs 1030 of p-type and n-type semiconductor pellets or chips, etc., coupled electrically in series and thermally in parallel, for example in the configuration shown in Figure 1A. In this configuration, charge carriers and heat can all flow in the same direction (bottom to top or top to bottom, depending on the applied voltage bias) through the pellets 1034, 1036. For example, in Figure 1A, the pellets 1034, 1036 may be biased such that the heat flow rate is from the lower active chip 101, through the Peltier elements and carrier elements 105, and upwards to the heat sink 107, as indicated by the arrows.

[0009] In some embodiments, the thermoelectric element 103 is not bonded to other elements of the device 100 by an adhesive or a thermally conductive material (TIM) that may impede heat transfer. Alternatively, the thermoelectric element 103 may be directly bonded to another element in the device 100, thus improving heat transfer efficiency. For example, a plurality of p-type and n-type semiconductor pellet pairs 1030 or a structure (e.g., a wafer, a die, etc.) including a plurality of p-type and n-type semiconductor pellet pairs 1030 may be directly bonded to the active chip 101. In other embodiments, the thermoelectric element 103 may be grown on the active chip 101 or die. The active chip 101 may be a die having active circuitry, for example, the active circuitry may include one or more transistors.

[0010] In some embodiments, the multiple p-type and n-type semiconductor thermoelectric pellet pairs 1030 can be divided into many groups, and each group can be controlled independently. For example, a sensor (e.g., a diode) can be used to measure the temperature at a location in the device 100. If the temperature at that location is higher than a threshold or optimal operating temperature of the device 100, the group of thermoelectric pellets 1030 associated with that location can be activated by passing a current through one or more pairs of electrical contact pins / pads 117. In this way, the temperature in the device 100 can be locally monitored and controlled. Also, by allowing each group or selected groups of thermoelectric pellets 1030 to be independently activated, the power consumption of the thermoelectric element can be reduced.

[0011] 1A is a schematic cross-sectional view of an example microelectronic system 100 including stacked semiconductor elements (e.g., die / chip / carrier) and a thermoelectric element 103 that can direct heat to a heat sink 107 (e.g., a metal heat sink or a heat pipe containing a fluid coolant) located at the top of the stack. Heat generated by the lower semiconductor element 101 (e.g., active chip) during operation can be actively transferred by the thermoelectric element 103 to the heat sink 107 and dissipated from the system 100 as indicated by the arrows. In some embodiments, the thermoelectric element 103 can be bonded to the element (e.g., lower active chip 101 or upper carrier 105) at a bonding interface 1077 by direct bonding without an intervening adhesive, for example, by a hybrid direct bonding process described below and commercially available from Adeia, Inc., San Jose, Calif. In some embodiments, the thermoelectric element 103 may be bonded to the lower active chip 101 in a F2F (front to front) or F2B (front to back) configuration. In some embodiments, the electrical contacts 117 of the thermoelectric element 103 may be connected directly or via conductive traces to TSVs (through substrate vias) 1015 that extend into the element 101 for powering the thermoelectric element. For example, the electrical contacts 117 of the thermoelectric element 103 may be directly bonded to the TSVs 1015 in the element 101. In other embodiments, the thermoelectric element 103 may be grown on the lower active chip 101.

[0012] FIG. 1B is a schematic plan view of the exemplary microelectronic system 100 shown in FIG. 1A. The thermoelectric element 103 may be configured to provide zoned control for cooling the lower active chip 101. As shown in FIG. 1B, by way of example, multiple electrical contacts 117 are used for multi-zone / position control of different groups of thermoelectric pellet pairs 1030 in the thermoelectric element 103 during cooling operation, providing localized heat dissipation in response to measured hot spot distribution. In various embodiments, the thermoelectric element 103 may be controlled using a signal measured by a temperature sensor, which may be located in the lower active chip 101 or in the thermoelectric element 103. In various embodiments, the thermoelectric element 103 may be controlled by the lower active chip 101 in the thermoelectric element 103 or by an external chip on a system board.

[0013] 2A-2F show a schematic of how the thermoelectric elements 103 are fabricated in a die stack. FIG. 2A shows a first step of fabricating N- or P-doped regions (2034, 3036, respectively) in a suitable thermoelectric substrate 2010 (e.g., a Bi2Te3 wafer) where the N- or P-doped regions are separated from each other by physical gaps 2015 or wide (e.g., >1 μm) intrinsic regions 2017. The physical gaps 2015 may be filled with one or more suitable organic or inorganic dielectrics. The width of the P or N regions (2036 or 2034) may vary from tens of μm to several mm in one or both planar directions. FIG. 2B shows a second step including dielectric deposition followed by metallization to form interconnected N / P pairs 2030. The metallization may be one or more conductive traces 2031 between each P and N region (2036 and 2034, respectively). In some embodiments, another metallization may also be formed to act as a hot plate or cold plate. If the width of the P and N regions is large, several conductive traces 2031 may be implemented to allow uniform carrier flow / distribution that effectively creates a uniform thermal gradient between the hot plate and the cold plate. In other embodiments, the formation of the metallization layer connecting the P and N regions (2036 and 2034, respectively) is followed by deposition of the dielectric 2032. The dielectric layer 2032 is pre-treated (e.g., cleaning, chemical mechanical polishing, or CMP plasma activation, etc.) to make it directly bondable (e.g., for direct-insulator-to-insulator or direct hybrid bonds). FIG. 2C shows the third step, which involves attaching the fabricated thermoelectric element 103 to a carrier 105 (e.g., by dielectric-to-dielectric (hereinafter sometimes referred to as "dielectric-to-dielectric") direct bonding, e.g., ZIBOND (registered trademark) commercially available from Adair Corporation).The carrier 105 may be a permanent carrier that is not subsequently removed and may be made of a suitable thermally conductive material (e.g., Si, ceramic, aluminum, aluminum nitride, silicon nitride, etc., or a material with a thermal conductivity of more than 1 W / cm / °C). In other embodiments, the carrier 105 may be removed during laser processing. FIG. 2D shows a fourth step including grinding, polishing, or any other suitable process to remove the thermoelectric substrate 2010 (e.g., Bi2Te3 wafer) to expose the N / P couple 2030. FIG. 2E shows a fifth step including dielectric 2042 deposition, metallization to make electrical contacts 117, and fabrication of a bonding layer 2051 (a layer configured to allow hybrid bonding, e.g., DBI® bonding, commercially available from Adair Corporation). FIG. 2F illustrates a sixth step of attaching (e.g., by direct hybrid bonding) the thermoelectric element 103 to the active chip 101 or wafer (face-to-face (F2F) or face-to-back (F2B)), which may include TSVs. In other embodiments, the thermoelectric element 103 is directly bonded to the active chip wafer without any electrical connection therebetween. The methods described in connection with FIGS. 2A-2F may be used to manufacture and / or work in connection with devices and systems described in U.S. Provisional Patent Application No. 63 / 265,770, filed December 20, 2021, entitled "TERMOELECTRIC COOLING IN MICROELECTRONICS," which is incorporated by reference in its entirety.

[0014] 3A-3C show a schematic of a part of another method for fabricating thermoelectric elements 103 in a die stack. FIG. 3A shows the steps starting with a carrier wafer 105 (which may have a high thermal conductivity, e.g., greater than 1 W / cm / °C). In some embodiments, the material may be Si or ceramic if used as a permanent carrier. Other carrier materials such as aluminum, aluminum nitride, silicon carbide may be used in some embodiments. FIG. 3B shows the next step of creating a small cavity 3033 in the wafer 105 (with or without a further step of depositing a layer of dielectric / insulator in the cavity 3033). FIG. 3C shows the step of filling the cavity with a mixture 3039 of Bi and Te, followed by high temperature sintering. Alternatively, a Bi2Te3 (doped) wafer is crushed and powder is forced into the cavity / pocket and sintered. Alternatively, the cavity 3033 may be filled by depositing, stenciling or 3D printing the doped material 3039 therein. The method may then proceed with the steps associated with Figures 2B-2F. The method described in association with Figures 3A-3C may be used to manufacture and / or act in association with the devices and systems described in U.S. Provisional Patent Application No. 63 / 265,770, filed December 20, 2021, entitled "TERMOELECTRIC COOLING IN MICROELECTRONICS," which is incorporated by reference in its entirety.

[0015] 4A-4D show schematic diagrams of yet another method of fabricating thermoelectric elements 103 in a die stack. FIG. 4A shows a first step starting with a carrier 105 (or interposer). FIG. 4B shows a second step of metallization to make electrical connections 4031, then depositing, stenciling, or 3D printing on the doped Bi2Te3 carrier 105 to form features / pellets 4034, 4036 that become the thermoelectric N / P couple 4030. FIG. 4C shows a third step of filling the gaps 4015 between the Bi2Te3 features with a dielectric 4017, metallization to make electrical connections 4033 and contacts 117, and forming a bonding layer 4051 (e.g., a layer configured to allow direct hybrid bonding, e.g., DBI® bonding, commercially available from Adair Corporation). FIG. 4D shows a fourth step of attaching (e.g., direct hybrid bonding) the fabricated thermoelectric element 103 to an active chip 101 or wafer, which may include TSVs, F2F or F2B. In other embodiments, the thermoelectric element 103 is directly bonded to the active chip 101 or wafer with no electrical connection between them. In some embodiments, the thermoelectric element 103 may range in size from about 1 mm to 3 mm. The pitch of the N-P 4030 may be about 0.5 mm to several mm, or about tens of microns. In some embodiments, the pitch of the N-P pair 4030 may be about 0.1 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm, 5 mm, or any value in between, or about 10 microns, 30 microns, 50 microns, 70 microns, 90 microns, or any value in between. The methods described in connection with Figures 4A-4D may be used to manufacture and / or act in connection with the devices and systems described in U.S. Provisional Patent Application No. 63 / 265,770, filed on December 20, 2021, entitled "TERMOELECTRIC COOLING IN MICROELECTRONICS," which is incorporated by reference in its entirety and is hereby incorporated by reference in its entirety.

[0016] 5A-5C show schematics of yet another method of fabricating thermoelectric elements 103 in a die stack by growing the thermoelectric elements 103 directly on the active wafer / chip 101. FIG. 5A shows the first step starting with the active wafer / chip 101. FIG. 5B shows the second step of metallization to make electrical connections 5031 and then depositing / stenciling / 3D printing doped Bi2Te3 on the backside 5010 of the active wafer / chip 101 to form pellets 5034, 5036 that become the thermoelectric N / P couple 5030. FIG. 5C shows the third step of filling the gaps 5015 between the Bi2Te3 features with a dielectric 5017 and then metallization to make the electrical connections 5033. In some embodiments, the thermoelectric elements 103 may range in size from about 0.5 mm to 3 mm. The pitch of the N-P 5030 may be about 0.5 mm to 1 mm, or about tens of microns. In some embodiments, the pitch of the N-P pair 5030 may be about 0.1 mm, 0.5 mm, 1 mm, 2 mm, 3 mm, 4 mm, 5 mm, or values ​​therebetween, or about 10 microns, 30 microns, 50 microns, 70 microns, 90 microns, or values ​​therebetween. The methods described in connection with Figures 5A-5C may be used to manufacture and / or work in connection with devices and systems described in U.S. Provisional Patent Application No. 63 / 265,770, filed December 20, 2021, entitled "TERMOELECTRIC COOLING IN MICROELECTRONICS," which is incorporated by reference in its entirety.

[0017] 6A is a schematic cross-sectional view of an example microelectronic system 600A that includes stacked semiconductor elements (e.g., carrier element 600 and active die 601A, 6001A, 6002A) and a thermoelectric element 603A that directs heat from the bottom chip (601A) to a heat sink 607A at the top of the stack. The thermoelectric element 603A and multiple chips (e.g., 6001A and 6002A) may be attached (mounted) to the bottom chip (601A). The thermoelectric element 603A may be directly bonded (e.g., by insulator-to-insulator (hereinafter sometimes referred to as "insulator-to-insulator") direct bonding or hybrid direct bonding) to the bottom chip 601A. The thermoelectric element 603A may be located adjacent to at least one chip (e.g., at least 6001A and / or 6002A), thus reducing the heat flow through at least one chip 6001 and 6002A. The thermoelectric element 603A may be powered by electrical contacts 617A coupled to the bottom chip 601A. FIG. 6A-2 is a schematic plan view of an example microelectronic system 600A shown in FIG. 6. FIG. 6B is a schematic cross-sectional view of another example microelectronic system 600B, which includes stacked semiconductor elements (e.g., carrier element 605 and active die 601B, 6001B, 6002B) and a thermoelectric element 603B that directs heat from the bottom chip (601B) to a heat sink 607B at the top of the stack. The thermoelectric element may be attached to the bottom chip (601B) and multiple chips (e.g., 6001B and 6002B) may be attached to the thermoelectric element 603B. The microelectronic element 603B may be powered and controlled by electrical contacts 617B coupled to the bottom chip (601B) in response to temperature detection by sensors located in any of the adjacent chips (e.g., 601B, 6001B, or 6002B).

[0018] FIG. 7A is a schematic cross-sectional view of an exemplary microelectronic system 700A similar to the microelectronic system shown in FIG. 6A, where like features are indicated by like reference numerals, but where thermoelectric element 603A is powered from the backside using bond wires 799A. Thermoelectric element 603A may be directly bonded to bottom chip 601A (e.g., by direct hybrid bonding or by insulator-to-insulator direct bonding). FIG. 7B is a schematic cross-sectional view of an exemplary microelectronic system 700B similar to the microelectronic system shown in FIG. 6B, where like features are indicated by like reference numerals, but where thermoelectric element 603B is powered from the backside using external connections, e.g., bond wires 799B. In the embodiments of FIGS. 7A and 7B, an external device can control the operation of thermoelectric element 603A or 603B. For example, a chip or die on a system board (not shown) can control the operation of thermoelectric element 603A or 603B.

[0019] 8A is a schematic cross-sectional view of an example microelectronic system 800 similar to the microelectronic system shown in FIG. 6B, where like features are designated with like reference numerals, but which additionally or alternatively includes a temperature sensor 826 embedded in the thermoelectric element 603B to control temperature distribution and chip activity. For example, when the sensor 826 is detecting temperature, the sensor 826 can send a signal to the circuitry in the die 601B, 6001B, and / or 6002B, which can send a control signal to the thermoelectric element 603B. FIG. 8B is a schematic plan view of the example microelectronic system 800 shown in FIG. 8A, where the thermoelectric N / P pellet is monitored by the temperature sensor 826 and continuously fed by a pair of electrical contacts 817.

[0020] 9 is a schematic cross-sectional view of an example microelectronic system 900 similar to the microelectronic system shown in FIG. 6A, where like features are designated with like reference numerals. Rather than being controlled by the bottom chip 601A or an external device, the thermoelectric element 603A is controlled by an adjacent chip (e.g., 6001A or 6002A) via an electrical path 909 (e.g., a trace) through the bottom chip 601A.

[0021] FIG. 10 is a schematic cross-sectional view of an exemplary microelectronic system 1000 that includes stacked semiconductor elements (e.g., active dies 10020, 1020, and 10051) and multiple thermoelectric elements 10003 that can be used to actively redirect heat into or out of the system 1000 (e.g., through a heat sink 10077 at the top of the stack).

[0022] In some embodiments, the thermoelectric elements 603A, 603B or 10003 may be grown on a carrier (e.g., 605 or 10051) or on an active chip (e.g., 601A, 601B, 10020 or 1020). In some embodiments, the thermoelectric elements 603A, 603B or 10003 may be grown on the back side of the active chip (e.g., 601A, 601B, 10020 or 1020) or may be directly bonded. In some embodiments, the stacked semiconductor elements may be directly bonded to each other without an intervening adhesive. For example, 6001A, 6001B, 6002A, 6002B and / or 10020 may be directly bonded to the bottom chip (e.g., 601A, 601B or 1020) or to the thermoelectric elements 603B. In some embodiments, the top heat sink 607A, 607B, or 10077 can be direct bonded to the carrier 605 or 10051 associated with the semiconductor device (e.g., 6001A, 6001B, 6002A, 6002B, or 10020) and / or thermoelectric device 603A, 603B, or 10003. For example, direct bonding processes include the ZIBOND® and DBI® processes configured for room temperature, atmospheric pressure direct bonding configured for low temperature hybrid bonding, or the DBI® Ultra process commercially available from Adeia, Inc., San Jose, Calif. The direct bond can be located between the dielectrics of the bonded elements and can include a conductive material at or near the bond interface to enable direct hybrid bonding. The conductive material at the bonding interface may be bond pads and / or passive electronic components formed in or on a redistribution layer (RDL) on the die.

[0023] Electronic Devices A die may refer to any suitable type of integrated device die. For example, an integrated device die may include electronic components, such as integrated circuits (e.g., a processor die, a controller die, or a memory die), a microelectromechanical system (MEMS) die, an optical device, or any other suitable type of device die. In some embodiments, the electronic components include passive devices, such as capacitors, inductors, or other surface mount devices. Circuitry (e.g., active components such as transistors) may be patterned at or near the active side in various embodiments. The active side may be located on the side of the die opposite the back side of the die (the front side). The back side may or may not include any active or passive circuitry.

[0024] The integrated device die may have a bonding surface and a back surface opposite the bonding surface (in this case, the "front surface"). The bonding surface may have a plurality of conductive bond pads including one conductive bond pad, and a non-conductive material located proximate the conductive bond pads. In some embodiments, the conductive bond pads of the integrated device die may be directly bonded to corresponding conductive pads of the substrate or wafer without an intervening adhesive, and the non-conductive material of the integrated device die may be directly bonded to a portion of the corresponding non-conductive material of the substrate or wafer without an intervening adhesive. Direct bonding without adhesives is described in U.S. Patent Nos. 7,126,212, 8,153,505, 7,622,324, 7,602,070, 8,163,373, 8,389,378, 7,485,968, 8,735,219, 9,385,024, 9,391,143, and 9,4 Nos. 31,368, 9,953,941, 9,716,033, 9,852,988, 10,032,068, 10,204,893, 10,434,749, and 10,446,532, each of which is incorporated by reference in its entirety and incorporated herein for all purposes.

[0025] Direct bonding method and direct bonded structure Various embodiments disclosed herein relate to a direct bonded structure in which two elements can be directly bonded without an intervening adhesive. The two or more electronic elements can be semiconductor elements (e.g., integrated device dies, wafers, etc.), and the two or more electronic elements can be stacked or bonded together to form a bonded structure. The conductive contact pads of one element can be electrically connected to the corresponding conductive contact pads of the other element. Any suitable number of elements can be stacked into a bonded structure. The contact pads can be metal pads formed on non-conductive bonding areas, and can be connected to an underlying metallization, such as a redistribution layer (RDL).

[0026] In some embodiments, the elements are directly bonded to each other without adhesive. In various embodiments, a non-conductive material or dielectric of a first element may be directly bonded to a corresponding non-conductive or dielectric field region of a second element without adhesive. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of a first element may be directly bonded to a corresponding non-conductive material of a second element using inter-dielectric bonding techniques. For example, inter-dielectric bonds may be formed without adhesive using direct bonding techniques as disclosed in at least U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference herein in its entirety for all purposes. Dielectrics suitable for direct bonding include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, silicon oxynitride, or carbon such as silicon carbide, silicon oxycarbonitride, silicon carbonitride, or diamond-like carbon. In some embodiments, the dielectric does not include a polymeric material such as an epoxy, resin, or molding compound.

[0027] In some embodiments, the direct hybrid bond can be formed without an intervening adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or an etchant to activate the surfaces. In some embodiments, the surfaces can be terminated with a chemical species after or during activation (e.g., during a plasma and / or etch process). Without being bound by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding surfaces, and the end-grouping process can provide additional chemical species at the bonding surfaces that improve the bonding energy during direct bonding. In some embodiments, activation and end-grouping can be provided in the same step, for example, the surfaces can be activated and end-grouped using a plasma or a wet etchant. In other embodiments, the bonding surfaces can be end-grouped in a separate process to provide additional chemical species that can be used for direct bonding. In various embodiments, the end-grouping chemical species can include nitrogen. For example, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, one or many fluorine peaks may appear near the layers and / or bonding interface. Thus, in a direct bonded structure, the bonding interface between the two dielectrics may comprise a very smooth interface with high nitrogen content and / or fluorine peaks at the bonding interface. Additional examples of activation and / or end group treatments can be found throughout U.S. Patent Nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference and incorporated herein in its entirety for all purposes.

[0028] In various embodiments, the contact pads of the first component may also be directly bonded to the corresponding conductive contact pads of the second component. For example, hybrid direct bonding techniques may be used to provide conductor-conductor direct bonds along a bond interface that includes a covalently directly bonded inter-dielectric surface that has been pretreated as described above. In various embodiments, conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds may be formed using direct bonding techniques as disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, each of which is incorporated by reference herein in its entirety for all purposes.

[0029] For example, the dielectric bonding surfaces may be pretreated and directly bonded to each other without an intervening adhesive as described above. The conductive contact pads, which may be surrounded by a non-conductive dielectric field region, may also be directly bonded to each other without an intervening adhesive. In some embodiments, the contact pads may be recessed below the dielectric field region or the outer surface (e.g., top surface) of the non-conductive bonding layer, for example by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, in the range of 2 nm to 20 nm or in the range of 4 nm to 10 nm. The non-conductive bonding layers may in some embodiments be directly bonded to each other without an adhesive at room temperature with a bonding tool described herein, after which the bonded structure may be annealed. The annealing may be performed in a separate apparatus. During annealing, the contact pads may expand and contact each other, thereby forming a metal-metal (intermetal) direct bond. Advantageously, the use of hybrid bonding technology, such as Direct Bond Interconnect, or DBI® technology, commercially available from Adair, Inc., San Jose, Calif., allows for a high density of pads connected across the direct bond interface (e.g., with a small or fine pitch for a regular array). In some embodiments, the pitch of the bond pads, or the conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 microns, or less than 10 microns, or even less than 2 microns. For some applications, the ratio of the bond pad pitch to one of the bond pad features is less than 5 or less than 3, and in some cases desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range from 0.3 microns to 5 microns. In various embodiments, the contact pads and / or traces may be made of copper, although other metals may be suitable.

[0030] Thus, in a direct bonding process, the first element can be directly bonded to the second element without an intervening adhesive. In some configurations, the first element can be a singulated element, such as a singulated integrated device die. In other configurations, the first element can be a carrier or substrate (e.g., a wafer) that includes multiple (e.g., tens, hundreds, or more) device regions that, when singulated, form multiple integrated device dies. In the embodiments described herein, the first element, whether a die or a substrate, may be considered a host substrate, which is attached to a support of a bonding tool for pick-and-placement of the second element or for receiving a robotic end effector. The second element in the illustrated embodiment is a die. In other configurations, the second element can be a carrier or flat panel, or a substrate (e.g., a wafer).

[0031] As described herein, the first and second elements can be directly bonded together without adhesive, which is different from a deposition process. In one application, the width of the first element in the bonded structure can be approximately the same as the width of the second element. In some other embodiments, the width of the first element in the bonded structure can be different from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Thus, the first and second elements can be comprised of non-deposited elements. Furthermore, unlike deposited layers, the direct bonded structure can include defect areas along the bond interface where nanocavities exist. The nanocavities can form due to activation (e.g., exposure to plasma) of the bonding surface. As discussed above, the bond interface can exhibit a concentration of material resulting from activation and / or final chemical treatment processes. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak can form at the bond interface. In embodiments utilizing oxygen plasma for activation, oxygen peaks may form at the bond interface. In some embodiments, the bond interface may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond may include a covalent bond, which is stronger than a van der Waals bond. The bonding layer may further have a polished surface that is planarized to a high degree of smoothness. For example, the bonding layer may have a surface roughness of 2 nm root mean square (RMS) per micron or 1 nm RMS per micron.

[0032] In various embodiments, the metal-metal bonds between the contact pads in the direct hybrid bonded structure may be bonded such that the conductive feature grains on the conductive features, e.g., copper grains, grow into one another across the bond interface. In some embodiments, the copper may have grains oriented along 111 crystal planes to improve diffusion of the copper across the bond interface. The bond interface may extend substantially completely to at least a portion of the bonded contact pad, such that there are substantially no gaps between the non-conductive bond regions at or near the bonded contact pad. In some embodiments, a barrier layer may be provided under the contact pad (e.g., which may include copper). However, in other embodiments, there may be no barrier layer under the contact pad, as described, for example, in U.S. Patent Application Publication No. 2019 / 0096741, which is incorporated by reference in its entirety and incorporated by reference herein for all purposes.

[0033] In one aspect, the disclosed technology relates to a microelectronic device having a first integrated device die, a thermoelectric element bonded to the first integrated device die, and a heat sink attached to at least the thermoelectric element, the thermoelectric element configured to transfer heat from the first integrated device die to the heat sink, and the thermoelectric element being directly bonded to the first integrated device die without an adhesive.

[0034] In one embodiment, the first integrated device die has active circuitry.

[0035] In one embodiment, the thermoelectric element is direct bonded to the back side of the first integrated device die.

[0036] In one embodiment, the interface between the first integrated device die and the thermoelectric element includes a conductor-to-conductor direct bond.

[0037] In one embodiment, the interface between the first integrated device die and the thermoelectric element further includes a non-conductor-to-non-conductor direct bond.

[0038] In one embodiment, a carrier element is disposed between the thermoelectric element and the heat sink.

[0039] In one embodiment, the carrier element is free of active circuitry.

[0040] In one embodiment, the carrier element is made of silicon, ceramic, aluminum, aluminum nitride, or silicon carbide.

[0041] In one embodiment, the carrier element is made of a material having a thermal conductivity greater than 1 W / cm / °C.

[0042] In one embodiment, the thermoelectric elements are grown on the carrier element by a stenciling or printing process.

[0043] In one embodiment, the thermoelectric elements are grown in cavities in the carrier element by a sintering process.

[0044] In one embodiment, the thermoelectric element is directly bonded to the carrier element without an adhesive.

[0045] In one embodiment, the interface between the thermoelectric element and the carrier element comprises a dielectric-to-dielectric direct bond.

[0046] In one embodiment, heat is transferred from the first integrated device die to a heat sink during operation of the thermoelectric element.

[0047] In one embodiment, A second integrated device die is disposed over the thermoelectric element and in contact with the heat sink.

[0048] In one embodiment, a second integrated device die is provided on the first integrated device die and is located adjacent to the thermoelectric element.

[0049] In one embodiment, the thermoelectric element is electrically connected to the second integrated device die through the first integrated device die.

[0050] In one embodiment, the thermoelectric elements are attached to bond wires that are connectable to an external power source.

[0051] In one embodiment, the thermoelectric element is electrically connected to the first integrated device die by metal contacts.

[0052] In one embodiment, the thermoelectric elements are electrically connected to through-substrate vias in the first integrated device die.

[0053] In one embodiment, the thermoelectric elements are configured to allow for zoned control of cooling the first integrated device die.

[0054] In one embodiment, a number of temperature sensors are provided within the first integrated device die or the thermoelectric element.

[0055] In one embodiment, the microelectronic device further comprises a plurality of electrical contact pairs, each electrical contact pair independently controlling a portion of the thermoelectric element.

[0056] In one embodiment, the thermoelectric element is actuated by the first integrated device die, the thermoelectric element, or an external chip.

[0057] In another aspect, the disclosed technology relates to a microelectronic device having a first integrated device die, a thermoelectric element formed on the first integrated device die, and a heat sink attached to at least the thermoelectric element, the thermoelectric element configured to transfer heat from the first integrated device die to the heat sink.

[0058] In one embodiment, the thermoelectric elements are grown on a first integrated device die.

[0059] In one embodiment, the thermoelectric element is deposited on a first integrated device die.

[0060] In one embodiment, the first integrated device die has active circuitry.

[0061] In one embodiment, the thermoelectric elements are grown on a first integrated device die.

[0062] In one embodiment, the thermoelectric elements are grown on the first integrated device die by a stenciling or printing process.

[0063] In one embodiment, heat is transferred from the first integrated device die to a heat sink during operation of the thermoelectric element.

[0064] In one embodiment, a second integrated device die is disposed over the thermoelectric element and in contact with the heat sink.

[0065] In one embodiment, a second integrated device die is provided on the first integrated device die and is located adjacent to the thermoelectric element.

[0066] In one embodiment, the thermoelectric element is electrically connected to the second integrated device die through the first integrated device die.

[0067] In one embodiment, the thermoelectric elements are attached to bond wires that are connectable to an external power source.

[0068] In one embodiment, the thermoelectric element is electrically connected to the first integrated device die by metal contacts.

[0069] In one embodiment, the thermoelectric elements are electrically connected to through-substrate vias in the first integrated device die.

[0070] In one embodiment, the thermoelectric elements are configured to allow for zoned control of cooling the first integrated device die.

[0071] In one embodiment, multiple temperature sensors are provided within the first integrated device die or thermoelectric element, with each temperature sensor associated with two electrical contacts to activate a portion of the thermoelectric element.

[0072] In one embodiment, the microelectronic device further comprises a plurality of electrical contact pairs, each electrical contact pair independently controlling a portion of the thermoelectric element.

[0073] In one embodiment, the thermoelectric element is actuated by the first integrated device die, the thermoelectric element, or an external chip.

[0074] In another aspect, the disclosed technology relates to a microelectronic device having a first integrated device die, a thermoelectric element disposed on the first integrated device die, and a carrier element disposed on the thermoelectric element, the thermoelectric element configured to provide zoned control for cooling the first integrated device die.

[0075] In one embodiment, the first integrated device die has a plurality of zones, at least one of which is actuated by a temperature trigger, the temperature trigger being received from a thermal sensor.

[0076] 44. The microelectronic device of claim 43, in one embodiment, the thermal sensor is provided within the first integrated device die or the thermoelectric element.

[0077] In one embodiment, the carrier element is free of active circuitry.

[0078] In one embodiment, the thermoelectric elements are grown on the back side of the first integrated device die by a stenciling or printing process.

[0079] In one embodiment, the thermoelectric element is direct bonded to the back side of the first integrated device die.

[0080] In another aspect, the disclosed technology relates to a microelectronic device having a first integrated device die, a thermoelectric element disposed on the first integrated device die, a carrier element disposed on the thermoelectric element, and a heat sink attached to at least the carrier element, the thermoelectric element configured to transfer heat from the first integrated device die to the heat sink.

[0081] In one embodiment, the carrier element is free of active circuitry.

[0082] In one embodiment, the microelectronic device includes an additional carrier element disposed between the first integrated device die and the thermoelectric element.

[0083] In one embodiment, a first integrated device die has active circuitry and the thermoelectric elements are grown on the back side of the first integrated device die by a stenciling or printing process.

[0084] In one embodiment, the thermoelectric device has active circuitry and is direct bonded to the back side of the first integrated device die.

[0085] In one embodiment, the carrier element is made of silicon or ceramic.

[0086] In one embodiment, the thermoelectric elements are grown on the carrier element by a stenciling or printing process.

[0087] In one embodiment, the thermoelectric element is directly bonded to the carrier element by a sintering process.

[0088] In one embodiment, the thermoelectric element is directly bonded to the carrier element without an adhesive.

[0089] In one embodiment, heat is transferred from the first integrated device die through the carrier element to the heat sink during operation of the thermoelectric element.

[0090] In one embodiment, a second integrated device die is disposed over the thermoelectric element and in contact with the heat sink.

[0091] In one embodiment, a second integrated device die is provided on the first integrated device die and is located adjacent to the thermoelectric element.

[0092] In one embodiment, the thermoelectric element is electrically connected to the second integrated device die through the first integrated device die.

[0093] In one embodiment, the thermoelectric elements are attached to bond wires that are connectable to an external power source.

[0094] In one embodiment, the thermoelectric element is electrically connected to the first integrated device die by metal contacts.

[0095] In one embodiment, the thermoelectric elements are electrically connected to through-substrate vias in the first integrated device die.

[0096] In one embodiment, multiple temperature sensors are provided within the thermoelectric device, with each temperature sensor associated with two electrical contacts to activate a portion of the thermoelectric device.

[0097] In one embodiment, the microelectronic device further comprises a plurality of electrical contact pairs, each electrical contact pair independently controlling a portion of the thermoelectric element.

[0098] In another aspect, the disclosed technology relates to a microelectronic device configured for direct bonding, the microelectronic device comprising a carrier element, the carrier element being devoid of active circuitry, the microelectronic device further comprising a thermoelectric element grown on the carrier element by a stenciling or printing process, the thermoelectric element having a surface configured for direct hybrid bonding.

[0099] In another aspect, the disclosed technology relates to a microelectronic device configured for direct hybrid bonding, the microelectronic device having a carrier element, the carrier element being devoid of active circuitry, the microelectronic device having a thermoelectric element grown in a cavity in the carrier element by a sintering process, the thermoelectric element having a surface configured for direct hybrid bonding.

[0100] In another aspect, the disclosed technology relates to a microelectronic device configured for direct bonding, the microelectronic device having a carrier element, the carrier element being devoid of active circuitry, the microelectronic device having a thermoelectric element with a surface that is directly bonded to the carrier element without an adhesive and an opposing surface that is configured for direct hybrid bonding.

[0101] In another aspect, the disclosed technology relates to a method of fabricating a microelectronic device, the method including the steps of providing a first integrated device die having active circuitry and growing a thermoelectric element on a back surface of the first integrated device die.

[0102] In one embodiment, the thermoelectric elements are grown on the carrier element by a stenciling or printing process.

[0103] In one embodiment, the thermoelectric element is electrically connected to the first integrated device die by metal contacts.

[0104] In another aspect, the disclosed technology relates to a method of making a microelectronic device, the method comprising the steps of providing a carrier element free of active circuitry, growing a thermoelectric element on the carrier element, and preparing a surface of the thermoelectric element for direct hybrid bonding.

[0105] In one embodiment, the thermoelectric elements are grown on the carrier element by a stenciling or printing process.

[0106] In one embodiment, the carrier element is made of silicon or ceramic.

[0107] In another aspect, the disclosed technology relates to a method of making a microelectronic device, the method including the steps of providing a carrier element free of active circuitry, forming a cavity in the carrier element, growing a thermoelectric element on the carrier element and in the cavity, and preparing a surface of the thermoelectric element for direct hybrid bonding.

[0108] In one embodiment, the thermoelectric elements are grown by a sintering process.

[0109] In one embodiment, the carrier element is made of silicon or ceramic.

[0110] In another aspect, the disclosed technology relates to a method of fabricating a microelectronic device, the method comprising the steps of providing a wafer having a thermoelectric element; direct bonding one side of the wafer to a carrier element; thinning the wafer from an opposite side to expose the thermoelectric element; and preparing a surface of the thermoelectric element for direct hybrid bonding.

[0111] In one embodiment, the carrier element is free of active circuitry.

[0112] In one embodiment, the carrier element is made of silicon or ceramic.

[0113] In another aspect, the disclosed technology relates to a microelectronic device having a first integrated device die, a thermoelectric element bonded to the first integrated device die, and a heat sink attached to at least the thermoelectric element, the thermoelectric element configured to transfer heat from the first integrated device die to the heat sink, and the thermoelectric element actuated by the first integrated device die.

[0114] In one embodiment, the thermoelectric element is directly bonded to the first integrated device die without an adhesive.

[0115] Unless the context clearly requires otherwise, throughout the specification and claims, the terms "comprise", "comprising", "include", "including" and the like are to be construed in an inclusive sense, i.e., "including, but not limited to", as opposed to an exclusive or exhaustive sense. As used generally herein, the term "coupled" means two or more elements that are directly connected to each other or that are connected to each other through one or more intermediate elements. Similarly, as used generally herein, the term "coupled" means two or more elements that are directly connected to each other or that are connected to each other through one or more intermediate elements. In addition, the terms "herein," "above," "below," and terms of similar import used in the parent application refer to the application as a whole and not to any particular portion of the application. Furthermore, as used herein, when a first element is described as being located "on" or "over" a second element, the first element may be directly located on or over the second element such that the first element and the second element are in direct contact with each other, or the first element may be indirectly located on or over the second element such that one or more elements are interposed between the first element and the second element. Where the context permits, terms in the above detailed description using the singular or plural may include the plural or singular, respectively. The term "or" in reference to a list of two or more items includes all of the following interpretations of that term: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0116] Furthermore, conditional terms used in the specification, particularly "can," "could," "might," "may," "eg," "for example," "such as," and the like, unless expressly specified otherwise or understood otherwise within the context in which they are used, are generally intended to imply that certain embodiments include certain features, elements, and / or conditions and that other embodiments do not include certain features, elements, and / or conditions. Thus, such conditional terms are not generally intended to imply that features, elements, and / or conditions are present in any required manner for one or more embodiments.

[0117] Although certain embodiments have been described, these embodiments are provided by way of example only and are not intended to limit the scope of the invention. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and furthermore, various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the scope of the invention. For example, although blocks are shown in a given arrangement, alternative embodiments may perform substantially the same functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, divided, combined, and / or modified. Each of these blocks may be embodied in a wide variety of ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The scope of the invention as set forth in the appended claims and equivalents thereto is intended to include such forms or modifications within the scope and spirit of the invention.

Claims

1. 1. A microelectronic device comprising: a first integrated device die; a thermoelectric element bonded to the first integrated device die; a heat sink attached to at least the thermoelectric element; A microelectronic device, wherein the thermoelectric element is configured to transfer heat from the first integrated device die to the heat sink, and the thermoelectric element is directly bonded to the first integrated device die without adhesive.

2. The microelectronic device of claim 1 , wherein the first integrated device die includes active circuitry.

3. The microelectronic device of claim 2 , wherein the thermoelectric element is directly bonded to a backside of the first integrated device die.

4. The microelectronic device of claim 1 , wherein the interface between the first integrated device die and the thermoelectric element comprises a conductor-to-conductor direct bond.

5. The microelectronic device of claim 4 , wherein the interface between the first integrated device die and the thermoelectric element further comprises a non-conductor-to-non-conductor direct bond.

6. The microelectronic device of claim 1 further comprising a carrier element disposed between the thermoelectric element and the heat sink.

7. The microelectronic device of claim 6 , wherein the thermoelectric element is directly bonded to the carrier element without adhesive, and the interface between the thermoelectric element and the carrier element comprises a dielectric-to-dielectric bond.

8. The microelectronic device of claim 1 , wherein heat is transferred from the first integrated device die to the heat sink during operation of the thermoelectric element.

9. The microelectronic device of claim 1 further comprising a second integrated device die disposed over the thermoelectric element and in contact with the heat sink.

10. The microelectronic device of claim 1 further comprising a second integrated device die disposed on the first integrated device die and positioned adjacent to the thermoelectric element.

11. The microelectronic device of claim 1 , wherein the thermoelectric element is attached to a bond wire that is connectable to an external power source.

12. The microelectronic device of claim 1 , wherein the thermoelectric element is electrically connected to the first integrated device die by a metal contact.

13. The microelectronic device of claim 1 , wherein the thermoelectric element is electrically connected to a through-substrate via in the first integrated device die.

14. The microelectronic device of claim 1 , wherein the thermoelectric element is configured to allow zoned control of cooling of the first integrated device die.

15. The microelectronic device of claim 14 , further comprising a plurality of temperature sensors disposed within the first integrated device die or the thermoelectric element.

16. The microelectronic device of claim 14 further comprising a plurality of pairs of electrical contacts, each pair of electrical contacts independently controlling a portion of the thermoelectric element.

17. The microelectronic device of claim 14 , wherein the thermoelectric element is actuated by the first integrated device die, the thermoelectric element, or an external chip.

18. 1. A microelectronic device comprising: a first integrated device die; a thermoelectric element formed on the first integrated device die; a heat sink attached to at least the thermoelectric element; The microelectronic device, wherein the thermoelectric element is configured to transfer heat from the first integrated device die to the heat sink.

19. The microelectronic device of claim 18 , wherein the first integrated device die includes active circuitry.

20. The microelectronic device of claim 18 , wherein heat is transferred from the first integrated device die to the heat sink during operation of the thermoelectric element.

21. The microelectronic device of claim 1 , wherein the thermoelectric element is attached to a bond wire that is connectable to an external power source.

22. 20. The microelectronic device of claim 18, wherein the thermoelectric element is electrically connected to the first integrated device die by a metal contact.

23. The microelectronic device of claim 18 , wherein the thermoelectric element is electrically connected to a through-substrate via in the first integrated device die.

24. 20. The microelectronic device of claim 18, wherein the thermoelectric element is configured to allow zoned control of cooling of the first integrated device die.

25. 25. The microelectronic device of claim 24, further comprising a plurality of temperature sensors disposed within the first integrated device die or the thermoelectric element, each temperature sensor associated with two electrical contacts for actuating a portion of the thermoelectric element.

26. 1. A microelectronic device comprising: a first integrated device die; a thermoelectric element disposed on the first integrated device die; a carrier element disposed on the thermoelectric element, The microelectronic device, wherein the thermoelectric element is configured to allow zoned control of cooling of the first integrated device die.

27. 27. The microelectronic device of claim 26, wherein the first integrated device die has a plurality of zones, at least one of the zones being activated by a temperature trigger, the temperature trigger being received from a thermal sensor.

28. 28. The microelectronic device of claim 27, wherein the thermal sensor is disposed within the first integrated device die or the thermoelectric element.

29. 27. The microelectronic device of claim 26, wherein the carrier element is free of active circuitry.

30. 27. The microelectronic device of claim 26, wherein the thermoelectric element is direct bonded to a backside of the first integrated device die.

Images