Signal supply device for signal transmission

Abstract

The single-power supply device for signal transmission includes two operational amplifiers (OA), two transistors, a resistor, a feedback circuit (FC) and a current setter. The output of the first OA is connected to a first electrode of the first transistor, and the first input of the first OA is connected to a terminal for receiving an input signal. The second transistor, the second OA and the resistor form a voltage stabilizer (CS). The input of the CS and the connection point between the third electrode of the first transistor and the first terminal of the FC are reserved for connecting a load. The second terminal of the FC is connected to the second input of the first OA. When made as an IC, the device can have the FC and the current setter externally. Using the single-power supply operation, the present invention can ensure the extension of the dynamic range of the transmission signal and the high growth rate of the output signal.

Description

[Technical field]

[0001] The present invention relates to the fields of radio engineering, electronics, and measurement technology and is designed for distortion-free transmission of wideband signals in a variety of electronic systems that use single-supply operation. [Background technology]

[0002] Unlike known devices for signal transmission using bipolar power supplies, in single-supply devices it is difficult to obtain an output voltage close to zero. For example, if a pedestal is added to the output power supply to shift the output voltage closer to zero, it becomes necessary to precisely control the preset level of the pedestal, especially for the transmission of small signals whose amplitudes can be on the order of a few millivolts. In other words, the reduction of supply voltages (especially with regard to mobile devices) is the main trend in the abovementioned fields, which urgently requires a lowering of the minimum undistorted output voltage in order to maintain or expand the dynamic range of the transmitted signals.

[0003] The above is the reason why the problem of having a minimum ("near-zero") output voltage in single-supply devices for signal transmission is one of the most pressing issues in modern electronics, especially in the design of analog and analog-digital chips. Also, in any device for signal transmission, including those using single-supply operation, it is important to provide a high signal growth rate necessary for distortion-free transmission of wideband signals.

[0004] In the art, a single-supply operational amplifier (OA) for transmitting signals is known, as disclosed in the Texas Instruments® Operational Amplifier OPA189 specification ( / data_sheets / OPAxl89 Precision, Lowest-Noise, 36-V, Zero-Drift, 14-MHz, MUX-Friendly, Rail-to-Rail Output Operational Amplifiers datasheet (SBOS830I - SEPTEMBER 2017 - REVISED OCTOBER 2021)). This disclosure shows an OA input circuit designed to operate with an input voltage range from -0.1 V to 2.5 V below the voltage supply, and a series connection of three amplification modules using an open feedback circuit to provide a transmission gain of 170 dB.

[0005] The output voltage of conventional designs is a function of the load resistance, so it is between 20mV (load resistance of 10K ohms) and 80mV (load resistance of 2K ohms). In some cases, this can be unacceptably large and distort the transmitted signal, which is near zero. The inability to provide a near zero output voltage, i.e., proportional to the transmitted signal, is considered a flaw in the design.

[0006] A similar design is known and disclosed in “Output stage for near rail operation” (U.S. Pat. No. 9,548,707, issued Jan. 17, 2017).

[0007] The circuit of this design for distortion-free transmission of low-voltage signals under a single power supply includes a differential amplifier having a non-inverting ("+") input and an inverting ("-") input, a main transistor arranged in a common-emitter configuration, a current generator, a buffer amplifier, and an output current circuit, in which the output of the differential amplifier is connected to a control electrode of the main transistor, the current generator is connected to one of the electrodes of the main transistor and to a control electrode of the buffer amplifier, and the emitter of the buffer amplifier is contacted to the input of the output current circuit, representing the output of the design.

[0008] The drawback of this design is that when implemented, its output voltage cannot be made smaller than 2 mV (column 3, lines 63-65 of the above patent). In practice, this is not sufficient to reach an output voltage close to zero and thus undistorted transmission of low voltage signals.

[0009] Another similar example is the technical determination described in “Output stage bleeder circuit applied to ultralow quiescent current LDO” (China Application No. 111930167, November 13, 2020).

[0010] The designed circuit is an operational amplifier OA with a non-inverting ("+") input and an inverting ("-") input which is the input of this design, a transistor with its gate connected to the output of OA and its source connected to the output of this design, a resistor divider connected between the output of this design and a current source made as a current mirror, and a current controller I b and the midpoint of the divider is connected to the non-inverting ("+") input of the OA.

[0011] The negative aspect of this design is that it cannot provide both a "near zero" output voltage and a high growth rate of the signal.

[0012] The closest analogue to the claimed design is the "Rail-to-rail input / output operational amplifier and method" disclosed in US Patent No. 6,356,153, March 12, 2002. This device includes an input stage, two gain boost amplifiers, and an output stage. Essential to achieve the goal of the proposed device is a piece of prior art design with two amplifiers and an output stage. This piece, selected as a prototype, includes two OAs, four transistors, two resistors, and a class AB operational circuit.

[0013] In this circuit, a first terminal of the first transistor is connected to the output of the first OA, a second terminal of the first transistor is connected to a first terminal of the class AB operational circuit and to a first terminal of the third transistor, a first input of the first OA is connected to a signal source, a third terminal of the first transistor is connected to another input of the first OA and to the first terminal of the first resistor, and a third terminal of the third transistor is connected to the second terminal of the first resistor.

[0014] Furthermore, a first terminal of the second transistor is connected to the output of the second OA, a second terminal of the second transistor is connected to the second terminal of the class AB arithmetic circuit and the first terminal of the fourth transistor, a third terminal of the second transistor is connected to the input of the second OA and the first terminal of the second resistor, a third terminal of the fourth transistor is connected to the second terminal of the second resistor, another input of the second OA is connected to a signal source, and second terminals of the third resistor and the fourth resistor are connected to each other.

[0015] The common configuration between the proposed design and the prototype is two OAs, two transistors, and a resistor, with a first terminal of the first transistor connected to the output of the first OA, a first input of the first OA for connecting to a source of a signal, a first terminal of the second transistor connected to the output of the second OA, and a third terminal of the second transistor connected to one of the inputs of the second OA and to the first terminal of the resistor.

[0016] This prototype works with class AB amplification conditions, which tend to have nonlinear distortion of signals, and for that reason, it cannot provide distortion-free transmission of signals, especially wideband "near-zero" signals. Summary of the Invention [Problem to be solved by the invention]

[0017] The object of the claimed invention is to overcome the drawbacks of the prior art and to provide a single-supply device for signal transmission for distortion-free signal transmission over a wide dynamic range, which device is capable of producing a minimum ("near-zero") output voltage (only a few mV) when a wideband "near-zero" signal is provided to its input.

[0018] The technical result, not available in prior art designs, is a substantial extension of the dynamic range of single-supply devices for signal transmission while at the same time providing a high growth rate of the output signal. [Means for solving the problem]

[0019] The above technical result can be achieved by providing a feedback circuit and an output current setter in a device including two OAs, two transistors and a resistor connected as above, in which the third terminal of the first transistor is connected to the second terminal of the second transistor, the connection being connected to the load and the feedback circuit, the feedback circuit being connected to the second input of the first OA and the output current setter being connected to the second input of the second OA. The above connection of the components of the claimed device makes it possible to define therein a current stabilizer, which includes the second OA, the second transistor and the resistor together with their connections. Thus, the output of the output current setter is the input of the current stabilizer and the output of the current stabilizer is the second terminal of the resistor.

[0020] The claimed device is of simple design compared to the prototype and is capable of producing a minimum ("near zero") output voltage (only a few mV vs. units and tens of millivolts of the prior art) while achieving a high growth rate of the output signal, which is necessary for distortion-free transmission of wideband signals, and eliminating nonlinear distortions by using class AB amplification conditions.

[0021] This substantially increases the dynamic range of single-supply devices for wideband signal transmission.

[0022] Additionally, the claimed technical solution is configured as an integral circuit (IC) combining multiple components of the claimed device, which is presented for patent protection.

[0023] In this embodiment, the above mentioned technical result is achieved by providing an IC including a complex of device components, namely two OAs, two transistors and a resistor. The output of the first OA is connected to a first terminal of the first transistor and the output of the second OA is connected to a first terminal of the second transistor. The second input of the first OA is connected to a terminal of the IC intended to provide an input signal. The third terminal of the second transistor is connected to a first input of the second OA and to a terminal of the resistor. The third terminal of the first transistor is connected to a second terminal of the second transistor, this connection being connected to a terminal of the IC intended to connect to a load and to a first terminal of a feedback circuit, this circuit being external to the IC.

[0024] Furthermore, the IC comprises a terminal intended for connection to a second terminal of an external feedback circuit, said IC terminal being connected to a second input of the first OA and capable of being used for connection to a source of a second input signal, and the integral circuit comprises a terminal connected to a second input of the second OA and intended for connection to an external current setter.

[0025] The claimed invention is further explained with the aid of the accompanying drawings, which show an implementation of an apparatus for signal transmission. [Brief description of the drawings]

[0026] [Figure 1] Figure 1 shows the prototype. [Figure 2a] FIG. 2a shows the claimed invention in comparison with the prototype. [Figure 2b] FIG. 2b shows the claimed invention formulated as an IC. [Diagram 3] FIG. 3 illustrates the claimed invention in one form of its implementation. [Figure 4] FIG. 4 illustrates the claimed invention in another implementation of the claimed invention. [Diagram 5] FIG. 5 shows the claimed invention in another form of implementation thereof. [Figure 6] FIG. 6 shows an embodiment of an output current setter for a current stabilizer in the claimed invention. [Figure 7] FIG. 7 shows another embodiment of a power setter for a current stabilizer in the claimed invention. [Figure 8] FIG. 8 shows another embodiment of a power setter for a current stabilizer in the claimed invention. [Figure 9] 9a-9f show graphs illustrating the reduction in distortion level of the transmitted signal when using the proposed technical solution. [Figure 10] FIG. 10 shows a screenshot of an oscillograph screen illustrating the results of an experiment demonstrating the achievement of the technical results described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Detailed Description of the Invention The claimed apparatus and its operation are described below with reference to the drawings.

[0028] Figure 1 shows a part of a prior art rail-to-rail differential amplifier according to US Patent No. 6,356,153. The part (prototype) includes two OAs (58A and 57A), four transistors (26, 30, 37, and 45), two resistors (89, 88), and a class AB arithmetic circuit (29), the prototype has two inputs (22, 33) connected to the inputs of the first OA and the second OA, respectively, and the junction (31) of the third terminal of the third and fourth transistors is the output of the prototype.

[0029] In comparison with this prototype, the present invention is shown in Fig. 2a, where the claimed device 100 includes a first OA 101, a first transistor (MOSFET in Fig. 2) 103, an output current setter 155, a terminal 107 for connection to the positive pole of a power supply (PS), a first input terminal 109, a first PS terminal 111 and a second PS terminal 113 of the first OA 101, a first input 115 of the first OA 101 (shown as non-inverted "+" in Fig. 2a) connected to the first input terminal 109, a second input 117 of the first OA 101 (shown as inverted "-" in Fig. 2a) connected to a second input terminal 118, and an output 119 of the first OA 101 is connected to a first (control) terminal 121 (gate terminal in Fig. 2a) of the first transistor 103.

[0030] A second terminal 125 (drain terminal in FIG. 2a) of the first transistor 103 is connected to the first PS terminal 111 and to terminal 107 of the first OA 101, and a second PS terminal 113 of the first OA 101 is connected to terminal 127 for connection to the common line (ground) and to the negative pole of the PS. A connection of a third terminal 123 (source terminal in FIG. 2a) of the first transistor 103 to a second terminal 191 (drain terminal in FIG. 2a) of the second transistor 153 (MOSFET in FIG. 2a) is used for connection to a load (not shown) via terminal 135.

[0031] A third terminal 193 (the source terminal in FIG. 2 a ) of the second transistor 153 is connected to a first input 169 (the inverted “−” one in FIG. 2 a ) of the second OA 151 and to a first terminal 187 of the resistor 157 .

[0032] A first (control) terminal 181 (the gate terminal in FIG. 2 a ) of the second transistor 153 is connected to the output 165 of the second OA 151 .

[0033] The first PS terminal 159 of the second OA 151 is connected to a contact 129 for connection with the positive pole of the PS, and the second PS terminal 161 of the second OA 151 and the second terminal 189 of the resistor 157 are connected to a terminal 127 of the device 100 intended to be connected to the common wiring (frame) and to the negative pole of the PS.

[0034] A first terminal 137 of the feedback circuit (FC) 143 is connected to the junction between the first transistor 103 and the second transistor 153, a second terminal 139 of the FC 143 is connected to the second input 117 of the first OA 101, and a third terminal 141 of the FC 143 is connected to the terminal 127 of the device 100.

[0035] It was mentioned above that the second OA 151, the second transistor 153 and the resistor 157 and the connections therebetween form the current stabilizer 105, whose input 131 is connected to the second terminal 191 of the second transistor 153 and to the terminal 35 of the device 100. The contact 133 connected to the second terminal 189 of the resistor 157 and to the terminal 127 serves as the output of the stabilizer 105. The potential controlling the value of the current of the stabilizer 105 is supplied from the second terminal 173 of the output current setter 155 to the second input 167 of the second OA 151 (the non-inverted "+" one in FIG. 2a) via the contact 163 of the stabilizer 105.

[0036] The contact 171 of the output current setting device 155 and the contact 129 of the stabilizer are connected to the positive pole of the PS, and the contact 177 of the output current setting device 155 is connected to the terminal 127 .

[0037] Not shown in FIG. 2a are the PS, the input signal source and the load connected to the respective terminals of the device.

[0038] For clarity, thicker lines are used in Figure 2a to indicate components (FC 143 and output current setter 155) and connections that are not in the prototype, and it is because of the provision of those components and connections that the above-mentioned technical effects are achieved.

[0039] A circuit diagram of the claimed device configured as an IC is shown in Fig. 2b. The device 200 includes a first OA 101, a first transistor 103 (MOSFET in Fig. 2b) and a current stabilizer 105 implemented similarly to that of Fig. 2a. The device 200 also has a terminal 107 for connection to the positive pole of the PS, a terminal 135 for connection to a load and an external FC, a terminal 127 for connection to the negative pole of the PS, a first input terminal 109 for connection to a signal source, a second input terminal 118 for connection to an external FC and another signal source, and a terminal 163 for connection to the output of the current setter.

[0040] A first input 115 (non-inverted "+" in FIG. 2b) of the first OA 101 is connected to a first input terminal 109 of the device 200, a second input 117 (inverted "-" in FIG. 2b) of the first OA 101 is connected to a second input terminal 118 of the device 200, and a first (control) terminal 121 (gate terminal in FIG. 2b) of the first transistor 103 is connected to an output 119 of the first OA 101. A second terminal 125 (drain terminal in FIG. 2b) of the first transistor 103 is connected to a first power supply terminal 111 of the first OA 101 and to a terminal 107 connected to the positive pole of the power supply. A second PS terminal 113 of the OA 101 is connected to a terminal 127 of the device 200.

[0041] The junction point between the third terminal 123 (source terminal in FIG. 2b) of the first transistor 103 and the first terminal 131 of the current stabilizer 105 is connected to a terminal 135 of the device 200. An output 133 of the current stabilizer 105 is connected to a terminal 127 of the device 200 intended for connection with the negative pole of PS. A contact 129 of the current stabilizer 105 is intended for connection with the positive pole of PS.

[0042] Although not shown in FIG. 2b, PS, the input signal source, the load, FC, and the output current setter and their connections are connected to the respective terminals of the integral circuit 200.

[0043] A circuit diagram of one of the embodiments of the claimed device is shown in Figure 3, in which device 100 is shown to include OA 101, transistor 103, current stabilizer 105, output current setter 155, and FC 143. Designated at 107 is a terminal for connection to the positive pole of PS. Also shown in Figure 3 and associated with OA 101 are a first input terminal 109 of the device, a first PS terminal 111, a second PS terminal 113, a first input 115 (non-inverting "+" in Figure 3) connected to first input terminal 109, and an output terminal 119 connected to a first terminal 121 (control-gate terminal in Figure 3) of transistor 103. The third terminal 123 (the source terminal in FIG. 3) of the transistor 103 is connected to the first terminal 131 of the current stabilizer 105 and to a terminal 135 of the device 100 reserved for connection to a load, and the second terminal 125 (the drain terminal in FIG. 3) of the transistor 103 is connected to the first PS terminal 111 of the OA 101 and to the terminal 107 of the device 100 and is intended to be connected to the positive pole of the PS.

[0044] A PS terminal 129 of the current stabilizer 105 is reserved for connection to the positive pole of the PS source. Furthermore, a terminal 127 is provided, which is reserved for connection to the negative pole of the PS source and is also connected to the second PS terminal 113 of the OA 101, to the second terminal 133 of the current stabilizer 105 and to the terminal 177 of the output current setter 155 via the common wiring (frame) of the device. A terminal 163 of the current stabilizer 105 is connected to the second terminal 173 of the output current setter 155.

[0045] A standard wire connecting the first terminal 137 and the second terminal 139 of FC 143 is used for FC 143 itself. The first terminal 137 of FC 143 is connected to the junction of transistor 103 and current stabilizer 105, the second terminal 139 of FC 143 is connected to the second input 117 of OA 101, and the unused third terminal 141 of FC 143 is connected to terminal 127 of the device.

[0046] The contact 171 of the output current setter 155 and the contact 129 of the current stabilizer 105 are each reserved for connection to the positive pole of the PS source. The terminal 135 connected to the first terminal 137 of the current stabilizer 105, the third terminal 123 of the transistor 103 and the first terminal 137 of the FC 143 is intended to be connected to a load.

[0047] The PS source, the input signal source and the load are connected to respective terminals of the device, although not shown in FIG.

[0048] A circuit diagram of another of the embodiments of the claimed device is shown in Figure 4, in which device 100 is shown as including OA 101, transistor 103, current stabilizer 105, output current setter 155, and FC 143. Also shown is a terminal 107 intended for connection to the positive pole of the PS source, a first input terminal 109 of device 100, and a first PS terminal (111) and a second PS terminal (113) of OA 101. OA 101 also has a first input 115 (non-inverted "+" in Figure 4) connected to the first input terminal 109 of device 100, a second input 117 (inverted "-" in Figure 4), and an output 119 connected to a first (control (gate terminal in Figure 4)) terminal 121 of transistor 103. The third terminal 123 (source terminal in FIG. 4) of the transistor 103 is connected to the first terminal 131 of the current stabilizer 105 and to the terminal 135 of the device reserved for connection to the load, and the second terminal 125 (drain terminal in FIG. 4) of the transistor 103 is connected to the first PS terminal 111 of the OA 101 and to the terminal 107 of the device. Also, the terminal 129 of the current stabilizer 105 is reserved for connection to the positive pole of the PS source. The terminal 127 is intended for connection to the negative pole of the PS source and is connected to the second PS terminal 113 of the OA 101, the second terminal 133 of the current stabilizer 105 and the terminal 177 of the output current setting device 155 via the common wiring (frame) of the device. The terminal 163 of the stabilizer 105 is connected to the second terminal 173 of the output current setting device 155. Each of the contacts 171 of the output current setter 155 and the contact 129 of the current stabilizer 105 is reserved for connection to the positive pole of the PS source.

[0049] 4 also shows FC143 including a first voltage divider of a first FC resistor 443 and a second FC resistor 445. A first terminal 447 of the first resistor 443 is connected to a first terminal 137 of FC143, a second terminal 449 of the first resistor 443 is connected to a second terminal 139 of FC143 and to a first terminal 451 of the second resistor 445. A second terminal 453 of the second resistor 445 is connected to a terminal 141 of FC143. A first one 137 of the three terminals of FC143 is connected to the junction of the transistor 103 and the current stabilizer 105, a second terminal 139 is connected to the second input 117 of OA101, and a third terminal 141 is connected to a terminal 127 of the device 100. Terminal 135 of device 100 , which is reserved for connection to a load, is connected to a first terminal 131 of current stabilizer 105 , a third terminal 123 of transistor 103 , and a first terminal 137 of FC 143 .

[0050] A PS source, an input signal source and a load are intended to be connected to the respective terminals of the device, although they are not shown in FIG.

[0051] A circuit diagram of a third of the embodiments of the claimed device is shown in Figure 5, in which device 100 is shown as including OA 101, transistor 103, current stabilizer 105, output current setter 155, and FC 143. Also shown is a terminal 107 intended for connection to the positive pole of the PS source, a first input terminal 109 of device 100, and a first PS terminal (111) and a second PS terminal (113) of OA 101. OA 101 also has a first input 115 (non-inverted "+" in Figure 5) connected to first input terminal 109, a second input 117 (inverted "-" in Figure 5), and an output 119 connected to a first (control (gate terminal in Figure 5)) terminal 121 of transistor 103. The third terminal 123 (source terminal in FIG. 5) of the transistor 103 is connected to the first terminal 131 of the current stabilizer 105 and to the terminal 135 of the device reserved for connection to the load, and the second terminal 125 (drain terminal in FIG. 5) of the transistor 103 is connected to the first PS terminal 111 of the OA 101 and to the terminal 107 of the device intended for connection to the positive pole of the PS source. Also, the terminal 129 of the current stabilizer 105 is reserved for connection to the positive pole of the PS source. The terminal 127 is intended for connection to the negative pole of the PS source. This terminal 127 is also connected to the second PS terminal 113 of the OA 101, the second terminal 133 of the current stabilizer 105 and the terminal 177 of the output current setting device 155 via the common wiring (frame) of the device. The terminal 163 of the stabilizer 105 is connected to the second terminal 173 of the output current setting device 155. A terminal 171 of the output current setter 155 and a terminal 129 of the current stabilizer 105 are used to connect to the positive pole of the PS source.

[0052] 5 also shows FC 143 including a resistor 443. A first terminal 447 of resistor 443 is connected to first terminal 137 of FC 143 and a second terminal 449 of resistor 443 is connected to second terminal 139 of FC 143. A first 137 of three terminals of FC 143 is connected to the junction of transistor 103 and current stabilizer 105, a second terminal 139 is connected to second input 117 of OA 101 and an unused third terminal 141 is connected to terminal 127 of the device.

[0053] 5, the device 100 includes a second input terminal 118, which includes a third resistor 545, a fourth resistor 547, and a fifth resistor 549, the fourth resistor 547 and the fifth resistor 549 forming a second voltage divider. The second input terminal 118 is connected to a first terminal of the third resistor 545, whose second terminal 555 is connected to the second input 117 of the OA 101 and the second terminal 139 of the FC 143. The first terminal 559 of the fourth resistor 547 is connected to the input 115 of the OA 101, and the second terminal 561 of the resistor 547 is connected to the terminal 127 of the device 100. The fifth resistor 549 is connected to the first input terminal 109 via its first terminal 563 and to the first input 115 of the OA 101 via its second terminal 565.

[0054] A PS source, an input signal source and a load are intended to be connected to the respective terminals of the device, although they are not shown in FIG.

[0055] Figure 6 shows one possible embodiment of the output current setter 155, which is made as a third voltage divider. This embodiment may be used in any embodiment of the claimed device, including but not limited to the embodiments shown in Figures 3-5. Figure 6 shows the output current setter 155, a first resistor 605 of the third voltage divider, and a second resistor 613 of the third voltage divider. The first terminal 621 of the first resistor 605 is connected to the first terminal 171 of the output current setter 155 and is intended to be connected to the positive pole of the PS source, the second terminal 629 of the second resistor 613 of the output current setter is connected to the third terminal 177 of the output current setter 155 reserved for connection with the negative pole of the PS source, and the second terminal 625 of the first resistor 605 of the output current setter and the first terminal 627 of the second resistor 613 of the current setter are connected to the second terminal 173 of the output current setter intended to be connected to the current stabilizer 105.

[0056] 7 shows another possible embodiment of the output current setter 155, which uses a field effect transistor (FET) and a fourth voltage divider. This embodiment may be used in any of the embodiments of the claimed apparatus, including but not limited to the embodiments shown in FIGS. 3-5. Shown in FIG. 7 are the output current setter 155, a FET 703, and a first resistor 707 and a second resistor 713 of the output current setter acting as the first and second elements of the fourth voltage divider. The drain terminal 741 of the FET 703 is connected to the first terminal 171 of the output current setter intended to be connected to the positive pole of the PS source, the source terminal 743 of the FET 703 is connected to the first terminal 737 of the first resistor 707 of the output current setter, and the gate terminal 731 of the FET 703 is connected to the junction of the second terminal 739 of the first resistor 707 of the output current setter and the first terminal 725 of the second resistor 713 of the output current setter and to the second terminal 173 of the output current setter intended to be connected to the current stabilizer 105. The second terminal 727 of the second resistor 713 of the output current setter is connected to the third terminal 177 of the output current setter intended to be connected to the negative pole of the PS source.

[0057] FIG 8 shows another possible embodiment of the output current setter 155, which uses a reference voltage source and a fifth voltage divider. This circuit diagram may be used in any embodiment of the claimed apparatus, including but not limited to the embodiments shown in FIGS. 3-5. FIG 8 shows the output current setter 155, the reference voltage source 801, and a first resistor 805, a second resistor 807, and a third resistor 813 of the output current setter, which act as the first, second, and third elements of the fifth voltage divider. The first terminal 831 of the first resistor 805 of the output current setter is connected to the first terminal 171 of the output current setter intended to be connected to the positive pole of the PS source, the second terminal 833 of the first resistor 805 is connected to the first terminal 835 of the reference voltage source 801 and to the first terminal 839 of the second resistor 807, and the second terminal 841 of the second resistor 807 is connected to the first terminal 843 of the third resistor 813 and to the second terminal 173 of the output current setter 155 intended to be connected to the current stabilizer 105. The second terminal 845 of the third resistor 813 of the output current setter is connected to the second terminal 837 of the reference voltage source 801 and to the third terminal 177 of the output current setter intended to be connected to the negative pole of the PS source.

[0058] Figures 9a-9f show graphs illustrating the reduction in distortion levels of an information signal when it is transmitted using the proposed device. With respect to the numbers in Figure 9, 901 is the input signal, 902 is the amplitude response of the prior art design, 903 is the amplitude response of the proposed device, 904 is the output signal (distorted) of the prior art design, and 905 is the output signal of the proposed device.

[0059] 10 is an oscillogram of the input and output signals of the claimed device, which is consistent with the results obtained in the claimed technology, where 1001 refers to the oscillogram of the input test voltage and 1002 refers to the oscillogram of the output voltage.

[0060] Detailed Description of the Invention The single-supply device 100 for signal transmission shown in FIG. 3 is one of the embodiments of the claimed device, which operates in a voltage repeater mode.m is applied to the terminal 109 reserved for connection to a source of the input signal and then to the first non-inverting ("+") input 115 of the OA 101, a voltage U1 appears at the output 119 of the OA 101, which reaches the first or control terminal 121 of the transistor 103 operating in linear mode. The current stabilizer 105 generates a DC stabilized current I0, the value of which depends on the voltage U0 applied from the second terminal 173 of the output current setter 155 to the control input 163 of the current stabilizer 105.

[0061] The parameters of the current stabilizer 105 are: the minimum voltage drop, U, corresponding to the start of the current stabilization mode of the current stabilizer (between its terminals 131 and 133); min cs , is chosen to ensure that it is, for example, 0.2 mV (or some other value that allows distortion-free signal transmission).

[0062] The flow of current I0 through the current stabilizer 105 produces an output voltage U between its terminals 131 and 133. out which is applied to a load (not shown) from terminals 135 and 127 of the device connected to terminals 131 and 133.

[0063] The current I1 flowing through the transistor 103 is the sum of the current I0 of the current stabilizer 105 and the current I2 of the load, out / R, where R is the resistance of the load.

[0064] When a load is connected between terminals 135 and 127 of the device, I1=I0+U out / R (1) and it is necessary that this current not exceed the maximum allowable value for transistor 103.

[0065] When a load is connected between terminal 135 and terminal 107 of the device, I1=I0-U out / R (2) and it is necessary that this current not be smaller than a value that allows for a linear mode of operation of transistor 103.

[0066] The voltage U is supplied from the first terminal 131 of the current stabilizer 105 via FC143, which is made as a standard wiring. out reaches the inverting ("-") input 117 of OA101, thus forming a strong feedback circuit: OA101-transistor 103-FC143-OA101. For some reason, the output voltage U at the inverting ("-") input 117 of OA101 out is the non-inverting ("+") input of 115 U in If the voltage U1 at the first or control terminal 121 of the transistor 103 increases, slightly opening the transistor 103 and thereby increasing the output voltage U out increases.

[0067] U out The value of U in and therefore the following relationship U out =U in (3) Fits.

[0068] On the other hand, the output voltage U at the inverting ("-") input 117 of OA101 out is U at the non-inverting ("+") input 115 of OA101 in If the value of U exceeds the threshold, the voltage U1 at the first (control) terminal 121 of the transistor 103 decreases, slightly closing the transistor 103 and thereby decreasing the output voltage U out decreases and U in and again conforms to relationship (3).

[0069] Therefore, the output voltage U out is as close to the input voltage U as practically possible. in is made equal to

[0070] The transmission response K of the above-described device shown in FIG. 3 is equal to 1, therefore it operates as a voltage repeater.

[0071] Conventional OAs for signal supply operation, such as Texas Instruments OPA189, OPA365, and others, which can be used as OA 101 in the proposed arrangement, cannot guarantee that the voltage U1 at the output 119 of OA 101 is less than a few tens of millivolts. However, U1 in the proposed arrangement according to FIG. 3 is reduced by the amount of the potential difference between the control terminal 121 of transistor 103 and the third terminal 123 of transistor 103, which is connected to the first terminal 131 of current stabilizer 105. out 103 is always greater than the value of 104. It is precisely this potential difference that ensures the biasing of the output voltage U1 of the conventional OA 101 towards the "near zero" value at the output of the proposed device, thereby contributing to a substantial reduction in the distortion level during the transmission of "near zero" signals in single-supply operation, which facilitates the extension of the dynamic range of the device for signal transmission with a single supply (the above is ensured when the gate-source voltage of the transistor 103 exceeds the minimum output voltage of the OA 101, which is shown in Figure 9c by U104). min (See ).

[0072] If we increase the input voltage Uin to a few volts (which corresponds to the parameters of the conventional OA101), the device behaves in a similar manner, guaranteeing the relationship (3), and U out The value of is always smaller than U1 by the value of the potential difference between the control terminal 121 and the third terminal 123 of the transistor 103. The device 200 made as an integral circuit operates in a similar manner, the only difference being that the FC 143 and the output current setting device 155 can be placed outside the integral circuit and connected to the above mentioned terminals.

[0073] If it is desired to obtain a transmission response greater than 1, such as 1.5, 10 or some other suitable value (amplification condition), then the FC 143 must include a voltage divider, such as a resistive type one.

[0074] A circuit diagram of such an embodiment of the claimed device is shown in FIG. 4 (amplifier circuit). The device 100 in such a case operates as follows: in When an input signal of U0 is applied to the terminal 109 intended for connection to the input signal source, and thus to the first or non-inverting ("+") input 115 of the OA 101, a voltage U1 appears at the output 119 of the OA 101. This U1 voltage passes to the first or control terminal 121 of the transistor 103, which operates in linear mode. The current stabilizer 105 generates a DC stabilized current I0, the value of which depends on the voltage U0 applied from the second terminal 173 of the output current setter 155 to the control input 163 of the current stabilizer 105. The parameters of the current stabilizer 105 are the minimum voltage drop, U0, corresponding to the start of the current stabilization mode of the current stabilizer (between its terminals 131 and 133), min cs , is chosen to ensure that it is, for example, 0.2 mV (or some other value that allows distortion-free signal transmission).

[0075] The flow of current I0 through the current stabilizer 105 produces an output voltage U between its terminals 131 and 133. out which is applied to a load (not shown) from terminals 135 and 127 of the device connected to terminals 131 and 133.

[0076] The current I1 flowing through the transistor 103 is the sum of the current I0 of the current stabilizer 105 and the current I2 of the load, out / R, where R is the resistance of the load.

[0077] When a load is connected between terminal 135 and terminal 127 of the device, relationship (1) must be met and this current must not exceed the maximum allowed value for transistor 103 .

[0078] When a load is connected between terminal 135 and terminal 107 of the device, it is necessary to comply with relationship (2) and to ensure that this current is not reduced below a value that allows the linear mode of operation of transistor 103.

[0079] A voltage U is supplied from the first terminal 131 of the current stabilizer 105 through an FC 143 that includes a first voltage divider (including a first resistor 443 and a second resistor 445). out arrives at the inverting ("-") input 117 of OA101. As a result, a feedback circuit appears: "OA101-transistor 103-FC143-OA101". The voltage is therefore: U out *R 445 / (R 445 +R 443 ) (4) Here, R 443 and R 445 is the nominal value of the resistance of the first resistor 443 and the second resistor 445, and is applied to the inverting "-" input of OA101.

[0080] For some reason, the output voltage U out is the U at the first input 115 of OA101 in If the voltage U1 at the first or control terminal 121 of the transistor 103 increases, slightly opening the transistor 103 and thereby increasing the output voltage U out increases. U out The incremented value of again arrives at the second input 117 of the OA 101, and this process U in =U out / (1+R 443 / R 445 ) (5) This will occur until it meets the

[0081] On the other hand, the voltage U at the inverting ("-") input 117 of OA101 out (1+R 443 / R 445 ) at the non-inverting ("+") input of OA101, U in If the voltage U1 at the first or control terminal 121 of the transistor 103 is greater than the value of Vref, the voltage U1 at the first or control terminal 121 of the transistor 103 decreases, thereby closing the transistor 103. In response, the output voltage U outdecreases and passes through FC 143, which includes a first voltage divider (443, 445), to the inverting ("-") input 117 of OA 101 until it again meets relationship (5).

[0082] Output voltage U for the circuit diagram in Figure 4 out is almost always the input signal voltage U in and the transmission response is K=U out / U in =1+R 443 / R 445 (6) It is.

[0083] Thus, in the proposed device embodiment of FIG. 4, a value of 1.5, 10, or any other suitable value (R 443 and R 445 A transmission response greater than unity is achieved, such that the response depends on the correlation between

[0084] Conventional OAs 101 for single-supply operation (such as Texas Instruments OPA189, OPA365, and others) that can be used as the OA 101 of the proposed device cannot provide a voltage U1 smaller than a few tens of millivolts at the output 119 of the OA 101. Therefore, U1 in the embodiment of the proposed device of FIG. 4 is limited to a voltage U1 of a magnitude of the potential difference between the control terminal 121 of the transistor 103 and the third terminal 123 of the transistor 103, which is connected to the first terminal 131 of the current stabilizer 105. out This potential difference ensures the biasing of the output voltage of the conventional OA 101 towards a "near zero" value at the output of the proposed device, which contributes to substantially lowering the distortion level during the transmission of low-voltage signals in single-supply operation and to extending the dynamic range of such a device for signal transmission. The above is ensured when the gate-source voltage of the transistor 103 exceeds the minimum output voltage of the OA 101 (U in Fig. 9c). min (see ).

[0085] Input voltage Uin If we increase U to a few volts (which corresponds to the parameters of the conventional OA101), the device behaves similarly, ensuring the relationship (3), and U out The value of is always smaller than U1 by the value of the potential difference between the control terminal 121 and the third terminal 123 of the transistor 103. The device 200 made as an integral circuit (the difference being that the FC 143 and the output current setter 155 can be placed outside the integral circuit) operates in a similar manner.

[0086] If it is required to obtain the difference between two voltages and amplify, attenuate or transmit it unchanged (differential amplification mode), the device will include an additional input connected to the inverting "-" input of the OA through an additional resistor. Furthermore, the device will include a second voltage divider included between the primary input of the device and the second input of the OA.

[0087] A circuit diagram of such a differential amplifier (a third possible implementation of the device) is shown in Figure 5. The device 100 operates as follows: A first input signal U in1 is applied to terminal 109, which serves to connect to a first source of input signal (not shown). A voltage U in1 arrives at the non-inverting ("+") input 115 of OA 101, forming the second input signal Uin2 arrives from terminal 118 of the device, through a third resistor 545, to the inverting ("-") input 117 of OA 101. A voltage U1 then appears at the output 119 of OA 101 and reaches the first or control terminal 121 of transistor 103 operating in linear mode.

[0088] The current stabilizer 105 generates a DC stabilized current I0, the value of which depends on a voltage U0 applied from a second terminal 173 of the output current setter 155 to a control input 163 of the current stabilizer 105. The parameters of the current stabilizer 105 are the minimum voltage drop, U0, corresponding to the start of the current stabilization mode of the current stabilizer (between its terminals 131 and 133), min cs, is chosen to ensure that it is, for example, 0.2 mV (or some other value that allows distortion-free signal transmission).

[0089] The flow of current I0 through the current stabilizer 105 produces an output voltage U at its terminals 131 and 133. out The voltage U is generated from terminals 135 and 127 of the device connected to terminals 131 and 133. out is applied to a load (not shown).

[0090] The current I1 flowing through the transistor 103 is the sum of the current I0 of the current stabilizer 105 and the current I2 of the load, out / R, where R is the resistance of the active load.

[0091] When a load is connected between terminal 135 and terminal 127 of the device, relationship (1) is met, which requires that the value of this current not exceed the maximum allowable value for transistor 103. When a load is connected between terminal 135 and terminal 107 of the device, relationship (2) is met, which requires that the value of this current not be less than a value that allows the linear mode of operation of transistor 103.

[0092] At the same time, the output voltage U through the first resistor 443 of FC143 out A portion of the output voltage U reaches the inverting ("-") input 117 of the OA 101 (the first resistor 443 and the third resistor 545 form a sixth voltage divider). out is a known relationship Uout = α*(U in1 -U in2 ) (7) According to the input voltage U in1 and U in2 Here, α=R 443 / R 545 =R 547 / R 549 (8) is the differential coefficient of transmission of the input voltage, and R443 , R 545 , R 447 , R 449 are the rated resistance values ​​of the first resistor 443, the third resistor 545, the fourth resistor 547, and the fifth resistor 549, respectively.

[0093] As a particular apparatus is implemented according to this embodiment, strict adherence to relationship (8) becomes optional, and the nominal values ​​for first resistor 443, third resistor 545, fourth resistor 547, and fifth resistor 549 may be selected based on the particular problem being solved in the apparatus.

[0094] Depending on the rated resistance of the resistors, the difference coefficient α can be greater than, less than, or equal to 1, thereby allowing the difference between the two voltages to be amplified, attenuated, or transmitted unchanged. In this way, the output voltage U out is always the input voltage difference U in1 -U in2 is proportional to

[0095] Furthermore, this embodiment allows amplifying or attenuating the difference between two voltages under appropriate selection of the rated values ​​of the first resistor 443, the third resistor 545, the fourth resistor 547, and the fifth resistor 549. Thus, it functions as a differential amplifier.

[0096] Conventional OAs for single-supply operation (such as Texas Instruments OPA189, OPA365, and others) that can be used as OA 401 in the proposed arrangement cannot provide a voltage U1 smaller than a few tens of millivolts at the output 119 of OA 101. However, U1 in the FIG. 5 embodiment of the proposed arrangement is a voltage U1 smaller than a few tens of millivolts by the value of the potential difference between the control terminal 121 of transistor 103 and the third terminal 123 of transistor 103, which is connected to the first terminal 131 of current generating device 105. outThis potential difference ensures the biasing of the output voltage of the conventional OA 101 towards a "near zero" value at the output of the proposed device, which contributes to substantially lowering the distortion level during the transmission of low-voltage signals in single-supply operation and to extending the dynamic range of such a device for signal transmission. This is ensured when the gate-source voltage of the transistor 103 exceeds the minimum output voltage of the OA 101 (U in Fig. 9e). min (see ).

[0097] Input voltage U in1 and U in2 If U is increased to a few volts (which corresponds to the parameters of the conventional OA101), the circuit will behave similarly, ensuring compliance with relation (7). When this is done, U out The value of is always smaller than U1 by the value of the potential difference between the control terminal 121 and the third terminal 123 of the transistor 103. The device 200 made as an integral circuit (the difference being that the FC 143 and the current setter 155 can be placed outside the integral circuit) operates in a similar manner.

[0098] Apart from the proposed design embodiment shown in Figures 3-5 and described above, there are other possible embodiments of the device that differ in the connections of the various circuits to the inputs and outputs of the OA, for example as described in the specifications of the operational amplifier OPA189 mentioned above.

[0099] Further, the operation of the current stabilizer shown in Figure 2a is explained. Without being limited thereto, this structure can be used for all possible implementations of the claimed device, specifically as shown in Figures 3-5.

[0100] Output voltage U out appears at terminals 135 and 127 of the proposed arrangement, it is applied to terminals 131 and 133 of the current stabilizer 105 and is distributed to the second transistor 153, i.e., between its terminals 181 and 193, and to the resistor 157, i.e., between its terminals 187 and 189.

[0101] The voltage from the terminal 187 of the resistor 157 arrives at the first input 169 of the OA 151 and is compared with the voltage U0 at the second input 167 of the second OA 151, which comes from the second terminal 173 of the output current setter 155 via the terminal 163 of the current stabilizer 105. If the voltage at the first input 169 of the second OA 151 exceeds the voltage U0 at the second input 167, an unbalance signal is formed at the output 165 of the second OA 151. The unbalance signal applied to the control terminal 181 of the second transistor 153 operating in linear mode causes the transistor 153 to close slightly, the current through it decreases and the voltage at the terminal 187 of the resistor 157, and therefore at the first input 169 of the second OA 151, becomes equal to the voltage U0 at the second input 167. Conversely, if the voltage at the first input 169 of the second OA 151 is lower than the voltage U0 at the second input 167, the level of the unbalanced signal at the output 165 of the second OA 151 changes. The unbalanced signal reaching the control terminal 181 of the second transistor 153 will cause the second transistor 153 to open slightly, increasing the current through it and causing the voltage at terminal 187 of the resistor 157, and therefore at the first input 169 of the second OA 151, to again become equal to the voltage U0 at the second input 167.

[0102] In this manner, the current stabilizer 105 constructed in accordance with FIG. 2a satisfies the following relationship: I0*R m =U0(9) where R is the nominal value of the resistance of the resistor 157 and U0 is the voltage at the second terminal 173 of the output current setting device 155.

[0103] In other words, the DC current that always flows through the current generator 105 is I0=U0 / R m (10) and its value is set by the voltage U0 at the output of the output current setter 155 (its second terminal 173).

[0104] The voltage drop U between terminals 131 and 133 of the current stabilizer 105 corresponding to the start of the current stabilization mode min cs is expressed by the following relationship: U min cs =I0*R cs (11) where I0 is the DC current of the current stabilizer 105 and R cs is the resistance between terminal 131 and terminal 133 of current stabilizer 105, R cs =R m +R DS(on) (12) and R m is the rated resistance of resistor 157, and R DS(on) is the static drain-source on-state resistance of the second transistor 153 in the open state.

[0105] Properly select the resistance rating R of resistor 157 and obtain the required R DS(on) It can be advantageously ensured that the above formulated relationship is satisfied by selecting the second transistor 153 having a voltage Vref = 0.05 V, such that the voltage between the terminals 131 and 133 of the current stabilizer 105 corresponding to the onset of current stabilization is, for example, 0.2 mV (or any other value that ensures distortion-free signal transmission).

[0106] For example, U of 0.2 mV min cs To obtain the drain-source channel resistance R of the second transistor 153 in the open state, ds(on) must be several hundred milliohms. The parasitic capacitances of the drain-source and gate-drain of the second transistor 153 can then reach values ​​of several tens of picofarads, respectively, which interfere with distortion-free transmission of wideband signals. However, in the claimed device, the gate-drain capacitance is shorted by the output resistance of the second OA 151, and the effect of the drain-source capacitance is neutralized by a feedback circuit from the source terminal 193 of the second transistor 153 through the first input 169 of the second OA 151 to the gate terminal 181 of the second transistor 153. As a result, a high growth rate of the output signal is achieved.

[0107] In view of the above, and unlike any other design, the structure shown in FIG. 2a ensures a substantial extension of the dynamic range of a single-supply device for signal transmission and at the same time provides a high growth rate of the output signal, thus achieving the claimed technical result.

[0108] We now turn to a description of the output current setter 155, represented diagrammatically in Figure 2a, understanding that this can be implemented in various ways. A circuit diagram of one of the possible implementations of the output current setter 155 for the current stabilizer 105 in the proposed arrangement is shown in Figure 6. It operates as follows.

[0109] When the power supply voltage E is applied to the first terminal 171 of the output current setting device 155, a direct current begins to flow through the series-connected resistors 605 and 603 of the output current setting device 155, and the value of the current is I3=E / (R 605 +R 613 ) (13) where R 605 and R 613 and are the rated resistance values ​​of the first resistor 605 and the second resistor 613 of the output current setting device 155, respectively.

[0110] At the second terminal 173 of the output current setting device 155, a voltage U0 appears as a result, which is equal to the voltage drop created by the current I3 across the second resistor 613 of the output current setting device 155, U0=E*R 613 / (R 605 +R 613 ) (14) It is.

[0111] Using the relationship (10), when an output current setter 155 configured as shown in FIG. 6 is used, the stable DC current flowing through the current stabilizer 105 is I0=U0 / R m =E*(R 613 / (R 605+R 613 )) / R m (15) is obtained.

[0112] E, R as necessary 605 , R 613 , and R m By selecting the value of I0, the required value of I0 can always be obtained. Thus, the current setter 155 shown in Fig. 6 guarantees the performance of both the current stabilizer of Fig. 2a and the proposed device.

[0113] However, the dependence of the output voltage U0 on the value of the power supply voltage E can be unstable, which appears to be a drawback of the circuit diagram of FIG.

[0114] A circuit diagram of another possible implementation of the current setter 155 for the current stabilizer 105 in the proposed arrangement, in which the stability of the voltage U0 is improved, is shown in Fig. 7. It works as follows.

[0115] When a power supply voltage E is applied to the first terminal 171 of the output current setter 155, a DC current I4 starts to flow through the series-connected FET 703, first setter resistor 707, and second setter resistor 713 of the output current setter 155. According to the characteristics of the FET, when the drain-source voltage between the terminal 741 (drain terminal) and the terminal 743 (source terminal) of the FET 703 of the output current setter 155 exceeds the cut-off voltage (a characteristic parameter of the FET), the current I4 between these terminals is determined only by the characteristics and gate-source voltage of the FET, independent of the drain-source voltage. The gate-source voltage between the terminal 731 and the terminal 743 of the FET 703 of the output current setter 155 is determined by the voltage drop across the first resistor 707, which is I4*R 707 At the same time, the voltage drop U0=I4*R 713 (16) occurs across the second resistor 713, where R 707 and R 713 is the rated resistance value of the first resistor and the second resistor of the output current setting device 155.

[0116] This voltage U0, which is independent of the supply voltage E, arrives at the second terminal 173 of the output current setter 155. Using the relationship (10), the stable DC current flowing through the current stabilizer 105 when using the output current setter 155 configured as shown in FIG. I0=U0 / R m =I4*R 713 / R m (17) is obtained.

[0117] FET703 and R 713 and R m By selecting the values ​​of I and I 0 , the required value of I 0 can always be obtained. The output current setter 155 shown in Fig. 7 therefore ensures all operability of the current stabilizer 105 with the proposed device, and the stability of the voltage U 0 and therefore of the current I 0 of the current stabilizer 105 is substantially higher than in the case of the circuit diagram of Fig. 6, since the current I 3 of the FET 703 is much more stable than the supply voltage E.

[0118] A circuit diagram of a third possible embodiment of a current setter 155 for the current stabilizer 105 in the proposed arrangement, in which the stability of the voltage U0 is improved, is shown in FIG. 8 and works as follows.

[0119] When a power supply voltage E is applied to the first terminal 171 of the output current setting device 155, a direct current starts to flow through the first resistor 805, the second resistor 807, and the third resistor 813, which are connected in series, of the output current setting device 155. The direct current I5 flowing through the first resistor 805 is expressed as follows: I5=(EV d ) / R 805 (18) where V d is the voltage between the terminal 835 and the terminal 837 of the reference voltage source 801 of the output current setter 155, and the current flowing through the second setter resistor 807 and the third setter resistor 813 is I6=V d / (R 807 +R 813) (19) It is.

[0120] In response, a voltage U0 is generated at the first terminal 843 of the third resistor 813, and therefore at the second terminal 173 of the output current setting device 155. U0 is independent of the power supply voltage E, and its value is equal to the voltage drop caused by I3 at the third resistor 813 of the output current setting device 155, U0=V d *R 813 / (R 807 +R 813 ) (20) It is.

[0121] Using the relationship (10), when an output current setting device 155 configured as shown in FIG. 8 is used, the DC current flowing through the current stabilizer 105 is I0=U0 / R m =V d *(R 813 / (R 807 +R 813 )) / R m (twenty one) is obtained.

[0122] E, R as necessary 813 , R 807 , and R m By selecting the value of I0 between terminals 835 and 837 of the reference voltage source 801, the required value of I0 can always be obtained. The output current setter 155 shown in FIG. 8 therefore makes it possible to guarantee the complete operability of the current stabilizer 105 with the proposed device. The stability of the voltage U0, and therefore of the current I0 of the current stabilizer 105, is substantially higher than in the case of the circuit diagram of FIG. 6, because the voltage V between terminals 835 and 837 of the reference voltage source 801 is d is much more stable than the power supply voltage E.

[0123] The claimed technical results obtained in view of the above are illustrated in the graphs of Figures 9a-9f. They are: An input undistorted signal 901 that looks like a sine wave with a minimum value of 0; The actual amplitude response 902 of the prior art design is substantially nonlinear in the initial range, resulting in distorting the "near zero" signal; The magnitude response 903 of the proposed design is close to linear, thus contributing to reduced distortion of "near zero" signals; The output signal 904 of the prior art design appears distorted due to the flattening of the sine wave in the fractional value range; 9 shows an output signal 905 of the proposed design, which substantially reduces distortion levels in the decimal range, thereby increasing the dynamic range of a single-supply signal transmission device.

[0124] Also, since a class A amplification mode is used, there is no nonlinear distortion which is characteristic of prior art including prototypes which use a class AB amplification mode.

[0125] The above-mentioned embodiments do not limit the scope of the proposed and claimed device. It is understood that various embodiments can be implemented in conjunction with specific component hardware. For example, the above-mentioned first voltage divider formed by resistors 443 and 445, the second voltage divider formed by resistors 549 and 547, the third voltage divider formed by resistors 605 and 613, the fourth voltage divider formed by resistors 707 and 713, and the fifth voltage divider formed by resistors 805, 807, and 813 in each of Figures 4, 5, 6, 7, and 8, as well as the sixth voltage divider formed by resistors 443 and 545 (Figure 5) can each be a resistive divider, can be made as a divider including transistors connected in series, or in any other manner that provides the required voltage at the midpoint of the divider. Furthermore, any of the resistors mentioned above can be made as components having active resistance, preferably. For example, a semiconductor layer isolated from other components can take the place of a resistor in an integral circuit.

[0126] Similarly, OA ICs such as OPA189, OPA365, and many others can be used as OA101 and 151 (Figure 2a). Important parameters of the ICs are that the open-loop gain should be 100 dB or more (at a load of 10 kOhms), the gain-bandwidth product should be 1 MHz or more, the minimum acceptable input signal should be lower than the neutral bus potential by, for example, 0.1 V, and the zero offset should be within the minimum output voltage U out The critical parameters of transistor 103 are that the drain current I0 is greater than or equal to 100 mA and that the gate-source voltage should exceed the minimum output voltage of OA101. For transistor 153, R DS(on) should be less than a few hundred milliohms. For both transistors, the parasitic capacitance should be minimal. Other types of transistors can also be used, such as bipolar, etc. In such a case, the first or control electrode is the base, the second electrode is the collector, and the third one is the emitter. In the function of the transistor 703 (Fig. 7), only FETs such as BSS83, RU1C001UN, etc. can be used. The main factor when setting the FET with its parameters is that the drain-source voltage should be greater than the cut-off voltage. In addition to the structures shown in Figs. 6-8, other circuit diagrams can also be used that are capable of creating a stable voltage U0 that sets the DC current I0 of the current stabilizer 105 in the function of the current setter 155 (Fig. 2a).

[0127] Some parts of some components described above may be different, overlap, or completely coincide with some parts of other components, unless specifically stated otherwise. Also, some parts of some components may be adapted to various parts of other components, unless specifically stated otherwise. When a component is described as being "connected" to another component, this is understood to mean that the component can be "directly connected" to the other component, or can be "electrically connected" through a third component. For example, a decoupling resistor or matching stage can be disposed between the OA 101 and the transistor 103. The same relates to the connection between the second OA 151 and the second transistor 153 in the current stabilizer 105. Also, unless stated otherwise, "comprises" and its derivatives, such as "comprising" are understood to mean the presence of the described components, but not the absence of any other components.

[0128] The claimed device can be made as an integral circuit or integral circuit assembly or micro-board having terminals 107, 109, 127, and 135. The claimed device can also be made as an integral circuit or integral circuit assembly or micro-board having terminals 107, 109, 119, 127, 129, 135, and 167 to which an integral circuit or integral circuit assembly or micro-board having terminals 121, 123, 125, 171, 173, and 177 is connected. The claimed device can also be made as an OA integral circuit or integral circuit assembly or micro-board having terminals 111, 113, 115, 117, 119, 131, 133, and 167 to which is connected an integral circuit or integral circuit assembly or micro-board having terminals 121, 123, 125, 137, 139, 141, 171, 173, and 177. Other options for breaking down the device into components are possible as well, and the claimed device can be part of other structures or other ICs.

[0129] Experimental Results To verify the feasibility of the claimed technical result, two versions of the device according to the circuit diagram of FIG. 2a (voltage repeater mode) were breadboarded. In one of the breadboard circuits, the integral circuit OPA2189 was used as OA101 and 151. In the other one, the integral circuit OPA365. For both circuits, the transistors RU1C001UN and NTNS3C68NZ were used as transistors 103 and 153, respectively. The table below illustrates the breadboarding results.

[0130] [Table 1]

[0131] According to this table, the technical result achieved by the claimed invention is clearly to substantially increase the dynamic range of a device with a single power supply compared to the prior art and at the same time to ensure a high growth rate of the output signal.

[0132] FIG. 10 shows oscillograms of the input test voltage (chart 1001) and the output voltage (chart 1002) for the breadboarded circuit 1. For better illustration, a sawtooth shaped input test voltage was chosen. The input voltage U in comes from oscillograph channel K3, whose scale is 10 mV per square. The output voltage U out is shown on oscillograph channel K4, with the same scale. According to this oscillogram, the minimum output signal distortion (rounding of the sawtooth) is less than 1 mV, which is a confirmation that the claimed technical result has been achieved.

[0133] A claimed device made in accordance with the above recommendations and drawings can be highly repeatable.

[0134] The claimed invention has been described based on what are currently contemplated possible implementations of various embodiments thereof. However, it should be noted that the invention is not limited thereby. On the contrary, various modifications and equivalent implementations are contemplated that are consistent with the concept, spirit, and scope of the following claims. For example, the dynamic range-enhanced single-supply operation device can be used as a signal buffer for high sensitivity, high impedance sensors, in the input stage of ADCs and output stage of DACs (including integral circuit versions thereof) and small signal detectors, among many other applications. Therefore, the description and drawings are merely illustrative and do not limit the feasibility of the invention.

[0135] The claimed technical designs are defined in the following claims.

Claims

1. A single-power supply device (100) for signal transmission, comprising: a first operational amplifier (101), a second operational amplifier (151), a first transistor (103), a second transistor (153), and a resistor (157); The output (119) of the first operational amplifier (101) is connected to a terminal (121) of a first electrode of the first transistor (103); a non-inverting input (115) of said first operational amplifier (101) is connected to a terminal (109) of said device (100) intended to receive an input signal; The output (165) of the second operational amplifier (151) is connected to a terminal (181) of a first electrode of the second transistor (153); A terminal (193) of the third electrode of the second transistor (153) is connected to the inverting input (169) of the second operational amplifier (151) and to a terminal (187) of the resistor (157). In the device (100), The device (100) includes a feedback circuit (143) and an output current setting unit (155); a connection point between a terminal (123) of the third electrode of the first transistor (103) and a terminal (191) of the second electrode of the second transistor (153) is connected to a first terminal (137) of the feedback circuit (143) intended to be connected to a load; a second terminal (139) of the feedback circuit (143) is connected to the inverting input (117) of the first operational amplifier (101); The output (173) of the output current setter (155) is connected to the non-inverting input (167) of the second operational amplifier (151); Thereby ensuring an extended dynamic range of the device and a high growth rate of the output signal. An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the feedback circuit (143) is fabricated as a wire.

3. 2. The apparatus of claim 1, The feedback circuit (143) includes a first voltage divider (443, 445); a first element (443) of the voltage divider (443, 445) is connected between a first terminal (137) and a second terminal (139) of the feedback circuit (143); a second element (445) of the voltage divider (443, 445) is connected between the second terminal (139) and a third terminal (141) of the feedback circuit (143); An apparatus comprising:

4. 2. The apparatus of claim 1, a second voltage divider (547, 549) disposed between the first terminal (109) of the device and the non-inverting input (115) of the first operational amplifier (101); and an element (545), preferably having an active resistance, connected between a second input (118) of the device and the inverting input (117) of the first operational amplifier (101); said feedback circuit (143) including an element (443) preferably having an active resistance and connected between said first terminal (137) and said second terminal (139) of said feedback circuit (143); An apparatus comprising:

5. 2. The apparatus of claim 1, the first transistor (103) and the second transistor (153) are FETs; the first electrodes having the terminals (121) and (181) of the first and second transistors are gates, respectively; The second electrodes having the terminals (125) and (191) of the first and second transistors are drains, respectively. An apparatus comprising:

6. 2. The apparatus of claim 1, the first transistor (103) and the second transistor (153) are bipolar; the first electrodes having the terminals (121) and (181) of the first and second transistors are bases, respectively; the second electrodes having the terminals (125) and (191) of the first and second transistors are collectors, respectively; An apparatus comprising:

7. 2. The apparatus of claim 1, The output current setting unit (155) includes a third voltage divider (605, 613); a first terminal (621) of a first element (605) of the third voltage divider (605, 613) is connected to a first terminal (171) of the output current setting device (155); a connection point between the first element (605) and the second element (613) of the third voltage divider (605, 613) is connected to the second terminal (173) of the output current setting device (155); A second terminal (629) of the second element (613) of the third voltage divider (605, 613) is connected to a third terminal (177) of the output current setter (155). An apparatus comprising:

8. 2. The apparatus of claim 1, The output current setting unit (155) includes a FET (703) and a fourth voltage divider (707, 713); A drain terminal (741) of the FET (703) is connected to a first terminal (171) of the output current setting unit (155); a source terminal (743) of the FET (703) is connected to a first terminal (737) of the first element (707) of the fourth voltage divider (707, 713); A terminal (731) of the gate of the FET (703) is connected to a connection point between the first element (707) and the second element (713) of the fourth voltage divider (707, 713) and to a second terminal (173) of the output current setting unit (155); a second terminal (727) of the second element (713) of the fourth voltage divider (707, 713) is connected to a third terminal (177) of the output current setter (155); An apparatus comprising:

9. 2. The apparatus of claim 1, The output current setting unit (155) includes a reference voltage source (801) and a fifth voltage divider (805, 807, 813); a first terminal (831) of a first element (805) of the fifth voltage divider (805, 807, 813) is connected to a first terminal (171) of the output current setting device (155); a second terminal (833) of the first element (805) of the fifth voltage divider (805, 807, 813) is connected to a first terminal (835) of the reference voltage source (801) and to a first terminal (839) of a second element (807) of the fifth voltage divider (805, 807, 813); a second terminal (841) of the second element (807) of the fifth voltage divider (805, 807, 813) is connected to a second terminal (173) of the output current setting device (155) and to a first terminal (843) of a third element (813) of the fifth voltage divider (805, 807, 813); a second terminal (845) of the third element (813) of the fifth voltage divider (805, 807, 813) is connected to a third terminal (177) of the output current setting device (155) and to a second terminal (837) of the reference voltage source (801); An apparatus comprising:

10. A single-power integral circuit (IC) (200) for signal transmission, comprising: a first operational amplifier (101), a second operational amplifier (151), a first transistor (103), a second transistor (153), and a resistor (157); The output (119) of the first operational amplifier (101) is connected to a terminal (121) of a first electrode of the first transistor (103); a non-inverting input (115) of said first operational amplifier (101) is connected to a terminal (109) of said integral circuit (200) intended to receive an input signal; The output (165) of the second operational amplifier (151) is connected to a terminal (181) of a first electrode of the second transistor (153); A terminal (193) of the third electrode of the second transistor (153) is connected to the inverting input (169) of the second operational amplifier (151) and to a terminal (187) of the resistor (157). In the integral circuit, A terminal (123) of a third electrode of the first transistor (103) of the integral circuit (200) is connected to a terminal (191) of a second electrode of the second transistor (153); The connection point is connected to a terminal (135) reserved for connection to a load; Thereby, ensuring that the dynamic range of the IC is extended and the growth rate of the output signal is high.

1. An integral circuit comprising:

11. 11. The integral circuit of claim 10, characterized in that said terminal (135) is also reserved for connection to a first terminal of an external feedback circuit (143).

12. 11. The integral circuit of claim 10, further comprising an additional terminal (118) connected to the inverting input (117) of the first operational amplifier (101) and reserved for connection to a second terminal of an external feedback circuit (143).

13. 13. The integral circuit of claim 12, wherein the additional terminal (118) is reserved for receiving a second input signal.

14. 11. The integral circuit of claim 10, an output current setting unit (155) including a third voltage divider (605, 613); a first terminal (621) of a first element (605) of the third voltage divider (605, 613) is connected to a first terminal (171) of the output current setting device (155); a connection point between the first element (605) and the second element (613) of the third voltage divider (605, 613) is connected to a second terminal (173) of the output current setting device (155); a second terminal (629) of the second element (613) of the third voltage divider (605, 613) is connected to a third terminal (177) of the output current setter (155); 1. An integral circuit comprising:

15. 11. The integral circuit of claim 10, an output current setting unit (155) including a FET (703) and a fourth voltage divider (707, 713); A drain terminal (741) of the FET (703) is connected to a first terminal (171) of the output current setting unit (155); a source terminal (743) of the FET (703) is connected to a first terminal (737) of the first element (707) of the fourth voltage divider (707, 713); A terminal (731) of the gate of the FET (703) is connected to a connection point between the first element (707) and the second element (713) of the fourth voltage divider (707, 713) and to a second terminal (173) of the output current setting unit (155); a second terminal (727) of the second element (713) of the fourth voltage divider (707, 713) is connected to a third terminal (177) of the output current setter (155); The output (173) of the output current setter (155) is connected to the non-inverting input (167) of the second operational amplifier (151).

1. An integral circuit comprising:

16. 11. The integral circuit of claim 10, an output current setting unit (155) including a reference voltage source (801) and a fifth voltage divider (805, 807, 813); a first terminal (831) of a first element (805) of the fifth voltage divider (805, 807, 813) is connected to a first terminal (171) of the output current setting device (155); a second terminal (833) of the first element (805) of the fifth voltage divider (805, 807, 813) is connected to a first terminal (835) of the reference voltage source (801); a first terminal (839) of a second element (807) of the fifth voltage divider (805, 807, 813) is connected to the second terminal (831) of the first element (805) of the fifth voltage divider (805, 807, 813); a second terminal (841) of the second element (807) of the fifth voltage divider (805, 807, 813) is connected to a second terminal (173) of the output current setting device (155) and to a first terminal (843) of a third element (813) of the fifth voltage divider (805, 807, 813); a second terminal (845) of the third element (813) of the fifth voltage divider (805, 807, 813) is connected to a third terminal (177) of the output current setting device (155) and to a second terminal (837) of the reference voltage source (801); A second terminal (173) of the output current setter (155) is connected to the non-inverting input (167) of the second operational amplifier (151).

1. An integral circuit comprising:

17. 11. The integral circuit of claim 10, further comprising an additional terminal (1163) connected to the inverting input (167) of the second operational amplifier (151) and reserved for connection to an external current setter.

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