Direct bonding on package substrate

Abstract

A bonding structure comprising a package substrate including a first bonding layer made of inorganic insulating material and a first conductive feature on its surface, and an electronic component including a second bonding layer made of inorganic insulating material and a second conductive feature on its surface, wherein the first bonding layer and the second bonding layer are directly bonded to each other, and the first and second conductive features are directly bonded to each other.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Application No. 63 / 293301, filed December 23, 2021, entitled "DIRECT BONDING ON PACKAGE SUBSTRATES," the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0002] (Technical field) The present invention relates to bonded structures, and more particularly to bonded structures in which electronic components are bonded directly onto package substrates without an intervening adhesive. [Background technology]

[0003] An integrated device package includes a package substrate and one or more integrated device dies mounted to the package substrate. The integrated device die typically includes bond pads that are bonded at a finer pitch than corresponding pads or terminals of the package substrate. It can be difficult to electrically connect a die having fine pitch pads to a package substrate having coarse pitch pads or terminals. Thus, there continues to be a need for improved package structures. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Pat. No. 9,564,414 [Patent Document 2] U.S. Pat. No. 9,391,143 [Patent Document 3] U.S. Patent No. 10,434,749 [Patent Document 4] U.S. Pat. No. 9,716,033 [Patent Document 5] U.S. Pat. No. 9,852,988 [Patent Document 6] US Patent Publication No. 2019 / 0096741

[0005] The detailed description will now be described with reference to the accompanying drawings, in which the use of the same numbers in different drawings indicates similar or identical items.

[0006] For purposes of this discussion, the devices and systems illustrated in the figures are shown as having multiple components. Various implementations of the devices and / or systems as described herein may include fewer components and remain within the scope of the present disclosure. Alternatively, other implementations of the devices and / or systems may include additional components or various combinations of the described components and remain within the scope of the present disclosure. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 2 is a schematic cross-sectional side view of a package substrate. [Figure 1B] 2 is a schematic cross-sectional side view of a package carrier and an electronic component bonded to the package carrier; [Fig. 1C-1D] 1 is a schematic cross-sectional side view showing a bonding structure including a package substrate having an inorganic insulating bonding layer. [Diagram 2] 1 is a schematic cross-sectional side view of a package carrier including a buffer layer having a thermal expansion coefficient between a package substrate and a bonding layer; [Diagram 3] FIG. 2 is a schematic cross-sectional side view of a bonding structure having a first bonding layer patterned to occupy less than the entire surface of a package substrate. [Figure 4A-4C] 1 is a schematic cross-sectional side view of one or more semiconductor devices connected to a package carrier in accordance with various embodiments. [Fig. 4D-4E] 1 is a schematic cross-sectional side view of one or more semiconductor devices connected to a package carrier in accordance with various embodiments. [Figure 5A-5C]1 is a schematic cross-sectional side view of a surface mount technology assembly mounted to a hybrid direct bond structure in accordance with various embodiments. [Fig. 5D-5E] 1 is a schematic cross-sectional side view of a surface mount technology assembly mounted to a hybrid direct bond structure in accordance with various embodiments. [Figure 6] 1 is a schematic cross-sectional side view of a semiconductor device directly bonded to a package substrate comprising a ceramic substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Creating a direct hybrid bond between an electrical component and a substrate without the use of adhesives can be difficult. Creating a suitable environment between the electrical component and the substrate to induce a stable bond is even more difficult, especially when the substrate is an organic or ceramic substrate. Direct hybrid bonding allows for extremely fine pitch electrical connections between vertically adjacent dies compared to solder bonding, while at the same time significantly reducing the thickness of the die stack compared to using thick solder balls between the dies. Various embodiments disclosed herein include bonding structures in which electronic components are bonded directly to a package substrate without an intervening adhesive. The electronic components can comprise integrated device dies with active circuitry, passive electronic devices, or other suitable types of components. As discussed above, electronic components such as semiconductor elements (e.g., integrated device dies) can have bond pads spaced apart at a fine pitch, due at least in part to the use of high resolution semiconductor fabrication techniques. In contrast, package substrates such as laminate substrates (e.g., printed circuit boards or PCB substrates) are formed using layered techniques that do not achieve such high resolution. A typical laminated package substrate can achieve a pitch of less than 35 microns, which is higher than the pitch of semiconductor devices, which are less than 1 micron, less than 0.5 microns, or less than 0.1 microns. For example, in various configurations, a typical laminated substrate can achieve a pitch or line width ranging from 50 microns to 500 microns, which is significantly higher than the pitch of semiconductor devices, which are in the range of 0.01 microns to 20 microns. Providing fine-pitch wiring layers on a package substrate is difficult due to at least a large difference in pitch between the semiconductor device and the package substrate. The difference in pitch between the semiconductor chip and the package substrate can substantially limit the number of interconnects between them, adversely affecting the bandwidth of the device. Also, longer path lengths, such as with interposer implementations, can increase parasitics and reduce system performance.

[0009] Hybrid direct bonding techniques have been used to bond semiconductor elements together without an intervening adhesive. For example, as described below, a die or wafer may include non-conductive bonding regions bonded directly to each other and conductive features (e.g., contact pads, vias, etc.) bonded directly to each other. Hybrid bonding techniques can form electrical connections between conductive features with pitches of less than 50 microns, less than 20 microns, less than 10 microns, less than 5 microns, less than 0.5 microns, or less than 0.1 microns. For example, hybrid bonding techniques can form electrical connections between conductive features with pitches or line widths ranging from 0.1 microns to 50 microns. However, direct bonding techniques are not considered compatible with packaging substrates (e.g., for bonding semiconductor elements to packaging substrates), such as organic laminate substrates, ceramic substrates, wafer-level or panel-level redistribution layer (RDL) substrates, etc. In fact, as described below, semiconductor elements that are directly bonded are polished (e.g., using chemical mechanical polishing, or CMP) to an extremely high smoothness, e.g., a surface roughness of less than 2 nm root mean square (RMS), or less than 1 nm RMS. Unlike semiconductor devices, package substrates, which contain multiple layers, each with a micron-order surface roughness, may not be polished to the smoothness used in direct bonding techniques, which has been an obstacle to mounting components to package substrates using hybrid bonding techniques. In addition, package substrates are made of materials (e.g., containing organic core materials) that are softer than semiconductor devices (e.g., semiconductor materials such as silicon), which can make it difficult to ensure flatness. PCB materials are also sensitive to high temperatures. Stresses can also be generated when connecting semiconductor devices or components to package substrates, due to factors such as mismatch in coefficient of thermal expansion (CTE). Further issues include contamination of the bonding surfaces in manufacturing facilities that process package substrates, which are typically not as clean as those that manufacture semiconductor devices. In fact, cleanroom standards in semiconductor manufacturing facilities are orders of magnitude better than those typically required for packaging facilities.

[0010] Advantageously, embodiments disclosed herein address these challenges by providing methods and structures for directly bonding electronic components (such as semiconductor devices, bonding layers, or any other type of electronic component) onto a package substrate. The disclosed embodiments can provide for the connection of fine pitch electronic components to coarse pitch package substrates without creating thermal stresses while providing a sufficiently smooth surface for direct bonding.

[0011] 1A shows a schematic cross-sectional side view of a package substrate 3. The package substrate 3 includes structures and components for providing electrical connections between a device or component (such as an integrated device die, passive device components, or other components) and an external device or system (such as a system motherboard of a larger electrical system). Such components of the package substrate 3 may include a laminate substrate including an upper insulating wiring layer 22, a core 23, a lower insulating wiring layer 24, vias 25, terminals 26, vertical interconnects 27, and horizontal traces 28. The terminals 26 may be configured to connect to an external device or system by, for example, solder balls or other conductive connectors. Electrical signals, power, or ground may be provided to the upper surface of the package substrate 3 by the horizontal traces 28, the interconnects 27, and the vias 25 that extend through the core 23. In the illustrated embodiment, the package substrate 3 may include an organic substrate in which one or more of the insulating layers and the core include an organic material, as described herein. In some embodiments, the package substrate 3 may be formed of a ceramic material, as described herein.

[0012] 1B shows a schematic cross-sectional side view of a packaging carrier 6 and an electronic component 14 directly bonded to the packaging carrier 6. The packaging carrier 6 has an inorganic, insulating first bonding layer 4 and a first conductive feature 5 as part of a bonding structure 2 on its surface. In this specification, "packaging carrier" refers to the combination of a package substrate 3 and a bonding structure 2 formed thereon. The material of the bonding layer 4 can include, for example, silicon oxide with nitrogen termination, or other materials as described below.

[0013] In the embodiments disclosed herein, the electronic component 14 may comprise any suitable type of electronic component bonded directly to the packaging carrier 6. In the illustrated embodiment, for example, the electronic component 14 includes a wiring layer 7, a temporary carrier 8, and a second insulating bonding layer 9 having a second conductive feature 10 at least partially embedded therein. The wiring layer 7 with the temporary carrier 8 is configured to be bonded to the packaging carrier 6 via the second bonding layer 9. The insulating bonding layer 4 of the package carrier 6 may be bonded directly to the second insulating bonding layer 9 of the electronic component 14 without the use of an adhesive. The first conductive feature 5 may be bonded directly to the corresponding second conductive feature 10 of the electronic component 14 without an intervening adhesive.

[0014] FIG. 1C shows a schematic cross-sectional side view of a joint structure 1 including a packaging carrier 6 directly bonded to an electronic component 14 bonded without the use of adhesive. The bonding layers 4 and 9 are directly bonded without the use of adhesive such that the electronic component 14 and the packaging carrier 6 form the joint structure 1. FIG. 1D shows a schematic cross-sectional side view of the joint structure 1. In FIG. 1D, the temporary carrier 8 is removed from the joint structure 1 (e.g., by lapping, polishing, etching, optical peeling, etc.), which in FIG. 1D includes a packaging carrier substrate 6 directly hybrid bonded to a wiring layer 7. For example, the wiring layer 7 can be directly bonded to the package carrier 6 and can include an insulating bonding layer 9 (e.g., a dielectric layer) and a second conductive contact 10 configured for hybrid direct bonding at an upper surface 30a of the joint structure 2 of the package carrier 6 opposite the lower surface 31 of the bonding layer 9 of the electronic component 14 to which the carrier is bonded. As shown in FIGS. 4A-E below, a semiconductor device 11 can be directly bonded to an upper hybrid bonding surface 30b of the electronic component 14 without adhesive. As described below, the semiconductor device 11 may comprise any suitable type of device, such as an integrated device die or chip with circuitry patterned therein, passive electronic components 14 (resistors, capacitors, inductors, etc.), optical components, or any other suitable type of components. It should be understood that in various embodiments, parameters such as material CTE, layer thickness, etc. may vary depending on the package design. In the illustrated embodiment, the carrier 8 of FIG. 1C is removed to form the wiring layer 7 of FIG. 1D, but it should be understood that in other embodiments, the carrier 8 may not be removed, e.g., the carrier 8 may comprise devices or components that remain in the bonded structure 1.

[0015] FIG. 2 is a schematic cross-sectional side view of a packaging carrier 6 including a buffer layer 12 having a thermal expansion coefficient between a package substrate 3 and an insulating bonding layer 4. In the illustrated embodiment of FIG. 1, an electronic component 14 includes a wiring layer 7 formed or bonded onto a temporary carrier 8. As seen in the detailed view of FIG. 2, in the illustrated embodiment, the package substrate 3 includes an organic substrate including an organic core 23 material and includes multiple organic insulating layers such as an upper insulating wiring layer 22 and a lower insulating wiring layer 24 patterned with metal. The organic insulating wiring layers (22 and 24) can include, for example, benzocyclobutene (BCB), silica-filled epoxy, bismaleimide triazine BT) resin, Ajinomoto Build-up Film (ABF) material (provided by Ajinomoto Group, Tokyo, Japan), polyimide, and the like. In various embodiments, the organic substrate can include a wafer-level package (WLP) substrate, a fan-out wafer-level package (FOWLP) substrate, and the like.

[0016] 1A-D and 2, the package substrate 3 can include a non-silicon and non-glass core material 23 (e.g., FR-4, which is a glass-reinforced epoxy material). The core material 23 can have a coefficient of thermal expansion (CTE) between about 1 ppm / °C and 20 ppm / °C, e.g., between about 5 ppm / °C and 25 ppm / °C, between about 10 ppm / °C and 25 ppm / °C, and / or between about 14 ppm / °C and 20 ppm / °C. Some low-CTE core materials 23 can have a CTE of less than about 10 ppm / °C, e.g., less than about 5 ppm / °C in some embodiments. In various embodiments, the organic insulating wiring layers (22 and / or 24) or build-up layers for forming metallization can typically include high-CTE materials, so that the effective CTE of the organic substrate can be in the range of 10 ppm / °C to 25 ppm / °C, e.g., in the range of about 10 ppm / °C to 20 ppm / °C. In the embodiment of FIGS. 1A-D and 2, the package substrate 3 comprises an organic core material 23 and a plurality of organic insulating wiring layers (22 and 24). In various embodiments, the organic core material 23 comprises interspersed glass particles. The package substrate 3 may comprise a printed circuit board (PCB) in various embodiments. The package substrate 3 may further comprise additional electrical interconnects, such as vias 25, terminals 26, vertical interconnects 27, and horizontal traces 28, disposed within the package substrate 3 for conducting electrical current within the package substrate 3. The vertical interconnects 27 of the package substrate 3 connect to the first conductive feature 5. The conductive feature 5 enables electrical connection between the component 14 (e.g., wiring layer 7) and the package substrate 3 through the bonding structure 2, which includes the bonding layer 4, the first conductive feature 9, and the upper bonding surface 30a.

[0017] As shown in FIG. 2, the packaging carrier 6 may include a buffer layer 12 between the package substrate 3 (e.g., the upper organic insulating layer 22) and the bonding structure 2 (e.g., the bonding layer 4). The buffer layer 12 may have a coefficient of thermal expansion (CTE) between the package substrate 3 and the first bonding layer 4. For example, the buffer layer 12 may have a coefficient of thermal expansion between the insulating bonding layer 4 and the top insulating layer of the upper insulating layer 22 of the package substrate 3. In some embodiments, the buffer layer 12 may have a CTE between the insulating bonding layer 4 and all organic insulating layers between the insulating bonding layer 4 and the core 23. The buffer layer 12 may have a CTE between the insulating bonding layer 4 and the core 23. The CTE of the buffer layer 12 may be in the range of 1 ppm / °C to 15 ppm / °C, in the range of 2 ppm / °C to 15 ppm / °C, or in the range of 1 ppm / °C to 10 ppm / °C. The Young's modulus of the buffer layer 12 can be in the range of 1 Gpa to 15 Gpa, in the range of 2 Gpa to 12 Gpa, or in the range of 2 Gpa to 6 Gpa. The CTE and modulus parameters are merely exemplary and can depend on the materials selected for the organic substrate as well as the semiconductor substrate of the electronic component 14. In the illustrated embodiment, the buffer layer 12 comprises an organic material, such as a polyimide, a liquid crystal polymer layer, or other suitable material. In some embodiments, the buffer layer 12 can comprise benzocyclobutene (BCB). The buffer layer 12 can beneficially have a CTE that provides a transition between the inorganic bonding layer 4 and the organic material of the package substrate 3 to reduce or eliminate thermally induced stresses that may otherwise occur when the substrate or package structure is heated or cooled. In some embodiments, the buffer layer 12 can comprise multiple layers of different materials (or multiple layers of the same material). Thus, the buffer layer 12 provides a CTE gradient between the inorganic bonding layer 4 and the organic material of the package substrate 3. In one embodiment, the CTE of the buffer material disposed on the surface of the package substrate 3 within the buffer layer 12 may include a material having a CTE that is less than 30% of the CTE of the package substrate 3 (e.g., less than 30% of the effective or composite CTE of the package substrate 3).Also, in some applications, the CTE of the material of buffer layer 12 beneath inorganic bonding layer 4 can include a material having a CTE less than 20 times, such as less than 15 times, of the inorganic bonding layer 4. Although Figure 2 shows only one material / layer for buffer layer 12, combinations of two or more materials with different thicknesses, CTEs and moduli may be implemented for buffer layer 12.

[0018] Further, as shown in FIG. 2, the packaging carrier 6 may include a hard mask layer 13 between the buffer layer 12 and the first bonding layer 4. The illustrated hard mask layer 13 may alternatively or additionally serve as an adhesion layer. The hard mask layer 13 may comprise an inorganic dielectric layer, such as silicon nitride. The hard mask layer 13 may function as a mask during patterning of the underlying buffer layer 12 and providing the conductive features 5, such as by dual damascene processing for copper features. Other examples of hard mask 13 materials include, but are not limited to, amorphous carbon, silicon oxynitride, silicon carbide, and the like. In some embodiments, the hard mask 13 coated on the package carrier 6 may be omitted. The top surface of the package carrier 6 may be activated by treating the surface with a plasma containing nitrogen or water vapor prior to coating the treated surface with the buffer layer 12. The activation step may improve adhesion of the buffer layer 12 to the package carrier 6. Other methods can be used to improve adhesion of the buffer layer 12 to the package substrate 3, for example, an adhesion promoter such as 0.1%-5% titanate coupling agent can be incorporated into the buffer layer 12 to improve adhesion of the spin-on buffer layer 12 to the package carrier 6. Metal embedded in the top surface of the organic insulating routing layer can be used as an etch stop to pattern the bonding layer 4 and buffer layer 12.

[0019] Returning to FIGS. 1C-D, the electronic component 14 can include a wiring layer 7. The wiring layer 7 can function as an interposer, and can be provided by a temporary carrier 8 that is easily removed, if desired, leaving only the wiring layer 7 bonded directly onto the packaging carrier 6. For example, in FIGS. 1C-D, the wiring layer 7 can serve to transition between the fine pitch of the electronic component 14 and the coarse pitch of the conductive features 5 of the bonding layer 4. As described herein, additional components can be hybrid bonded (or bonded with a conductive adhesive such as solder) directly to the wiring layer 7. In various embodiments, the wiring layer 7 includes lines having a pitch of less than 5 μm, e.g., less than 3 μm. In various embodiments, the conductive features 5 can have a pitch of less than 40 microns, e.g., in the range of 1 micron to 50 microns or in the range of 2 microns to 50 microns. In some embodiments, the electronic component 14 further includes a semiconductor substrate having active devices at least partially formed therein. Additional electronic components 14 for fine pitch connections can then be mounted thereon by conventional bonding or direct bonding (see FIG. 3), as described below with respect to FIGS. 4A-E and 5A-E.

[0020] As shown in Figures 1C-D, the electronic component 14 can be directly bonded to the packaging carrier 6 without an adhesive bond along the adhesive interface. The insulating bonding layer 4 can include an inorganic dielectric material that can be polished (e.g., by chemical mechanical polishing) and prepared for direct bonding. The insulating bonding layer 4 can be prepared to have a bonding surface with a surface roughness of less than about 20 Å rms, such as less than about 15 Å rms. The bonding interface can have a higher nitrogen content than portions of the first bonding layer 4 and the second bonding layer 9 away from the bonding interface. The first bonding layer 4 can include silicon oxide in various embodiments and can have a fluorine peak content proximate to the bonding interface. The first bonding layer 4 can have a coefficient of thermal expansion (CTE) between about 0.5 ppm / °C and 12 ppm / °C, between about 0.5 ppm / °C and 10 ppm / °C, between about 0.5 ppm / °C and 5 ppm / °C, and / or between about 0.5 ppm / °C and 4 ppm / °C. The interface between buffer layer 12 and package substrate 3 in FIG. 2 may have a higher nitrogen content than portions of buffer layer 12 or package substrate 3.

[0021] FIG. 3 is a schematic cross-sectional side view of a bonding structure 1 including a wiring layer 7 bonded to a package carrier 6 of the bonding structure 1. The wiring layer 7 can have conductive features 35 embedded in a dielectric layer of an upper hybrid bonding surface 30b. In some embodiments, such as in FIGS. 1C-D and 2, the bonding structure 2 including the bonding layer 4, the first conductive features 9, and the upper bonding surface 30a of the package carrier 6 can completely or substantially completely occupy the entire surface of the package substrate 3. FIG. 3 is a schematic cross-sectional side view of a bonding structure 1 having a first bonding layer 4 patterned to occupy less than the entire surface of the package substrate 3. In other embodiments, such as in FIG. 3, the first bonding layer 4 can be patterned to occupy less than the entire surface of the package substrate 3 to form islands 29 on the surface of the package substrate 3. Utilizing less than the entire surface by improving the distribution of the bonding layer 4 (and / or the buffer layer 12 as shown in FIG. 2) on the top surface of the organic material layer of the package substrate 3 can beneficially reduce stress in some implementations. For example, in some embodiments, the first bonding layer 4 can be patterned to form a plurality of islands 29 with physical gaps 32 between adjacent layers or islands 29 across the surface of the package substrate 3, also shown in FIGS. 4A-E and 5A-E. The gaps 32 can be filled with any suitable filler material (e.g., a low modulus material such as polyimide) if desired to support wiring. In some embodiments, after forming the first bonding layer 4, unwanted portions of the first bonding layer 4 can be selectively removed by dry or wet etching methods, or a combination thereof, to form islands 29 or islands of the first bonding layer 4. The bonding structure 1 can include an electronic (e.g., semiconductor, glass, etc.) component 14, such as a packaging substrate 3 with an inorganic, insulating second bonding layer 9 and a second conductive feature 10 on its surface. The first bonding layer 4 and the second bonding layer 9 can be directly bonded to each other, and the first conductive feature 5 and the second conductive feature 10 can be directly bonded to each other.The electronic components 14 may comprise a substrate including any suitable type of component on a substrate, such as any one of silicon, InGaP, GaN, SiC, etc. The substrate may additionally or alternatively include glass.

[0022] 4A-E are schematic cross-sectional side views of one or more semiconductor devices 11 mounted on a bonding structure 1. FIGS. 4A-4E show various examples of additional devices such as semiconductor devices 11 bonded to electronic components 14 (e.g., bonding layer 7) with vertical pathways of conduction 33 from the semiconductor devices 11 through the packaging carrier 6 and the electronic components 14. In FIG. 4A, the semiconductor devices 11 can be soldered to features (e.g., copper pillars) of the bonding layer 4 of the underlying package substrate 3 or package carrier 6, bypassing the directly bonded devices (e.g., wiring layer 7). In the illustrated example, a portion of one device 11 is soldered using multiple solder balls 18, and another portion is directly hybrid bonded to the wiring layer 7 along a hybrid bond interface 19. In FIG. 4B, the entire semiconductor device 11 can be directly hybrid bonded to the directly bonded devices (wiring layer 7) along the hybrid bond interface 19. In FIG. 4C, multiple semiconductor devices 11 are directly hybrid bonded to the wiring layer 7 along the hybrid bond interface 19. The wiring layer 7 can function as bridges 15 for horizontal electrical communication to provide electrical communication between adjacent dies 11a, 11b and to provide electrical communication between the semiconductor devices 11a, 11b and the terminals 26 on the bottom side of the packaging carrier 6. In FIG. 4D, multiple bridges 15 for lateral electrical communication are provided for two or more (e.g., three) adjacent semiconductor devices 11a, 11b, 11c. The multiple bridges 15 provide lateral communication between adjacent semiconductor devices 11 through the wiring layer 7 of the electronic component 14. In FIG. 4E, the first semiconductor device 11a is directly hybrid bonded to the wiring layer 7, and the second semiconductor device 11b is conventionally connected to the wiring layer 7 (e.g., wire bonded or flip-chip soldered with multiple solder balls 18 as shown), and the wiring layer 7 can function as bridges to electrically connect the first semiconductor device 11 and the second semiconductor device 11. A third semiconductor device 11 c is also shown conventionally connected (eg, soldered) to the packaging carrier 6 using a plurality of solder balls 18 .

[0023] 5A-E are schematic cross-sectional side views of a surface mount technology assembly mounted to a hybrid direct bond structure 1 using surface mount technology. FIGS. 5A-5E show additional examples of semiconductor devices 11 bonded to directly bonded electronic components 14 (e.g., wiring layer 7) of the type shown in FIGS. 1B-D, without an upper hybrid bonding layer on the components 14. The further devices can be connected by conventional connectors such as solder balls 18 (e.g., bond wire, thermocompression or solder). In the illustrated example, the connection between the further devices and the directly bonded electronic components 14 (wiring layer 7) comprises a conductive adhesive (e.g., solder balls 18). Thus, in some embodiments, the electronic components 14 (wiring layer 7) are directly bonded to the packaging carrier 6 along the hybrid bonding surface 19, and one or more semiconductor devices 11 can be bonded or mounted to the electronic components 14 (wiring layer 7) with a conductive adhesive such as solder balls 18.

[0024] FIG. 6 is a schematic cross-sectional side view showing a state where a semiconductor device 11 is directly hybrid-bonded to a package substrate 3 comprising a ceramic substrate. FIG. 6 shows another embodiment where the package substrate 3 comprises a ceramic substrate. The ceramic substrate can include cordierite, silicon nitride, sapphire, alumina, silicon carbide (SiC), aluminum nitride (AlN), yttria, zirconia, mullite, high temperature co-fired ceramic (HTCC), beryllium oxide (BeO), low temperature co-fired ceramic (LTCC), and the like. In some embodiments, the electronic component 14 may be directly bonded to the activated smooth surface of the ceramic substrate at room temperature, and the heating and cooling rates of the bond can be less than 10° C. / min, less than 5° C. / min, or less than 2° C. / min to reduce the CTE difference and associated defects. Although not shown in FIG. 6, when there is a large CTE difference between the dielectric layer of the electronic component 14 and the dielectric layer of the ceramic substrate, a buffer layer similar to the buffer layer 12 of FIG. 2 can be provided and coated on the ceramic substrate to bond the ceramic package to the bonding layer 4. The electronic component 14 includes a temporary carrier 8 that is removable after the insulating bonding layer 4 and contact pads 5 are bonded with the insulating bonding layer 10 and contact pads 5 of the electronic component 14. In some embodiments, the buffer layer 12 can include a low CTE polymer layer having a CTE of less than 8 ppm / ° C. In some embodiments, the bonding layer 4 can be bonded directly onto the ceramic substrate of the package substrate 3. The process of forming the bonding layer 4 can include activating a smooth surface of the ceramic material prior to bonding. The activation step can include exposing the smooth bonding surface of the ceramic substrate to one or more plasma environments. The plasma environment can include oxygen plasma, nitrogen plasma, helium plasma, water vapor plasma, or combinations thereof. The bonding surface of the ceramic substrate can be subjected to a similar plasma exposure prior to forming the buffer layer 12 on the ceramic substrate. In some embodiments, an adhesion layer 20 can be provided (e.g., deposited) on the ceramic substrate. An adhesion layer 4 as described above can be provided on the adhesion layer 20 such that the adhesion layer 20 is disposed between the ceramic substrate and the adhesion layer 4.In various embodiments, the adhesive layer 20 comprises an inorganic material such as silicon nitride, silicon oxynitride, silicon carbide, or silicon oxide. The thickness of the adhesive layer 20 can be less than 500 nm, less than 100 nm, or less than 50 nm. In some embodiments, the surfaces or recesses of the conductive pads of the electronic component 14 or the pads of the bonding layer can be coated with nanoparticles of a conductive material (not shown) to reduce the bonding temperature between the conductive pads of the electronic component 14 and the bonding layer 4. For example, the coating layer can be copper or gold or silver nanoparticles. In some embodiments, the electronic component 14 having conductive pads containing nanoparticles can be directly bonded to the package substrate 3. In some embodiments, the buffer layer 20 can be omitted on the surface of the ceramic package 3 and instead incorporated under the bonding surface of the electronic component 14. The electronic component 14 having a bonding surface with an integrated buffer layer (not shown) and conductive pads containing nanoparticles can be directly bonded to the ceramic package 3. The conductive nanoparticles, by nature of their size, can be bonded at a lower temperature compared to that of the bulk. The bonding temperature of the electronic component and the package with nanoparticle coated pads is below 180° C., e.g., below 160° C., which is typically below the reflow temperature of Ag-Sn solder (typically above 200° C.). Reducing the direct bonding temperature between the electronic component 14 and the organic or ceramic package is beneficial in reducing stresses associated with CTE differences in the bonded structures.

[0025] Examples of direct bonding method and direct bonded structure Various embodiments disclosed herein relate to direct bond structures that allow two elements to be directly bonded together without an intervening adhesive. Two or more electronic elements, which may be semiconductor elements (integrated device dies, wafers, etc.) or non-semiconductor elements such as package substrates with inorganic insulating bonding layers as described herein, may be stacked or bonded together to form a bond structure. In embodiments disclosed herein, the electronic component (e.g., wiring layer) may comprise a first element and the package carrier may comprise a second element. The semiconductor device may comprise a third element. The conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements may be stacked on the bond structure. The contact pads may comprise metal pads formed on non-conductive bonding areas and may be connected to an underlying metallization such as a redistribution layer (RDL).

[0026] In some embodiments, the elements are directly bonded to each other without adhesive. In various embodiments, the non-conductive or dielectric material of the first element can be directly bonded to the corresponding non-conductive or dielectric field area of ​​the second element without adhesive. The non-conductive material can be referred to as the non-conductive bonding area or bonding layer of the first element. In some embodiments, the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-to-dielectric bonding techniques. For example, the dielectric-dielectric bond can be formed without adhesive using direct bonding techniques disclosed in at least U.S. Pat. No. 9,564,414, U.S. Pat. No. 9,391,143, and U.S. Pat. No. 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes. Suitable dielectric materials for the direct bonding layer described herein include, but are not limited to, inorganic dielectrics such as silicon oxide, silicon nitride, or silicon oxynitride, or can include carbon such as silicon carbide, silicon oxynitride, silicon carbonitride, or diamond-like carbon. In some embodiments, the dielectric material of the bonding layer does not comprise a polymeric material such as an epoxy, resin, or molding compound, but the underlying layers may include organic materials such as the layers described herein.

[0027] In various embodiments, the hybrid direct bond can be formed without an intervening adhesive. For example, the dielectric bonding surfaces can be polished to a high degree of smoothness. The bonding surfaces can be cleaned and exposed to a plasma and / or an etchant to activate the surfaces. In some embodiments, the surfaces can be terminated with chemical species after activation or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, the activation process can be activated to break chemical bonds at the bonding surfaces, and the termination process can provide additional chemical species to the bonding surfaces that improve the bonding energy during direct bonding. In some embodiments, activation and termination are provided in the same step, e.g., plasma or wet etchant, to activate and terminate the surfaces. In other embodiments, the bonding surfaces can be terminated in a separate process to provide additional chemical species for direct bonding. In various embodiments, the termination species can include nitrogen. Additionally, in some embodiments, the bonding surfaces can be exposed to fluorine. For example, there can be one or more fluorine peaks near the layers and / or bonding interface. Thus, in a direct bond structure, the bond interface between the two dielectric materials can have a very smooth interface with a higher nitrogen content and / or fluorine peak at the bond interface. Additional examples of activation and / or termination treatments can be found throughout U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes.

[0028] In various embodiments, the conductive contact pads of the first element can also be directly bonded to the corresponding conductive contact pads of the second element. For example, hybrid direct bonding techniques can be used to provide conductor-to-conductor direct bonding along a bonding interface that includes the covalently directly bonded dielectric-to-dielectric surfaces prepared as described above. In various embodiments, conductor-conductor (e.g., contact pad-contact pad) direct bonds and dielectric-dielectric hybrid bonds can be formed using direct bonding techniques disclosed in at least U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated herein by reference in their entirety for all purposes.

[0029] For example, the dielectric bonding surfaces of the bonding layers described herein can be prepared and bonded directly to one another without an intervening adhesive, as described above. The conductive contact pads (which may be surrounded by non-conductive dielectric field regions) can also be bonded directly to one another without an intervening adhesive. In some embodiments, each contact pad can be recessed, e.g., less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm, below the outer (e.g., upper) surface of the dielectric field region or non-conductive bonding region. The non-conductive bonding regions can be directly bonded to one another without adhesive bonding at room temperature in a bonding tool described herein, in some embodiments, and the bonded structure can then be annealed. The annealing can be performed in a separate apparatus. Upon annealing, the contact pads can expand and contact one another, resulting in a direct metal-to-metal bond. Advantageously, the use of hybrid bonding technologies such as DBI® (Direct Bond Interconnect) commercially available from Adeia, Inc., San Jose, Calif., allows for a high density of connected pads across the direct bond interface (e.g., small or fine pitch for regular arrays). In some embodiments, the pitch of the bond pads, or the conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 microns, or less than 10 microns, or less than 2 microns. In some applications, the ratio of the bond pad pitch to the bond pad dimension is less than 5, or less than 3, and in some cases desirably less than 2. In other applications, the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range from 0.3 microns to 5 microns. In various embodiments, the contact pads and / or traces may include copper, although other metals may be suitable.

[0030] As described herein, the first and second elements (e.g., electronic components and packaging carriers exemplified herein as wiring layers) can be directly bonded to each other without adhesive, which is different from a deposition process. Accordingly, the first and second elements can include non-deposited elements. Furthermore, the direct bond structure, unlike a deposition layer, can include defect areas along the bond interface where nanovoids exist. The nanovoids can be formed by activation (e.g., exposure to plasma) of the bond surfaces. As described above, the bond interface can include concentrations of materials from the activation and / or last chemical treatment process. For example, in an embodiment utilizing nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface. In an embodiment utilizing oxygen plasma for activation, an oxygen peak can be formed at the bond interface. In some embodiments, the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond can comprise covalent bonds that are stronger than van der Waals bonds. The bond layer can also comprise a polished surface that is planarized to a high degree of smoothness. For example, the bonding layer may have a surface roughness of less than 2 nm root mean square (RMS) per micron, or less than 1 nm RMS per micron.

[0031] In various embodiments, the metal-to-metal bond between conductive features (e.g., contact pads) in a direct hybrid bond structure can be bonded such that the grains of the conductive features, e.g., copper grains on the conductive features, grow together across the bond interface. In some embodiments, the copper can have grains oriented along 111 crystal planes to improve diffusion of copper across the bond interface. The bond interface can extend substantially completely to at least a portion of the bonded contact pad, such that there is substantially no gap between the non-conductive bond regions at or near the bonded contact pad. In some embodiments, a barrier layer can be provided (e.g., can include copper) under the contact pad. However, in other embodiments, there may be no barrier layer under the contact pad, as described, for example, in U.S. Patent Publication No. 2019 / 0096741, which is incorporated herein by reference in its entirety and for all purposes.

[0032] In one embodiment, a bonding structure comprises a packaging substrate including a first bonding layer that is inorganic insulating and a first conductive feature on its surface; and an electronic component including a second bonding layer that is inorganic insulating and a second conductive feature on its surface, wherein the first bonding layer and the second bonding layer are directly bonded to each other and the first conductive feature and the second conductive feature are directly bonded to each other.

[0033] In some embodiments, the package substrate comprises a non-silicon and non-glass core material. In some embodiments, the package substrate comprises a core material having a coefficient of thermal expansion (CTE) between about 5 ppm / ° C. and 25 ppm / ° C. In some embodiments, the package substrate comprises an organic core material. In some embodiments, the organic core material comprises interspersed glass particles. In some embodiments, the package substrate comprises a printed circuit board (PCB). In some embodiments, the bonding structure can include a buffer layer between the package substrate and the first bonding layer, the buffer layer having a coefficient of thermal expansion (CTE) between the package substrate and the first bonding layer. In some embodiments, the buffer layer comprises an organic material. In some embodiments, the buffer layer comprises a polyimide. In some embodiments, the buffer layer comprises a liquid crystal polymer layer. In some embodiments, the buffer layer comprises benzocyclobutene (BCB). In some embodiments, the bonding structure can include a hard mask layer between the buffer layer and the first bonding layer. In some embodiments, the hard mask layer comprises an inorganic dielectric layer. In some embodiments, the hard mask layer comprises silicon nitride. In some embodiments, the package substrate comprises a ceramic substrate. In some embodiments, the bonding structure may include an adhesive layer between the bonding layer and the package substrate. In some embodiments, the bonding layer comprises an inorganic material. In some embodiments, the electronic component comprises a wiring layer. In some embodiments, the wiring layer comprises lines having a pitch of less than 20 μm. In some embodiments, the wiring layer functions as an interposer without a bulk substrate. In some embodiments, the bonding structure may include a semiconductor device directly bonded onto the electronic component. In some embodiments, the bonding structure may include a semiconductor device soldered onto the electronic component. In some embodiments, the electronic component further comprises a semiconductor substrate having active devices formed at least partially therein. In some embodiments, the bonding interface between the first bonding layer and the second bonding layer comprises a higher nitrogen content than portions of the first bonding layer and the second bonding layer away from the bonding interface.In some embodiments, the first bonding layer comprises at least one of silicon oxide and has a fluorine peak content proximate to the bonding interface between the first bonding layer and the second bonding layer. In some embodiments, the first bonding layer comprises at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, aluminum oxide, aluminum nitride, and zirconium oxide. In some embodiments, the first bonding layer has a coefficient of thermal expansion (CTE) between about 0.5 ppm / °C and about 12 ppm / °C. In some embodiments, the first bonding layer is patterned to occupy less than the entire surface of the package substrate. In some embodiments, the first bonding layer is patterned to form a plurality of islands across the surface of the package substrate.

[0034] In another embodiment, a packaging carrier configured for direct bonding with another electronic component is disclosed, the packaging carrier comprising a ceramic or organic packaging core, an inorganic insulating bonding layer, and embedded and exposed conductive features at its bonding surface, the bonding surface having a surface roughness of less than about 20 Å rms.

[0035] In some embodiments, the package core comprises an organic material. In some embodiments, the package carrier can include an organic layer between the package core and the first bonding layer. In some embodiments, the organic layer comprises a polyimide. In some embodiments, the packaging carrier can include an inorganic dielectric layer interposed between the organic layer and the first bonding layer. In some embodiments, the interposed inorganic dielectric layer comprises silicon nitride. In some embodiments, the bonding surface comprises a higher nitrogen content than a portion of the bonding layer away from the bonding surface. In some embodiments, the bonding layer comprises silicon oxide and has a fluorine peak content proximate to the bonding surface. In some embodiments, the bonding layer has a coefficient of thermal expansion (CTE) between about 0.5 ppm / °C and about 12 ppm / °C. In some embodiments, the bonding layer is patterned to occupy less than the entire surface of the packaging carrier. In some embodiments, the bonding layer is patterned to form a plurality of islands across the packaging carrier. In some embodiments, the conductive features are recessed between about 2 nm and 20 nm below the bonding surface. In some embodiments, the bonding layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, and zirconium oxide.

[0036] In another embodiment, a method for direct bonding can include depositing an inorganic bonding layer on an organic or ceramic packaging substrate, embedding conductive features in the bonding layer, and preparing the bonding layer for direct hybrid bonding with a second electronic component.

[0037] In some embodiments, the method may include directly hybrid bonding a second electronic component to the bonding layer such that a second inorganic bonding layer of the second electronic component directly bonds to the bonding layer and a second conductive feature of the second electronic component directly bonds to the conductive feature embedded in the bonding layer. In some embodiments, the second electronic component comprises a wiring layer. In some embodiments, the wiring layer comprises lines having a pitch of less than 20 μm. In some embodiments, the method may include thinning or removing the carrier from the second electronic component after direct bonding to leave an interposer structure. In some embodiments, embedding the conductive feature comprises a damascene process. In some embodiments, embedding the conductive feature comprises recessing the conductive feature between 2 nm and 20 nm below a bonding surface of the bonding layer. In some embodiments, preparing the bonding layer for direct bonding comprises polishing the bonding layer to have a surface roughness of less than about 20 Å rms. In some embodiments, preparing the bonding layer for direct bonding further comprises treating the surfaces of the bonding layer and the conductive feature to form a nitrogen termination. In some embodiments, the method may include depositing a buffer layer on the package substrate prior to depositing the bonding layer, the package substrate comprising an organic core material, the buffer layer having a coefficient of thermal expansion (CTE) between the package carrier and the first bonding layer. In some embodiments, the buffer layer comprises a polymer layer. In some embodiments, the core material comprises FR-4. In some embodiments, the method may include depositing a masking layer on the buffer layer prior to depositing the bonding layer. In some embodiments, the masking layer comprises a silicon nitride layer. In some embodiments, depositing the bonding layer comprises plasma deposition. In some embodiments, the bonding layer comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, and zirconium oxide.In some embodiments, the method can include patterning the bonding layer to remove the bonding layer from a surface of the package substrate to leave the bonding layer in the locations to be directly bonded. In some embodiments, the method can include masking the package substrate such that depositing the bonding layer is limited to the locations of the package substrate to be directly bonded. In some embodiments, the method can include depositing an adhesion layer on the package substrate prior to depositing the bonding layer, the package substrate comprising a ceramic material.

[0038] In another embodiment, a packaging carrier configured for direct bonding with another electronic component is disclosed. The packaging carrier can include a package core including a ceramic or organic material and an inorganic insulating bonding layer having embedded conductive features exposed at a bonding surface thereof, the bonding surface having a surface roughness of less than about 20 Å rms.

[0039] In some embodiments, the package core comprises a ceramic material including at least one of cordierite, silicon nitride, silicon carbide, aluminum nitride, alumina, yttria, sapphire, zirconia, and mullite.

[0040] In some embodiments, the bonding structure comprises an inorganic bonding layer deposited on an organic or ceramic package substrate and conductive features embedded in the bonding layer, the bonding layer being prepared for direct hybrid bonding with a second electronic component. In some embodiments of the bonding structure, the second electronic component is directly hybrid bonded to the bonding layer such that the second inorganic bonding layer of the second electronic component is directly bonded to the bonding layer and the second conductive features of the second electronic component are directly bonded to the conductive features embedded in the bonding layer. In some embodiments of the bonding structure, the carrier is thinned or removed from the second electronic component after direct bonding, leaving the interposer structure.

[0041] In some embodiments, a packaging carrier configured for direct bonding with another electronic component includes a package core including a ceramic or organic material and an inorganic insulating bonding layer having embedded conductive features exposed at a bonding surface thereof, the bonding surface of the conductive features including nanoparticles. In some embodiments, the package core includes an organic material. In some embodiments, the packaging carrier further includes an organic layer between the package core and the first bonding layer. In some embodiments, the organic layer includes a polyimide.

[0042] Unless the context clearly requires otherwise, the terms "comprises," "comprising," "including," "including," and the like, throughout this specification and claims, are to be construed in an inclusive sense, i.e., meaning "including, but not limited to," as opposed to an exclusive or exhaustive sense. The term "coupled," as generally used herein, refers to two or more elements that are either directly coupled or coupled through one or more intermediate elements. Similarly, the term "connected," as generally used herein, refers to two or more elements that are either directly connected or connected through one or more intermediate elements. Additionally, the terms "herein," "up," "down," and similar terms, when used in this application, refer to this application as a whole and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as being "on" or "on" a second element, the first element may be directly on or on the second element such that the first and second elements are in direct contact, or the first element may be indirectly on or on the second element such that one or more elements are interposed between the first and second elements. Wherever the context permits, words using singular or plural numbers in the above Detailed Description may include plural or singular numbers, respectively. The term "or" in reference to a list of two or more items covers the following interpretations of this term: any of the items in the list, all of the items in the list, and all of any combination of the items in the list.

[0043] Additionally, conditional language used herein, such as, among others, "can," "may," "might," "for example," "such as," and the like, are generally intended to convey that certain embodiments include certain features, elements and / or conditions, and that other embodiments do not include certain features, elements and / or conditions, unless otherwise specified or understood within the context in which they are used. Thus, such conditional language is generally not intended to imply that a feature, element and / or condition is in any way required for one or more embodiments.

[0044] Although specific embodiments have been described, these embodiments are presented as examples only and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, although blocks are shown in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of elements and acts of the various embodiments described above may be combined to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications as fall within the scope and spirit of the disclosure. [Explanation of symbols]

[0045] 1 Joined structure 3 Package Substrate 4 Bonding layer 6 Packaging Carrier 7 wiring layer 9 Bonding layer 10 Conductive Contact 14 Electronic Components 30a Upper surface 30b Upper hybrid interface 31 Lower surface

Claims

1. A bonded structure, a package substrate including an inorganic insulating first bonding layer and a first conductive feature on a surface thereof; an electronic component including an inorganic insulating second bonding layer and a second conductive feature on a surface thereof; Equipped with the first bonding layer and the second bonding layer are directly bonded to one another, and the first and second conductive features are directly bonded to one another. bonded structure.

2. 2. The bonded structure of claim 1, further comprising a buffer layer between the package substrate and the first bonding layer, the buffer layer having a coefficient of thermal expansion (CTE) between the package substrate and the first bonding layer.

3. The bonded structure of claim 2 , further comprising a hard mask layer between the buffer layer and the first bonding layer.

4. The bonded structure of claim 3 , further comprising an adhesive layer between the bonding layer and the package substrate.

5. The bonded structure according to any one of claims 1 to 4, wherein the electronic component comprises a wiring layer.

6. The bonded structure of claim 4 further comprising a semiconductor device bonded directly onto the electronic component.

7. A packaging carrier configured for direct bonding with another electronic component, comprising: a ceramic or organic package core; an inorganic insulating bonding layer; an exposed conductive feature embedded in the joining surface; Equipped with The packaging carrier, wherein the mating surfaces have a surface roughness of less than about 20 Å rms.

8. The packaging carrier of claim 7 , wherein the package core comprises an organic material.

9. The packaging carrier of claim 8 , further comprising an organic layer between the package core and the first bonding layer.

10. The packaging carrier of claim 9 , further comprising an inorganic dielectric layer interposed between the organic layer and the first bonding layer.

11. 9. The packaging carrier of claim 7 or 8, wherein the bonding layer is patterned to occupy less than the entire surface of the packaging carrier.

12. A direct bonding method comprising the steps of: depositing an inorganic bonding layer on an organic or ceramic package substrate; embedding conductive features in the bonding layer; preparing the bonding layer for direct hybrid bonding with a second electronic component; A method comprising:

13. 13. The method of claim 12, further comprising hybrid bonding the second electronic component directly to the bonding layer such that a second inorganic bonding layer of the second electronic component directly bonds to the bonding layer and a second conductive feature of the second electronic component directly bonds to the conductive feature embedded in the bonding layer.

14. The method of claim 13 , wherein the second electronic component comprises an interconnect layer.

15. The method of claim 12 , further comprising thinning or removing the carrier from the second electronic component after being directly bonded to leave an interposer structure.

16. 16. The method of claim 14 or 15, wherein the step of embedding the conductive features comprises a damascene process.

17. The method of claim 12 , wherein preparing the bonding layer for direct bonding comprises polishing the bonding layer to have a surface roughness of less than about 20 Å rms.

18. 20. The method of claim 17, wherein preparing the bonding layer for direct bonding further comprises treating the surfaces of the bonding layer and the conductive feature to form nitrogen terminations.

19. 20. The method of claim 12, further comprising depositing a buffer layer on the package substrate before depositing the bonding layer, wherein the package substrate comprises an organic core material, and the buffer layer has a coefficient of thermal expansion (CTE) between the package carrier and the first bonding layer.

20. 20. The method of claim 19, further comprising depositing a masking layer on the buffer layer before depositing the bonding layer.

21. 19. The method of any one of claims 12 to 15, 17, and 18, further comprising patterning the bonding layer to remove the bonding layer from a surface of a portion of the package substrate and leave the bonding layer in a location where direct bonding will be performed.

22. 19. The method of any one of claims 12 to 15, 17, and 18, further comprising depositing an adhesive layer on the package substrate before depositing the bonding layer, wherein the package substrate comprises a ceramic material.

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