Priority-based cache lines that fit into a compressed memory system for a processor-based system

Abstract

The compressed memory system includes a memory region including cache lines having priority levels. The compressed memory system also includes a compressed memory region including compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line having a first priority level or a portion of the first cache line after compression. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite the first direction, either a portion of a second cache line having a priority level lower than the first priority level or a portion of the second cache line after compression. The first set of data bits includes a greater number of bits than the second set of data bits.

Description

[Technical field]

[0001] Priority Application This application claims priority to U.S. patent application Ser. No. 17 / 572,472, entitled "PRIORITY-BASED CACHE-LINE FITTING IN COMPRESSED MEMORY SYSTEMS OF PROCESSOR-BASED SYSTEMS," filed Jan. 10, 2022, which is incorporated by reference in its entirety.

[0002] This application claims priority to U.S. patent application Ser. No. 17 / 572,471, entitled "PRIORITY-BASED CACHE-LINE FITTING IN COMPRESSED MEMORY SYSTEMS OF PROCESSOR-BASED SYSTEMS," filed Jan. 10, 2022, which is incorporated by reference in its entirety.

[0003] The disclosed embodiments relate generally to memory systems, and more particularly to priority-based cache lines that fit into compressed memory systems in processor-based systems. [Background technology]

[0004] As the size and complexity of applications executed by conventional processor-based systems increase, memory bandwidth can become a constraint on system performance. While the available memory bandwidth can be increased through the use of wider memory communication channels, this approach can incur a penalty in terms of increased cost and / or additional area required for memory on an integrated circuit (IC). One approach to increase memory bandwidth in processor-based systems without increasing the width of the memory communication channel is through the use of data compression. Data compression systems can be used in processor-based systems to store data in a compressed format, thus increasing effective memory capacity without increasing physical memory capacity. In this regard, some conventional data compression systems provide a compression engine for compressing data to be written to a main system memory. After performing the compression, the compression engine writes the compressed data to the system memory along with metadata that maps the virtual addresses of the compressed data to physical addresses in the system memory where the compressed data is actually stored. However, because metadata is used for address mapping, memory accesses incur extra reads and writes that adversely affect system performance. For example, accessing a particular cache line in memory may require access to metadata in memory and an additional layer of address calculations to determine the location of the compressed cache line in memory that corresponds to that particular cache line, which can increase complexity, cost, and latency for processor-based systems that use memory capacity compression. Summary of the Invention

[0005] Therefore, there is a need for systems, methods, and techniques that minimize the overhead of conventional compression systems. The techniques described herein can be used to remove metadata for a large portion of a cache line, thus improving the average performance of cache line accesses.

[0006] In one aspect, a method for compressing data in a compressed memory system of a processor-based system is provided. The method includes dividing a memory region into a plurality of data regions, each data region associated with a respective priority level. The method also includes (i) selecting a first cache line from a first data region of the plurality of data regions, and (ii) selecting a second cache line from a second data region of the plurality of data regions. The first data region has a higher priority level than the second data region. The method also includes (i) compressing the first cache line to obtain a first compressed cache line, and (ii) compressing the second cache line to obtain a second compressed cache line. In accordance with a determination that the first cache line is compressible, the method includes (i) writing the first compressed cache line to a first predetermined portion of a candidate compressed cache line, and (ii) writing either the second cache line or a second portion of the second compressed cache line to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion.

[0007] In some implementations, the method further includes setting an overflow pointer in the candidate compressed cache line according to a determination that (i) the first cache line is not compressible, (ii) the second cache line is not compressible, or (iii) the second compressed cache line does not fit within the second predetermined portion of the candidate compressed cache line. The overflow pointer points to one of a plurality of overflow blocks depending on a compression ratio of the second cache line or a size of the second compressed cache line. Each overflow block of the plurality of overflow blocks is of a different size.

[0008] In some implementations, the method further includes receiving a read request for the first cache line or the second cache line, and in response to receiving the read request, retrieving data from one of the multiple overflow blocks in accordance with the overflow pointer in accordance with a determination that the overflow pointer is set.

[0009] In some implementations, the method further includes setting a first compression ratio control bit in the candidate compressed cache line in accordance with a determination that the first cache line is compressible; and, in accordance with a determination that the first cache line is not compressible, writing a first portion of the first cache line to the candidate compressed cache line and writing a remaining portion of the first cache line to an overflow block, resetting the first compression ratio control bit in the candidate compressed cache line, and setting an overflow pointer in the candidate compressed cache line to point to the overflow block.

[0010] In some implementations, the method further includes, in response to receiving a read request for the first cache line, retrieving the first cache line from the candidate compressed cache lines in accordance with a determination that the first compression ratio control bit is set; retrieving a first portion of the first cache line from the candidate compressed cache lines in accordance with a determination that the first compression ratio control bit is reset; and retrieving a second portion of the first cache line from the overflow block based on the overflow pointer.

[0011] In some implementations, the method further includes, in accordance with a determination that the first cache line is not compressible, writing either the second cache line or the second compressed cache line to the overflow block depending on whether the second cache line is compressible, and resetting a second compression ratio control bit in the candidate compressed cache line to indicate whether the second cache line is not compressible.

[0012] In some implementations, the method further includes, in response to receiving a read request for the second cache line, retrieving either the second cache line or the second compressed cache line from the overflow block based on the second compression ratio control bit.

[0013] In certain implementations, the method includes: in response to receiving a cache line write request for the first cache line, compressing the first cache line to obtain a first updated cache line of a first size; writing the first updated cache line to the candidate compressed cache line in accordance with a determination that the first size is less than or equal to a first predetermined size of the candidate compressed cache line; performing a read-modify-write operation on the candidate compressed cache line based on the first updated cache line in accordance with a determination that the first size is greater than the first predetermined size and less than or equal to a second predetermined size of the candidate compressed cache line; and performing the read-modify-write operation on the candidate compressed cache line based on the first updated cache line in accordance with a determination that the first size is greater than the second predetermined size of the candidate compressed cache line and performing a read-modify-write operation on an overflow block of the plurality of overflow blocks.

[0014] In some implementations, the first predetermined size is half the size of the candidate compressed cache line.

[0015] In some implementations, the method further includes, while writing either the second cache line or the second portion of the second compressed cache line to the second predetermined portion of the candidate compressed cache line, writing an end bit index within the candidate compressed cache line to indicate where within the candidate compressed cache line the second cache line or the second portion of the second compressed cache line was written, and calculating the second predetermined size based on the end bit index within the candidate compressed cache line.

[0016] In some implementations, the method further includes, in response to receiving a cache line write request for the second cache line, compressing the second cache line to obtain a second updated cache line of a second size; and, in accordance with a determination that a sum of the second size and a size of the first compressed cache line is less than a first predetermined size of the candidate compressed cache line, performing a read-modify-write operation to write the second updated cache line to the candidate compressed cache line; and, in accordance with a determination that the sum of the second size and the size of the first compressed cache line is greater than or equal to the first predetermined size of the candidate compressed cache line, (i) performing a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line and (ii) performing a second read-modify-write operation to write a remaining portion of the second updated cache line to an overflow block pointed to by the overflow pointer.

[0017] In some implementations, the method further includes, in response to receiving a cache line write request for the first cache line or the second cache line, compressing the first cache line or the second cache line to obtain an updated compressed cache line of the updated size, and, in accordance with a determination that the update size does not fit within the overflow block pointed to by the overflow pointer, releasing the overflow pointer and updating the overflow pointer to point to a new overflow block of one of the multiple overflow blocks.

[0018] In some implementations, the first compressed cache line, the second compressed cache line, and the candidate compressed cache line are equal in size.

[0019] In some implementations, the first data area and the second data area are of equal size.

[0020] In some implementations, the second predetermined portion is less than half the size of the candidate compressed cache line.

[0021] In some implementations, the first compressed cache line and the second compressed cache line are written in opposite directions to the candidate compressed cache line, the first compressed cache line and the second compressed cache line are separated by one or more bytes.

[0022] In another aspect, a compressed memory system for a processor-based system is provided. The compressed memory system includes a memory partitioning circuit configured to partition a memory region into a plurality of data regions. Each data region is associated with a respective priority level. The compressed memory system also includes a cache line selection circuit configured to (i) select a first cache line from a first data region of the plurality of data regions and (ii) select a second cache line from a second data region of the plurality of data regions. The first data region has a higher priority level than the second data region. The compressed memory system also includes a compression circuit configured to (i) compress the first cache line to obtain the first compressed cache line and (ii) compress the second cache line to obtain the second compressed cache line. The compressed memory system also includes a cache line packing circuit configured to (i) write the first compressed cache line to a first predetermined portion of a candidate compressed cache line and (ii) write either the second cache line or the second portion of the second compressed cache line to the second predetermined portion of the candidate compressed cache line according to a determination that the first cache line is compressible. The first predetermined portion is greater than the second predetermined portion.

[0023] In some implementations, the cache line packing circuitry is further configured to set an overflow pointer in the candidate compressed cache line according to a determination that (i) the first cache line is not compressible, (ii) the second cache line is not compressible, or (iii) the second compressed cache line does not fit within a second predetermined portion of the candidate compressed cache line. The overflow pointer points to one of a plurality of overflow blocks depending on a compressibility of the second cache line or a size of the second compressed cache line, where each overflow block of the plurality of overflow blocks is of a different size.

[0024] In some implementations, the cache line packing circuit is further configured to receive a read request for the first cache line or the second cache line, and in response to receiving the read request, retrieve data from one of the multiple overflow blocks in accordance with the overflow pointer in accordance with a determination that the overflow pointer is set.

[0025] In some implementations, the cache line packing circuitry is further configured to: set a first compression ratio control bit in the candidate compressed cache line in accordance with a determination that the first cache line is compressible; and, in accordance with a determination that the first cache line is not compressible, write a first portion of the first cache line to the candidate compressed cache line and write a remaining portion of the first cache line to an overflow block, reset the first compression ratio control bit in the candidate compressed cache line, and set an overflow pointer in the candidate compressed cache line to point to the overflow block.

[0026] In some implementations, the cache line packing circuit is further configured, in response to receiving a read request for the first cache line, to retrieve the first cache line from the candidate compressed cache lines in accordance with a determination that the first compression ratio control bit is set, to retrieve a first portion of the first cache line from the candidate compressed cache lines in accordance with a determination that the first compression ratio control bit is reset, and to retrieve a second portion of the first cache line from the overflow block based on the overflow pointer.

[0027] In some implementations, the cache line packing circuitry is further configured, in accordance with a determination that the first cache line is not compressible, to write either the second cache line or the second compressed cache line to the overflow block depending on whether the second cache line is compressible, and to reset a second compression ratio control bit in the candidate compressed cache line to indicate whether the second cache line is not compressible.

[0028] In some implementations, the cache line packing circuitry is further configured to, in response to receiving a read request for the second cache line, retrieve either the second cache line or the second compressed cache line from the overflow block based on the second compression ratio control bit.

[0029] In some implementations, the cache line packing circuitry is further configured to: in response to receiving a cache line write request for the first cache line, compress the first cache line to obtain a first updated cache line of a first size; write the first updated cache line to the candidate compressed cache line in accordance with a determination that the first size is less than or equal to a first predetermined size of the candidate compressed cache line; perform a read-modify-write operation on the candidate compressed cache line based on the first updated cache line in accordance with a determination that the first size is greater than the first predetermined size and less than or equal to a second predetermined size of the candidate compressed cache line; perform a read-modify-write operation on the candidate compressed cache line based on the first updated cache line in accordance with a determination that the first size is greater than the second predetermined size of the candidate compressed cache line; and perform a read-modify-write operation on one of the multiple overflow blocks.

[0030] In some implementations, the first predetermined size is half the size of the candidate compressed cache line.

[0031] In some implementations, the cache line packing circuitry is further configured to: while writing either the second cache line or the second portion of the second compressed cache line to the second predetermined portion of the candidate compressed cache line, write an end bit index within the candidate compressed cache line to indicate where within the candidate compressed cache line the second cache line or the second portion of the second compressed cache line was written, and calculate the second predetermined size based on the end bit index within the candidate compressed cache line.

[0032] In some implementations, the cache line packing circuitry is further configured to: in response to receiving a cache line write request for the second cache line, compress the second cache line to obtain a second updated cache line of the second size; in accordance with a determination that a sum of the second size and the size of the first compressed cache line is less than a first predetermined size of the candidate compressed cache line, perform a read-modify-write operation to write the second updated cache line to the candidate compressed cache line; and in accordance with a determination that the sum of the second size and the size of the first compressed cache line is greater than or equal to the first predetermined size of the candidate compressed cache line, (i) perform a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line, and (ii) perform a second read-modify-write operation to write a remaining portion of the second updated cache line to the overflow block pointed to by the overflow pointer.

[0033] In some implementations, the cache line packing circuit is further configured to: in response to receiving a cache line write request for the first cache line or the second cache line, compress the first cache line or the second cache line to obtain an updated compressed cache line of the updated size, and, according to a determination that the update size does not fit within the overflow block pointed to by the overflow pointer, release the overflow pointer and update the overflow pointer to point to a new overflow block of one of the multiple overflow blocks.

[0034] In some implementations, the first compressed cache line, the second compressed cache line, and the candidate compressed cache line are equal in size.

[0035] In some implementations, the first data area and the second data area are of equal size.

[0036] In some implementations, the second predetermined portion is less than half the size of the candidate compressed cache line.

[0037] In some implementations, the cache line packing circuitry is further configured to write the first compressed cache line and the second compressed cache line in opposite directions to the candidate compressed cache line, the first compressed cache line and the second compressed cache line being separated by one or more bytes.

[0038] In another aspect, a compressed memory system for a processor-based system is provided. The compressed memory system includes a memory region including a plurality of cache lines. Each cache line has one of a plurality of priority levels. The compressed memory system also includes a compressed memory region comprising a plurality of compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line having a first priority level or a portion of the first cache line after compression. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line having a second priority level lower than the first priority level or a portion of the second cache line after compression. The first set of data bits includes a greater number of bits than the second set of data bits.

[0039] In some implementations, the compressed memory system further includes an overflow memory area including a plurality of overflow bins, each overflow bin configured to hold a distinct number of bytes, and each compressed cache line further includes a set of overflow pointer bits configured to hold a pointer to an overflow bin of the plurality of overflow bins.

[0040] In some implementations, each compressed cache line further includes a first control bit for indicating a compression ratio of the first cache line and a second control bit for indicating a compression ratio of the second cache line.

[0041] In some implementations, the compressed memory system further includes an overflow memory area including a plurality of overflow bins, each overflow bin configured to hold a distinct number of bytes, and each compressed cache line further includes a set of bits configured to hold a size of an overflow bin of the plurality of overflow bins.

[0042] In some implementations, each compressed cache line further includes an end bit index that indicates the end of the second set of data bits.

[0043] In some implementations, each overflow bin is configured to hold bits of a first cache line and / or bits of a second cache line or a compressed second cache line in a first direction.

[0044] In some implementations, the first set of data bits is separated from the second set of data bits by one or more bytes.

[0045] In some implementations, each cache line and each compressed cache line is of the same size.

[0046] In some implementations, when the compressed first cache line or the compressed second cache line does not fit into the compressed cache line, each compressed cache line further includes a set of overflow pointer bits configured to hold a pointer to an overflow bin of the multiple overflow bins, wherein the overflow bin is configured to hold bits of the first cache line, the compressed first cache line, the second cache line, and / or the compressed second cache line.

[0047] In some implementations, the second set of data bits is further configured to hold a number of control bits that indicate overflow and end of the second set of data bits in the compressed cache line.

[0048] In another aspect, a non-transitory computer-readable medium is provided that stores computer-executable instructions that, when executed by a processor, cause the processor to perform any of the methods described herein.

[0049] Various embodiments of the systems, methods and devices within the scope of the appended claims each have several aspects, no single aspect of which is solely responsible for the attributes described herein. Without limiting the scope of the appended claims, after considering this disclosure, and in particular the section entitled "Detailed Description of the Invention," it will be understood how aspects of the various embodiments are used to enable higher throughput of storage for memory devices.

[0050] So that the present disclosure may be more particularly understood, a more particular description may be made by reference to the features of its various embodiments, some of which are illustrated in the accompanying drawings, which, however, are merely illustrative of the more pertinent features of the present disclosure and therefore should not be considered limiting, since the description may acknowledge other useful features. [Brief description of the drawings]

[0051] [Figure 1] FIG. 1 is a schematic diagram of an example system having a cache line compression / decompression hardware engine, according to some implementations. [Figure 2A] 2 is a schematic diagram of a compressed memory system 200 according to some implementations. [Figure 2B] 2B is a sequence diagram illustrating a method for reading a cache line using the compressed memory system shown in FIG. 2A according to some implementations. [Figure 2C] 2B is a sequence diagram illustrating a method for writing a cache line using the compressed memory system shown in FIG. 2A according to some implementations. [Diagram 3] 1 is a schematic diagram of a packing scheme for a compressed memory system, according to some implementations. [Figure 4] 1 illustrates an example compression line layout, according to some implementations. [Diagram 5] 1 illustrates an example compression line layout, according to some implementations. [Figure 6] 1 illustrates an example compression line layout, according to some implementations. [Figure 7] 1 illustrates an example compression line layout, according to some implementations. [Figure 8] 1 illustrates an example compression line layout, according to some implementations. [Figure 9] 1 illustrates an example compression line layout, according to some implementations. [Figure 10] 1 illustrates a flowchart of an exemplary method for reading a high priority cache line according to some implementations. [Figure 11] 1 illustrates a flowchart of an exemplary method for reading a low priority cache line according to some implementations. [Figure 12] 1 illustrates a flowchart of an example method for writing a high priority cache line according to some implementations. [Figure 13] 1 illustrates a flowchart of an example method for writing a low priority cache line according to some implementations. [Figure 14] 1 is a block diagram of an example compressed memory system for a processor-based system, according to some implementations.

[0052] According to common practice, the various features illustrated in the figures may not be drawn to scale. Thus, dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the figures may not depict all of the components of a given system, method or device. Finally, like reference numerals may be used to denote like features throughout the specification and figures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0053] Numerous details are described herein to provide a thorough understanding of the exemplary implementations shown in the accompanying drawings. However, some embodiments may be practiced without many of the specific details, and the claims are limited only by the features and aspects specifically recited in the claims. Moreover, well-known methods, components, and circuits have not been described in exhaustive detail so as not to unnecessarily obscure more pertinent aspects of the implementations described herein.

[0054] FIG. 1 is a schematic diagram of an exemplary system 100 having a cache line compression / decompression hardware engine 110 according to some implementations. The system 100 includes a chip 102 including a processor 104, a level 2 (L2) cache or L2 tightly coupled memory (TCM) 106, and the compression / decompression hardware engine 110. The processor 104 includes a memory management unit (MMU), a data cache, and an instruction cache. The data cache and the instruction cache constitute a level 1 (L1) cache. The L2 cache or L2 TCM 106 includes an L2 control and L2 cache tag or status module 108. The system also includes a memory controller 114 for accessing a primary external memory (e.g., double rate dynamic random access memory (DRAM), sometimes referred to as DDR). Although not shown in FIG. 1, some implementations may include conventional peripherals, other storage, an express peripheral component interconnect (PCI) interface, a direct memory access (DMA) controller, and / or an integrated memory controller (IMC). Some implementations may include two or more processors or processor blocks, and / or a shared level 3 (L3) cache for storing cache data used by either each of the processor blocks or shared between each of the processor blocks. Some implementations include an internal system bus that allows each of the processor blocks to access the shared L3 cache and / or other shared resources, including the memory controller 114. The processor-based system 100 is configured to store the cache data in an uncompressed format in cache entries in the cache memory.The cache entries may be cache lines. For example, the cache memory may be an L2 cache memory (e.g., L2 cache 106). The cache memory may be private to a processor core in processor 104 or may be shared among multiple processor cores. Processor-based system 100 includes a system memory 112 that includes a compressed data area configured to store data in a compressed format in memory entries (which may be memory lines). For example, system memory 112 may include a double data rate (DDR) static random access memory (SRAM). Processor 104 is configured to access system memory 112 during read and write operations to execute software instructions and perform other processor operations.

[0055] 2A is a schematic diagram of a compressed memory system 200 according to some implementations. The compressed memory system is configured to compress cache data from evicted cache entries in a cache memory and read metadata used to access physical addresses in a compressed system memory to write the compressed cache data. Providing the ability to store compressed data in a compressed data area (e.g., blocks 202, 204, 206) increases the memory capacity of the processor-based system 100 beyond the physical memory size of the system memory 112. In some implementations, the processor 104 uses virtual addressing. A virtual-to-physical address translation is performed to effectively address the compressed data area without awareness of the compression system and compressed size of the compressed data area. In this regard, the compressed memory system 200 is provided with a compression or decompression engine 212 to compress uncompressed data from the processor 104 to be written to the compressed data area and to decompress compressed data received from the compressed data area and provide it to the processor 104 in uncompressed form. The compression or decompression engine 212 may include a compression circuit configured to compress data from the processor 104 to be written to the compressed data area. For example, as shown in FIG. 1, the compression circuit may be configured to compress a 64-byte (64B) data word into a 48-byte (48B) compressed data word, a 32-byte (32B) compressed data word, or a 16-byte (16B) compressed data word, which may be stored in respective memory blocks 202 (64B), 204 (48B), 206 (32B), and 204 (16B), each of the memory blocks 202 having a size smaller than each of the entire memory entries of the system memory 112. If uncompressed data from the processor 104 cannot be compressed into the next smaller sized memory block 125 configured for the compressed memory system 102, such uncompressed data is stored uncompressed across the full width of one of the memory entries. For example, one of the memory entries may be 64B wide and therefore be capable of storing a 64B memory block, such as memory block 202 (64B).The compression or decompression engine 212 also includes a decompression circuit configured to decompress the compressed data from the compressed data domain provided to the processor 104 .

[0056] However, to provide faster memory access without requiring compression and decompression, a cache memory 214 (e.g., L2 cache 106) is provided. Cache entries in cache memory 214 are configured to store cache data in an uncompressed format. Each of the cache entries may be as wide as each of the memory entries to perform efficient memory read and write operations. The cache entries are accessed by their respective virtual address ("virtual address, VA") tags (e.g., tags stored in L2 cache tag 108). Because, as described above, compressed memory system 200 provides processor 104 with a more addressable memory space than the physical address space provided in the compressed data region. When processor 104 issues a memory read request for a memory read operation, the virtual address of the memory read request is used to search cache memory 214 to determine whether the virtual address matches one of the virtual address tags of the cache entries. If so, a cache hit occurs, and the cache data in the hit one of the cache entries is returned to processor 104 without the need to decompress the cache data. However, because the number of cache entries is less than the number of memory entries, a cache miss may occur in which the cache memory 214 does not contain the cached data for a memory read request.

[0057] Thus, with continued reference to FIG. 2A, in response to a cache miss, the cache memory 214 is configured to provide the virtual address of the memory read request to the compression circuit to retrieve data from the compressed data area. In this regard, the compression circuit may first consult a metadata cache that includes metadata cache entries that each include metadata indexed by a virtual address. The metadata cache is faster to access than the compressed data area. Metadata is data, such as a pointer, that is used to access a physical address (PA) in the compressed data area to access a memory entry that includes compressed data for the virtual address. If the metadata cache includes metadata for the memory read request, the compression circuit uses the metadata to access the correct one of the memory entries in the compressed data area to provide the corresponding compressed data area to the decompression circuit. If the metadata cache does not include metadata for the memory read request, the compression circuit provides the virtual address for the memory read request to the metadata circuit 210, which includes metadata in corresponding metadata entries for all virtual address spaces in the processor-based system 100. Thus, the metadata circuit 210 may be linearly addressed by the virtual address of the memory read request. The metadata is used to access the correct memory entries within the compressed data area for a memory read request in order to provide the corresponding compressed data area to the decompression circuitry.

[0058] 2, the decompression circuit receives the compressed data region in response to a memory read request. The decompression circuit decompresses the compressed data region into uncompressed data, which may then be provided to the processor 104. The uncompressed data is also stored in the cache memory 214. However, if the cache memory 214 does not have an available one of the cache entries, the cache memory 214 may evict one of the existing cache entries into the compressed data region to make room for storing the uncompressed data.

[0059] To do so, the cache memory 214 first sends the virtual address and the uncompressed cache data of the evicted cache entry to a compression circuit. The compression circuit receives the virtual address and the uncompressed cache data of the evicted cache entry. The compression circuit initiates a metadata read operation to the metadata cache to obtain the metadata associated with the virtual address. During, before, or after the metadata read operation, the compression circuit compresses the uncompressed cache data into compressed data that is stored in the compressed data area. If the metadata read operation to the metadata cache results in a cache miss, the metadata cache issues a metadata read operation to the metadata circuit 210 in the system memory 112 to obtain the metadata associated with the virtual address. The metadata cache is then stopped. Because access to the compressed data area may take much longer than the processor 104 can issue a memory access operation, the uncompressed data received from the processor 104 for a subsequent memory write request may be buffered in a memory request buffer.

[0060] After the metadata returns from the compressed data area and updates the metadata cache, the metadata cache provides the metadata as metadata to the compression circuit. The compression circuit determines whether the new compressed size of the compressed data area fits into the same memory block size in the compressed data area that was used to previously store the data for the virtual address of the evicted cache entry. For example, the processor 104 may have updated the cache data in the evicted cache entry since it was last stored in the compressed data area. If a new memory block is needed to store the compressed data area for the evicted cache entry, the compression circuit reuses a pointer to the current memory block in the compressed memory system 200 associated with the virtual address of the evicted cache entry into one of the free memory lists of pointers to available memory blocks in the compressed data area (e.g., list of free 64B blocks 216, list of free 48B blocks 218, list of free 32B blocks 220, and list of free 16B blocks 222). The compression circuit then obtains a pointer to a new available memory block of the desired memory block size in the compressed data area from one of the free memory lists for storing the compressed data area for the evicted cache entry. The compression circuit then stores the compressed data area for the evicted cache entry in a memory block in the compressed data area associated with the virtual address for the evicted cache entry determined from the metadata.

[0061] When a new memory block is allocated for the virtual address for the evicted cache entry, the metadata in the metadata cache entry of the metadata cache entry that corresponds to the virtual address tag of the evicted cache entry is updated based on a pointer to the new memory block. The metadata cache then updates the metadata in the metadata entry of the metadata entry that corresponds to the virtual address in the metadata cache based on the pointer to the new memory block 125.

[0062] Because the metadata of the metadata circuit 210 is stored in the system memory 112, the metadata circuit 210 may consume an excessive amount of the system memory 112 and thus adversely affect system performance. It is therefore desirable to minimize the amount of system memory 112 required to store the metadata while still providing effective data compression. In this regard, some implementations of the compressed memory system 200 reduce metadata size. The techniques described herein may be used

[0063] 2A illustrates uncompressed data linearly indexed through metadata according to some implementations. An uncompressed cache line is represented by 3 bytes of metadata, which points to compressed blocks (e.g., blocks 202, 204, and 206) having sizes 16, 32, 48, or 64 bytes. In some implementations, if the entire uncompressed line is 0, the metadata circuit 210 flags the entire uncompressed line without pointing to any compressed block. In some implementations, the compressed memory system 200 includes a register file 208 that holds base pointers for blocks 202, 204, and 206, and the metadata circuit 210 provides the offsets from the base pointers for the blocks.

[0064] FIG. 2B is a sequence diagram illustrating a method for reading a cache line using the compressed memory system shown in FIG. 2A according to some implementations. Following an L2 cache miss, a read address for an external memory is sent to the compression or decompression engine 212, which fetches the cached L2 metadata if it is available. If the metadata is not available in the cache, the metadata is read from the external memory (e.g., DDR). Based on the metadata, compressed data is fetched from the external memory from a block of the compressed data area. The compressed data is then decompressed by a decompression circuit, and the uncompressed data is returned to the processor. In this methodology, a 0 cache line (e.g., 64 bytes of 0) requires one read, and other cache lines require two reads, i.e., one read for the metadata and one read for the compressed block.

[0065] FIG. 2C is a sequence diagram illustrating a method for writing a cache line using the compressed memory system shown in FIG. 2A according to some implementations. Following an L2 cache miss, the uncompressed data is sent to the compression or decompression engine 212, and the compression circuit compresses the data to the new size. Similar to FIG. 2B, if the metadata is not available in the metadata cache, the metadata is retrieved from the external memory. If the metadata is available in the metadata cache, the metadata is retrieved from the metadata cache. A new index for the new size may be retrieved from a free list (e.g., one of lists 216, 218, 220, 222) depending on the size of the compressed data, and the compressed data is written to the compressed data area. In some circumstances, the old index can be reused and the metadata is updated in the external memory. In this methodology, for a cache line write, if the cache line is all zeros, the write requires one read-modify-write for the metadata, other cache lines require one read-modify-write for the metadata, and one write or one read-modify-write for the compressed data depending on the size of the compressed block.

[0066] FIG. 3 is a schematic diagram of a packing scheme 300 for a compressed memory system that helps to avoid extra reads and writes of metadata as described above, according to some implementations. FIG. 3 shows a memory region (e.g., compressed data candidates) divided into a high priority portion 302 and a low priority portion 304 having equal sizes. In practice, the memory region may be divided into any number of partitions having different priority levels and / or the partitions may have unequal amounts of data. One high priority cache line and one low priority cache line are selected and compressed to fit into a compressed cache line 306. If the compressed high and low cache lines do not fit into one compressed cache line, an overflow pointer is reserved in the compressed line that points to an overflow block (e.g., overflow bins 308, 310, or 312, each bin having a different size). To avoid read-modify-write, some implementations use multiple overflow blocks (e.g., overflow bin 310 holds 32 bytes of data, overflow bin 310 holds 64 bytes of data, and overflow bin 312 holds 96 bytes of data).To improve write performance of high priority lines, compressed low priority lines occupy only the bottom half of the compressed line.

[0067] 4-9 show exemplary compressed line layouts according to some implementations. These examples are provided for illustration and should not be construed to mean that the layout or organization is limited to only these examples. With reference to FIG. 4, a compressed line (CL) 400 may include: (i) HP 402 indicating compressed data for a high priority cache line; (ii) LP 404 indicating compressed data for a low priority cache line; (iii) HPC 406, a flag indicating whether the high priority cache line is compressed, e.g., 1 indicates compressed and 0 indicates not compressed; (iv) LPC 408, a flag indicating whether the low priority cache line is compressed, e.g., 1 indicates compressed and 0 indicates not compressed; and (v) OFB 410 indicating an overflow bin size. For example, 0 indicates 32 bytes, 1 indicates 64 bytes, 2 indicates 96 bytes, 3 indicates no overflow, (vi) OFP 412 indicating an overflow pointer index, and / or (vii) LPE 414 indicating a low priority end bit index indicating where the low priority compressed data ends. This information can be used to expand the high priority cache line on the write path. Values ​​may be between 11 and 255. 0 may mean there is no space left for the HP to expand. Implementations may use any number of these fields. In some implementations, high priority compression or decompression starts from the HPC bit towards the OFP, as indicated by arrow 416. In some implementations, low priority compression or decompression starts from the OFP towards where the LPE points (as indicated by arrow 418) and continues from right to left in the overflow area if it has an overflow (as indicated by arrow 420). According to some implementations, region 420 of the CL is not used by the CL and / or HP 402 and LP 404 are separated by a gap 422.In the example shown in Figure 4, 32 bytes are dedicated to HP, 32 bytes can be used by either HP / LP, and there are 31 control bits including OFP 412, LPE 414, OFB 410, and LPC 408. According to some implementations, depending on the HP and LP compressed sizes, as further described below with reference to Figures 5-10, the compressed lines may have slightly different layouts. For example, the number of control bits may be reduced (e.g., because there is no overflow and no need for OFP, those bits are consumed by LP instead).

[0068] 5 shows an example compressed line layout 500 when HP is less than 256 bits and low priority lines fit in CL, according to some implementations. According to some implementations, HPC is set to 1, OFB is set to 0x11, and LPC is set to 1. There are only 11 control bits (as opposed to 31 bits in FIG. 4).

[0069] 6 illustrates an example compressed line layout 600 when both HP and LP fit into one CL and HP is greater than 255 bits, according to some implementations. According to some implementations, HPC is set to 1, OFB is set to 0x11, and LPC is set to 1. In this example, HP extends into the lower half of the CL.

[0070] 7 shows an example compressed line layout 700 when HP is less than 256 bits and LP has an overflow, according to some implementations. According to some implementations, HPC is set to 1, OFB is any value between 0x0 and 0x2, LPC is set to either 1 or 0, and OFP points to overflow block 424.

[0071] 8 shows an example compressed line layout 800 when HP is greater than 255 bits but less than 480 bits and LP has an overflow, according to some implementations. According to some implementations, HPC is set to 1, OFB is set to a value between 0 and 2, LPC is either 1 or 0, and OFP points to overflow block 426.

[0072] 9 shows an example compressed line layout 900 when HP is equal to 512 (not compressible) and LP has overflow, according to some implementations. According to some implementations, HPC is set to 0, OFB is set to a value between 0 and 2, LPC is set to 0 or 1, and OFP points to overflow block 428. Overflow block 428 includes the remaining 32 bits of HP 430, gap 432, and LP 404.

[0073] Example read / write overhead and statistics For cache line reads, high and low priority cache lines that fit into one compressed cache line require one read, while other cache lines require two reads, one for the compressed line and one for the overflow block. For cache line writes, compressed high priority cache lines that fit into 255 bits require one write, compressed high priority cache lines that fit between 256 and 480 bits require one read-modify-write, other uncompressed high priority cache lines (>480 bits) require one read-modify-write to the compressed line and one read-modify-write to the overflow block, low priority cache lines that fit into a compressed line require one read-modify-write, and low priority cache lines that do not fit into a compressed line require one read-modify-write to the compressed line and one read-modify-write to the overflow block.

[0074] The following table shows exemplary cache line read / write costs and statistics for modem data (50017075 bytes of compression candidate data). [Table 1]

[0075] From the statistics, 84.7% of high priority cache lines require only 1 read / 1 write for the cache line read / write. An additional 11% of high priority cache lines above require 1 read / 1 read-modify-write for the cache line read / write. Only 4.3% of high priority cache lines require 2 reads / 2 read-modify-write for the cache line read / write. 78.6% of low priority cache lines require 1 read / 1 read-modify-write for the cache line read / write. 21.4% of low priority cache lines require 2 reads / 2 read-modify-write for the cache line read / write.

[0076] In Figures 10-13 described below, memory reads and writes are shown by patterns within rectangular boxes, and all other operations (except the initial block that receives a read or write request) are shown without patterns. Also, operations that are predicted to be likely are shown with solid lines (i.e., solid arrows indicate likely paths), and other paths are shown with dashed lines or arrows. The likelihood of a path is based on the data distribution of a particular data set (e.g., modem data).

[0077] 10 shows a flowchart of an example method 1000 for reading a high priority cache line according to some implementations. The method 1000 includes receiving a request for an HP read (1002) and reading the CL (1004). The method also includes determining whether the HPC is equal to 1 (1006). If the HPC is 1, the HP is decompressed. If the HPC is not 1, the overflow block pointed to by the OFP is read (1010) and 480 bits are copied from the compressed line (1012) and 32 bits are copied from the OFP block.

[0078] 11 shows a flowchart of an example method 1100 for reading a low priority cache line according to some implementations. The method 1100 includes receiving a request to read an LP (1102) and reading a CL (1104). The method also includes determining whether OFB is set to 3 (hexadecimal value 0x11) (1106). If OFB is set to 3, the LPE bits LP from the 11th bit are decompressed (1108). If OFB is not set to 3, the OFP is read (1110), the LPE bits from the 32nd bit of the CL are decompressed, and the bits from the overflow block pointed to by the OFP are added (1112).

[0079] FIG. 12 shows a flowchart of an exemplary method 1200 for writing a high priority cache line according to some implementations. The method includes receiving an HP write request (1202) and compressing the HP line into HPSZ bits (1204). The method also includes determining whether the HPSZ is less than 256 bits (1206). If the HPSZ is less than 256 bits, the HPC is set to 1 and 32 bytes of HP are written (1210). The path through blocks 1202, 1204, 1206, and 1210 forms a short path, leading to a fast write access for the high priority cache line. If the HPSZ is 256 bits or more, the CL is read (1208). It is then determined whether the HPSZ is less than 511-LPE (1212). If HPSZ is less than 511-LPE, CL is updated with HP (1214), HPC is set to 1, and CL is written (1216). If HPSZ is greater than or equal to 511-LPE, it is further determined whether OFP is set (or whether CL has OFP) (1218). If OFP is present, OFP is read (1220). If OFP is not present, LP contents are read and OFP is released (1222). It is further determined whether HP is compressible (1224) (1224). If HP is compressible, a new OFP block with a bit size greater than LPSZ-(480-HPSZ) is obtained (1232), the new OFP with LP is updated (1234), CL is filled with HP, and HPC is set to 1 (1236). If HP is not compressible, a new OFP block with a bit size greater than LPSZ+32 is obtained (1226), the 32-bit HP overflow is copied, the new OFP is updated with LP (1228), CL is filled with HP, and HPC is set to 0 (1230). Then, OFP is written (1238) and CL is written (1240).

[0080] FIG. 13 illustrates a flowchart of an exemplary method 1300 for writing a low priority cache line according to some implementations. The method 1300 includes receiving an LP write request (1302) and compressing the line to LPSZ bits and setting LPC to 1 (1304). The method also includes determining whether LPSZ is greater than 480 bits (1306). If LPSZ is greater than 480 bits, LPSZ is set to 512 (to indicate no compression) and LPS is set to 0 (1308). If LPSZ is not greater than 480 bits, the compressed line is read (1310). Further, it is determined whether HPC is set to 0 (1312). If HPC is set to 0, the OFP line is read (1314). Further, it is determined whether the current block is greater than LPSZ+32. If the current block is greater than LPSZ+32, the OFP is updated (1324). If the current block is not larger than LPSZ+32, a new OFP block with a bit size larger than LPSZ+32 is obtained (1318), 32 bits of HP are copied, the new OFP is updated (1320), and the old OFP is pushed to the free list (1322). Then, the OFP is written (1326), the compressed line is updated for the OFP, OFB, and LPC (1328), and the CL is written (1330). If the HPC is not equal to 0 (block 1312), it is further determined whether the OFP is not set to 0xFF (1332). If not, the OFL is freed (1334). If the OFP is set to 0xFF, the HP is decompressed to find the HP end bit (1336). It is further determined whether the HP is more than 32 bytes (1338). If so, the LPSPACE is set to the HP end bit minus 11. If not, LPSPACE is set to 256-11. In either case, it is further determined whether LPSZ is less than LPSPACE (1344). If LPSZ is less than LPSPACE, LP is packed into CL (1346), the compressed line is updated (1348) with OFP, LPC, and LPE set to 0x11), and CL is written (1350).If LPSZ is greater than or equal to LPSPACE, then an OFP block having a bit size greater than LPSZ-CL-20 is obtained (1352), LP is packed into OFP and LPSPACE (1354), CL is updated for (OFP, OFB, LPC, and LPE) (1356), CL is written (1358), and OFP is written (1360).

[0081] FIG. 14 is a block diagram of an exemplary compressed memory system 1400 for a processor-based system, according to some implementations. The system 1400 includes a memory divider circuit 1402 configured to divide a memory region into multiple data regions. Each data region is associated with a respective priority level. The memory regions include compressed data candidates and may include data and / or instructions. For example, a software image may be linked to different sections. Each section may have a different address range. The memory divider circuit 1402 may be configured to distinguish between different data regions based on the address range. In FIG. 3, a memory region is shown divided into a high priority aperture 302 and a low priority aperture 304, according to some implementations. Although only two apertures or priority levels are shown in FIG. 3, in some implementations, more than two apertures (sometimes referred to as data regions) and / or more than two priority levels may be used.

[0082] The compressed memory system 1400 also includes a cache line selection circuit 1404 configured to (i) select a first cache line from a first data region of the plurality of data regions, and (ii) select a second cache line from a second data region of the plurality of data regions. For example, an address of a cache line may be used by the cache line selection circuit 1404 to determine whether the cache line belongs to the first data region or the second data region. According to the determination, the cache line selection circuit 1404 may select the first cache line and the second cache line. The first data region has a higher priority level than the second data region. For example, in FIG. 3, a cache line from the high priority aperture 302 and a cache line from the low priority aperture 304 are selected to form a compressed cache line 306.

[0083] The compressed memory system also includes a compression circuit 1406 configured to (i) compress the first cache line to obtain a first compressed cache line and (ii) compress the second cache line to obtain a second compressed cache line. Examples of compression circuits are described above with reference to Figures 1, 2A, 2B, and 2C, according to some implementations.

[0084] The compressed memory system 1400 also includes a cache line packing circuit 1408 configured to, in accordance with a determination that the first cache line is compressible, (i) write the first compressed cache line to a first predetermined portion of the candidate compressed cache line, and (ii) write either the second cache line or the second portion of the second compressed cache line to a second predetermined portion of the candidate compressed cache line. The first predetermined portion is larger than the second predetermined portion. For example, FIG. 5 illustrates a high priority cache line being compressed and written to HP 402, which represents the first predetermined portion. FIG. 5 also illustrates a low priority cache line being compressed and written to LP 404, which is the second predetermined portion. In some implementations, the first and second predetermined portions may correspond to two separate portions of a compressed cache line. The first predetermined portion may be filled first with high priority compressed data, and the second predetermined portion may be filled next with low priority data. The high priority data may overflow into the second predetermined portion, but the low priority data may not overflow into the first predetermined portion. In some implementations, the second predetermined portion includes the control bits and the first predetermined portion does not. In some implementations, the compressed data is written in a different direction (e.g., toward the intersection of the two portions).

[0085] In some implementations, the cache line packing circuit 1408 is further configured to set an overflow pointer (e.g., OFP 412 of FIG. 4 ) in the candidate compressed cache line according to a determination that (i) the first cache line is not compressible, (ii) the second cache line is not compressible, or (iii) the second compressed cache line does not fit within the second predetermined portion of the candidate compressed cache line. The overflow pointer points to one of a plurality of overflow blocks (e.g., one of overflow bins 308, 310, or 312) depending on the compressibility of the second cache line or the size of the second compressed cache line. Each overflow block of the plurality of overflow blocks is of a different size. For example, the overflow bins 308, 310, and 312 hold data of different sizes. In some implementations, the cache line packing circuit 1408 is further configured to receive a read request for the first cache line or the second cache line, and in response to receiving the read request, retrieve data from one of the multiple overflow blocks according to the overflow pointer according to a determination that the overflow pointer is set. Examples of overflow blocks and overflow logic are described above with reference to Figures 3, 4, 7, 8, and 9 according to some implementations. Exemplary methods for reading are described above with reference to Figures 10 and 11 according to some implementations.

[0086] In some implementations, the cache line packing circuit 1408 is further configured to: set a first compression ratio control bit (e.g., HPC406) in the candidate compressed cache line according to a determination that the first cache line is compressible, and write a first portion of the first cache line to the candidate compressed cache line, write a remaining portion of the first cache line to an overflow block, reset the first compression ratio control bit in the candidate compressed cache line, and set an overflow pointer in the candidate compressed cache line to point to the overflow block according to a determination that the first cache line is not compressible. An example is described above with reference to FIG. 9, according to some implementations. In some implementations, the cache line packing circuit 1408 is further configured to, in response to receiving a read request for the first cache line, fetch the first cache line from the candidate compressed cache lines in accordance with a determination that the first compression ratio control bit is set, fetch a first portion of the first cache line from the candidate compressed cache line in accordance with a determination that the first compression ratio control bit is reset, and fetch a second portion of the first cache line from the overflow block based on the overflow pointer. In some implementations, the cache line packing circuit 1408 is further configured to, in response to a determination that the first cache line is not compressible, write either the second cache line or the second compressed cache line to the overflow block depending on whether the second cache line is compressible, and reset a second compression ratio control bit (e.g., LPC408) in the candidate compressed cache line to indicate whether the second cache line is not compressible. In some implementations, the cache line packing circuit 1408 is further configured to, in response to receiving a read request for the second cache line, retrieve either the second cache line or the second compressed cache line from the overflow block based on the second compression ratio control bit.Exemplary methods for reading high and low priority cache lines are described above with reference to Figures 10 and 11, respectively, according to some implementations.

[0087] In some implementations, the cache line packing circuit 1408 is further configured to: in response to receiving a cache line write request for the first cache line, compress the first cache line (e.g., using the compression circuit 1406) to obtain a first updated cache line of a first size; write the first updated cache line to the candidate compressed cache line in accordance with a determination that the first size is less than or equal to a first predetermined size of the candidate compressed cache line; perform a read-modify-write operation on the candidate compressed cache line based on the first updated cache line in accordance with a determination that the first size is greater than the first predetermined size and less than or equal to a second predetermined size of the candidate compressed cache line; perform a read-modify-write operation on the candidate compressed cache line based on the first updated cache line in accordance with a determination that the first size is greater than the second predetermined size of the candidate compressed cache line; and perform a read-modify-write operation on one of the overflow blocks of the multiple overflow blocks. In some implementations, the first predetermined size is half the size of the candidate compressed cache line. In some implementations, the cache line packing circuit 1408 is further configured to: while writing either the second cache line or the second portion of the second compressed cache line to the second predetermined portion of the candidate compressed cache line, write an end bit index (e.g., LPE 414) within the candidate compressed cache line to indicate where within the candidate compressed cache line the second cache line or the second portion of the second compressed cache line was written, and calculate the second predetermined size based on the end bit index within the candidate compressed cache line.

[0088] In some implementations, the cache line packing circuit 1408 is further configured to: in response to receiving a cache line write request for the second cache line, compress the second cache line to obtain a second updated cache line of a second size; in accordance with a determination that the sum of the second size and the size of the first compressed cache line is less than the first predetermined size of the candidate compressed cache line, perform a read-modify-write operation to write the second updated cache line to the candidate compressed cache line; in accordance with a determination that the sum of the second size and the size of the first compressed cache line is equal to or greater than the first predetermined size of the candidate compressed cache line, (i) perform a first read-modify-write operation to write a first portion of the second updated cache line to the candidate compressed cache line; and (ii) perform a second read-modify-write operation to write a remaining portion of the second updated cache line to the overflow block pointed to by the overflow pointer. For high priority cache lines, in some implementations, there is no control bit to indicate where the HP ends. In such cases, the system decompresses the HP portion to determine the information. In some implementations, this is not a true decompression, but rather a scan of the HP compressed bits to determine the end (the process is very similar to decompression). Some implementations reserve 8-9 bits to indicate the end of the HP, just like the LP side.

[0089] In some implementations, the cache line packing circuit 1408 is further configured to: in response to receiving a cache line write request for the first cache line or the second cache line, compress the first cache line or the second cache line to obtain an updated compressed cache line of the updated size, and according to a determination that the updated size does not fit within the overflow block pointed to by the overflow pointer, release the overflow pointer and update the overflow pointer to point to one new overflow block of the multiple overflow blocks. Examples of free list operations are described above with reference to Figures 12 and 13 according to some implementations.

[0090] In some implementations, the first compressed cache line, the second compressed cache line, and the candidate compressed cache line are of equal size. For example, in FIG. 3, each cache line from regions 302, 304, and compressed cache line 306 is 64 bytes.

[0091] In some implementations, the first data region and the second data region are of equal size. For example, in FIG. 3, regions 302 and 304 are of equal size (e.g., the regions have an equal number of cache lines).

[0092] In some implementations, the second predetermined portion is less than half the size of the candidate compressed cache line. Example layouts are described above with reference to Figures 4-9, according to some implementations.

[0093] In some implementations, the cache line packing circuit 1408 is further configured to write the first compressed cache line and the second compressed cache line in opposite directions to the candidate compressed cache line, the first compressed cache line and the second compressed cache line being separated by one or more bytes.

[0094] In another aspect, a compressed memory system for a processor-based system is provided. The compressed memory system includes a memory region including a plurality of cache lines. For example, FIG. 3 shows two memory regions 302 and 304. Each cache line has one of a plurality of priority levels. For example, the cache lines in region 302 have a higher priority than the cache lines in region 304. The compressed memory system also includes a compressed memory region (e.g., a region including compressed cache line 306) that comprises a plurality of compressed cache lines. Each compressed cache line includes a first set of data bits configured to hold, in a first direction, either a portion of a first cache line having a first priority level or a portion of the first cache line after compression. For example, the layout shown in FIG. 4 shows a compressed cache line including a HP 402 for storing bits of a high priority cache line according to some implementations. Each compressed cache line also includes a second set of data bits configured to hold, in a second direction opposite to the first direction, either a portion of a second cache line having a second priority level lower than the first priority level or a portion of the second cache line after compression. For example, the layout shown in Figure 4 illustrates a compressed cache line including an LP 404 for storing bits for a low priority cache line, according to some implementations. A first set of data bits includes a greater number of bits than a second set of data bits. HP 402 stores the compressed bits in a direction opposite to that of LP 404. The layout of Figure 4 illustrates that bits of a high priority cache line may occupy HP 402 and region 420, while bits of a low priority cache line may only occupy LP 404, which is smaller in size than HP 402.

[0095] In some implementations, the compressed memory system further includes an overflow memory area including a plurality of overflow bins (e.g., overflow block 426). Each overflow bin is configured to hold a distinct number of bytes. For example, overflow blocks 308, 310, and 312 each include a different number of bytes. Each compressed cache line further includes a set of overflow pointer bits (e.g., OFP 412) configured to hold a pointer to one of the plurality of overflow bins.

[0096] In some implementations, each compressed cache line further includes a first control bit (e.g., HPC406) for indicating a compression ratio of the first cache line and a second control bit (e.g., LPC408) for indicating a compression ratio of the second cache line.

[0097] In some implementations, the compressed memory system further includes an overflow memory area including a plurality of overflow bins, each overflow bin configured to hold a distinct number of bytes, and each compressed cache line further includes a set of bits (e.g., OFB 410) configured to hold a size of one of the plurality of overflow bins.

[0098] In some implementations, each compressed cache line further includes an end bit index (e.g., LPE414) that indicates the end of the second set of data bits.

[0099] In some implementations, each overflow bin is configured to hold bits of a first cache line and / or bits of a second cache line or a compressed second cache line in a first orientation. For example, as shown in FIG. 4, overflow bin 420 holds bits in the same orientation as HP 402.

[0100] In some implementations, the first set of data bits is separated from the second set of data bits by one or more bytes. For example, in FIG. 4, HP 402 and LP 404 are separated by gap 422.

[0101] In some implementations, each cache line and each compressed cache line is of the same size. For example, in Figure 3, each cache line 302 and 304 and each compressed cache line 306 includes 64 bytes.

[0102] In some implementations, when the first cache line after compression or the second cache line after compression does not fit into the compressed cache line, each compressed cache line further includes a set of overflow pointer bits configured to hold a pointer to one of the overflow bins of the multiple overflow bins. The overflow bin is configured to hold bits of the first cache line, the first cache line after compression, the second cache line, and / or the second cache line after compression. In other words, as shown in Figures 5 and 6, OFP 412 is optional and is used only when there is an overflow. If both cache lines after compression fit into the compressed cache line, the OFP bit is not used.

[0103] In some implementations, the second set of data bits is further configured to hold a number of control bits indicating overflow (e.g., OFP 412, OFB 410) and end (e.g., LPE 414) of the second set of data bits within the compressed cache line.

[0104] It will be understood that although terms such as "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another.

[0105] The terms used herein are intended to describe particular embodiments only and are not intended to limit the scope of the claims. The singular forms "a," "an," and "the," as used in the description of the embodiments and the appended claims, are intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the term "and / or," as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will also be understood that the terms "comprises" and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0106] As used herein, the term "if" may be interpreted to mean "when" or "upon" or "in response to determining that" or "in accordance with a determination that" or "in response to detecting that" a stated antecedent condition is true, depending on the context. Similarly, the phrase "if it is determined that [the stated antecedent condition is true]" or "if [the stated antecedent condition is true]" or "when [the stated antecedent condition is true]" may be interpreted to mean "upon determining that" or "in response to determining that" or "in accordance with a determination that" or "in response to detecting that" a stated antecedent condition is true, depending on the context.

[0107] The foregoing description has been described with reference to specific implementations for purposes of explanation. However, the above exemplary discussion is not intended to be exhaustive or to limit the scope of the claims to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The implementations have been selected and described to best explain the principles of operation and practical applications, thereby enabling others skilled in the art.

Claims

1. 1. A compressed memory system for a processor-based system, comprising: a memory region comprising a plurality of cache lines, each cache line having one of a plurality of priority levels; A compressed memory region comprising a plurality of compressed cache lines, each compressed cache line comprising: a first set of data bits configured to hold, in a first direction, either a portion of a first cache line or a portion of the first cache line after compression, the first cache line having a first priority level; a second set of data bits configured to hold either a portion of a second cache line or a portion of the second cache line after compression in a second direction opposite to the first direction, the second cache line having a second priority level lower than the first priority level, and the first set of data bits including a greater number of bits than the second set of data bits; a compressed memory area comprising: A compressed memory system comprising:

2. an overflow memory area including a plurality of overflow bins, each overflow bin configured to hold a distinct number of bytes; Each compressed cache line a set of overflow pointer bits configured to hold a pointer to an overflow bin of the plurality of overflow bins; 2. The compressed memory system of claim 1.

3. Each compressed cache line a first control bit for indicating a compression ratio of the first cache line; a second control bit for indicating a compression ratio of the second cache line; 2. The compressed memory system of claim 1 further comprising:

4. an overflow memory area including a plurality of overflow bins, each overflow bin configured to hold a distinct number of bytes; Each compressed cache line a set of bits configured to hold a size of an overflow bin of the plurality of overflow bins; 2. The compressed memory system of claim 1.

5. 2. The compressed memory system of claim 1, wherein each compressed cache line further comprises an end bit index indicating an end of said second set of data bits.

6. 3. The compressed memory system of claim 2, wherein each overflow bin is configured to hold bits of the first cache line and / or bits of the second cache line or the second cache line after compression in the first direction.

7. 2. The compressed memory system of claim 1, wherein said first set of data bits is separated from said second set of data bits by one or more bytes.

8. 2. The compressed memory system of claim 1, wherein each cache line and each compressed cache line is of the same size.

9. 2. The compressed memory system of claim 1, wherein each compressed cache line further comprises a set of overflow pointer bits configured to hold a pointer to an overflow bin of the plurality of overflow bins when the first cache line after compression or the second cache line after compression does not fit into the compressed cache line, the overflow bins configured to hold bits of the first cache line, the first cache line after compression, the second cache line, and / or the second cache line after compression.

10. 2. The compressed memory system of claim 1, wherein the second set of data bits is further configured to hold a plurality of control bits indicating overflow and end of the second set of data bits in a compressed cache line.

Images