Channel Crosstalk Cancellation Technique for Audio Ground Switches

Abstract

An aspect of the disclosure relates to an apparatus including an audio interface including first and second outputs; a crosstalk cancellation circuit including first and second inputs respectively coupled to the first and second outputs of the audio interface; a first summer including a first input coupled to the first output of the audio interface and a second input coupled to the first output of the crosstalk cancellation circuit; a second summer including a first input coupled to the second output of the audio interface and a second input coupled to the second output of the crosstalk cancellation circuit; a first digital-to-analog converter (DAC) including an input coupled to the output of the first summer; and a second DAC including an input coupled to the output of the second summer.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS)

[0001] This patent application claims priority to pending U.S. non-provisional application No. 17 / 580,505, filed on January 20, 2022, and assigned to the assignee of this patent application, which is expressly incorporated by reference into this specification as if fully set forth below and for all applicable purposes.

[0002] Aspects of the present disclosure relate generally to audio signal processing, and more particularly to channel crosstalk cancellation techniques for audio ground switches. [Background technology]

[0003]

[0003] Audio over Universal Serial Bus (USB), Type C (referred to herein as "USB-C") is becoming popular, especially in small form factor devices such as smartphones, tablet devices, and smart watches. USB-C connectors or ports are popular because they can be used for multiple purposes, such as sending analog or digital audio to headphones or speakers, sending and receiving USB data from USB devices, controlling battery chargers, sending multimedia data (e.g., DisplayPort data), and other functions. Additionally, providing audio over USB-C in small form factor devices allows these devices to eliminate the 3.5 millimeter (mm) jack typically used to send analog audio to headphones or speakers. Summary of the Invention

[0004]

[0004] Below, a simplified summary of one or more implementations is presented to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations, and is not intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the "Description of the Preferred Embodiments" presented later.

[0005]

[0005] An aspect of the present disclosure relates to an apparatus including an audio interface including a first and a second output, a crosstalk cancellation circuit including a first and a second input coupled to the first and the second output of the audio interface, respectively, a first adder including a first input coupled to the first output of the audio interface and a second input coupled to the first output of the crosstalk cancellation circuit, a second adder including a first input coupled to the second output of the audio interface and a second input coupled to the second output of the crosstalk cancellation circuit, a first digital-to-analog converter (DAC) including an input coupled to the output of the first adder, and a second DAC including an input coupled to the output of the second adder.

[0006] Another aspect of the present disclosure relates to a method, the method including generating first and second channel digital audio signals, processing the first and second channel digital audio signals to generate first and second crosstalk compensated digital audio signals, converting the first and second crosstalk compensated digital audio signals to first and second analog audio signals, respectively, and providing the first and second analog audio signals to first and second speakers, respectively, having a common terminal coupled to ground via a ground switch.

[0007] Another aspect of the present disclosure relates to an apparatus including means for generating first and second channel digital audio signals, means for processing the first and second channel digital audio signals to generate first and second crosstalk compensated digital audio signals, means for converting the first and second crosstalk compensated digital audio signals to first and second analog audio signals, respectively, and means for providing the first and second analog audio signals to first and second speakers, respectively, having a common terminal coupled to ground via a ground switch.

[0008]

[0008] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes at least one antenna, a transceiver coupled to the at least one antenna, one or more signal processing cores coupled to the transceiver, an audio interface including a first and a second output, the audio interface being coupled to the one or more signal processing cores, a crosstalk cancellation circuit including a first and a second input respectively coupled to the first and second output of the audio interface, a first adder including a first input coupled to the first output of the audio interface and a first output of the crosstalk cancellation circuit, a second adder including a second input coupled to the second output of the audio interface and a second output of the crosstalk cancellation circuit, a first digital-to-analog converter (DAC) including an input coupled to the output of the first adder, and a second DAC including an input coupled to the output of the second adder.

[0009]

[0009] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0010] [Figure 1A] 1 shows a block / schematic diagram of an exemplary Universal Serial Bus (USB) interface circuit according to an aspect of the present disclosure. [Figure 1B]

[0011] 1 illustrates a pin diagram of an exemplary Universal Serial Bus (USB) Type-C (USB-C) connector, according to another aspect of the disclosure. [Diagram 2]

[0012] 2 shows a block diagram of an exemplary channel crosstalk cancellation system according to another aspect of the present disclosure. [Diagram 3]

[0013] 2 shows a block diagram of an example channel crosstalk canceller according to another aspect of the present disclosure. [Figure 4]

[0014] 1 shows a block / schematic diagram of another exemplary Universal Serial Bus (USB) interface circuit according to another aspect of the disclosure. [Diagram 5]

[0015] 1 illustrates a flow diagram of an exemplary method for reducing channel crosstalk due to a common ground switch according to another aspect of the disclosure. [Figure 6]

[0016] 1 illustrates a block diagram of an exemplary wireless communication device according to another aspect of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0017] The detailed description of the present invention, described below in connection with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description of the present invention includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to one skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0012]

[0018] 1A illustrates a block / schematic diagram of an exemplary Universal Serial Bus (USB) interface circuit 100 according to an embodiment of the disclosure. The USB interface circuit 100 is configured to provide analog audio to a pair of stereo right speaker 180-R and stereo left speaker 180-L (e.g., headphones) via a USB connector 170. As used herein, the subscripts -R and -L refer to the right and left audio channels, respectively. When the USB connector 170 is implemented as a USB-C connector, the provision of analog audio to speakers 180-R and 180-L may be referred to as audio over USB-C mode or audio accessory mode.

[0013]

[0019] USB interface circuit 100 may also be optionally configured to transmit and / or receive other information to and from an external device connected to USB connector 170. For example, USB interface 100 may transmit and / or receive USB application data signals to and from an external USB device. USB interface 100 may transmit and / or receive battery charging data signals to and from an external battery charger.

[0014]

[0020] The USB interface circuit 100 includes an audio interface (INTF) 112, stereo digital-to-analog converters (DACs) 114-R and 114-L, a channel crosstalk (x-talk) canceller 115, and an off-chip inductor L R and L L Stereo amplifiers 116-R and 116-L including a stereo switching element SW R and SW L The audio interface 112 may include an integrated circuit (IC) 110 (depicted by a dashed bounding box) including a DAC 114-R and a DAC 114-L. The audio interface 112 includes an input configured to receive an audio stream, for example, from a processor and / or memory device of a host device (e.g., a wireless communication device, a smartphone, a tablet device, a laptop, a desktop, or other device). The audio interface 112 may output a stereo digital audio signal D at a stereo output coupled to an input of the stereo DACs 114-R and 114-L, respectively, based on the audio stream. R and D. L Generate.

[0015]

[0021] The stereo DACs 114-R and 114-L each output a stereo digital audio signal D R and D. L , at its output coupled to the input of the channel crosstalk canceller 115, into a stereo analog audio signal V R and V L As described in more detail herein, the channel crosstalk canceller 115 converts the stereo analog audio signal V R and V L to obtain a crosstalk-compensated stereo analog audio signal V RX and V LX The off-chip inductor L R and L L The stereo audio amplifiers 116-R and 116-L each include a stereo analog audio signal VRX and V LX Amplified and stereo switching element SW R and SW L At a first terminal, an amplified stereo analog audio signal V AR and V AL Generate.

[0016]

[0022] IC110 is a switching element SW P and SW N "P" represents the positive side of the USB differential data DP, and "N" represents the negative side of the USB differential data. P and SW N Each of the switching elements SW may be implemented as a single-pole double-throw (SPDT) switch with an optional floating configuration. P and SW N are stereo switching element SW R and SW L (and pins of IC110, represented as solid circles at the dashed border of IC110). P and SW N each includes a first throw coupled to the positive data port DP of the application processor 140 and the charger circuit 150. P and SW N each include a second throw coupled to the negative data port DN of the application processor 140 and the charger circuit 150.

[0017]

[0023] As an exemplary operation, an analog audio signal V AR and V AL is sent to speakers 180-R and 180-L, the configuration controller 195 controls the stereo switching element SW R and SW L Switching element SW P and SW N In this configuration, the analog audio signal V AR and V ALare closed stereo switching elements SW R and SW L , via overvoltage (OVP) switches 160-N and 160-P (eg, field effect transistors (FETs)) to speakers 180-R and 180-L.

[0018]

[0024] When a USB application data signal is transmitted between application processor 140 and a USB device connected to USB connector 170, configuration controller 195 controls stereo switching element SW R and SW L to the open state, and the switching element SW P and SW N , respectively, such that their poles are connected to their first throws. In this configuration, the USB application data signals DP and DN are each selectively set to the first throw of the switching element SW P and SW N , may be transmitted between application processor 140 and the USB device via OVP switches 160-N and 160-P and USB connector 170. When a battery charging data signal is transmitted between battery charger circuit 150 and a battery charger connected to USB connector 170, configuration controller 195 switches stereo switching element SW R and SW L to the open state, and the switching element SW P and SW N , respectively, are selectively set to have their poles connected to their second throws. In this configuration, the battery charging data signals DP and DN are respectively connected to the switching elements SW P and SW N , transmitted between the battery charger circuit 150 and the battery charger via OVP switches 160-N and 160-P and USB connector 170.

[0019]

[0025] The IC 110 further includes an overvoltage protection (OVP) circuit 130, a cross-coupling switching element 118, a microphone bias (MB) circuit 124, a microphone amplifier 120, and a microphone analog-to-digital converter (ADC) 122. The OVP circuit 130 is configured to control off-chip switches 160-N, 160-P, 162-1, 162-2, 164-1, and 164-2 (e.g., implemented as FETs) via a set of IC pins for the purpose of protecting the IC 110 from an external overvoltage through the USB connector 170. That is, when the OVP circuit 130 detects an overvoltage through the USB connector 170, the OVP circuit 130 may turn off the corresponding FETs 160-N, 160-P, 162-1, 162-2, 164-1, and 164-2 to prevent the overvoltage from propagating to the IC 110 and damaging the IC 110. In normal operation, FETs 160-N, 160-P, 162-1, 162-2, 164-1, and 164-2 are turned on.

[0020]

[0026] The cross-coupling switching element 118 includes an "input" terminal coupled to the OVP FETs 162-1 and 162-2, respectively. The cross-coupling switching element 118 includes an "output" terminal coupled to ground and an "output" terminal coupled to an off-chip inductor L M The MB circuit 124 includes an IC pin coupled to an off-chip resistor R M The microphone amplifier 120 is coupled to an off-chip inductor L through another IC pin. M and resistor R M The microphone amplifier 120 includes an input coupled to an input of the ADC 122. The ADC 122 includes an output coupled to an input of the audio interface 112.

[0021]

[0027] For microphone audio processing, analog audio signals generated by microphones (e.g., integrated microphones in headphones) that may be associated with speakers 180-R and 180-L are received via OVP FETs 162-1 or 162-2 and coupled to off-chip inductors L through cross-coupling switching element 118. M The inductor L M and resistor R M The ADC 122 converts the microphone audio signal to a digital audio signal. The audio interface 112 converts the digital audio signal to an audio stream and sends the audio stream to a processor and / or memory of the host device. The ADC 122 converts the microphone audio signal to a digital audio signal. The ADC 122 converts the microphone audio signal to a digital audio signal. The audio interface 112 converts the digital audio signal to an audio stream and sends the audio stream to a processor and / or memory of the host device. The audio interface 112 converts the digital audio signal to a digital audio stream ... and sends the audio stream to a processor and / or memory of the host device.

[0022]

[0028] For purposes of crosstalk cancellation, IC 110 includes a crosstalk (x-talk) sensor 128 that includes an input coupled to OVP FETs 164-1 and 164-2 and an output that generates a crosstalk sense signal and is coupled to an input of crosstalk canceller 115.

[0023]

[0029] The USB connector 170 includes a negative differential data pin DN that is coupled to the OVP FET 160-N and to a first "1" terminal of the right speaker 180-R when a speaker is connected to the USB connector 170. The USB connector 170 includes a positive differential data pin DP that is coupled to the OVP FET 160-P and to a first "1" terminal of the left speaker 180-L when a speaker is connected to the USB connector 170. As mentioned above, the USB connector 170 includes an SBU1 pin that may be coupled to the OVP FET 162-1 and to a common (coupled together) second "2" terminal of the right speaker 180-R and the left speaker 180-L, or to a microphone (not shown) associated with the speakers 180-R and 180-L when the speaker connection to the USB connector 170 is in a first orientation. Also, as described above, USB connector 170 includes an SBU2 pin that may be coupled to OVP FET 162-2 and to the microphone or a common second terminal of right speaker 180-R and left speaker 180-L when the speaker connection to USB connector 170 is in the second (inverted) orientation.

[0024]

[0030] 1B illustrates a pin diagram of an exemplary female USB-C connector that may be used as the USB connector 170 of the USB interface circuit 100 according to another embodiment of the disclosure. The USB-C connector 170 is a rotationally symmetric connector. That is, the corresponding male USB connectors associated with the speakers 180-R and 180-L and the microphone (or other USB device) may be plugged into the female USB connector 170 in a first orientation or a second (flipped) orientation, and signal functionality should not be affected.

[0025]

[0031] For example, the USB-C connector 170 has a top row of pins labeled A1 through A12 from left to right, with the pins designated as ground return (GND), first transmit differential positive (TX1+), first transmit differential negative (TX1-), bus power (VBUS), first configuration channel (CC1), positive differential data (DP or D+), negative differential data (DP or D-), first sideband use (SBU1), bus power (VBUS), second receive differential negative (RX2-), second receive differential positive (RX2+), and ground return (GND). Similarly, the USB-C connector 170 has a bottom row of pins labeled B1 through B12 from right to left, with the pins designated as ground return (GND), second transmit differential positive (TX2+), second transmit differential negative (TX2-), bus power (VBUS), second configuration channel (CC2), positive differential data (DP or D+), negative differential data (DP or D-), second sideband usage (SBU2), bus power (VBUS), first receive differential negative (RX1-), first receive differential positive (RX1+), and ground return (GND). Thus, pins A1-A12 substantially correspond to pins B1-B12, respectively, with some differences in that some of pins A1-A12 are designated with the suffixes "1" and "2" (CC1, SBU1, TX1+ / TX1-, and RX2+ / RX2-) and some of pins B1-B12 are also designated with the suffixes "2" and "1" (CC2, SBU2, TX2+ / TX2-, and RX1+ / RX1-).

[0026]

[0032] Thus, for the positive differential data pin DP and the negative differential data pin DN, the first terminals of the speakers 180-R and 180-L may contact the DP and DN pins, respectively, regardless of whether the speaker male connector is plugged into the USB-C connector 170 in a first orientation or a second (flipped) orientation. For the SBU1 and SBU2 pins, in the first configuration, the common second terminal of the speakers 180-R and 180-L may contact the SBU1 (A8) pin and the associated microphone may contact the SBU2 (B8) pin. In the second (flipped) orientation, the common second terminal of the speakers 180-R and 180-L may contact the SBU2 (B8) pin and the associated microphone may contact the SBU1 (A8) pin.

[0027]

[0033] The configuration controller 195 may detect the orientation (first or second) in which the speaker connector is plugged into the USB-C connector 170 and may configure the cross-coupling switching element 118, as well as the crosstalk sensor 128, accordingly. For example, if the controller 195 detects a first orientation, the controller 195 may couple the SBU1 pin (speaker common terminal) to ground via OVP FET 162-1 and the SBU2 pin (microphone) to the microphone audio processing circuit (e.g., inductor L) via OVP FET 162-2. M , resistor R M , microphone bias circuit 124, microphone amplifier 120, and ADC 122. When controller 195 detects the second (inverted) orientation, controller 195 couples SBU2 pin (speaker common terminal) to ground through OVP FET 162-2 and SBU1 pin (microphone) to microphone audio processing circuitry (e.g., inductor L M , resistor R M , microphone bias circuit 124, microphone amplifier 120, and ADC 122.

[0028]

[0034] As previously described, when the USB interface circuit 100 is configured to send analog audio to the speakers 180-R and 180-L, the configuration controller 195 controls the stereo switching element SW R and SW L Close the stereo audio signal V AR and V AL to right speaker 180-R and left speaker 180-L via FETs 160-N and 160-P, respectively. The speaker return signal is sent to ground via OVP FETs 162-1 or 162-2 (e.g., sometimes referred to herein as ground switches) to which the common terminals of speakers 180-R and 180-L are connected. Ground switches 162-1 and 162-2 each have a finite turn-on resistance R ON As described further herein, the turn-on resistance R ON generates linear and non-linear crosstalk between the right speaker 180-R and the left speaker 180-L.

[0029]

[0035] For example, the stereo audio signal current I passing through the right speaker 180-R and the left speaker 180-L is R and I L are summed at a common second terminal and flow through the ground switch 162-1 or 162-2. Thus, the voltage across the ground FET 162-1 or 162-2 is (I L +I R )*R ON The voltage at the first terminal of the right speaker 180-R and the voltage at the first terminal of the left speaker 180-L are substantially equal to V AR and V AL (Switching element SW R and SW L (Assume there is no IR loss between the first terminal of the right speaker 180-R and the first terminal of the left speaker 180-L.) Therefore, the voltage drop ΔV R and ΔV L becomes:

[0030]

number

[0031] In addition, the voltage drop ΔV between both ends of the right speaker 180-R and the left speaker 180-L R and ΔV L are the crosstalk components I L *R ON and I R *R ON That is, according to Equation 1, the voltage drop ΔV across the right speaker 180-R is R is the current I flowing through the left speaker 180-L. L Similarly, according to Equation 2, the voltage drop ΔV across the left speaker 180-L is L is the current I flowing through the right speaker 180-R. R Such a crosstalk component I L *R ON and I R *R ON affects the accuracy and fidelity of the sound produced by speakers 180-R and 180-L and may be eliminated or reduced to improve the accuracy and fidelity of the sound.

[0032]

[0036] In this regard, configuration controller 195 configures crosstalk sensor 128 during a calibration procedure to sense current through “replica ground” FETs 164-1 or 164-2 that are coupled to the common second terminals of speakers 180-R and 180-L. During the calibration procedure, FETs 162-1 and 162-2 may be turned off such that all return current from speakers 180-R and 180-L flows to crosstalk sensor 128. During the first stage of the calibration procedure, voltage V AL is set to zero (0) volts (V), and the voltage V AR is the known voltage V CAL The crosstalk sensor 128 then calculates the sensed current I SNS1 Then, during the second stage of the calibration procedure, the voltage V AR is set to 0V, and the voltage V AL is the known voltage V CALThe crosstalk sensor 128 then calculates the sensed current I SNS2 The crosstalk sensor 128 measures the sensed current I SNS1 and I SNS2 and providing the crosstalk detection signal to the crosstalk canceller 115.

[0033]

[0037] The crosstalk canceller 115 detects the current I SNS1 and I SNS2 Based on this, the resistance R of the right speaker and the left speaker R and R L The crosstalk canceller 115 may then calculate the crosstalk component I L *R ON and I R *R ON , R L / R ON and R R / R ON or some other formula (e.g., R L | / (R R ||R ON ) and R R / (R L ||R ON ), where || denotes a parallel resistance. The crosstalk canceller 115 may estimate the crosstalk component est(I L *R ON ) and est(I R *R ON ) to stereo analog signal V R and V L Thus, with crosstalk compensation, the voltage across speakers 180-R and 180-L can be expressed as:

[0034]

number

[0035] Therefore, according to Equation 3 and Equation 4, the voltage ΔV across the speakers 180-R and 180-L isR and ΔV L has substantially no crosstalk components due to the crosstalk compensation provided by the crosstalk canceller 115.

[0036]

[0038] The crosstalk cancellation approach in the USB interface circuit 100 has several disadvantages. First, additional FETs 164-1 and 164-2 are required to perform crosstalk sensing for cancellation purposes. Second, the additional FETs 164-1 and 164-2 need to be wired to the SBU1 and SBU2 pins of the USB connector 170, which may require printed circuit board (PCB) routing and star connections to the USB connector 170. Third, the IC 110 requires additional pins to couple the crosstalk sensor 128 to the FETs 164-1 and 164-2. Thus, the crosstalk cancellation approach in the USB interface circuit 100 is complex, increasing the wiring, routing, PCB and IC pin complexity, product cost, build of material (BOM) cost, reliability issues, and other adverse issues.

[0037]

[0039] 2 shows a block diagram of an exemplary stereo crosstalk cancellation system 200 according to another aspect of the present disclosure. The crosstalk cancellation system 200 can replace the audio interface 112, the DACs 114-R and 114-L, the crosstalk canceller 115, the audio amplifiers 116-R and 116-L, and the crosstalk sensor 128 of the USB interface circuit 100. In addition, the stereo crosstalk cancellation system 200 does not require additional off-chip FETs 164-1 and 164-2, and associated IC pins, PCB traces, and star connections to the USB connector 170. Thus, the disadvantages of using the FETs 164-1 and 164-2 described above are eliminated using the crosstalk cancellation system 200.

[0038]

[0040] In particular, stereo crosstalk cancellation system 200 includes an audio interface (INTF) 202, optional stereo interpolators 204-R and 204-L, a channel crosstalk (x-talk) canceller 206, stereo summers 208-R and 208-L, stereo digital-to-analog converters (DACs) 210-R and 210-L, stereo amplifiers 212-R and 212-L (including off-chip inductors that are not shown in this figure for simplicity), and a speaker resistance detector 220.

[0039]

[0041] Audio interface 202 includes an input configured to receive an audio stream, for example from a processor and / or memory device of a host device (e.g., a wireless communication device, a smartphone, a tablet device, a laptop, a desktop, or other device). Audio interface 202 outputs a stereo digital audio signal D based on the audio stream at a stereo output coupled to an input of optional stereo interpolators 204-R and 204-L, respectively. R1 and D. L1 The stereo interpolators 204-R and 204-L each generate a stereo digital audio signal D R1 and D. L1 to produce an upsampled stereo digital audio signal D at an output coupled to the stereo input of the crosstalk canceller 206 and to the inputs of the stereo summers 208-R and 208-L. R2 and D. L2 As mentioned above, the interpolators 204-R and 204-L are optional and the stereo outputs of the audio interface 202 may be coupled directly to the stereo inputs of the crosstalk canceller 206 and to the inputs of the stereo summers 208-R and 208-L, respectively.

[0040]

[0042] As described in more detail herein, the crosstalk canceller 206 receives a stereo digital audio signal D R2 and D.L2 (or D R1 and D. L1 ) and the speaker resistance signal Z generated by the speaker resistance detector 220 S Based on and, the stereo crosstalk cancellation signal D RXC and D. LXC The speaker resistance signal ZS is generated by the resistance R of the right speaker 180-R. R and the resistance R of the left speaker 180-L L The measured value of the turn-on resistance R of the ground switch 162-1 or 162-2 is provided. ON can vary from manufacturer to manufacturer and from lot to lot, and the headphone speaker resistance R R and R L may vary depending on the model or type of headphones connected to the USB connector 170.

[0041]

[0043] Crosstalk cancellation signal D RXC and D. LXC is the estimated crosstalk compensation component est(I L *R ON ) and est(I R *R ON ) can correspond to a digital version of the turn-on resistance R ON is the current I flowing through the ground switch 162-1 or 162-2. R +I L Therefore, as described in more detail herein, the crosstalk compensation signal D RXC and D. LXC are the turn-on resistances R of the ground switches 162-1 and 162-2, respectively. ON The filter includes linear and nonlinear components to compensate for linear and nonlinear variations in the filter.

[0042]

[0044] The stereo summers 208-R and 208-L respectively produce crosstalk compensated stereo digital audio signals D at their outputs coupled to the inputs of the stereo DACs 210-R and 210-L. RXand D. LX To generate the stereo digital audio signal D R2 and D. L2 Crosstalk cancellation signal D RXC and D. LXC The stereo DACs 210-R and 210-L each output a crosstalk-compensated stereo digital audio signal D RX and D. LX at the differential outputs coupled to the differential inputs of audio amplifiers 212-R and 212-L to produce a crosstalk compensated differential analog audio signal V RX and V LX The audio amplifiers 212-R and 212-L, which may have variable or programmable gain, each convert the crosstalk compensated differential analog audio signal V RX and V LX to produce an amplified stereo audio signal V AR and V AL These are respectively stereo switching elements SW R and SW L to speakers 180-R and 180-L via

[0043]

[0045] The speaker resistance detector 220 detects the amplified audio signal V AR and V AL 2. The speaker resistance detector 220 includes inputs coupled to the outputs of the stereo audio amplifiers 212-R and 212-L for receiving V, respectively. AR Or V AL Either a known calibrated voltage V CAL Based on this, the resistance R of the right speaker 180-R and the left speaker 180-L is R and R L For example, with amplifiers 212-R and 212-L isolated from the inputs of speaker resistance detector 220, the voltage V AR is a calibrated voltage V CAL, and the speaker resistance detector 220 is set to V AL The first sensed current I received through the terminal SNS1 According to the first calibration stage, the speaker resistance detector 220 may derive the following equation:

[0044]

number

[0045] According to the second calibration step, the voltage V AR With the ground switch 162-1 or 162-2 now turned off, the calibrated voltage V CAL , and the speaker resistance detector 220 then sets V AL The second sensed current I received through the terminal SNS2 The speaker resistance detector 220 may measure the following equation:

[0046]

number

[0047] According to the first calibration option, the resistance of the right speaker, R R and the resistance of the left speaker R L are assumed to be the same. V CAL Since R is known, the speaker resistance detector 220 uses two equations - two unknowns algebra to find R R / R L and R ON This allows the speaker resistance detector 220 to solve R R , R L and R ON The impedance signal ZS includes:

[0048] According to the second calibration option, the resistance R R and the resistance of the left speaker R L are assumed to be different. In this regard, an additional third stage of calibration is AL The calibrated voltage VCAL , and the ground switch 162-1 or 162-2 is turned on, the speaker resistance detector 220 detects V AR The third sensed current I received through the terminal SNS3 The speaker resistance detector 220 may measure the following equation:

[0049]

number

[0050] V CAL Since R is known, the speaker resistance detector 220 uses a three equation - three unknown algebraic process to find R R , R L , and R ON Similarly, the speaker resistance detector 220 can solve R R , R L , and R ON The impedance signal ZS includes:

[0051] 3 shows a block diagram of an exemplary stereo crosstalk canceller 300 according to another aspect of the present disclosure. The stereo crosstalk canceller 300 may be a more detailed exemplary implementation of the crosstalk canceller 206 of the stereo crosstalk cancellation system 200.

[0052]

[0048] In particular, the crosstalk canceller 300 includes a linear crosstalk cancellation circuit 310 and a nonlinear crosstalk cancellation circuit 320. The linear crosstalk cancellation circuit 310 includes a first coefficient C1 multiplier 312-R, a second coefficient C2 multiplier 312-L, a first adder 314-R, and a second adder 314-L. The first multiplication coefficient C1 is R L / R ON , R L / (R R ||R ON), or some other formula, since these values ​​were provided to the crosstalk canceller 300 by the speaker resistance detector 220. Similarly, the second multiplication coefficient C2 is related to R R / R ON , R R / (R L ||R ON ), or some other formula. The C1 multiplier 312-R and the C2 multiplier 312-L each multiply the stereo digital audio signal D R2 and D. L2 Thus, the C1 multiplier 312-R and the C2 multiplier 312-L each include an input coupled to an output of the interpolator 204-R and 204-L to receive the linear crosstalk cancellation signal C1*D at an output coupled to a first input of the adder 314-R and 314-L, respectively. R2 and C2*D L2 The method is configured to generate

[0053] The nonlinear crosstalk cancellation circuit 320 similarly includes a first coefficient C1 multiplier 322-R, a second coefficient C2 multiplier 322-L, an adder 324, a nonlinear calculation block (e.g., a squarer) 326, and a third coefficient K multiplier 328. The first coefficient C1 multiplier 322-R and the second coefficient C2 multiplier 322-L also respectively multiply the stereo digital audio signal D R2 and D. L2 Thus, the C1 multiplier 322-R and the C2 multiplier 322-L each include an input coupled to the output of the interpolators 204-R and 204-L to receive a first set of intermediate signals C1*D R2 and C2*D L2 It should be understood that since multipliers 322-R and 322-L perform substantially the same functions as multipliers 312-R and 312-L, crosstalk canceller 300 may optionally use one pair of them to perform both operations.

[0054] The adder 324 produces a summed second intermediate signal C1*D at its output coupled to an input of the non-linear calculation block 326. R2 +C2*D L2 The first set of intermediate signals are summed to generate a third intermediate signal (C1*D R2 +C2*D L2 ) 2 Although the nonlinear calculation block 326 is illustrated as a squarer, it should be understood that the nonlinear calculation block 326 may further perform higher order nonlinearization calculations. A third multiplication factor K multiplier 328 generates a nonlinear crosstalk cancellation signal K*(C1*D R2 +C2*D L2 ) 2 To generate the third intermediate signal (C1*D R2 +C2*D L2 ) 2 is multiplied by a third coefficient K. The third coefficient K is the turn-on resistance R ON can be empirically determined based on the nonlinear characteristics of

[0055] The output of the third coefficient multiplier 328 is coupled to second inputs of the first and second adders 314-R and 314-L of the linear crosstalk cancellation circuit 310. The first adder 314-R and the second adder 314-L respectively generate a crosstalk-canceled stereo signal D RXC and D. LXC To generate the linear crosstalk cancellation signal C2*D L2 and C1*D R2 is the nonlinear crosstalk cancellation signal K*(C1*D R2 +C2*D L2 ) 2 and add it up.

[0056] 4 illustrates a block / schematic diagram of another exemplary universal serial bus (USB) interface circuit 400 according to another aspect of the present disclosure. The USB interface circuit 400 is based on the USB interface circuit 100 and includes an integrated circuit (IC) 410, which includes an audio interface 412 and an off-chip inductor L R and L L a right channel audio amplifier 416-R and a left channel audio amplifier 416-L, and a stereo switching element SW R and SW L and SPDT switching element SW P and SW N an overvoltage protection (OVP) circuit 430; a cross-coupling switching element 418; and an off-chip resistor R M a microphone bias (MB) circuit 424 coupled to an off-chip inductor L M and resistor R M 4. The USB interface circuit 400 includes an application processor 440, a charger circuit 450, a configuration controller 495, over-voltage protection (OVP) switches 460-N, 460-P, 462-1, and 462-2 (e.g., FETs), and a USB connector 470 that may be connected to headphone speakers 480-R and 480-L. These aforementioned elements, including their connections and operation, have been described in detail with respect to the USB interface circuit 100.

[0057]

[0053] The USB interface circuit 400 differs from the USB interface circuit 100 in that it includes a crosstalk canceller 402, summers 404-R and 404-L, and a speaker resistance detector 406. The crosstalk canceller 402 may correspond to the crosstalk cancellers 206 or 300 described in detail above. The summers 404-R and 404-L may correspond to the summers 208-R and 208-L, and the speaker resistance detector 406 may correspond to the speaker resistance detector 220 described in detail above.

[0058] More specifically, the crosstalk canceller 402 receives a stereo digital audio signal D R and D. L 4. The USB interface circuit 400 includes a crosstalk canceller 402 which is coupled to a stereo input of the crosstalk compensated stereo digital signal D RX and D. LX to generate a stereo digital audio signal D R and D. L The USB interface circuit 400 is configured to generate a right crosstalk compensation signal and a left crosstalk compensation signal that are respectively summed with the crosstalk compensated stereo digital signal D RX and D. LX Receives a crosstalk-compensated stereo analog signal V RX and V LX The system further includes stereo DACs 414-R and 414-L coupled to the outputs of summers 404-R and 404-L, respectively, for generating therefrom:

[0059] The stereo audio amplifiers 416-R and 416-L each output a crosstalk compensated stereo analog signal V RX and V LX Receive and amplify the amplified crosstalk compensated stereo analog signal V AR and V AL and an input coupled to the outputs of stereo DACs 414-R and 414-L to generate R and SW L, may be provided to headphone speakers 480-R and 480-L via OVP switches 460-N and 460-P, and pins DN and DP of USB connector 470.

[0060]

[0056] The speaker resistance detector 406 includes inputs coupled to the outputs of the stereo audio amplifiers 416-R and 416-L, respectively. As previously described, the speaker resistance detector 406 may perform a first calibration option to determine the assumed equal resistances of the right speaker 480-R and the left speaker 480-L and the resistance of the ground switch 462-1 or 462-2 using Equations 5 and 6. Alternatively, the speaker resistance detector 406 may perform a second calibration option to determine the resistances of the right speaker 480-R and the left speaker 480-L and the resistance of the ground switch 462-1 or 462-2 using Equations 5 to 7. The speaker resistance detector 406 uses the resistance information of the speaker and the ground switch to generate a speaker resistance signal ZS and provides it to the crosstalk canceller 402, which determines the coefficients C1 and C2 based on the speaker resistance signal ZS, as previously described.

[0061]

[0057] Note that replica overvoltage (OVP) switches 164-1 and 164-2, their connections to the SBU1 and SBU2 pins of USB connector 170, and their connections to the pins of IC 110 have been eliminated in USB interface circuit 400. This reduces and / or eliminates wiring, routing, PCB and IC pin complexity, product cost, build of materials (BOM) cost, reliability issues, and other adverse issues.

[0062] 5 shows a flow diagram of an example method 500 for reducing stereo crosstalk due to a common ground switch according to another aspect of the present disclosure. The method 500 includes generating first and second channel digital audio signals (block 510). Examples of means for generating the first and second channel digital audio signals include the audio interface 112, the audio interface 202, the audio interface 412, and the interpolators 204-R and 204-L.

[0063]

[0059] The method 500 further includes processing the first and second channel digital audio signals to generate first and second crosstalk compensated digital audio signals (Block 520). Examples of means for processing the first and second channel digital audio signals to generate the first and second crosstalk compensated digital audio signals include any one of the crosstalk canceller 206, the crosstalk canceller 300, the linear crosstalk cancellation circuit 310 or the nonlinear crosstalk cancellation circuit 320, or the crosstalk canceller 402.

[0064]

[0060] Additionally, the method 500 includes converting the first and second crosstalk compensated digital audio signals to first and second analog audio signals, respectively (block 530). Examples of means for converting the first and second crosstalk compensated digital audio signals to first and second analog audio signals, respectively, include DACs 210-R and 210-L, and DACs 414-R and 414-L.

[0065]

[0061] The method 500 further includes providing the first and second analog audio signals, respectively, to first and second speakers having a common terminal coupled to ground via a ground switch (Block 540). Examples of means for providing the first and second analog audio signals, respectively, to first and second speakers having a common terminal coupled to ground via a ground switch include USB connectors 170, 470, and 550.

[0066]

[0062] The processing of the first and second channel digital audio signals according to block 520 may include multiplying the first channel digital audio signal by a first coefficient to generate a first intermediate digital signal, and multiplying the second channel digital audio signal by a second coefficient to generate a second intermediate digital signal. Examples of means for multiplying the first channel digital audio signal by a first coefficient to generate a first intermediate digital signal include multipliers 312-R and 322-R. Examples of means for multiplying the second channel digital audio signal by a second coefficient to generate a second intermediate digital signal include multipliers 312-L and 322-L.

[0067]

[0063] The processing of the first and second channel digital audio signals according to block 520 may further include summing the first and second intermediate digital signals to generate a third intermediate signal, squaring the third intermediate digital signal to generate a fourth intermediate digital signal, and multiplying the fourth intermediate digital signal by a third coefficient to generate a fifth intermediate digital signal. An example of a means for summing the first and second intermediate digital signals to generate the third intermediate signal includes the adder 324. An example of a means for squaring the third intermediate digital signal to generate the fourth intermediate digital signal includes the non-linear calculation block 326. An example of a means for multiplying the fourth intermediate digital signal by a third coefficient to generate the fifth intermediate digital signal includes the multiplier 328.

[0068]

[0064] Processing the first and second channel digital audio signals according to block 520 may further include summing the second intermediate signal with the fifth intermediate signal to generate a first crosstalk cancellation digital signal, summing the first intermediate signal with the fifth intermediate signal to generate a second crosstalk cancellation digital signal, summing the first crosstalk cancellation digital signal with the first channel digital audio signal to generate a first crosstalk compensated digital audio signal, and summing the second crosstalk cancellation digital signal with the second channel digital audio signal to generate a second crosstalk compensated digital audio signal.

[0069]

[0065] An exemplary means for summing the second intermediate signal with the fifth intermediate signal to generate a first crosstalk-canceled digital signal includes the adder 314-R. An example of a means for summing the first intermediate signal with the fifth intermediate signal to generate a second crosstalk-canceled digital signal includes the adder 314-L. An example of a means for summing the first crosstalk-canceled digital signal with the first channel digital audio signal to generate a first crosstalk-compensated digital audio signal includes the adder 208-R. And an example of a means for summing the second crosstalk-canceled digital signal with the second channel digital audio signal to generate a second crosstalk-compensated digital audio signal includes the adder 208-L.

[0070] 6 illustrates a block diagram of an exemplary wireless communication device 600 according to another aspect of the present disclosure. The wireless communication device 600 may be implemented as any type of wireless communication device, such as a mobile handset device, a tablet device, a laptop computer, a desktop computer, a wearable device (e.g., a smart watch, a health monitoring device, a human activity monitoring device, etc.), an Internet of Things (IoT) device, etc.

[0071] The wireless communication device 600 includes an integrated circuit (IC) 610, which may be implemented as a system on a chip (SOC). The SOC 610 may include one or more signal processing cores 615 coupled to a USB application processor 625. The one or more signal processing cores 615 may be configured to generate and / or process baseband (BB) signals. The USB application processor 625 may be configured to generate an audio stream based on audio data received from the one or more signal processing cores 615. The USB application processor 625 also generates a USB differential data signal V based on data received from the one or more signal processing cores 615. OUN / V OUP and / or a USB differential data signal V received from a client device connected to the USB-C host connector 650. OUN / V OUP The device may be configured to process

[0072]

[0068] The wireless communication device 600 further includes a USB interface circuit 640 (with an integrated digital crosstalk canceller), which may be implemented per IC 410 as previously described. The USB interface circuit 640 is coupled to the USB application processor 625 to receive and / or provide an audio stream thereto. The USB interface circuit 640 is also differentially coupled to the USB application processor 625 to provide a USB differential data signal V OUN / V OUPa USB-C connector 650. A USB interface circuit 640 may be coupled to the charger circuit 635 to receive and / or provide a charger data signal. The USB interface circuit 640 includes at least a portion of the USB differential transmission lines DP / DN, which are coupled to an overvoltage protection (OVP) circuit 645, as well as the DN and DN pins of the USB-C connector 650. The OVP circuit 645 may include a ground switch or FET as previously described, which may generate crosstalk distortion between the right and left stereo audio channel signals.

[0073] A client device may be plugged into the USB-C connector 650. If the mode signal indicates USB data communication, the USB interface circuit 640 outputs the USB differential data signal V OUN / V OUP to the client device or the USB application processor 625. If the mode signal indicates stereo audio transmission, the USB interface circuit 640 may route the stereo analog audio signal V AR and V AL to the client device. Also, if the mode signal indicates a charger data communication, the USB interface circuit 640 may route the charger data signal to the client device or the charger circuit 635.

[0074] For wireless transmission, the wireless communication device 600 includes a transceiver 660 coupled to the one or more signal processing cores 615 to provide baseband (BB) signals to and / or receive from the one or more signal processing cores 615. The wireless communication device 600 also includes at least one antenna 665 (e.g., an antenna array) to provide radio frequency (RF) signals to and / or receive from the transceiver 660. According to a transmission application, the transceiver 660 is configured to process the transmit BB signal to generate a transmit RF signal for wireless transmission to a remote device via the at least one antenna 665. According to a reception application, the transceiver 660 is configured to process the RF signal received from the at least one antenna 665 to generate a receive BB signal for signal processing by the one or more signal processing cores 615.

[0075]

[0071] The following provides a summary of aspects of the present disclosure.

[0076]

[0072] Aspect 1: An apparatus comprising: an audio interface including a first and a second output; a crosstalk cancellation circuit including a first and a second input coupled to the first and second output portions of the audio interface, respectively; a first adder including a first input coupled to the first output portion of the audio interface and a second input coupled to the first output portion of the crosstalk cancellation circuit; a second adder including a first input coupled to the second output portion of the audio interface and a second input coupled to the second output portion of the crosstalk cancellation circuit; a first digital-to-analog converter (DAC) including an input coupled to the output portion of the first adder; and a second DAC including an input coupled to the output portion of the second adder.

[0077]

[0073] Aspect 2: The apparatus of aspect 1, wherein the crosstalk cancellation circuitry includes a linear crosstalk cancellation circuit.

[0078]

[0074] Aspect 3: The apparatus of aspect 2, wherein the linear crosstalk cancellation circuit includes a first multiplier including a first input portion coupled to a first output portion of the audio interface, and a second multiplier including a second input portion coupled to a second output portion of the audio interface.

[0079]

[0075] Aspect 4: The apparatus of aspect 3, wherein the first multiplier has a first multiplication coefficient related to a first resistance across the first speaker, and the second multiplier has a second multiplication coefficient related to a second resistance across the second speaker.

[0080]

[0076] Aspect 5: The apparatus of aspect 4, wherein the first multiplication coefficient is related to the first resistance divided by the turn-on resistance of the ground switch, and the second multiplication coefficient is related to the second resistance divided by the turn-on resistance of the ground switch.

[0081]

[0077] Aspect 6: The apparatus of aspect 4, wherein the first multiplication coefficient is related to the first resistance divided by a first parallel resistance of the turn-on resistance of the ground switch and the second resistance, and the second multiplication coefficient is related to the second resistance divided by a second parallel resistance of the turn-on resistance of the ground switch and the first resistance.

[0082]

[0078] Example 7: The apparatus of any one of Examples 1-6, wherein the crosstalk cancellation circuitry comprises a non-linear crosstalk cancellation circuit.

[0083]

[0079] Aspect 8: The apparatus of aspect 7, wherein the nonlinear crosstalk cancellation circuit comprises a third multiplier including a third input portion coupled to a first output portion of the audio interface, a fourth multiplier including a fourth input portion coupled to a second output portion of the audio interface, a third adder including input portions coupled to the third and fourth output portions of the third and fourth multipliers, respectively, a nonlinear calculation block including an input portion coupled to the output portion of the third adder, and a fifth multiplier including an input portion coupled to the output portion of the nonlinear calculation block.

[0084]

[0080] Aspect 9: The apparatus of aspect 8, wherein the nonlinear calculation block comprises a squarer.

[0085]

[0081] Aspect 10: The apparatus of aspect 8 or 9, wherein the fifth multiplier includes a multiplication coefficient related to a non-linear characteristic of the turn-on resistance of the ground switch.

[0086]

[0082] Aspect 11: An apparatus of any one of aspects 8 to 10, wherein the linear crosstalk cancellation circuit further includes a fourth adder having input portions coupled to the output portions of the second and fifth multipliers, respectively, and an output portion coupled to the second input portion of the first adder, and a fifth adder having input portions coupled to the output portions of the first and fifth multipliers, respectively, and an output portion coupled to the second input portion of the second adder.

[0087]

[0083] Example 12: The apparatus of any one of Examples 1 to 6, wherein the crosstalk cancellation circuitry comprises a non-linear crosstalk cancellation circuit.

[0088]

[0084] Aspect 13: The apparatus of aspect 12, wherein the nonlinear crosstalk cancellation circuit comprises a first multiplier having an input portion coupled to a first output portion of the audio interface, a second multiplier having an input portion coupled to a second output portion of the audio interface, a third adder having input portions respectively coupled to the outputs of the first and second multipliers, a nonlinear calculation block having an input portion coupled to the output portion of the third adder, and a third multiplier having an input portion coupled to the output portion of the nonlinear calculation block.

[0089]

[0085] Aspect 14: The device of any one of aspects 1 to 13, further comprising a first audio amplifier including an input portion coupled to the output portion of the first DAC, and a second audio amplifier including an input portion coupled to the output portion of the second DAC.

[0090]

[0086] Aspect 15: The apparatus of aspect 14, further comprising a speaker resistance detector including first and second input portions respectively coupled to the first and second output portions of the first and second audio amplifiers, and an output portion coupled to the crosstalk cancellation circuit.

[0091]

[0087] Aspect 16: The apparatus of aspect 14 or 15, further comprising a Universal Serial Bus (USB) connector, the Universal Serial Bus connector including a first pin selectively coupled to a first output of the first audio amplifier and configured to couple to a first terminal of the first speaker, a second pin selectively coupled to a second output of the second audio amplifier and configured to couple to a first terminal of the second speaker, and a third pin coupled to a ground switch and configured to couple to a common second terminal of the first and second speakers.

[0092]

[0088] Aspect 17: A method comprising: generating first and second channel digital audio signals; processing the first and second channel digital audio signals to generate first and second crosstalk compensated digital audio signals; converting the first and second crosstalk compensated digital audio signals to first and second analog audio signals, respectively; and providing the first and second analog audio signals to first and second speakers, respectively, having a common terminal coupled to ground via a ground switch.

[0093]

[0089] Aspect 18: The method of aspect 17, wherein processing the first and second channel digital audio signals includes multiplying the first channel digital audio signal by a first coefficient to generate a first intermediate digital signal, and multiplying the second channel digital audio signal by a second coefficient to generate a second intermediate digital signal.

[0094]

[0090] Aspect 19: The method of aspect 18, wherein the first coefficient is related to a first resistance across the second speaker and the second coefficient is related to a second resistance across the first speaker.

[0095]

[0091] Aspect 20: The method of aspect 18 or 19, wherein processing the first and second channel digital audio signals further includes summing the first and second intermediate digital signals to generate a third intermediate signal, squaring the third intermediate digital signal to generate a fourth intermediate digital signal, and multiplying the fourth intermediate digital signal by a third coefficient to generate a fifth intermediate digital signal.

[0096]

[0092] Aspect 21: The method of aspect 20, wherein the third coefficient is related to the nonlinear resistance of the ground switch.

[0097]

[0093] Aspect 22: The method of aspect 20 or 21, wherein processing the first and second channel digital audio signals further includes: summing the second intermediate signal with the fifth intermediate signal to generate a first crosstalk cancellation digital signal; summing the first intermediate signal with the fifth intermediate signal to generate a second crosstalk cancellation digital signal; summing the first crosstalk cancellation digital signal with the first channel digital audio signal to generate a first crosstalk compensated digital audio signal; and summing the second crosstalk cancellation digital signal with the second channel digital audio signal to generate a second crosstalk compensated digital audio signal.

[0098]

[0094] Aspect 23: An apparatus comprising: means for generating first and second channel digital audio signals; means for processing the first and second channel digital audio signals to generate first and second crosstalk compensated digital audio signals; means for converting the first and second crosstalk compensated digital audio signals into first and second analog audio signals, respectively; and means for providing the first and second analog audio signals, respectively, to first and second speakers having a common terminal coupled to ground via a ground switch.

[0099]

[0095] Aspect 24: The apparatus of aspect 23, wherein the means for processing the first and second channel digital audio signals comprises means for multiplying the first channel digital audio signal by a first coefficient to generate a first intermediate digital signal, and means for multiplying the second channel digital audio signal by a second coefficient to generate a second intermediate digital signal.

[0100]

[0096] Aspect 25: The apparatus of aspect 24, wherein the first coefficient is related to a first resistance across the second speaker and the second coefficient is related to a second resistance across the first speaker.

[0101]

[0097] Aspect 26: The apparatus of aspect 24 or 25, wherein the means for processing the first and second channel digital audio signals further comprises means for adding the first and second intermediate digital signals to generate a third intermediate signal, means for squaring the third intermediate digital signal to generate a fourth intermediate digital signal, and means for multiplying the fourth intermediate digital signal by a third coefficient to generate a fifth intermediate digital signal.

[0102]

[0098] Aspect 27: The apparatus of aspect 26, wherein the third coefficient is related to the nonlinear resistance of the ground switch.

[0103]

[0099] Aspect 28: The apparatus of aspect 26 or 27, wherein the means for processing the first and second channel digital audio signals further comprises means for summing the first intermediate signal with the fifth intermediate signal to generate a first crosstalk cancellation digital signal, means for summing the second intermediate signal with the fifth intermediate signal to generate a second crosstalk cancellation digital signal, means for summing the second crosstalk cancellation digital signal with the first channel digital audio signal to generate a first crosstalk compensated digital audio signal, and means for summing the first crosstalk cancellation digital signal with the second channel digital audio signal to generate a second crosstalk compensated digital audio signal.

[0104]

[0100] Aspect 29: A wireless communications device comprising: at least one antenna, a transceiver coupled to the at least one antenna, one or more signal processing cores coupled to the transceiver, an audio interface including first and second output portions, the audio interface coupled to the one or more signal processing cores, a crosstalk cancellation circuit including first and second input portions respectively coupled to the first and second output portions of the audio interface, a first adder including a first input portion coupled to the first output portion of the audio interface and a first output portion of the crosstalk cancellation circuit, a second adder including a second input portion coupled to the second output portion of the audio interface and a second output portion of the crosstalk cancellation circuit, a first digital-to-analog converter (DAC) including an input portion coupled to the output portion of the first adder, and a second DAC including an input portion coupled to the output portion of the second adder.

[0105]

[0101] Aspect 30: The wireless communication device of aspect 29, further comprising a first audio amplifier including an input coupled to the output of the first DAC, a second audio amplifier including an input coupled to the output of the second DAC, a universal serial bus (USB) application processor, a charger circuit, and a USB connector selectively coupled to the first and second audio amplifiers, the USB application processor, and the charger circuit.

[0106]

[0102] The above description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. an audio interface including first and second outputs; a crosstalk cancellation circuit including first and second inputs respectively coupled to the first and second outputs of the audio interface; a first summer having a first input coupled to the first output of the audio interface and a second input coupled to a first output of the crosstalk cancellation circuit; a second summer having a first input coupled to the second output of the audio interface and a second input coupled to a second output of the crosstalk cancellation circuit; a first digital-to-analog converter (DAC) including an input coupled to an output of the first summer; a second DAC including an input coupled to the output of the second summer; An apparatus comprising:

2. The apparatus of claim 1 , wherein the crosstalk cancellation circuitry comprises a linear crosstalk cancellation circuitry.

3. The linear crosstalk cancellation circuit comprises: a first multiplier including a first input coupled to the first output of the audio interface; a second multiplier including a second input coupled to the second output of the audio interface; The apparatus of claim 2 , comprising:

4. the first multiplier having a first multiplication coefficient related to a first resistance across a first speaker; the second multiplier having a second multiplication coefficient related to a second resistance across a second speaker; 4. The apparatus of claim 3.

5. the first multiplication factor is related to the first resistance divided by a turn-on resistance of a switch to ground; the second multiplication factor being related to the second resistance divided by the turn-on resistance of the ground switch; 5. The apparatus of claim 4.

6. the first multiplication factor is related to the first resistance divided by a first parallel resistance of a turn-on resistance of a switch to ground and the second resistance; the second multiplication factor is related to the second resistance divided by a second parallel resistance of the turn-on resistance of the ground switch and the first resistance.

5. The apparatus of claim 4.

7. The apparatus of claim 3 , wherein the crosstalk cancellation circuitry comprises a non-linear crosstalk cancellation circuitry.

8. The nonlinear crosstalk cancellation circuit comprises: a third multiplier including a third input coupled to the first output of the audio interface; a fourth multiplier including a fourth input coupled to the second output of the audio interface; a third adder including inputs coupled to third and fourth outputs of the third and fourth multipliers, respectively; a non-linear computation block including an input coupled to the output of the third adder; a fifth multiplier having an input coupled to the output of the nonlinear computation block; The apparatus of claim 7 , comprising:

9. The apparatus of claim 8 , wherein the non-linear computation block comprises a squarer.

10. The apparatus of claim 8 , wherein the fifth multiplier includes a multiplication factor related to a non-linear characteristic of a turn-on resistance of a ground switch.

11. The linear crosstalk cancellation circuit comprises: a fourth adder having inputs respectively coupled to the outputs of the second and fifth multipliers and an output coupled to the second input of the first adder; a fifth adder including inputs respectively coupled to the outputs of the first and fifth multipliers and an output coupled to the second input of the second adder; The apparatus of claim 8 further comprising:

12. The apparatus of claim 1 , wherein the crosstalk cancellation circuitry comprises a non-linear crosstalk cancellation circuitry.

13. The nonlinear crosstalk cancellation circuit comprises: a first multiplier including an input coupled to the first output of the audio interface; a second multiplier including an input coupled to the second output of the audio interface; a third adder including inputs respectively coupled to the outputs of the first and second multipliers; a non-linear computation block including an input coupled to the output of the third adder; a third multiplier having an input coupled to the output of the nonlinear computation block; The apparatus of claim 12 , comprising:

14. a first audio amplifier including an input coupled to an output of the first DAC; a second audio amplifier including an input coupled to an output of the second DAC; The apparatus of claim 1 further comprising:

15. 15. The apparatus of claim 14, further comprising a speaker resistance detector including first and second inputs respectively coupled to first and second outputs of the first and second audio amplifiers and an output coupled to the crosstalk cancellation circuit.

16. and a Universal Serial Bus (USB) connector, the Universal Serial Bus connector comprising: a first pin selectively coupled to a first output of the first audio amplifier, the first pin configured to couple to a first terminal of a first speaker; a second pin selectively coupled to a second output of the second audio amplifier, the second pin configured to couple to a first terminal of a second speaker; a third pin coupled to a ground switch, the third pin configured to couple to a common second terminal of the first and second speakers; The apparatus of claim 14 , comprising:

17. generating first and second channel digital audio signals; processing the first and second channel digital audio signals to generate first and second crosstalk compensated digital audio signals; converting the first and second crosstalk compensated digital audio signals into first and second analog audio signals, respectively; providing the first and second analog audio signals to first and second speakers, respectively, having a common terminal coupled to ground via a ground switch; A method comprising:

18. Processing the first and second channel digital audio signals includes: multiplying the first channel digital audio signal by a first coefficient to generate a first intermediate digital signal; multiplying the second channel digital audio signal by a second coefficient to generate a second intermediate digital signal; 20. The method of claim 17, comprising:

19. the first coefficient being related to a first resistance across the second speaker; the second coefficient being related to a second resistance across the first speaker; 20. The method of claim 18.

20. Processing the first and second channel digital audio signals includes: summing the first and second intermediate digital signals to generate a third intermediate signal; squaring the third intermediate digital signal to generate a fourth intermediate digital signal; multiplying the fourth intermediate digital signal by a third coefficient to generate a fifth intermediate digital signal; 20. The method of claim 18, further comprising:

21. The method of claim 20 , wherein the third coefficient is related to a non-linear resistance of the ground switch.

22. Processing the first and second channel digital audio signals includes: summing the second intermediate signal with the fifth intermediate signal to generate a first crosstalk-canceled digital signal; summing the first intermediate signal with the fifth intermediate signal to generate a second crosstalk-canceled digital signal; summing the first crosstalk cancellation digital signal with the first channel digital audio signal to generate the first crosstalk compensated digital audio signal; summing the second crosstalk cancellation digital signal with the second channel digital audio signal to generate the second crosstalk compensated digital audio signal; 21. The method of claim 20, further comprising:

23. means for generating first and second channel digital audio signals; means for processing the first and second channel digital audio signals to generate first and second crosstalk compensated digital audio signals; means for converting the first and second crosstalk compensated digital audio signals into first and second analog audio signals, respectively; means for providing the first and second analog audio signals, respectively, to first and second speakers having a common terminal coupled to ground via a ground switch; An apparatus comprising:

24. The means for processing the first and second channel digital audio signals comprises: means for multiplying the first channel digital audio signal by a first coefficient to generate a first intermediate digital signal; means for multiplying the second channel digital audio signal by a second coefficient to generate a second intermediate digital signal; 24. The apparatus of claim 23, comprising:

25. the first coefficient being related to a first resistance across the second speaker; the second coefficient being related to a second resistance across the first speaker; 25. The apparatus of claim 24.

26. The means for processing the first and second channel digital audio signals comprises: means for summing the first and second intermediate digital signals to generate a third intermediate signal; means for squaring the third intermediate digital signal to generate a fourth intermediate digital signal; means for multiplying the fourth intermediate digital signal by a third coefficient to generate a fifth intermediate digital signal; 25. The apparatus of claim 24, further comprising:

27. 27. The apparatus of claim 26, wherein the third coefficient is related to a non-linear resistance of the ground switch.

28. The means for processing the first and second channel digital audio signals comprises: means for summing the second intermediate signal with the fifth intermediate signal to generate a first crosstalk-canceled digital signal; means for summing the first intermediate signal with the fifth intermediate signal to generate a second crosstalk-canceled digital signal; means for summing the first crosstalk cancellation digital signal with the first channel digital audio signal to generate the first crosstalk compensated digital audio signal; means for summing the second crosstalk cancellation digital signal with the second channel digital audio signal to generate the second crosstalk compensated digital audio signal; 27. The apparatus of claim 26, further comprising:

29. 1. A wireless communication device, comprising: At least one antenna; a transceiver coupled to the at least one antenna; one or more signal processing cores coupled to the transceiver; an audio interface including first and second outputs, the audio interface coupled to the one or more signal processing cores; a crosstalk cancellation circuit including first and second inputs respectively coupled to the first and second outputs of the audio interface; a first summer having a first input coupled to the first output of the audio interface and a second input coupled to a first output of the crosstalk cancellation circuit; a second summer having a first input coupled to the second output of the audio interface and a second input coupled to a second output of the crosstalk cancellation circuit; a first digital-to-analog converter (DAC) including an input coupled to an output of the first summer; a second DAC including an input coupled to the output of the second summer; A wireless communication device comprising:

30. a first audio amplifier including an input coupled to an output of the first DAC; a second audio amplifier including an input coupled to an output of the second DAC; a universal serial bus (USB) application processor; A charger circuit; a USB connector selectively coupled to the first and second audio amplifiers, the USB application processor, and the charger circuit; 30. The wireless communication device of claim 29, further comprising:

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