Parity protection for control registers

Abstract

An integrated circuit (IC) device for detecting an error in a register, the IC device including a register and a parity check circuit. The parity check circuit is coupled to the register and includes a first parity circuit, a second parity circuit, and an error detection circuit. The first parity circuit receives a first register value from the register and determines a first value from the first register value. The second parity circuit receives a second register value from the register and determines a second value from the second register value. The error detection circuit compares the first value with the second value to detect a first error in the register and outputs an error signal indicative of the first error.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to detecting invalid register values, and more specifically to detecting invalid register values ​​using parity circuits. [Background technology]

[0002] In applications requiring a high level of operational safety, integrated circuit (IC) devices are required to meet safe operation standards. Such applications correspond to operational environments in which a failure of the IC device may place an operator in a dangerous situation. One example of such an application is an automotive application. In an automotive application, an IC device is required to meet one of the automotive safety integrity levels defined in the ISO 26262 standard. For example, an IC device is required to meet the ASIL-D standard (e.g., single point fault coverage (SPFM)), which requires that the IC device be able to detect 99% of random faults. In various implementations, various IC devices can achieve 99% SPFM by applying monitoring techniques. In some implementations, an IC device employs software monitoring to periodically check register values ​​of the IC device to determine the validity of the register values. However, because the software monitoring techniques periodically check the validity of the register values, one or more changes to the register values ​​may not be detected until the operation of the IC device is adversely affected. Furthermore, software monitoring solutions use processing resources of the IC device, reducing the amount of processing resources available to one or more applications executing on the IC device. Summary of the Invention [Means for solving the problem]

[0003] An integrated circuit (IC) device includes a hardware-based technique for detecting erroneous value changes (e.g., invalid values) to values ​​of control registers of the IC device. The hardware-based technique can continuously monitor the control registers such that erroneous value changes are detected before they adversely affect the operation of the IC device. In one example, the IC device includes a parity check circuit that monitors the values ​​of the control registers of the IC device and reports errors detected in the control registers. The parity check circuit generates a parity value for a subset of the registers and uses the parity value to detect errors present in the values ​​of the control registers.

[0004] In one example, an IC device for detecting an error in a register includes a register and a parity check circuit. The parity check circuit is coupled to the register and includes a first parity circuit, a second parity circuit, and an error detection circuit. The first parity circuit receives a first register value from the register and determines a first value from the first register value. The second parity circuit receives a second register value from the register and determines a second value from the second register value. The error detection circuit compares the first value with the second value to detect a first error in the register and outputs an error signal indicative of the first error.

[0005] In one example, a method includes determining, by a first parity circuit of a parity check circuit of an IC device, a first value from first register values ​​of a plurality of registers of the IC device. The method further includes determining, by a second parity circuit of the parity check circuit, a second value from second register values ​​of the plurality of registers. The method further includes comparing the first value to the second value to determine a first error in the plurality of registers and outputting an error signal indicative of the first error.

[0006] In one example, the parity check circuit includes a first parity circuit, a second parity circuit, and an error detection circuit. The first parity circuit receives first register values ​​from the plurality of registers and determines a first value from the first register values. The second parity circuit receives second register values ​​from the plurality of registers and determines a second value from the second register values. The error detection circuit compares the first value to the second value to determine a first error in the plurality of registers and outputs an error signal indicative of the first error.

[0007] So that the above features briefly summarized may be understood in detail, a more particular description can be made by reference to exemplary implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical example implementations and therefore should not be considered as limiting the scope thereof. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of an integrated circuit device according to one embodiment. [Diagram 2] 1 is a schematic diagram of a portion of an integrated circuit device, according to one embodiment. [Diagram 3] FIG. 2 is a schematic diagram of a parity circuit according to one embodiment. [Figure 4] 2 is a schematic diagram of a portion of an error detector circuit, according to one embodiment. [Diagram 5] 4 is a flow diagram of a method for detecting an error in a register according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] For ease of understanding, wherever possible, identical reference numbers have been used to designate identical elements common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments.

[0010] Integrated circuit (IC) devices include registers, and the values ​​of the registers may control the operation of the IC device. Such registers may be referred to as control registers. A change in the value of a register changes the operation of the IC device. In some embodiments, an application executing on the IC device changes the value of one or more of the registers to configure or change the operation of the IC device. However, in other embodiments, the register values ​​of one or more of the registers may be erroneously changed. When a register's value is erroneously changed, the value of the register may become an unintended value that may adversely affect the operation of the IC device. The value of a register may be erroneously changed due to a defect in the corresponding IC device, a single event upset (SEU) in the register, or an incorrect (e.g., unintended) write to the register. An SEU changes the value of a register due to concomitant electrical effects in the circuit elements of the register. An erroneous write corresponds to data being routed to an incorrect register.

[0011] A register with an invalid value may change the operation of a corresponding IC device, which may result in a fault in the corresponding system. In a system where a fault may endanger operator safety, detecting the invalid value in a register ensures that the operation of the IC device is not altered, reducing the likelihood of a fault occurring in the corresponding system and increasing operator safety.

[0012] Described below is an IC device including a parity check circuit that monitors the values ​​of registers. The parity check circuit uses a hardware-based technique to detect erroneously modified register values. The parity check circuit receives register values ​​from a subset of the registers and uses a parity calculation to determine whether an error exists in the values ​​of the registers. Because the parity check circuit uses a hardware-based technique to monitor the register values, processing resources of the corresponding device are not dedicated to monitoring the register values. Furthermore, the parity check circuit can monitor the values ​​of the registers uninterruptedly. Thus, compared to IC devices employing software monitoring techniques, increased processing resources are available to applications executing on the IC device and invalid register values ​​are detected more quickly.

[0013] Various features are described below with reference to the drawings. It should be noted that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by similar reference numerals throughout the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as an exhaustive description of the claimed invention or as limiting the scope of the claimed invention. In addition, an illustrated embodiment need not have all the aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment and may be implemented in any other embodiment even if not so illustrated or explicitly described.

[0014] FIG. 1 illustrates an IC device 100 according to one or more embodiments. The IC device 100 includes a controller 110, a control circuit 120, a register block 130, a parity check circuit 140, and an interconnect 150. The IC device 100 can be a programmable logic device, such as a field programmable gate array (FPGA). In other embodiments, the IC device 100 is an application specific integrated circuit (ASIC), a central processing unit (CPU), or a graphics processing unit (GPU), among others. In one or more embodiments, the IC device 100 is a system on a chip (SoC). The IC device 100 also includes one or more IC chips. In various examples, the IC device 100 includes a programmable logic and a hardened control circuit. The programmable logic can be reprogrammed via control data (e.g., a bitstream) to change the functionality of the programmable logic, while the functionality of the hardened control circuit remains constant.

[0015] The controller 110 communicates with the control circuitry 120 via an interconnect 150. The interconnect 150 may be an Advanced eXtensible Interface (AXI) interconnect. In other embodiments, the interconnect 150 is another type of interconnect. The controller 110 provides instructions and data to the control circuitry 120 to update values ​​of one or more registers in the register block 130. Additionally, the controller 110 provides instructions to the control circuitry 120 to read values ​​of one or more registers in the register block 130. In one embodiment, the controller 110 executes instructions stored in the memory to perform one or more corresponding functions. The instructions correspond to an application, and the functions correspond to one or more actions to be performed by the IC device based on the application. For example, the application may correspond to monitoring sensor data received from a sensor device in the automobile.

[0016] Register block 130 may be referred to as a control register block. Register block 130 includes one or more registers (e.g., control registers), each having one or more corresponding register values. In one embodiment, the number of registers in register block 130 is N. N is a positive integer greater than 1. In other embodiments, N is 16, 32, 64, 128, 256, or more. Each register in register block 130 is an M-bit register. M is a positive integer greater than 1. In one embodiment, M is 16, 32, 64, 128, 256, or more. Each of the registers in register block 130 includes a number of flip-flops, each of which stores a corresponding register value. The flip-flops are arranged in a number of rows and columns. Each row of flip-flops corresponds to a different register in register block 130. Furthermore, each flip-flop stores a corresponding bit (e.g., a register value) of a corresponding register.

[0017] The register block 130 connects to and is controlled by the control circuitry 120. For example, the register block 130 can receive read commands, write commands, and data from the controller 110 via the interconnect 150 and the control circuitry 120.

[0018] The parity check circuit 140 couples to the register block 130. The parity check circuit 140 further couples to one or more of the control circuit 120 and the controller 110. The parity check circuit 140 receives register values ​​from the register block 130 and determines whether one or more values ​​of the register block 130 store an invalid value. An invalid value indicates that the value in the register block 130 differs from an expected value and has been erroneously modified.

[0019] The parity check circuit 140 outputs an error signal 160 based on detection of an invalid value in the register block 130. The value of the register block 130 may be altered due to a defect in the IC device 100, an SEU in the register block 130, or an erroneous (e.g., unintended) write to one of the registers. The parity check circuit 140 outputs the error signal 160 from the IC device 100 to a processing system that is configured to take one or more corrective actions based on the error signal 160. For example, the processing system may reset the IC device 100, halt an application executing on the IC device 100, or reset the register block 130, among other actions, based on the error signal 160 indicating an invalid register value (e.g., an error).

[0020] The parity check circuit 140 receives a monitor signal from the controller 110 or control circuit 120. The monitor signal (also called a "monitor enable signal") is asserted to indicate to the parity check circuit 140 to monitor the values ​​of the register block 130. The monitor signal is deasserted to indicate to the parity check circuit 140 to stop (or pause) monitoring one or more registers in the register block 130. In one embodiment, the monitor signal is deasserted when one or more of the values ​​in the register block 130 are updated. The monitor signal corresponding to the registers that should be updated is deasserted, while the monitor signal corresponding to the registers that should not be updated is asserted. In one embodiment, the controller 110 or control circuit 120 determines that the register values ​​should be updated and deasserts the corresponding monitor signal to pause (e.g., stop) the parity check circuit 140 from monitoring the registers in the register block 130 that should be updated. In another embodiment, a single monitor signal is used to control the monitoring operation of the parity check circuit 140. In such an embodiment, upon the monitoring signal being deasserted, the parity check circuit 140 suspends monitoring of the entire register block 130 .

[0021] 1, IC device 100 is illustrated as including one register block 130. In other embodiments, IC device 100 includes two or more register blocks. In one embodiment, IC device includes N register blocks, where N is 3 or greater. Furthermore, in such an embodiment, each register block may be monitored by a corresponding parity check circuit 140, such that IC device 100 includes two or more parity check circuits 140.

[0022] 2 illustrates a portion of an IC device 100 in accordance with one or more embodiments. For example, FIG. 2 illustrates a register block 130 and a parity check circuit 140. The register block 130 includes registers 1321-1322. N where N is an integer greater than 1. For example, N can be 8, 16, 32, 64, 138, 256, or more. Each of the registers 132 stores M bits (e.g., M values), where M is 2 or more. For example, M can be 4, 8, 16, 32, 64, 128, 256, or more.

[0023] Each of the registers 132 is coupled to a parity check circuit 140. The parity check circuit 140 includes parity calculation circuits 210 and 220 and an error detection circuit 230. The parity calculation circuits 210 and 220 are similar to each other. For example, the parity calculation circuit 210 includes a parity circuit 212, and the parity calculation circuit 220 includes a parity circuit 222. In one embodiment, the parity calculation circuit 210 includes parity circuits 2121-212. N The parity calculation circuit 220 includes parity circuits 2221 to 222 N N is an integer greater than 1. For example, N can be 8, 16, 32, 64, 138, 256, or more.

[0024] Each of the parity circuits 212 and 222 determines a corresponding value 214, 224 from the register value of the corresponding register 132 in the register block 130. In one embodiment, each of the parity circuits 212 determines a value 214 for the first bit of each respective register in the register block 132. For example, the parity circuit 2121 determines a value 2141 from bit[1] of each of the registers 132, and the parity circuit 2122 determines a value 2142 from bit[2] of each of the registers 132. In addition, the parity circuits 212 N is a value 214 from each bit [N] of the register 132. N Further, each of the parity circuits 222 determines a value 224 for the first bit of each register of the registers 132. For example, the parity circuit 2221 determines a value 2241 from bit [1] of each of the registers 132. And the parity circuit 2222 determines a value 2242 from bit [2] of each of the registers 132. Further, the parity circuit 222 determines a value 224 for the first bit of each of the registers of the registers 132. For example, the parity circuit 2221 determines a value 2241 from bit [1] of each of the registers 132. And the parity circuit 2222 determines a value 2242 from bit [2] of each of the registers 132. N is a value 224 from each bit [N] of the register 132. N Such a scheme for determining values ​​214 and 224 may be referred to as a vertical parity scheme. Furthermore, each of parity circuits 212 and 222 may determine a value based on a register value from a respective register 132. In other embodiments, each of parity circuits 212 and 222 may determine a value from a register value 202 of a respective register 132. In one embodiment, a first parity circuit (e.g., parity circuit 2121) receives a register value (e.g., register value 202) and compares the register values ​​to determine a first value. The register value may include one or more bits of one or more registers 132. Determining the first value is further described with respect to FIG. 3.

[0025] Each of the parity circuits 212 and 222 compares the respective register values ​​to determine a respective value. Each of the parity circuits 212 and each of the parity circuits 222 is coupled to the registers 132. In one embodiment, each of the parity circuits 212 and each of the parity circuits 222 is coupled to two or more of the registers 132. In one particular embodiment, each of the parity circuits 212 and each of the parity circuits 222 is coupled to a respective subset of the registers 132, the subset including one or more of the registers 132. In one or more embodiments, each of the parity circuits 212 and each of the parity circuits 222 is coupled to a respective subset of the registers 132, the subset including one or more of the registers 132.

[0026] In one embodiment, the number of registers 132 is equal to or greater than the number of parity circuits 212 and the number of parity circuits 222. In such an embodiment, each of the parity circuits 212 and 222 receives bits from each of the registers 132. The parity circuits 212 and 222 function in a vertical parity check scheme. In another embodiment, the number of registers 132 is less than the number of parity circuits 212 and the parity circuits 222. In such an embodiment, each of the parity circuits 212 receives bits from a respective one of the registers 132 and each of the parity circuits 222 receives bits from a respective one of the registers 132.

[0027] The parity circuits 212 and 222 function in pairs such that one of the parity circuits 212 and one of the parity circuits 222 receive the same register value from the same register. In such an embodiment, the pair of parity circuits 212 and 222 process the same register value to determine corresponding values ​​214, 224. Additionally, the pair of parity circuits 212 and 222 receive the same mask 204.

[0028] The mask 204 is received from the controller 110 or the control circuitry 120. The mask 204 is received from a memory in the IC device 100. In one embodiment, the mask 204 is stored in a register of the IC device 100. The controller 110 provides the mask 204 from the memory or register of the IC device 100 to the control circuitry. The mask 204 identifies the bits of the register values ​​202 that the parity circuits 212 and 222 use to determine the values ​​214, 224. For example, the mask 204 sets one or more of the register values ​​202 to a predetermined value (e.g., 1 or 0) so as not to affect the parity calculations performed by the corresponding parity circuits 212 and 222. Each mask 204 has a number of bits equal to the number of registers 132. For example, the mask 2041 includes a value (e.g., a bit) for each of the register values ​​202, the mask 2042 includes a value (e.g., a bit) for each of the register values ​​202, and the mask 2044 includes a value (e.g., a bit) for each of the register values ​​202. N includes values ​​(e.g., bits) for each of the register values ​​202. In one embodiment, the mask 204 corresponds to a read-write field, or a field where the value written to the register is predictable within the registers 132 of the register block 130. The mask 204 may be used to filter out bits within the registers 132 that may be unpredictable (e.g., have values ​​that may vary without the knowledge of the parity check circuitry 140). In one or more embodiments, the mask 204 may be hard coded.

[0029] In one embodiment, the parity circuit 2121 includes registers 1321-1322. N From register value 2021 to 202 N The parity circuit 2122 receives one or more first bits from the registers 1321 to 1322. N From register value 2021 to 202 N and a parity circuit 212 receiving one or more second bits from the N Registers 1321 to 132 N From register value 2021 to 202 NThe parity circuit 2121 receives the mask 2041, the parity circuit 2122 receives the mask 2042, and the parity circuit 212 N Mask 204 N The parity circuit 2221 receives the registers 1321 to 132 N From register value 2021 to 202 N The parity circuit 2222 receives one or more first register values ​​of the registers 1321 to 1322. N From register value 2021 to 202 N and a parity circuit 222 receiving one or more second register values ​​of N Registers 1321 to 132 N From register value 2021 to 202 N The parity circuit 2221 receives the mask 2041, the parity circuit 2222 receives the mask 2042, and the parity circuit 2223 receives the third register value. N Mask 204 N Receive.

[0030] Each of the parity circuits 212 and 222 determines a corresponding value 214, 224 from the corresponding register value 202 and the mask 204. N The parity circuit 2122 determines a value 2141 from the first bit of the register values ​​2021 to 202 N and the mask 2042 to determine the value 2142. N is the register value 2021~202 N and the third bit of mask 204 N From value 214 N The parity circuit 2221 determines the register values ​​2021 to 202 N The parity circuit 2222 determines a value 2241 from the first bit of the register 2021 to 2022 and the mask 2041. N and the mask 2042 to determine the value 2242. N is the register value 2021~202 Nand the third bit of mask 204 N From value 224 N Determine.

[0031] The error detection circuit 230 receives the values ​​214 and 224 from each of the parity circuits 212 and 222. The error detection circuit 230 determines the error signal 160 from the values ​​214 and 224. In one embodiment, the error detection circuit 230 processes the values ​​214 and 224 to determine the error signal 160. In one embodiment, the error detection circuit 230 determines the error signal 160 based on the monitor signal 206 being enabled and stops processing the values ​​214 and 224 to determine the error signal 160 based on the monitor signal 206 being disabled. The monitor signal 206 is received from the controller 110 or the control circuit 120 and is generated (e.g., enabled or disabled) by the controller 110 or the control circuit 120.

[0032] In one embodiment, a monitor signal is received by each of the parity circuits 212 and 222. In such an embodiment, one or more of the parity circuits 212 and 222 are disabled while one or more second parity circuits of the parity circuits 212 and 222 are enabled. The monitor signal may correspond to one or more of the registers 132. In one embodiment, if a monitor signal corresponds to two or more registers 132 (e.g., a group of registers 132), one or more of the parity circuits 212 and one or more of the parity circuits 222 receive the same monitor signal. Further, in such an embodiment, the monitoring functions of multiple registers 132 are disabled simultaneously such that multiple registers 132 may be written (e.g., changed or updated) during a common period. The enabled parity circuits 212 and 222 monitor the values ​​of the registers 132 while the disabled parity circuits 212 and 222 suspend monitoring the values ​​of the registers 132. Therefore, when parity circuits 212 and / or 222 are disabled, the disabled parity circuits do not generate values ​​to be used by error detection circuit 230 to detect invalid values ​​in registers 132 that the disabled parity circuits 212 and 222 are monitoring.

[0033] In one or more embodiments, the monitoring of the registers 132 via the parity circuits 212 and 222 may be controlled such that the registers 132 are monitored independently of one another. In such embodiments, multiple monitor signals are used to independently control the monitoring functions of the parity circuits 212 and 222. In one embodiment, the parity circuits 212, 222 associated with one or more first registers 132 are enabled based on one or more first monitor signals, while the parity circuits 212 and 222 associated with one or more second registers 132 are disabled based on one or more second monitor signals. Thus, one or more first registers 132 are monitored by the parity circuits 212 and 222, while one or more second registers 132 are not monitored, allowing the values ​​of one or more second registers 132 to be updated.

[0034] In one embodiment, two or more of the parity circuits 212 receive corresponding register values ​​202 and masks 204 and generate corresponding values ​​214 during at least partially overlapping time periods. For example, one or more of the parity circuits 212 generate values ​​224 during time periods that at least partially overlap with when one or more of the parity circuits 222 generate values ​​214. In other embodiments, two or more of the parity circuits 212 receive corresponding register values ​​202 and masks 204 and generate corresponding values ​​214 during non-overlapping time periods. In one embodiment, the parity circuits 212 generate values ​​in a pipelined manner.

[0035] In one embodiment, the parity check circuit 140 operates in the clock domain of the controller 110. In another embodiment, the parity check circuit 140 operates in the clock domain of the register 132. In one or more embodiments, the parity check circuit 140 operates in another clock domain. In an embodiment in which the parity check circuit 140 operates in the clock domain of the register 132, the register 132 outputs the output value 202 directly to the parity check circuit 140. In another embodiment, the parity check circuit 140 and one or more of the registers 132 operate in different clock domains. In such an embodiment, the parity check circuit 140 monitors the output of a synchronous circuit coupled to the register 132. For example, the parity check circuit 140 receives the register value 202 output by the synchronous circuit coupled to the register 132.

[0036] FIG. 3 illustrates a schematic circuit diagram of a parity circuit 300 according to one or more embodiments. The parity circuits 212 and 222 of FIG. 2 may be configured similarly to the parity circuit 300. In one embodiment, the parity circuit 300 receives a register value 302 from a register (e.g., one or more of the registers 132) and determines a value (e.g., the value 214 or the value 224) from the register value. The parity circuit 300 includes an AND gate 310, an XOR gate 312, a synchronization circuit 314, a latch circuit 316, and a comparison circuit 318. In one or more embodiments, other logic gates may be used in place of the logic gates illustrated in FIG. 3. For example, NAND gates may be used in place of the AND gates 310 and / or 318.

[0037] Each AND gate 310 receives a respective register value (e.g., register bit) from one or more registers and a value of a mask (e.g., mask bit). For example, AND gate 3101 receives a first register value (e.g., register value 3021) of register value 302 and a first mask value (e.g., mask bit 3041) of mask 304. Register value 302 is a combination of register values ​​2021-202 in FIG. N2. The mask 304 corresponds to one or more of the masks 2041 to 204 in FIG. N In one embodiment, register values ​​302 correspond to the register values ​​of a subset of registers 132.

[0038] Each AND gate 310 generates a signal 311 based on a comparison of the register value to the mask value. Additionally, each AND gate 310 receives a bit from each of the registers 132. For example, each AND gate 310 receives a bit in the same position of the value 202 of each of the registers 132. For example, AND gate 3101 receives the first bit of the value 2021. Additionally, AND gate 310 N returns the value 202. N In one embodiment, register block 130 includes an array of registers 132 that include a plurality of bits. In such an embodiment, each AND gate 310 receives a bit from each register 132, where each bit is in the same position within each register 132.

[0039] Signal 311 may be referred to as an intermediate value. In one embodiment, AND gate 3101 generates signal 3111 based on register value 3021 (e.g., the first bit of register value 2021) and mask bit 3041, and AND gate 310 N is the register value 302 N (For example, register value 202 N 1st bit of 304), and mask bit 304 N Based on signal 311 N AND gate 3101 generates signal 3111 having a logic value of 1 based on register value 3021 and mask bit 3041 having a logic value of 1, and generates signal 3111 having a logic value of 0 based on register value 3021 and / or mask bit 3041 having a logic value of 0. In one embodiment, mask bit 3041 having a logic value of 0 generates an output of AND gate 3101 having a logic value of 0. The value of mask 304 corresponds to the type of data stored in the corresponding register.

[0040] AND Gate 310N is the register value 302 N , and a mask bit (e.g., value) 304 having a logical value of 1. N Based on this, the signal 311 having a logic value of 1 N Generates register value 302 N , and / or a mask bit 304 having a logical value of 0 N Based on this, the signal 311 having a logic value of 0 N For example, mask bit 304 has a logical value of 0. N 3, which is an AND gate 310 having a logic value of 0. N Generates the output:

[0041] In various embodiments, by selectively setting bits of mask 304 to a logic value of 0, the output of AND gate 310 is controlled to have a logic value of 0. Thus, the mask value can control the logic value of signal 311, which is used in the subsequent parity calculation.

[0042] Signal 311 is output to XOR gate 312. The XOR gate outputs signal 313 based on the comparison of signals 311. For example, the XOR gate outputs signal 313 having a logic value 1 if the number of signals 313 having a logic value 1 is odd, and outputs logic value 313 having a logic value 0 if the number of signals 311 having a logic value 1 is even. Signal 313 may be referred to as a middle value. In one embodiment, signal 313 may be referred to as a parity signal in real time. In an embodiment where there are only two input signals to the XOR gate and the input signals have the same value of either a logic value 0 or a logic value 1, signal 313 has a logic value 0 and signals 3111 and 311 N have different values ​​(eg, either a logical value of 0 or 1), the logical value of signal 313 is 1. Signal 313 is output to a latch circuit 316 and a comparison circuit 318.

[0043] The synchronization circuit 314 receives the monitor signal 306 and monitors the monitor signal 306 to enable or disable the latch circuit 316 to output a signal 317. The synchronization circuit 314 enables the latch circuit 316 to output a signal 317 based on the monitor signal 306 being asserted, and disables the latch circuit 316 to output a signal 317 based on the monitor signal 306 being deasserted. Thus, the monitor signal 306 can enable or disable a corresponding monitoring function. The signal 317 is referred to as a parity signal, or a golden parity value. The signal 317 is a valid parity value (e.g., a known good parity value) for the parity circuit 300 and the corresponding register 132. For example, the logic value of the signal 317 is a valid parity value for the corresponding register 132, or a subset of the registers 132. The signal 317 is based on the value of the corresponding register 132. In one embodiment, the value of signal 317 may be received from controller 110, or control circuitry 120, or may be determined from one or more values ​​stored in a corresponding register. In one embodiment, the value of signal 317 is determined based on the value of the corresponding one or more registers 132 when monitor signal 306 enables a monitoring function of the corresponding one or more registers 132 (e.g., a rising edge of the monitor signal).

[0044] The monitor signal 306 is received by the parity circuit 300, which determines when to monitor the corresponding one or more registers 132 based on the value of the monitor signal 306. In one embodiment, the synchronization circuit 314 is omitted and the monitor signal 306 is received by a latch circuit 316 to enable or disable the monitoring function of the parity circuit 300. In such an embodiment, the monitor signal 306 is in the clock domain of the parity circuit 300.

[0045] The comparison circuit 318 receives the signals 313 and 317 and outputs a logical value 1 if the signals 313 and 317 both have the same value and outputs a logical value 0 if the signals 313 and 317 have different values. The comparison circuit 318 generates the value 214 or the value 224 indicating that there is an error in the register value 302 based on the signals 313 and 317 being unequal to each other. Furthermore, the comparison circuit 318 generates the value 214 or the value 224 indicating that the register value 302 is error-free based on the signals 313 and 317 being equal. The value 214 or the value 224 is output to an error detection circuit (e.g., the error detection circuit 230 of FIG. 2).

[0046] 4 illustrates a schematic block diagram of an error detection circuit 230 in accordance with one or more embodiments. In one embodiment, the error detection circuit 230 receives the value 214 and the value 224 and determines an error in a register (e.g., the register 132 of FIG. 2) and / or an error in a parity check circuit (e.g., the parity check circuit 140) based on a comparison of the values. The error detection circuit 230 includes an OR gate 410, an OR gate 420, an AND gate 430, and an XOR gate 440. In one or more embodiments, other logic gates may be used in place of the logic gates illustrated in FIG. 4. For example, a NAND gate may be used instead of the AND gate.

[0047] OR gate 410 receives value 214 from each of parity circuits 222, and OR gate 420 receives a value from each of parity circuits 212. Value 214 and value 224 are determined similarly to how value 214 was determined with respect to the description of FIG.

[0048] OR gate 410 generates a signal 412 based on a comparison of values ​​214. For example, the OR gate generates a signal 412 having a logical value 1 based on one or more of values ​​214 having a logical value 1, and generates a signal 412 having a logical value 0 based on each of values ​​214 having a logical value 0. Thus, if one or more of the values ​​indicates an error (e.g., have a logical value 1), OR gate 410 generates a signal 412 having a logical value 1 indicating that an error has been detected.

[0049] OR gate 420 generates signal 422 based on the comparison of values ​​224. For example, OR gate 420 generates signal 422 having a logical value 1 based on one or more of values ​​224 having a logical value 1, and generates signal 422 having a logical value 0 based on each of values ​​224 having a logical value 0. Thus, if one or more of the values ​​indicates an error (e.g., has a logical value 1), OR gate 420 generates signal 422 having a logical value 1 indicating that an error has been detected.

[0050] AND gate 430 receives signals 412 and 422 and generates signal 432 based on a comparison of signals 412 and 422. For example, AND gate 430 generates signal 432 having a logic value of 1 if signals 412 and 422 both have a logic value of 1. AND gate 430 generates signal 442 having a logic value of 0 based on one or more of signals 412 and 422 having a logic value of 0.

[0051] XOR gate 440 receives signals 412 and 422 and generates signal 442 based on a comparison of signals 412 and 422. For example, if only one of signals 412 and 422 has a logic value of 1, XOR gate 440 generates signal 442 having a logic value of 1. XOR gate 440 generates signal 442 having a logic value of 0 based on signals 412 and 422 having the same logic value (e.g., either a logic value of 1 or a logic value of 0).

[0052] In one embodiment, the parity calculation circuit 220 and the error detection circuit 230 determine whether a fault exists in the parity check circuit 140. For example, as described above, the parity calculation circuit 220 is configured similarly to the parity calculation circuit 210 and receives the same data (e.g., the register value 202 and the mask 204). The parity calculation circuit 220 can be referred to as being redundant with respect to the parity calculation circuit 210. Thus, if there is no fault in the parity check circuit 140, the signals 412 and 422 have the same value. If there is one or more faults in the parity check circuit 140, the signals 412 and 422 have different values. Thus, the combination of the AND gate 430 and the XOR gate 440 provides the two-bit error signal 160, which includes bits corresponding to the signals 432 and 442.

[0053] The value of signal 442 is used to determine whether signals 412 and 422 are the same (e.g., no error). For example, if signal 432 has a logic value of 0 and signal 442 has a logic value of 0, then signals 412 and 422 both have a logic value of 0. Thus, no error is detected in the corresponding IC device. Furthermore, if signal 432 has a logic value of 0 and signal 442 has a logic value of 1, then signals 412 and 422 have different values. Thus, signal 432 having a logic value of 0 and signal 442 having a logic value of 1 indicates that parity check circuit 140 has one or more faults.

[0054] Signals 432 and 442 are output from an IC device (e.g., IC device 100 of FIG. 1) as bits of error signal 160. Error signal 160 is provided to a processing system, which determines which corrective action, if any, to take. In one embodiment, a first bit of error signal 160 corresponds to the logical value of signal 432. Based on the first bit having a logical value of 1, an error in the register value is determined, and the processing system stops operation of IC device 100, resets IC device 100, or changes the register value of IC device 100, among other actions. A second bit of error signal 160 corresponds to the logical value of signal 442. Based on the first bit having a logical value of 0 and the second bit having a logical value of 1, the processing system determines that one or more faults exist in parity check circuit 140, and stops operation of IC device 100, resets IC device 100, or resets the value of parity check circuit 140, among other actions. Based on the first bit having a logical value of 0 and the second bit having a logical value of 0, the processing system determines that the register value and the parity check circuit 140 are error-free and takes no corrective action.

[0055] FIG. 5 illustrates a flow diagram of a method 500 for detecting errors in register values ​​of a register block, in accordance with one or more embodiments. FIG. 5 is described with reference to FIGS. 2 and 4. In block 510, a first value for a subset of the register values ​​of the registers is determined. For example, the parity circuit 2121 determines a first value for a subset of the register values ​​of the registers. N From register value 2021 to 202 N 1. The parity circuit 2121 further receives a mask 2041. The mask 2041 is received from a controller (e.g., the controller 110 in FIG. 1) or a control circuit (e.g., the control circuit 120 in FIG. 1). The parity circuit 2121 receives one or more bits (e.g., values) from each of the register values ​​2021-202. NCompare each bit (e.g., value) of each of them with the value of mask 2041 to determine the register value to be used in the calculation of value 2141. Use the value of mask 2041 to set the corresponding value of register value 202 to a known value (e.g., a value of 1 or 0) for parity calculation. Parity circuit 2121 compares the value (bit) from each of register values 2021 - 202 N with the corresponding value of the mask (e.g., logical AND or another logical operation), generates a plurality of signals (e.g., signal 311), and by comparing these signals with each other, determines whether the number of signals having a logical value of 1 is odd or even. In one embodiment, based on the determination that the number of signals having a logical value of 1 is odd, a signal having a logical value of 1 is output, and based on the determination that the number of signals having a logical value of 1 is even, a signal having a logical value of 0 is output. Referring to FIG. 3, this signal is 313. Compare this signal with the corresponding golden parity signal (e.g., signal 317) to determine the parity mismatch and / or change between parity circuit 2121 and register 1321. In one embodiment, parity circuit 2121 determines value 2141 based on the corresponding monitor signal that is asserted. This value has a logical value of 1 when the signals are the same (i.e., the register has a valid value), and has a logical value of 0 when the signals are different (i.e., the register has an invalid value).

[0056] In block 520, a second value regarding the second register subset is determined. For example, parity circuit 2122 receives a second value (e.g., a second bit) from register values 2021 - 202 N from register 132. Further, parity circuit 2122 receives mask 2042. Mask 2042 is received from a controller (e.g., controller 110 of FIG. 1) or a control circuit (e.g., control circuit 120 of FIG. 1). Parity circuit 2122 receives register values 2021 - 202 NThe second value of each of the registers 2022 is compared to a value of the mask 2042 to determine a register value to be used in the calculation of the value 2142. The value of the mask 2042 is used to set the corresponding value of the register value 202 to a known value (e.g., a value of 1 or 0) for the parity calculation. The parity circuit 2122 compares each register value 2022 to a corresponding value of the mask to generate a number of signals (e.g., signal 311) and compares these signals to each other to determine whether the number of signals having a logic 1 value is odd or even. In one embodiment, a signal having a logic 1 value is output based on the number of signals having a logic 1 value being determined to be odd, and a signal having a logic 0 value is output based on the number of signals having a logic 1 value being determined to be even. With reference to FIG. 3, this signal is signal 313. This signal is compared to a corresponding golden parity signal (e.g., signal 317) to determine discrepancies and / or changes in the parity of the parity circuit 2122 and the register 1322. In one embodiment, parity circuit 2122 determines a value 2142 based on the corresponding monitor signal being asserted, which has a logic value of 1 if the signals are the same (i.e., the registers have valid values) and a logic value of 0 if the signals are different (i.e., the registers have invalid values).

[0057] At block 530, errors are detected in the plurality of registers based on the first value and the second value. For example, the error detection circuit 230 compares the values ​​2141 and 2142. If either of the values ​​2141 and 2142 indicate an error in the value of the corresponding register, then at block 540 the parity check circuit 140 outputs an error signal 160 indicating an error. If neither of the values ​​2141 and 2142 indicate an error in the value of the corresponding register, then at block 540 the parity check circuit 140 outputs an error signal 160 indicating no error exists in the register.

[0058] Hardware-based techniques for detecting erroneous value changes (e.g., invalid values) to values ​​in control registers of an IC device are described above. For example, a parity check circuit monitors the control registers such that erroneous value changes to the register values ​​are detected before they adversely affect the operation of the IC device. The parity check circuit generates values ​​for a subset of the registers and uses the values ​​to determine whether an error exists in the values ​​of the control registers.

[0059] While the above is directed to particular examples, other and further embodiments may be devised without departing from the basic scope thereof, which is determined by the following claims.

Claims

1. 1. An integrated circuit (IC) device comprising: A plurality of registers; a parity check circuit coupled to the plurality of registers, a first parity circuit configured to receive first register values ​​from the plurality of registers and to determine a first value from the first register values; a second parity circuit configured to receive second register values ​​from the plurality of registers and to determine a second value from the second register values; An error detection circuit, comprising: comparing the first value to the second value to detect a first error in the plurality of registers; and an error detection circuit configured to perform a parity check circuit and an error detection circuit configured to perform an error signal indicative of the first error.

2. The parity check circuit is a third parity circuit configured to receive the first register value and to determine a third value from the first register value; 2. The IC device of claim 1 , further comprising: a fourth parity circuit configured to receive the second register value and determine a fourth value from the second register value, wherein the error detection circuit is further configured to detect a second error within the parity check circuit based on the first value, the second value, the third value, and the fourth value.

3. The error detection circuit detects the second error as: generating a first signal based on a comparison of the first value and the second value; generating a second signal based on a comparison of the third value and the fourth value; 3. The IC device of claim 2, configured to detect by: comparing the first signal with the second signal.

4. 2. The IC device of claim 1, wherein the first parity circuit is configured to determine the first value by applying a mask to the first register values ​​to determine a first intermediate value, the mask including mask values, each of the first register values ​​corresponding to a respective one of the mask values.

5. The first parity circuit determines the first value as: determining a second intermediate value based on the first intermediate value; The IC device of claim 4 , further configured to determine by: comparing the second intermediate value to a valid value.

6. 2. The IC device of claim 1, wherein the parity check circuitry is configured to determine the first value based on a monitor enable signal.

7. 2. The IC device of claim 1, wherein the first value is determined during a first time period and the second value is determined during a second time period, the first and second time periods being non-overlapping.

8. A parity check circuit, a first parity circuit configured to receive first register values ​​from a plurality of registers and to determine a first value from the first register values; a second parity circuit configured to receive second register values ​​from the plurality of registers and to determine a second value from the second register values; An error detection circuit, comprising: comparing the first value to the second value to determine a first error in the plurality of registers; outputting an error signal indicative of the first error; and an error detection circuit configured to perform the above steps.

9. a third parity circuit configured to determine a third value from the first register value; 9. The parity check circuit of claim 8, further comprising: a fourth parity circuit configured to determine a fourth value from the second register value, wherein the error detection circuit is further configured to determine a second error within the parity check circuit based on the first value, the second value, the third value, and the fourth value.

10. The error detection circuit detects the second error as: generating a first signal based on a comparison of the first value and the second value; generating a second signal based on a comparison of the third value and the fourth value; 10. The parity check circuit of claim 9, configured to determine by: comparing the first signal with the second signal.

11. 9. The parity check circuit of claim 8, wherein the first parity circuit is configured to determine the first value by applying a mask to the first register values ​​of a first subset of the plurality of registers to determine a first intermediate value, the mask including mask values, each of the first register values ​​corresponding to a respective one of the mask values.

12. The first parity circuit determines the first value as: determining a second intermediate value based on the first intermediate value; 12. The parity check circuit of claim 11, configured to determine by: comparing the second intermediate value with a valid value.

13. 9. The parity check circuit of claim 8, wherein the first parity circuit is configured to determine the first value during a first time period and the second parity circuit is configured to determine the second value during a second time period, the first and second time periods being non-overlapping.

14. 1. A method comprising: determining, by a first parity circuit of a parity check circuit of an integrated circuit (IC) device, a first value from first register values ​​of a plurality of registers of the IC device; determining a second value from second register values ​​of the plurality of registers by a second parity circuit of the parity check circuit; comparing the first and second values ​​to determine a first error in the plurality of registers; and outputting an error signal indicative of the first error.

15. determining a third value from the first register value by a third parity circuit of the parity check circuit; determining a fourth value from the second register value by a fourth parity circuit of the parity check circuit; determining a second error in the parity check circuitry based on the first value, the second value, the third value, and the fourth value, wherein determining the second error comprises: generating a first signal based on a comparison of the first value and the second value; generating a second signal based on a comparison of the third value and the fourth value; and comparing the first signal to the second signal.

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