Double-sided redistribution layer (RDL) substrate for passive and device integration.

Abstract

The device includes a redistribution layer (RDL) substrate. The device also includes passive components in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate opposite the first surface of the RDL substrate.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application Publication No. 17 / 579,038, filed January 19, 2022, entitled "DOUBLE-SIDED REDISTRIBUTION LAYER (RDL) SUBSTRATE FOR PASSIVE AND DEVICE INTEGRATION," the disclosure of which is expressly incorporated by reference in its entirety into this specification.

[0002] Aspects of the present disclosure relate to semiconductor devices, and more particularly, to wafer-level double-sided redistribution layer (RDL) substrates for integration of passive and active devices. [Background technology]

[0003]

[0003] Wireless communication devices incorporate radio frequency (RF) modules that facilitate the communications and features that users expect. As wireless systems become more prevalent and include more capabilities, chips become more complex. Fifth generation (5G) new radio (NR) wireless communication devices incorporate the latest generation of electronic dies housed in smaller modules with smaller interconnects. Design challenges include integrating passive and active devices to implement RF front-end modules (FEMs).

[0004]

[0004] An RF front-end module may be implemented by integrating RF filters, active devices, and surface-mount technology (SMT) devices on a laminate substrate. These RF filters, active devices, and SMT devices are conventionally arranged in a side-by-side package configuration supported by a laminate substrate. Unfortunately, these conventional side-by-side on-package stacking configurations are limited by the reduction of form factors of future applications in terms of XY size and Z height. That is, the XY size and Z height dimensions of the conventional side-by-side on-package stacking configuration exceed the form factor of future RF front-end module applications. An RF front-end implementation that meets the reduced XY size and Z height dimensions specified by the form factor of future RF front-end module applications is desired. Summary of the Invention

[0005] The device includes a redistribution layer (RDL) substrate. The device also includes passive components in the RDL substrate proximate a first surface of the RDL substrate. The device further includes a first die coupled to a second surface of the RDL substrate opposite the first surface of the RDL substrate.

[0006] A method for fabricating a device is described. The method includes forming a redistribution layer (RDL) substrate on a carrier glass substrate. The method also includes forming passive components in an interlayer dielectric (ILD) layer of the RDL substrate proximate a first surface of the RDL substrate and the carrier glass substrate. The method further includes bonding a first die to a second surface of the RDL substrate opposite the first surface of the RDL substrate. The method also includes removing the carrier glass substrate from the first surface of the RDL substrate.

[0007]

[0007] The above has outlined rather broadly the features and technical advantages of the present disclosure in order to better understand the detailed description that follows. Additional features and advantages of the present disclosure are described below. Those skilled in the art will appreciate that the present disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also recognize that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features believed to be characteristic of the present disclosure, both with respect to its composition and its method of operation, together with further objects and advantages, will be better understood by considering the following description in conjunction with the accompanying drawings. It should be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only, and is not intended to define the scope of the present disclosure. [Brief description of the drawings]

[0008] For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Figure 1]

[0009] FIG. 1 is a schematic diagram of a radio frequency front-end (RFFE) module employing active and passive devices. [Diagram 2]

[0010] FIG. 1 is a schematic diagram of a radio frequency front-end (RFFE) module employing active and passive devices in a chipset. [Diagram 3]

[0011] FIG. 1 is a block diagram illustrating a cross-sectional view of a radio frequency front-end (RFFE) module including a semiconductor die and an integrated passive device (IPD) filter die, in accordance with an embodiment of the present disclosure. [Figure 4A]

[0012] FIG. 1 is a block diagram illustrating a radio frequency front-end (RFFE) module including a wafer-level double-sided redistribution layer (RDL) substrate for integration of passive and active devices, according to an aspect of the disclosure. [Figure 4B] FIG. 1 is a block diagram illustrating a radio frequency front-end (RFFE) module including a wafer-level double-sided redistribution layer (RDL) substrate for integration of passive and active devices, according to an aspect of the disclosure. [Figure 4C] FIG. 1 is a block diagram illustrating a radio frequency front-end (RFFE) module including a wafer-level double-sided redistribution layer (RDL) substrate for integration of passive and active devices, according to an aspect of the disclosure. [Figure 5A]

[0013] FIG. 4B is a block diagram further illustrating the radio frequency front end (RFFE) module of FIG. 4A according to an embodiment of the disclosure. [Figure 5B] FIG. 4B is a block diagram further illustrating the radio frequency front end (RFFE) module of FIG. 4A according to an embodiment of the disclosure. [Figure 5C] FIG. 4B is a block diagram further illustrating the radio frequency front end (RFFE) module of FIG. 4A according to an embodiment of the disclosure. [Figure 6A]

[0014] FIG. 4B is a block diagram further illustrating the radio frequency front end (RFFE) module of FIG. 4A according to an embodiment of the disclosure. [Figure 6B] FIG. 4B is a block diagram further illustrating the radio frequency front end (RFFE) module of FIG. 4A according to an embodiment of the disclosure. [Figure 7A]

[0015] 1A-1C are block diagrams illustrating various options for assembling a redistribution layer (RDL) substrate and an active die to form a radio frequency front end (RFFE) module, according to aspects of the disclosure. [Figure 7B] 1A-1C are block diagrams illustrating various options for assembling a redistribution layer (RDL) substrate and an active die to form a radio frequency front end (RFFE) module, according to aspects of the disclosure. [Figure 7C] 1A-1C are block diagrams illustrating various options for assembling a redistribution layer (RDL) substrate and an active die to form a radio frequency front end (RFFE) module, according to aspects of the disclosure. [Figure 7D] 1A-1C are block diagrams illustrating various options for assembling a redistribution layer (RDL) substrate and an active die to form a radio frequency front end (RFFE) module, according to aspects of the disclosure. [Figure 8A]

[0016] 1 is a block diagram illustrating an assembly process for forming a radio frequency front end (RFFE) module fixed to a mobile motherboard according to an aspect of the disclosure. [Figure 8B] 1 is a block diagram illustrating an assembly process for forming a radio frequency front end (RFFE) module fixed to a mobile motherboard according to an aspect of the disclosure. [Figure 8C] 1 is a block diagram illustrating an assembly process for forming a radio frequency front end (RFFE) module fixed to a mobile motherboard according to an aspect of the disclosure. [Figure 9A]

[0017] FIG. 1 is a block diagram illustrating a radio frequency (RF) filter including a redistribution layer (RDL) substrate, according to an aspect of the present disclosure. [Figure 9B] FIG. 1 is a block diagram illustrating a radio frequency (RF) filter including a redistribution layer (RDL) substrate, according to an aspect of the present disclosure. [Figure 9C] FIG. 1 is a block diagram illustrating a radio frequency (RF) filter including a redistribution layer (RDL) substrate, according to an aspect of the present disclosure. [Figure 10A]

[0018] FIG. 1 is a block diagram illustrating a process for fabricating a radio frequency front end (RFFE) module including a redistribution layer (RDL) substrate according to an aspect of the present disclosure. [Figure 10B] FIG. 1 is a block diagram illustrating a process for fabricating a radio frequency front end (RFFE) module including a redistribution layer (RDL) substrate according to an aspect of the present disclosure. [Figure 10C] FIG. 1 is a block diagram illustrating a process for fabricating a radio frequency front end (RFFE) module including a redistribution layer (RDL) substrate according to an aspect of the present disclosure. [Figure 11]

[0019] FIG. 1 is a process flow diagram illustrating a method for fabricating a radio frequency front end (RFFE) module including a redistribution layer (RDL) substrate according to an embodiment of the present disclosure. [Figure 12]

[0020] FIG. 1 is a block diagram illustrating an example wireless communication system in which the configurations of the present disclosure may be advantageously employed. [Figure 13]

[0021] FIG. 1 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of semiconductor components according to one configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0022] The following detailed description, taken in conjunction with the accompanying drawings, is intended as an illustration of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details intended to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0010]

[0023] As described herein, the use of the term "and / or" is intended to indicate an "inclusive or," and the use of the term "or" is intended to indicate an "exclusive or." The term "exemplary" as used throughout this description means "serving as an example, instance, or illustration," and should not necessarily be construed as preferred or advantageous over other exemplary configurations. The term "coupled" as used throughout this description means "connected directly or indirectly through an intervening electrical, mechanical, or other connection (e.g., a switch)," and is not necessarily limited to a physical connection. In addition, a connection can be such that the objects are permanently connected or releasably connected. A connection can be through a switch. The term "adjacent" as used throughout this description means "adjacent, in close proximity, next to, or nearby." The term "on" as used throughout this description means "directly on" in some configurations and "indirectly on" in other configurations.

[0011]

[0024] Wireless communication devices incorporate radio frequency (RF) modules that facilitate the communications and features that users expect. As wireless systems become more prevalent and include more capabilities, chips become more complex. For example, mobile RF chips (e.g., mobile RF transceivers) are moving to deep sub-micron process nodes due to cost and power consumption considerations. Mobile RF transceiver designs are complicated by added circuit functions to support enhanced communications, such as fifth generation (5G) new radio (NR) communication systems. In particular, 5G NR wireless communication devices incorporate the latest generation of electronic dies housed in smaller modules with smaller interconnects. Design challenges include integrating passive and active devices to implement RF front-end modules (FEMs).

[0012]

[0025] RF filters in mobile RF transceivers may include high performance capacitor and inductor components. For example, RF filters use various types of passive devices, such as integrated capacitors and integrated inductors. Integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, pn junction capacitors, metal-insulator-metal (MIM) capacitors, poly-poly capacitors, metal-oxide-metal (MOM) capacitors, and other similar capacitor structures. Capacitors are generally passive elements used in integrated circuits to store charge. For example, parallel plate capacitors are often made using plates or structures that are conductive with an insulating material between the plates.

[0013]

[0026] An inductor is an example of an electrical device used to temporarily store energy in a magnetic field in a coil of wire according to an inductance value, which is a measure of the ratio of voltage to the rate of change of current passing through the inductor. When the current flowing through the inductor changes, energy is temporarily stored in the magnetic field in the coil. In addition to their magnetic field storage capabilities, inductors are often used in alternating current (AC) electronic devices, such as wireless devices. For example, mobile RF transceiver designs include using inductors with improved inductance density while reducing magnetic losses at millimeter wave (mmW) frequencies (e.g., frequency range two (FR2)).

[0014]

[0027] A radio frequency front-end (RFFE) module may include a 5G broadband FR2 filter including MIM capacitors and inductors. In practice, the RFFE module may be implemented by integrating RF filters, active devices, and surface mount technology (SMT) devices on a laminate substrate. These RF filters, active devices, and SMT devices are conventionally arranged in a side-by-side package configuration supported by a laminate substrate. Unfortunately, this conventional side-by-side on-package stacking configuration is limited by the reduction in form factor of future RF applications in terms of XY size and Z height reduction. That is, the XY size and Z height dimensions of the conventional side-by-side on-package stacking configuration exceed the form factor of future RFFE module applications. An RFFE implementation that meets the reduced XY size and Z height dimensions specified by the form factor of future RFFE module applications is desired.

[0015]

[0028] Various aspects of the present disclosure provide a wafer-level double-sided redistribution layer (RDL) substrate for the integration of passive and active devices. The process flow for fabricating the RDL substrate may include wafer-level processes such as front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) processes. It should be understood that the term "layer" includes films and is not to be construed as indicating vertical or horizontal thickness unless otherwise stated. As described, the term "substrate" may refer to the substrate of a diced or undiced wafer. Similarly, the terms "chip" and "die" may be used interchangeably.

[0016]

[0029] As described, a back-end-of-line (BEOL) interconnect layer may refer to a conductive interconnect layer (e.g., first interconnect layer (M1) or metal 1 M1, metal 2 (M2), metal 3 (M3), metal 4 (M4), etc.) for electrically coupling to a front-end-of-line active device of an integrated circuit. Various BEOL interconnect layers are formed in corresponding BEOL interconnect layers where a lower BEOL interconnect layer uses a thinner metal layer compared to an upper BEOL interconnect layer. The BEOL interconnect layer may be electrically coupled to a middle-of-line (MOL) interconnect layer, for example, may connect M1 to an oxide diffusion (OD) layer of the integrated circuit. The MOL interconnect layer may include a zero interconnect layer (M0) for connecting M1 to an active device layer of the integrated circuit. A BEOL first via (V2) may connect M2 to M3 or other layers of the BEOL interconnect layer. BEOL vias may also provide via pads (VP) to support package (or device) interconnects, such as package balls.

[0017]

[0030] According to an embodiment of the present disclosure, the RFFE module includes a redistribution layer (RDL) substrate. Additionally, the RFFE module includes a passive component in the RDL substrate proximate a first surface of the RDL substrate. In some embodiments of the present disclosure, the RFFE module includes a first die coupled to a second surface of the RDL substrate opposite the first surface of the RDL substrate. In some embodiments of the present disclosure, the RFFE module includes a second die coupled to the passive component opposite the first die. In a multi-die configuration, the RFFE module includes a third die coupled to the passive component opposite the first die proximate the second die. In some embodiments of the present disclosure, the first die, the second die, and the third die may provide active components of the antenna module, such as an RF switch.

[0018]

[0031] FIG. 1 is a schematic diagram of a radio frequency front-end (RFFE) module 100 employing a redistribution layer (RDL) substrate that integrates active and passive devices according to an embodiment of the disclosure. The RFFE module 100 includes a power amplifier 102, a duplexer / filter 104, and a radio frequency (RF) switch module 106. The power amplifier 102 amplifies a signal(s) to a certain power level for transmission. The duplexer / filter 104 filters input and output signals according to a variety of different parameters, including frequency, insertion loss, rejection, or other similar parameters. Additionally, the RF switch module 106 may select a particular portion of the input signal to pass to the remainder of the RFFE module 100.

[0019]

[0032] The radio frequency front-end (RFFE) module 100 also includes a tuner circuit 112 (e.g., a first tuner circuit 112A and a second tuner circuit 112B), a diplexer 190, a capacitor 116, an inductor 118, a ground terminal 115, and an antenna 114. The tuner circuit 112 (e.g., a first tuner circuit 112A and a second tuner circuit 112B) includes components such as a tuner, a portable data entry terminal (PDET), and a housekeeping analog-to-digital converter (HKADC). The tuner circuit 112 may perform impedance tuning (e.g., voltage standing wave ratio (VSWR) optimization) for the antenna 114. The RFFE module 100 also includes a passive combiner 108 coupled to a wireless transceiver (WTR) 120. The passive combiner 108 combines the detected power from the first tuner circuit 112A and the second tuner circuit 112B. The wireless transceiver 120 processes the information from the passive combiner 108 and provides the information to a modem 130 (e.g., a mobile station modem (MSM)). The modem 130 provides a digital signal to an application processor (AP) 140.

[0020]

[0033] As shown in FIG. 1, the diplexer 190 is located between the tuner components of the tuner circuit 112 and the capacitor 116, the inductor 118, and the antenna 114. The diplexer 190 may be disposed between the antenna 114 and the tuner circuit 112 to provide high system performance from the radio frequency front end (RFFE) module 100 to a chipset including the wireless transceiver 120, the modem 130, and the application processor 110. The diplexer 190 also performs frequency domain multiplexing for both high and low band frequencies. After the diplexer 190 performs its frequency multiplexing function on the input signal, the output of the diplexer 190 is sent to an optional inductor / capacitor (LC) network including the capacitor 116 and the inductor 118. The LC network may provide additional impedance matching components for the antenna 114, if necessary. A signal having a particular frequency is then transmitted or received by the antenna 114. Although single capacitors and inductors are shown, multiple components are also contemplated.

[0021]

[0034] 2 is a schematic diagram of a radio frequency integrated circuit (RFIC) chip 200 having a wireless local area network (WLAN) (e.g., Wi-Fi) module 150 and a radio frequency front-end (RFFE) module 170 for a chipset 210. The Wi-Fi module 150 includes a first diplexer 162 that communicatively couples an antenna 164 to a WLAN module 152. The first RF switch 160 communicatively couples the first diplexer 162 to the WLAN module 152. The RFFE module 170 includes a second diplexer 190 that communicatively couples an antenna 192 to a wireless transceiver (WTR) 120 via a duplexer 172. The second RF switch 180 communicatively couples the second diplexer 190 to the duplexer 172.

[0022]

[0035] The WTR 120 and the WLAN module 152 of the Wi-Fi module 150 are coupled to a modem (Mobile Station Modem (MSM), e.g., a baseband modem) 130, which is powered by a power source 202 via a power management integrated circuit (PMIC) 140. The chipset 210 also includes capacitors 144 and 148 and inductor(s) 146 to provide signal integrity. Each of the PMIC 140, the modem 130, the WTR 120, and the WLAN module 152 includes a capacitor (e.g., 142, 132, 122, and 154) and operates according to a clock 204. Additionally, the inductor 146 couples the modem 130 to the PMIC 140. The shape and arrangement of the various inductor and capacitor components in the RFIC chip 200 may reduce electromagnetic coupling between the components.

[0023]

[0036] The WTR 120 of the wireless device generally includes a mobile RF transceiver for transmitting and receiving data for bidirectional communication. The WTR 120 and the RFFE module 170 may be implemented using high-performance complementary metal oxide semiconductor (CMOS) RF switch technologies to implement the switch transistors of the first RF switch 160 and the second RF switch 180. The RFFE module 170 may utilize these high-performance CMOS RF switch technologies to implement active dies for good operation. In practice, the active dies used to implement the CMOS RF switch technologies may involve integration with passive RF filters to implement an antenna module, for example, as shown in FIG. 3.

[0024]

[0037] FIG. 3 is a block diagram illustrating a cross-sectional view of a radio frequency front-end (RFFE) module 300 including a semiconductor die and an integrated passive device (IPD) filter die according to an embodiment of the disclosure. In this example, the RFFE module 300 includes a semiconductor die 350 and an IPD filter die 320 supported by a package substrate 310 (e.g., a laminate substrate). The semiconductor die 350 may be an active die having a semiconductor substrate 360 ​​(e.g., an active silicon substrate) coupled to package balls 302 via a back-end-of-line (BEOL) layer 370. The BEOL layer 370 includes multiple BEOL metallization layers (M1, M2, M3, ..., Mn) on the semiconductor substrate 360 ​​(e.g., a diced silicon wafer). An interconnect layer 312 is coupled to the package balls 302.

[0025]

[0038] The IPD filter die 320 includes a substrate 330 (e.g., a passive substrate) coupled to package balls 302 via a back-end-of-line (BEOL) layer 340 and a redistribution layer (RDL) 342. The interconnect layer 312 is coupled to the IPD filter die 320 via the package balls 302. In some aspects of the disclosure, the substrate 330 is constructed of glass, and the IPD filter die 320 is a glass-substrate integrated passive device (GIPD) filter die. In practice, the RFFE module 300 integrates the IPD filter die 320, a semiconductor die 350, and a surface mount technology (SMT) device on a package substrate 310 (e.g., a laminate). The IPD filter die 320, the semiconductor die 350, and the SMT device (not shown) are arranged in a side-by-side package configuration supported by the package substrate 310. Unfortunately, this side-by-side on package substrate configuration is limited by the reduced form factor of future RF applications in terms of reduced XY size and Z height. That is, the XY size and Z height dimensions of the conventional side-by-side on package stack configuration exceed the form factor of future RFFE module applications. RFFE implementations that meet the reduced XY size and Z height dimensions dictated by the form factor of future RFFE module applications are shown, for example, in Figures 4A-4C.

[0026]

[0039] 4A-4C are block diagrams illustrating a radio frequency front-end (RFFE) module including a wafer-level double-sided redistribution layer (RDL) substrate for integration of passive and active devices according to an embodiment of the present disclosure. Typically, the RFFE module 400 includes an RDL substrate constructed from an interlayer dielectric (ILD) layer 404 constructed from, for example, polyimide. In some embodiments of the present disclosure, the ILD layer 404 includes a metal-insulator-metal (MIM) capacitor C and an inductor L formed from back-end-of-line layers (BEOLs) M1, M2, M3, and M4. The ILD layer 404 also includes a first redistribution layer (RDL1) to complete the RDL substrate 402. In this example, the MIM capacitor C is formed using plates of M1 and M2 metallization layers under the metallization layer M3 using an insulating layer (I) that is not present during the fabrication of an organic laminate substrate, such as silicon nitride (SiN) or other similar dielectric material. Capacitor C and inductor L provide passive components that may be interconnected to provide the RF filter and surface mount technology (SMT) matched passive components of RFFE module 400.

[0027]

[0040] 4A, according to an embodiment of the disclosure, the RFFE module 400 further includes a first active die 420 coupled to the RDL substrate 402 using flip-chip bonding. In this example, package balls 422 (e.g., device interconnects) secure the first active die 420 to the landing pads of the first RDL 1 and the inductor L. Additionally, the first active die 420 is encapsulated in a molding compound 430, such as an epoxy molding compound. In some embodiments of the disclosure, the first active die 420 implements an antenna module that includes active components such as an RF switch and / or a low noise amplifier.

[0028]

[0041] In some aspects of the disclosure, the RDL substrate 402 provides a double-sided substrate that allows for integration of RF filters, SMT passive component matching, and stacked routing / inductors. Advantages of the RDL substrate 402 include a significant (e.g., 2x) reduction in size of the RFFE module 400 in the XY dimensions. In addition, the RDL substrate 402 also allows for a significant (e.g., 2x) reduction in Z height. For example, a four layer (4L) stacked package substrate may have a thickness of 260 microns compared to the 50 micron thickness of the RDL substrate 402. Eliminating the stacked package substrate by using the RDL substrate 402 can reduce both the cost and size of the RFFE module 400 while providing performance comparable to a side-by-side-on stacked package substrate RFFE module configuration.

[0029]

[0042] 4B is a block diagram illustrating an RFFE module 440 including an RDL substrate 402 for integration of passive and active devices according to an alternative embodiment of the present disclosure. Typically, the RFFE module 440 includes similar components as the RFFE module 400 of FIG. 4A, which are identified using the same reference numerals. In this alternative configuration, the first active die 420 is bonded to the RDL substrate 402 using through via pads (VP) using metal-metal direct bonding, or metal-metal or metal-semiconductor eutectic bonding.

[0030]

[0043] 4C is a block diagram illustrating an RFFE module 450 including an RDL substrate 402 for integration of passive and active devices according to an alternative embodiment of the present disclosure. The RFFE module 450 includes similar components as the RFFE module 440 of FIG. 4B, which are identified using the same reference numbers. In addition, the first active die 420 is bonded to the RDL substrate 402 using through VP with metal-metal direct bonding, metal-metal or metal-semiconductor eutectic bonding, or other similar thermo-compression bonding. In these alternative embodiments of the present disclosure, a backgrinding process is applied to the molding compound to further reduce the Z-height of the RFFE module 450.

[0031]

[0044] 5A-5C are block diagrams further illustrating the RFFE module 400 of FIG. 4A according to an embodiment of the disclosure. As shown in FIG. 5A, an RFFE module 500 is shown in which the XY dimensions of the RDL substrate 402 are larger than the XY dimensions of the first active die 420 to accommodate additional passive components. This configuration of the RDL substrate 402 is similar to the configuration shown in FIG. 4A and is described using similar reference numbers. In this example, the RDL substrate 402 includes a first RDL 1, a second RDL 2, and a third RDL 3 coupled to a 3D inductor 460. In some embodiments of the disclosure, the 3D inductor 460 is comprised of through mold vias (TMVs) 410 coupled to the second RDL 2 and the third RDL 3 and bonded together via conductive traces 462 on the surface of the molding compound 430. In this example, package balls 422 also secure the first active die 420 to the landing pads of the first RDL1 and the inductor L.

[0032]

[0045] FIG. 5B illustrates an RFFE module 540 in a multi-active die configuration according to an embodiment of the disclosure. This configuration of the RFFE module 540 is similar to the configuration shown in FIG. 4A and is described using similar reference numbers. In this example, the RDL substrate 402 also includes a second RDL 2 and a third RDL 3 coupled to a 3D inductor 460. The 3D inductor 460 is also coupled to the second RDL 2 and the third RDL 3 and is composed of a TMV 410 (e.g., a first TMV and a second TMV) bonded to each other via a conductive trace 462 on the surface of the molding compound 430. In some embodiments of the disclosure, a ball grid array (BGA) 412 is coupled to the conductive trace 462. In addition, package balls 422 also secure the first active die 420 to the first RDL 1 and the landing pad of the inductor L.

[0033]

[0046] In some aspects of the disclosure, the antenna module function of the first active die 420 of FIG. 4A is separated to provide a second active die 470 and a third active die 480. The first active die 420, the second active die 470, and the third active die 480 may be implemented as silicon (Si) or III-V material active dies. Alternatively, one of these active dies is implemented as a passive die or an acoustic die, but this configuration is unlikely due to the hermetic sealing specifications of acoustic / micro-electromechanical system (MEMS) devices. In addition, the connection of the active die and the passive components may be performed using flip-chip bonding or copper-copper (Cu-Cu) bonding (not shown). In some aspects of the disclosure, the first active die 420 provides an RF switch die, the second active die 470 provides a low noise amplifier (LNA) die, and the third active die 480 is implemented as a gallium arsenide (GaAs) die. In this example, package balls 472 secure the second active die 470 to the landing pads of the first RDL1 and the second RDL2. In addition, package balls 482 also secure the third active die 480 to the landing pads of the second RDL1 and the inductor L. The molding compound 430 encapsulates the second active die 470 and the third active die 480.

[0034]

[0047] FIG. 5C illustrates an RFFE module 550 in a multi-active die configuration according to an embodiment of the disclosure. This configuration of the RFFE module 550 is similar to the configuration shown in FIG. 5B and is described using similar reference numbers. In this example, the RDL substrate 402 includes a second RDL 2 and a third RDL 3, but does not include a 3D inductor 460 or a TMV 410. Instead, the package balls 414 are secured to the via pads of the second RDL 2 and the third RDL 3. The RFFE module 550 also includes a second active die 470 and a third active die 480, which may be configured similarly to that shown in FIG. 5B.

[0035]

[0048] 6A and 6B are block diagrams further illustrating the RFFE module 400 of FIG. 4A according to an embodiment of the disclosure. As shown in FIG. 6A, an RFFE module 600 is shown in which the XY dimensions of the RDL substrate 402 are smaller than the XY dimensions of the first active die 420 to accommodate additional active components. This configuration of the RDL substrate 402 is similar to the configuration shown in FIG. 4A and is described using similar reference numbers. In this example, the RDL substrate 402 includes a first active die 420 coupled to a 3D inductor 460. In some embodiments of the disclosure, the 3D inductor 460 is composed of a TMV 410 coupled to the first active die 420. In this example, the package balls 422 also secure the first active die 420 to the landing pads of the first RDL 1 and the inductor L.

[0036]

[0049] FIG. 6B illustrates an RFFE module 640 in a multi-active die configuration according to an embodiment of the disclosure. This configuration of the RFFE module 640 is similar to the configuration shown in FIG. 4A and is described using similar reference numbers. In this example, the RDL substrate 402 also includes a first active die 420 coupled to a 3D inductor 460 via a TMV 410. The 3D inductor 460 is composed of a TMV 410 coupled to the first active die 420 and bonded together via conductive traces 462 on the surface of the molding compound 430. In some embodiments of the disclosure, a ball grid array (BGA) 416 is coupled to the conductive traces 462. In addition, package balls 472 secure the second active die 470 to the landing pads of the first RDL 1 and the inductor L.

[0037]

[0050] 7A-7D are block diagrams illustrating various options for assembling an RDL substrate 402 and a first active die 420 to form an RFFE module, according to an embodiment of the disclosure. As shown in FIG. 7A, an RFFE module 700 is shown in which a front side of the RDL substrate 402 is secured to a front side of the first active die 420 according to a front-to-front configuration. This configuration of the RDL substrate 402 is similar to the configuration shown in FIG. 4A and is described using similar reference numbers. In this example, the capacitor C side of the RDL substrate 402 is the front side of the RDL substrate 402. The back side of the RDL substrate 402 includes micro-bumps 406 and the front side of the first active die 420 includes package balls 414.

[0038]

[0051] In FIG. 7B, an RFFE module 740 is shown in which the front side of the RDL substrate 402 is secured to the front side of the first active die 420 according to a front-to-front configuration. This configuration of the RDL substrate 402 is similar to the configuration shown in FIG. 4A and is described using similar reference numbers. As mentioned above, the capacitor C side of the RDL substrate 402 is the front side of the RDL substrate 402. In some aspects of the disclosure, the back side of the RDL substrate 402 includes sidewall interconnects 408 that are coupled to the front side of the first active die 420, which includes conductive pillars 418 rather than the package balls 414 shown in FIG. 7A.

[0039]

[0052] In FIG. 7C, an RFFE module 750 is shown in which the backside of the RDL substrate 402 is secured to the frontside of the first active die 420 according to a back-to-front configuration. This configuration of the RDL substrate 402 is similar to the configuration shown in FIG. 4A and is described using similar reference numbers. In this example, the inductor L side of the RDL substrate 402 is the backside of the RDL substrate 402. In some aspects of the disclosure, the backside of the RDL substrate 402 includes micro-pillar interconnects 409 that are coupled to the frontside of the first active die 420, which includes conductive pillars 418 rather than the package balls 414 shown in FIG. 7A.

[0040]

[0053] In FIG. 7D, an RFFE module 790 is shown in which the backside of the RDL substrate 402 is secured to the frontside of the first active die 420 according to a back-to-front configuration. This configuration of the RDL substrate 402 is similar to the configurations shown in FIG. 4B and FIG. 4C and is described using similar reference numbers. As mentioned above, the inductor L side of the RDL substrate 402 is the backside of the RDL substrate 402. In some aspects of the present disclosure, the backside of the RDL substrate 402 includes through via pads (VPs) that are bonded to the frontside of the first active die 420. In this alternative configuration, the first active die 420 is bonded to the RDL substrate 402 using through VPs using metal-metal direct bonding or metal-metal or metal-semiconductor eutectic bonding. Additionally, the frontside of the RDL substrate 402, including the package balls 419, may be part of a land grid array (LGA), ball grid array (BGA), or other similar interconnect structure.

[0041]

[0054] 8A-8C are block diagrams illustrating an assembly process for forming a radio frequency front-end (RFFE) module secured to a mobile motherboard according to an embodiment of the disclosure. As shown in FIG. 8A, an RFFE module 800 is shown in which a front side of an RDL substrate 402 is secured to a front side of a first active die 420 according to a front-to-front configuration. This configuration of the RFFE module 800 is similar to the configuration shown in FIG. 7A and is described using similar reference numbers. In this example, the front side of the first active die 420 includes conductive pillars 418 rather than package balls 414 shown in FIG. 7A. In some embodiments of the disclosure, the first conductive pillars 418-1 provide a ground (GND) and the second conductive pillars 418-2 provide an input to the first active die 420. In addition, the first micro-bumps 406-1 provide an antenna (ANT) and the second micro-bumps 406-2 provide a passive output of the RFFE module 800.

[0042]

[0055] As shown in Figure 8B, a molding compound is deposited on the front side of the first active die 420 according to a fan-out wafer level package (FOWLP) configuration according to an embodiment of the disclosure. As shown in Figure 8C, an overmolding process is performed (e.g., on an LGA / BGA / leadframe) to secure the RFFE module 800 to a printed circuit board (PCB) 490. In some embodiments of the disclosure, the RFFE module 800 is secured to a motherboard to complete the assembly of the RFFE module package 840.

[0043]

[0056] 9A-9C are block diagrams illustrating a radio frequency (RF) filter including a redistribution layer (RDL) substrate according to an embodiment of the present disclosure. As shown in FIG. 9A, an RF filter module 900 is shown with a configuration similar to that of the RFFE module 500 shown in FIG. 5A. This configuration of the RF filter module 900 is similar to that shown in FIG. 7A and will be described using similar reference numerals. In this example, the first active die 420 has been omitted from the RF filter module 900.

[0044]

[0057] As shown in FIG. 9B, an RF filter module 940 is shown with a configuration similar to that of the RFFE module 400 shown in FIG. 4A. This configuration of the RF filter module 940 is similar to that shown in FIG. 7A and is described using similar reference numbers. In some aspects of the disclosure, through mold vias (TMVs) 410 secure a ball grid array (BGA) 412 to the inductor L and the first RDL1. In this example, the first active die 420 is also omitted from the RF filter module 940.

[0045]

[0058] As shown in FIG. 9C, an RF filter module 950 according to a similar configuration to the RF filter module 940 shown in FIG. 9B is shown. This configuration of the RF filter module 950 is similar to the configuration shown in FIG. 9B and is described using similar reference numbers. In some aspects of the present disclosure, the TMV 410 also secures the BGA 412 to the inductor L and the first RDL 1. In this example, the RF filter module 950 is shown according to a six-layer configuration, as opposed to the four-layer configuration of the RF filter module 940 shown in FIG. 9B. In operation, the six-layer configuration of the RF filter module 950 may improve RF performance compared to the four-layer configuration of the RF filter module 940 shown in FIG. 9B. In addition, the first active die 420 is also omitted from the RF filter module 950. A process for fabrication of an RFFE module including an RDL substrate is shown, for example, in FIG. 10A-10C.

[0046]

[0059] 10A-10C are block diagrams illustrating a process for fabricating an RFFE module including an RDL substrate, according to an embodiment of the present disclosure. As shown in FIG. 10A, in step 1000, an RDL substrate 402 including at least one passive component (e.g., C and / or L) in an interlayer dielectric (ILD) layer 404 of the RDL substrate 402 is formed on a carrier glass substrate 1002. In some embodiments of the present disclosure, the carrier glass substrate 1002 is temporarily secured to the RDL substrate 402 by an adhesive layer 1004.

[0047]

[0060] As shown in Figure 10B, in step 1010, the first active die 420 is bonded to a second surface of the RDL substrate 402 opposite the first surface of the RDL substrate 402 adjacent the carrier glass substrate 1002. As shown in Figure 10C, in step 1020, the carrier glass substrate 1002 is removed from the first surface of the RDL substrate 402, and a molding compound 430 is formed on the first active die 420 to complete the formation of the RFFE module 400 as shown in Figure 4A. In some aspects of the present disclosure, the carrier glass substrate 1002 is removed from the RDL substrate 402 by exposing and irradiating the adhesive layer 1004 through the carrier glass substrate 1002.

[0048]

[0061] 11 is a process flow diagram illustrating a method for fabricating a radio frequency front end (RFFE) module including a redistribution layer (RDL) substrate according to an embodiment of the present disclosure. The method 1100 begins at block 1102 where a redistribution layer (RDL) substrate is formed on a carrier glass substrate. For example, as shown in FIG. 10A, in step 1000, the RDL substrate 402 is formed on a carrier glass substrate 1002. In this example, the carrier glass substrate 1002 is temporarily secured to the RDL substrate 402 using an adhesive layer 1004. That is, the carrier glass substrate 1002 provides a wafer supporting system (WSS).

[0049]

[0062] In block 1104, passive components are formed in an interlayer dielectric (ILD) layer of the RDL substrate proximate a first surface of the RDL substrate and a carrier glass substrate. As shown in FIG. 4A, the RDL substrate 402 is composed of an interlayer dielectric (ILD) layer 404 composed of, for example, polyimide. In some aspects of the present disclosure, the ILD layer 404 includes a metal-insulator-metal (MIM) capacitor C and an inductor L formed from back-end-of-line layers (BEOLs) M1, M2, M3, and M4. The ILD layer 404 also includes a first redistribution layer (RDL1) to complete the RDL substrate 402. In this example, the MIM capacitor C is formed using plates of M1 and M2 metallization layers under the metallization layer M3 using an insulating layer (I) that is not present during the fabrication of the organic laminate substrate, such as silicon nitride (SiN) or other similar dielectric material. Capacitor C and inductor L provide passive components that may be interconnected to provide an RF filter for RFFE module 400 as well as a surface mount technology (SMT) matched passive device.

[0050]

[0063] Referring again to FIG. 11, in block 1106, a first die is bonded to a second surface of the RDL substrate opposite the first surface of the RDL substrate. For example, as shown in FIG. 4A, according to an aspect of the disclosure, the RFFE module 400 further includes a first active die 420 bonded to the RDL substrate 402 using flip-chip bonding. In this example, package balls 422 secure the first active die 420 to the landing pads of the first RDL 1 and the inductor L. As shown in FIG. 10B, in step 1010, the first active die 420 is bonded to a second surface of the RDL substrate 402 opposite the first surface of the RDL substrate 402 adjacent the carrier glass substrate 1002.

[0051]

[0064] In block 1108, the carrier glass substrate is removed from the first surface of the RDL substrate. For example, as shown in FIG. 10C, in step 1020, the carrier glass substrate 1002 is removed from the first surface of the RDL substrate 402, and a molding compound 430 is formed on the first active die 420 to complete the formation of the RFFE module 400, for example, as shown in FIG. 4A. In some aspects of the disclosure, the carrier glass substrate 1002 is removed from the RDL substrate by exposing and irradiating the adhesive layer 1004 through the carrier glass substrate 1002.

[0052]

[0065] In some embodiments of the present disclosure, the RDL substrate provides a double-sided substrate that allows for integration of RF filters, SMT passive component matching, and stacked routing / inductors. Advantages of the RDL substrate include a significant (e.g., 2x) reduction in size of the RFFE module in the XY dimensions. In addition, the RDL substrate also allows for a significant (e.g., 2x) reduction in Z-height. For example, a four-layer (4L) stacked package substrate may have a thickness of 260 microns compared to the 50 micron thickness of the RDL substrate. Eliminating the stacked package substrate by using the RDL substrate can reduce both the cost and size of the RFFE module while providing performance comparable to a side-by-side-on stacked package substrate RFFE module.

[0053]

[0066] According to a further aspect of the disclosure, a device includes a redistribution layer (RDL) substrate and a first die coupled to a second surface of the RDL substrate opposite the first surface of the RDL substrate. In one configuration, the device has a means for storing charge proximate to the first surface of the RDL substrate. In one configuration, the charge storage means may be a MIM capacitor C, as shown in FIG. 4. In another aspect, the aforementioned means may be any structure or any material configured to perform the functions recited by the aforementioned means.

[0054]

[0067] FIG. 12 is a block diagram illustrating an example wireless communication system 1200 in which an aspect of the present disclosure may be advantageously employed. For illustrative purposes, FIG. 12 shows three remote units 1220, 1230, and 1250 and two base stations 1240. It will be appreciated that the wireless communication system may have more remote units and base stations. The remote units 1220, 1230, and 1250 include integrated circuit (IC) devices 1225A, 1225C, and 1225B that include the disclosed RDL substrate. It will be appreciated that other devices, such as base stations, switching devices, and network equipment, may also include the disclosed RDL substrate. FIG. 12 shows forward link signals 1280 from the base station 1240 to the remote units 1220, 1230, and 1250, and reverse link signals 1290 from the remote units 1220, 1230, and 1250 to the base station 1240.

[0055]

[0068] In FIG. 12, remote unit 1220 is shown as a mobile phone, remote unit 1230 is shown as a portable computer, and remote unit 1250 is shown as a stationary remote unit in a wireless local loop system. For example, the remote units may be portable data units such as mobile phones, handheld personal communication systems (PCS) units, personal digital assistants, stationary data units such as GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading devices, or other devices that store or retrieve data or computer instructions, or combinations thereof. Although FIG. 12 illustrates remote units according to aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Aspects of the present disclosure may be suitably employed in many devices that include the disclosed RDL substrates.

[0056]

[0069] FIG. 13 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of semiconductor components, such as the RDL boards disclosed above. The design workstation 1300 includes a hard disk 1301 that contains operating system software, support files, and design software, such as Cadence or OrCAD. The design workstation 1300 also includes a display 1302 to facilitate design of a circuit 1310, or a radio frequency (RF) component 1312, such as an RDL board. A storage medium 1304 is provided for tangibly storing the design of the circuit 1310 or the RF component 1312 (e.g., an RDL board). The design of the circuit 1310 or the RF component 1312 may be stored on the storage medium 1304 in a file format, such as GDSII or GERBER. The storage medium 1304 may be a compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a hard disk, a flash memory, or other suitable device. Additionally, the design workstation 1300 includes a drive 1303 for receiving input from or writing output to a storage medium 1304 .

[0057]

[0070] The data recorded on the storage medium 1304 may define logic circuit configurations, pattern data for photolithography masks, or mask pattern data for continuous write tools such as electron beam lithography. The data may further include logic verification data such as timing diagrams and net circuits associated with logic simulations. Providing the data on the storage medium 1304 facilitates the design of the circuit 1310 or RF component 1312 by reducing the number of processes for designing a semiconductor wafer.

[0058]

[0071] The following numbered clauses describe example implementations. 1. a redistribution layer (RDL) substrate; a passive component in the RDL substrate proximate to a first surface of the RDL substrate; a first die coupled to a second surface of the RDL substrate opposite the first surface of the RDL substrate; A device comprising: 2. The device of clause 1, further comprising a device interconnect coupled between the first die and the second surface of the RDL substrate. 3. The device of clause 1 or 2, further comprising a second die on an opposite side to the first die and coupled to a passive component. 4. The device of clause 3, further comprising a third die opposite the first die, proximate to the second die and coupled to the passive component. 5. a molding compound on the second surface of the RDL substrate and on the first die; a first RDL in the RDL substrate; a second RDL in the RDL substrate; and a first through-mold via (TMV) coupled to the first RDL; a second TMV coupled to a second RDL; a 3D inductor comprising a trace coupled to the first TMV and the second TMV on a surface of the molding compound. A device according to any one of clauses 1 to 4. 6. The device of any of clauses 1-5, wherein the first die comprises an antenna module. 7. A device according to any of clauses 1 to 6, wherein the passive component comprises a metal-insulator-metal (MIM) capacitor. 8. The device of claim 7, further comprising an inductor coupled to the MIM capacitor. 9. A device as described in any of clauses 1 to 8, wherein the device comprises a radio frequency (RF) filter. 10. A device as described in any of clauses 1 to 9, wherein the device comprises a radio frequency front end (RFFE) module. 11. A method for fabricating a device, comprising: forming a redistribution layer (RDL) substrate on a carrier glass substrate; forming passive components in an interlayer dielectric (ILD) layer of the RDL substrate proximate a first surface of the RDL substrate and a carrier glass substrate; bonding a first die to a second surface of the RDL substrate opposite the first surface of the RDL substrate; removing the carrier glass substrate from the first surface of the RDL substrate; A method comprising: 12. The method of clause 11, further comprising forming device interconnects on a second surface of the RDL substrate for bonding the first die to the second surface of the RDL substrate. 13. The method of claim 11 or 12, further comprising coupling a second die to a passive component on an opposite side to the first die. 14. The method of claim 13, further comprising coupling a third die to the passive component on an opposite side to the first die and adjacent to the second die. 15. depositing a molding compound on the second surface of the RDL substrate and on the first die; forming a first RDL in a RDL substrate; forming a second RDL in the RDL substrate; forming a first through-mold via (TMV) coupled to the first RDL; forming a second TMV coupled to a second RDL; forming a 3D inductor by depositing a trace coupled to the first TMV and the second TMV on a surface of the molding compound; 15. The method according to any one of clauses 11 to 14, further comprising: 16. The method of any of clauses 11-15, wherein the first die comprises an antenna module. 17. The method of any of clauses 11-16, wherein the passive component comprises a metal-insulator-metal (MIM) capacitor. 18. The method of claim 17, further comprising forming an inductor coupled to the MIM capacitor. 19. The method of clause 18, further comprising integrating the device into a radio frequency (RF) filter. 20. The method of any of clauses 11-19, further comprising integrating the device into a radio frequency front-end (RFFE) module.

[0059]

[0072] For a firmware and / or software implementation, the methods may be implemented with modules (e.g., procedures, functions, etc.) that perform the functions described herein. Machine-readable media tangibly embodying instructions may be used in implementing the methods described herein. For example, software code may be stored in a memory and executed by a processor unit. The memory may be implemented within the processor unit or external to the processor unit. The term "memory" as used herein may refer to long-term memory, short-term memory, volatile memory, non-volatile memory, or other types of memory, and is not limited to a specific type or number of memories, or to a specific type of medium on which the memory is stored.

[0060]

[0073] If implemented in firmware and / or software, the functions may be stored as one or more instructions or code on a computer-readable medium. Examples include computer-readable media encoded with data structures and computer-readable media encoded with a computer program. Computer-readable media include physical computer storage media. A storage medium may be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc, where disks typically reproduce data magnetically while discs reproduce data optically using lasers. Combinations of the above are also intended to be included within the scope of computer readable media.

[0061]

[0074] In addition to storage on a computer-readable medium, the instructions and / or data may be provided as signals on a transmission medium included in a communications device. For example, a communications device may include a transceiver having signals indicative of the instructions and data. The instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

[0062]

[0075] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made in the specification without departing from the technology of the present disclosure as defined by the appended claims. For example, relative terms such as "top" and "bottom" are used in reference to a substrate or electronic device. Of course, if the substrate or electronic device is inverted, top becomes bottom and bottom becomes top. In addition, if in landscape orientation, top and bottom may refer to the side of the substrate or electronic device. Moreover, the scope of the present application is not intended to be limited to the particular configurations of the processes, machines, manufactures, compositions, means, methods, and steps described herein. As one skilled in the art would readily appreciate from this disclosure, any existing or later developed process, machine, manufacture, composition, means, method, or step that performs substantially the same function or achieves substantially the same results as the corresponding configurations described herein may be utilized in accordance with the present disclosure. Accordingly, it is intended that the appended claims include within their scope such processes, machines, manufactures, compositions, means, methods, or steps.

[0063]

[0076] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as a departure from the scope of the present disclosure.

[0064]

[0077] The various example logic blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0065]

[0078] The steps of a method or algorithm described in relation to the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory (EPROM), an electrically erasable programmable read only memory (EEPROM), a register, a hard disk, a removable disk, a compact disk read only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application specific integrated circuit (ASIC). The ASIC may reside in a user terminal. Alternatively, the processor and the storage medium may reside in a user terminal as discrete components.

[0066]

[0079] In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store program code means specified in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. In addition, any connection may be properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc, where disks typically reproduce data magnetically while discs reproduce data optically using lasers. Combinations of the above are also intended to be included within the scope of computer readable media.

[0067]

[0080] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications of the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A double-sided RDL substrate having an interlayer dielectric layer (IDL) and a redistribution layer (RDL); a passive component in the double-sided RDL substrate proximate a first surface of the double-sided RDL substrate; a first die coupled to a second surface of the double-sided RDL substrate opposite the first surface of the double-sided RDL substrate; a second die coupled to the passive component opposite the first die; A device comprising:

2. The device of claim 1 , further comprising a device interconnect coupled between the first die and the second surface of the double-sided RDL substrate.

3. The device of claim 1 further comprising a third die opposite the first die, proximate to the second die, and coupled to the passive component.

4. a molding compound on the second surface of the double-sided RDL substrate and on the first die; a first RDL in the double-sided RDL substrate; a second RDL in the double-sided RDL substrate; and a first through-mold via (TMV) coupled to the first RDL; a second TMV coupled to the second RDL; a 3D inductor comprising a trace on a surface of the molding compound coupled to the first TMV and the second TMV; The device of claim 1 further comprising:

5. The device of claim 1 , wherein the first die comprises an antenna module.

6. The device of claim 1 , wherein the passive components comprise a metal-insulator-metal (MIM) capacitor and an inductor coupled to the MIM capacitor.

7. 10. The device of claim 1, wherein the device comprises a radio frequency (RF) filter, or alternatively, the device comprises a radio frequency front end (RFFE) module.

8. 1. A method for fabricating a device, comprising: forming a double-sided RDL substrate comprising an interlayer dielectric layer (IDL) and a redistribution layer (RDL) on a carrier glass substrate; forming passive components in an interlayer dielectric (ILD) layer of the double-sided RDL substrate proximate a first surface of the double-sided RDL substrate and the carrier glass substrate; bonding a first die to a second surface of the double-sided RDL substrate opposite the first surface of the double-sided RDL substrate; removing the carrier glass substrate from the first surface of the double-sided RDL substrate; coupling a second die to the passive component opposite the first die; A method comprising:

9. 10. The method of claim 8, further comprising forming device interconnects on the second surface of the double-sided RDL substrate to couple the first die to the second surface of the double-sided RDL substrate.

10. The method of claim 8 , further comprising coupling a third die to the passive component on an opposite side of the first die and adjacent to the second die.

11. depositing a molding compound on the second surface of the double-sided RDL substrate and on the first die; forming a first RDL in the double-sided RDL substrate; forming a second RDL in the double-sided RDL substrate; forming a first through-mold via (TMV) coupled to the first RDL; forming a second TMV coupled to the second RDL; forming a 3D inductor by depositing traces coupled to the first TMV and the second TMV on a surface of the molding compound; The method of claim 8 further comprising:

12. The method of claim 8 , wherein the first die comprises an antenna module.

13. The method of claim 8 , wherein the passive component comprises a metal-insulator-metal (MIM) capacitor and an inductor coupled to the MIM capacitor.

14. The method of claim 13 , further comprising integrating the device into a radio frequency (RF) filter.

15. The method of claim 8 , further comprising integrating the device into a radio frequency front end (RFFE) module.

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