Data Processing

Abstract

The data processing apparatus comprises a vector processing circuit for accessing an array register having at least n×n memory locations, n being an integer greater than 1, the vector processing circuit comprising an instruction decoder circuit for decoding program instructions and an instruction processing circuit for executing the instructions decoded by the instruction decoder circuit. The instruction decoder circuit is responsive to an array access instruction to control the instruction processing circuit to access a set of n memory locations, each having a respective array location in the array register, for a vector of n vector elements. The array location accessed for a given vector element of the vector is defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.

Description

[Technical field]

[0001] The present disclosure relates to data processing.

[0002] Some data processing configurations allow for vector processing operations, which involve applying a single vector processing instruction to a data item of a data vector that has multiple data items at each position within the data vector. In contrast, scalar operations effectively operate on a single data item rather than on a data vector. Summary of the Invention

[0003] In an exemplary configuration, a data processing apparatus is provided, the data processing apparatus comprising: 1. A vector processing circuit for accessing an array register having at least n×n memory locations, n being an integer greater than 1, the vector processing circuit comprising: an instruction decoder circuit for decoding program instructions; an instruction processing circuit that executes the instructions decoded by the instruction decoder circuit; A vector processing circuit comprising: The instruction decoder circuit controls the instruction processing circuitry to access, in response to an array access instruction, a set of n memory locations, each having a respective array location in the array register, for a vector of n vector elements, the array location accessed for a given vector element of the vector being defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.

[0004] In another exemplary configuration, a method of data processing is provided, the method comprising: accessing an array register having at least n×n memory locations, where n is an integer greater than 1; Decoding program instructions; executing the instructions decoded by the decoding step; and including, including applying The decoding step controls the executing step to access, in response to an array access instruction, a set of n memory locations, each having a respective array location in an array register, for a vector of n vector elements, the array location accessed for a given vector element of the vector being defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.

[0005] In another exemplary configuration, a virtual machine is provided that includes a data processor that executes a computer program including machine-readable instructions, the execution of which causes the data processor to operate as a data processing apparatus, the data processing apparatus comprising: 1. A vector processing circuit for accessing an array register having at least n×n memory locations, n being an integer greater than 1, the vector processing circuit comprising: an instruction decoder circuit for decoding program instructions; an instruction processing circuit that executes the instructions decoded by the instruction decoder circuit; a processing circuit comprising: The instruction decoder circuit controls the instruction processing circuitry to access, in response to an array access instruction, a set of n memory locations, each having a respective array location in the array register, for a vector of n vector elements, the array location accessed for a given vector element of the vector being defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.

[0006] Further and respective aspects and features of the present disclosure are defined in the appended claims. [Brief description of the drawings]

[0007] The present technology will now be further described, by way of example only, with reference to embodiments thereof illustrated in the accompanying drawings, in which:

[0008] [Figure 1] FIG. 1 shows a schematic diagram of a data processing device; [Diagram 2] 1 illustrates a schematic of a storage array. [Diagram 3] FIG. 3 is a schematic diagram of storage locations within the storage array of FIG. 2. [Figure 4] FIG. 2 shows a schematic diagram of a linear array access; [Diagram 5] FIG. 2 shows a schematic diagram of a linear array access; [Figure 6] 1 illustrates a schematic representation of an addressing notation. [Figure 7] 11A-11C are schematic diagrams illustrating further respective examples of array accesses; [Figure 8] 11A-11C are schematic diagrams illustrating further respective examples of array accesses; [Figure 9] 11A-11C are schematic diagrams illustrating further respective examples of array accesses; [Figure 10] 11A-11C are schematic diagrams illustrating further respective examples of array accesses; [Figure 11] 1 illustrates a schematic diagram of a virtual machine. [Figure 12] 1 is a schematic flow chart illustrating a method. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] 1 shows a schematic diagram of a data processing system 10 comprising a processor 20 coupled to a memory 30 storing data values ​​32 and program instructions 34. The processor 20 includes an instruction fetch unit 40 for fetching the program instructions 34 from the memory 30 and providing the fetched program instructions to a decoder circuit 50. The decoder circuit 50 decodes the fetched program instructions and generates control signals for controlling processing circuitry 60 to perform processing operations on registers stored in a register circuit 70 as specified by a decoded vector instruction.

[0010] Processor 20 has access to a storage array 90 of at least n×n memory locations, which is depicted in dashed lines to indicate that it may or may not be provided as part of processor 20. In various embodiments, the storage array comprises one or more of the following: architecturally addressable registers, architecturally non-addressable registers, scratchpad memory, and cache.

[0011] The processing circuitry 60 may be, for example, vector processing circuitry and / or scalar processing circuitry. A general distinction between scalar and vector processing is as follows: Vector processing involves applying a single vector processing instruction to data items of a data vector with multiple data items at each position in the data vector. Scalar processing effectively operates on a single data item rather than on the data vector. Vector processing may be useful when processing operations are performed on many different instances of the data being processed. In a vector processing configuration, a single instruction may be applied to multiple data items (of a data vector) simultaneously. This may improve the efficiency and throughput of data processing compared to scalar processing.

[0012] The present technology relates to processing a two-dimensional array of data items stored, for example, in storage array 90. A two-dimensional storage array may, at least in some examples, be accessed, for example, as a vector of n elements.

[0013] In an exemplary embodiment, storage array 90 may store a square array portion of a larger or higher dimensional array or matrix of data items in memory.

[0014] Multiple instances (ie, two or more instances) of storage array 90 may be provided to store multiple respective arrays of data items.

[0015] The following description refers to exemplary program instructions 34. Embodiments of the present disclosure include, for example, apparatus of the type shown in Figure 1, operable or configured to decode and execute such program instructions. Figure 1 thus provides an example of processing circuitry for selectively applying processing operations to perform the functions described below.

[0016] Optionally, if a vector processing device is used, the vector processing operations may be under the control of so-called predicates, where each predicate may control whether or not a particular vector function is applied to one of the data item positions in the linear array (which may be treated as a data vector in this exemplary configuration).

[0017] As mentioned above, processing circuitry 60 is configured to access registers 70 and / or storage array 90 under control of instructions decoded by decoder circuitry 50. Further details of this latter arrangement will now be described with reference to FIG.

[0018] In this embodiment, storage array 90 is organized as an array 205 of at least n×n storage locations 200, where n is an integer greater than 1. In this embodiment, n is 16, which means that the granularity of access to storage locations 200 is 1 / 16 of the total storage in either the horizontal or vertical array direction. This aspect is described further below.

[0019] Exemplary Access as a Linear Array From the perspective of the processing circuitry, the array of n x n locations is accessible as n linear (one-dimensional) arrays in a first direction (e.g., horizontal as depicted) and as n linear arrays in a second array direction (e.g., vertical as depicted). Each linear array has n elements such that each storage array stores a linear array of n data items. In other words, the n x n storage locations are organized, or at least accessible, from the perspective of the processing circuitry 60, as 2n linear arrays, each of n data items.

[0020] This therefore provides one example in which an array of n×n storage locations comprises an array of storage elements accessible by the instruction processing circuitry as 2n linear arrays, the 2n linear arrays including n linear arrays in a first array direction and n linear arrays in a second array direction, each linear array including n data items (e.g., although this is not a requirement) as a data vector register. The example instructions described below may specify one or more of the 2n linear arrays.

[0021] Implementations of these techniques are described below with reference to Figures 3-5. Further details are provided in US Patent No. 11,074,214, the contents of which are incorporated herein by reference.

[0022] Further Exemplary Access Technologies In a further example, rather than simply accessing a linear array as described above, for a vector of n vector elements, a set of n storage locations, each having a respective array location in an array register, is accessed, where the array location accessed for a given vector element of the vector is defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction. Such parameters may be, for example, a reference to an index vector or a register storing a vector of such indices.

[0023] For example, the array location accessed for a given vector element of the vector may be defined by at least a pair of coordinates associated with the given vector element of the vector by a parameter of the array access instruction. In an example, the pair of coordinates may define an array location in each of a first array direction and a second array direction different from the first array direction (e.g., x and y directions as shown generally below) for the given vector element of the vector.

[0024] One of these coordinates may be implied by the element position or lane, in that the array location accessed for a given vector element of a vector may be defined by a coordinate in a first array direction that depends on the vector position of the given vector element, and a coordinate in a second array direction that is different from the first array direction defined by parameters of the array access instruction. This arrangement applies to examples where in a two-dimensional system one index vector is provided and the other index is implied or provided by the vector element position (such as the example shown in FIG. 7).

[0025] In various examples, the second array direction may be orthogonal to the first array direction, with the example of horizontal rows and vertical columns being described here.

[0026] If indexing is used in the directions or coordinate axes, the instruction decoder circuitry may be configured to select the first and second array directions from the two candidate array directions in response to a parameter of the array access instruction, for example, the "HV" parameter described below may be used.

[0027] Predicate control of operations may optionally be used in which instruction processing circuitry is responsive to a set of one or more predicates associated with each vector element to control access of the array registers for each vector element.

[0028] In an exemplary configuration, techniques such as those defined by the so-called Scalable Vector Extension (SVE) or SVE2 arrangement by Arm Limited can be used to configure the vector processing circuit to select a vector length applicable to the vector processing circuit.

[0029] Implementations of these techniques are described with reference to FIGS. 7-10 below.

[0030] Access - Circuit example The array of storage locations 200 is accessible by access circuits 210 , 220 , column select circuitry 230 and row select circuitry 240 under the control of control circuitry 250 which communicates with at least the processing circuitry and optionally the decoder circuitry 50 .

[0031] In connection with a given access, only access circuitry 210 or only access circuitry 220 may be active.

[0032] The type of access being described, which is applicable to any of the types of array access described herein, including those described with reference to FIGS. ● a write access that takes data from a vector register 260 (e.g., register 70) having n elements and stores each element in a respective memory location 200 of the array; ● a write access to retrieve data items from the set 270 of n locations 32 in memory 30 and store each data item in a respective storage location 200 in the array; ● read accesses that store data retrieved from the n storage locations 200 of the array into each element of the vector register 260; A read access which stores data retrieved from the n storage locations 200 of the array in each of a set 270 of n locations 32 in the memory 30 .

[0033] In other words, the array access instruction may comprise an instruction selected from the list consisting of a vector store instruction for storing a data item into a respective location in the array register, and a vector fetch instruction for retrieving a data item from a respective location in the array register. The array access instruction may comprise a vector store instruction for storing vector elements of an input data vector into respective locations in the array register, or a vector fetch instruction for retrieving data items of a set of memory locations in the main memory into respective vector elements of a destination data vector. In case the data processing apparatus comprises a main memory accessible by the vector processing circuit, the vector store instruction may comprise an instruction selected from the list consisting of a first vector fetch instruction for retrieving vector elements of an output data vector from respective locations in the array register, and a second vector fetch instruction for retrieving data items from respective locations in the array register into a set of memory locations in the main memory.

[0034] Each of these types of access may be selectable by use of a separate respective instruction or opcode and / or by use of respective parameters of the instruction. For example, a single instruction may provide any of these accesses, with the direction (write or read as above) defined by an instruction parameter and the source / destination (a vector register or a set of memory locations) defined and / or identified by another parameter.

[0035] Writing to or reading from registers 260 or set of locations 270 may be performed serially, e.g., one data item or element at a time in a predetermined order, in parallel (all substantially simultaneously), or in groups of, e.g., four or eight data items or elements. The routing of data items to or from vector elements or memory locations may be under the control of access circuits 210, 220 and / or control circuitry 250.

[0036] In the following figures, register 260 and set 270 of memory locations are not depicted solely for clarity of illustration.

[0037] Exemplary Linear Array Access Implementation With reference to FIG. 3 and the above-referenced U.S. Pat. No. 11,074,214, for an exemplary storage array 90 designated as "A1," the n linear arrays in a first direction (the depicted horizontal or "H" direction) are each 16 data items 0...F (in hexadecimal notation) and may be referenced in this example as A1H0...A1H15. Note that multiple such storage arrays 90 may be implemented, e.g., A0, A1, A2, etc. The same underlying data stored in the 256 entries (16x16 entries) of storage array 90A1 of FIG. 3 may instead be referenced in a second direction (the depicted vertical or "V" direction) as A1V0...A1V15. Note, for example, that data item 260 is item F of A1H0 but is referenced as item 0 of A1V15. It should be noted that the use of "H" and "V" does not imply any spatial or physical layout requirements with respect to the storage of the data elements that make up storage array 90, nor does it relate to whether the storage array stores row or column data in an exemplary application involving row and column processing.

[0038] In the exemplary arrangement, the second array direction (eg, vertical or horizontal as depicted in FIG. 2) is orthogonal to the first array direction (eg, horizontal or vertical, respectively, as depicted).

[0039] To access one of the linear arrays A1H0...A1H15 in a first direction, e.g. the horizontal direction depicted, refer to Fig. 4 where an arbitrary linear array A1Hm 300 (where m is any number from 0 to 15 in this example) is being accessed. Here, the row selection circuit 240 is controlled by the control circuit 250 to select a row of storage locations corresponding to the linear array 300, and the access circuit 210 controls the access (input or output) from the individual data items 310 of the linear array 300 which are provided to the processing circuit via the interface 320.

[0040] Similarly, referring to FIG. 5, to access any linear array in the other direction depicted, such as linear array A1Vm400, column selection circuit 230 selects the column of storage elements corresponding to linear array 400, and data is read (output) via access circuit 220, which is interfaced with processing circuitry by interface 410.

[0041] Next, the so-called granularity of the configurations of Figs. 3-5 will be described. The linear array A1Hm represents 16 data items of 32 bits each. There are 16 such linear arrays, and each linear array A1Vm in the second array direction also has 16 entries of 32 bits. However, instead, this storage can be organized as a vector (so to speak) of 64 data items of 8 bits in each direction. In other words, the granularity of the access to the storage providing the storage array 90 can be 8-bit granularity instead of 32-bit granularity. However, in this embodiment, the granularity and the number of data items in each linear array in the first and second direction should be the same (16 in the first embodiment, 64 in the second embodiment).

[0042] Note that this is merely an exemplary configuration for purposes of this description. In general, the exemplary architecture may support scalable or processor-selectable vector lengths as described above, for example by maintaining a variable VL that indicates the vector length in use by the processor 20. The value of VL is established or selected using techniques defined by the SVE / SVE2 configurations described above. Thus, although an exemplary vector length of 512 bits is used in this particular example, in general, A1Hm represents (VL / 32) items of 32 bits each, or even more generally (VL / ELEM_SIZE()) items of ELEM_SIZE() bits each.

[0043] In an exemplary configuration, the instruction processing circuit 60 is configured to store an input vector or linear array in an array of storage locations as a group of n storage locations (A1Hm) arranged in a first array direction, and in response to a data retrieval instruction, retrieves a set of n storage locations (e.g., A1Hm or A1Vm) arranged in a selected array direction from a set of candidate array directions under control of the data retrieval instruction as a linear array, the first array direction being a predetermined array direction (e.g., the depicted horizontal direction). In other words, data writing is constrained to a first direction, but data reading is allowed in either direction. However, it will be appreciated that another exemplary configuration may be provided in which data writing and data reading are allowed in either direction.

[0044] Further Exemplary Access Technology Implementations The above examples relate to accessing a multi-dimensional storage array, such as a two-dimensional storage array, either horizontally or vertically oriented, to store or retrieve linear arrays to or from the two-dimensional storage array.

[0045] In contrast to the linear array system described above, the array location accessed for a given vector element of a vector is defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction, such parameters may be, for example, a reference to an index vector or a register storing such an index vector.

[0046] Examples of the technology described below provide further instructions or variations of instructions that, when decoded and executed, provide for the use of one or more vectors of indexes to perform indexed access by row (horizontal) and / or column (vertical) to store or collect individual elements from a storage array to (or from) a destination / source vector in a register or memory.

[0047] In these examples, the apparatus of FIGS. 1 and 2, operating according to the techniques described below, A vector processing circuit 20 for accessing an array register having at least n×n memory locations, n being an integer greater than 1, the vector processing circuit comprising: an instruction decoder circuit 50 for decoding program instructions; an instruction processing circuit 60 for executing instructions decoded by the instruction decoder circuit; A vector processing circuit 20 comprising: The instruction decoder circuit 50 provides an example of a data processing apparatus 10 in which, in response to an array access instruction, the instruction processing circuit 60 controls the instruction processing circuit 60 to access a set of n memory locations, each having a respective array location in an array register, for a vector of n vector elements, the array location accessed for a given vector element of the vector being defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.

[0048] For purposes of the following discussion, FIG. 6 provides a diagram of an exemplary 4×4 storage array (the 4×4 array size is a simplification for clarity of illustration, keeping in mind that the actual array size may be somewhat larger than 4×4 in an actual embodiment) where the array is identified as ZA0, rows are identified by “H”+indexes n, m, p, q (e.g., 0-3), and columns are identified by “V”+indexes.

[0049] FIG. 7 illustrates diagrammatically a move (MOV) instruction that moves data from a two-dimensional ZA0 array to a one-dimensional vector register Zd according to a vector Zc of indexes applicable in the depicted vertical direction.

[0050] To generate the elements of destination vector Zd, each element is derived from a respective column ZA0V of array ZA0 of FIG. 7. For each such column, index vector Zc defines a respective vertical coordinate or row for extracting the data item applicable to that column. Thus, for column ZA0Vn, the respective index element is n, such that element a is extracted from row ZA0Hn. For the next adjacent column ZA0Vm, the index is q and element b is extracted from row ZA0Hq, and so on. Each of these operations is subject to a predicate, such that the predicate vector defines, for each processing lane (corresponding to an element of Zd), whether the operation is performed as shown. If not, the predicate construction can allow that element of Zd to be zeroed out or left unchanged. In this way, assuming the predicate allows all lanes to be processed, destination vector Zd is assembled as [abcd] by collecting four respective data values ​​from storage locations defined by the horizontal location applicable to the location in the destination vector of each destination vector element and the vertical location defined by the respective element of index vector Zc.

[0051] It will be appreciated that instead of vertical indexed access, a horizontal indexed access configuration can be used, where (again assuming the predicate allows all lanes to be processed) the destination vector Zd is assembled by collecting the four respective data values ​​from storage locations defined by the vertical positions applicable to the location in the destination vector of the respective destination vector elements and the horizontal positions defined by the respective elements of the index vector Zc. An example of such a configuration is shown diagrammatically by FIG.

[0052] The syntax used in these examples is as follows: MOVA <zd> .B、 <pg> / M、 <zat> <hv> .B[ <zc>]

[0053] Here, MOVA represents the move array instruction. Zd is the destination vector register. B indicates the byte format in this example. Pg is the predicate register that controls the operation per vector lane. M is a modifier associated with the predicate operation, for example defining whether an inactive predicate indicates that the elements of that lane should be set to 0 or should be kept at their previous value. ZAt defines the array in use (such as the depicted ZA0). H or V defines whether the indexed access is horizontal or vertical. Again, B indicates the byte format. Zc is a vector of indexes.

[0054] FIG. 9 provides an example of using two index vectors stored by respective vector registers Zb, Zc to access array ZA0.

[0055] In the first operation, MOVA Zd.B, Pg / M, ZA0V.B[Zb], the destination register Zd is populated by [abef] using a vertical indexed access to array ZA0 according to the index vector Zb.

[0056] In the second operation, MOVAZe.B, Pg / M, ZA0V.B[Zc], the destination register Ze is populated by [cdgh] using a vertical indexed access to array ZA0 according to the index vector Zc.

[0057] The previously proposed primary zip operation (ZIP1) takes a vector register Zf and reads adjacent vector elements in pairs from the lower halves of two source registers (in this case Zd and Ze), places the pairs in an interleaved vector, and writes the vector to a destination register Zf. The first pair from the first source register is placed into the two lowest vector elements, and subsequent pairs are taken alternately from each source register.

[0058] The previously proposed quadratic zip operation (ZIP2) takes a vector register Zg. The ZIP2 operation reads adjacent vector elements as pairs from the top halves of two source vector registers, places the pairs in an interleaved manner into a vector, and writes the vector to a destination vector register. The first pair from the first source register is placed into the two lowest vector elements, and subsequent pairs are taken alternately from each source register.

[0059] Potential uses of such instructions could be the extraction of small patches from a storage array, for example to provide processing of a patch of pixels from an image, or to extract rows of a sub-matrix generated by a predicated cross product instruction, e.g. an instruction smaller than the streaming vector length divided by the element size.

[0060] In a variation of the above operations, a move operation from a source vector register to a storage array can be provided, where the storage array locations to which data is moved from each vector element of the source vector register are defined by indexed accesses, either horizontally or vertically, using these same techniques. Here, the syntax can be similar to that described above, but using a "store" command, and the destination is defined by indexed accesses to the array (examples are given in the previous section). <zat> <hv> .B[ <zc>]), the source is defined by a vector register (example used above <zd>.B). Again, we can use predicates in the same way as above.

[0061] In this example, the move instruction described (MOVA) can operate in either direction between a vector register and a set of array locations, with the meaning or direction of the operation (read from or write to an array location) defined by the ordering of the operands that define the origin and destination of the data (in the exemplary syntax shown here, destination defined first, then origin). However, at least in the example described here, the store operations described below are always memory from a set to an array location.

[0062] Another variation is illustrated by the following example command: ST1W{ <zat> <hv> .S[ <zc> ]}、 <pg>、[<Xn|SP>{、 <xm>, LSL#2}]

[0063] where ST1W is a word-based store instruction. The suffix, S, indicates the data element size in the vector, selected from a list which may include (for example): .B -> 8-bit element .H -> 16-bit elements .S -> 32-bit elements .D -> 64-bit elements .Q -> 128 bit elements

[0064] The data destination is <zat> <hv> .S[ <zc>] is defined in the same way as above, in that it defines an access to the array ZAt, either horizontally (H) or vertically (V) indexed by the index vector stored in Zc. The optional predicate is <pg>Provided by.<Xn|SP> {, <xm>, LSL#2}] provides a known definition (in the context of the SVE system) of a corresponding set of memory locations by defining a base address (Xn or SP) and then an offset (Xm) that is defined as some number of elements.

[0065] In the above example, the instruction decoder circuitry, in response to an array access instruction (such as the move or store instructions discussed above), controls the instruction processing circuitry to access (e.g., read from or write to) a set of n storage locations, each having a respective array location in an array register, for a vector of n vector elements (whether embodied in a vector register or in memory), where the array location accessed for a given vector element of the vector is defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction. Examples of such parameters include, for example, definitions of horizontal or vertical indexes. <hv>Combined with, i.e., the index vector, > <hv> .B[ <zc>In another example given below, such an example parameter may define a respective index (or pair of indices, etc.) for each of two (or indeed more) coordinate directions.

[0066] Two-dimensional index example Any of the techniques described above can be used in the context of two-dimensional indexing. An example is shown diagrammatically in FIG. 10, where a pair of index vectors are provided by respective vector registers Zx, Zy to provide access to an exemplary storage array ZA0. To generate a destination vector (Zd) element for a particular lane or location, the pair of index vectors is accessed at that lane or location to generate a pair of (X,Y) coordinates that define the array storage location to be accessed (read from or stored to) associated with that lane or location.

[0067] Here the syntax can be similar to that described above, except that both the H and V parameters can be set (to indicate indexing in both directions), and a pair of index registers are defined as the source of index information. MOVA <zd> .B、 <pg> / M、 <zat> <hv> .B[ <zx> 、 <zy>.]

[0068] In various embodiments, the array comprises one or more of the following: architecturally addressable registers, architecturally non-addressable registers, a scratchpad memory, and a cache.

[0069] More than 2 dimensions - Example The techniques described herein can be extended to arrays with more than two dimensions, such as three-dimensional arrays, e.g., an n×n×n storage array, where one or more coordinates of a storage location to be accessed relative to a vector element position or lane can be defined by an entry in an index vector, zero or more coordinates can be implied by the vector element position or lane, and zero or more coordinates can be specified by one or more parameters of the access instruction.

[0070] Virtual Machine Example FIG. 11 shows a schematic diagram of a virtual machine in which some or all of the above-mentioned functions may be provided. The virtual machine comprises a central processing unit (CPU) as an example of a data processing circuit 1100, a non-volatile memory 1110, a control interface 1120, and an input / output (IO) interface 1130, all interconnected by a bus arrangement 1140. A random access memory (RAM) 1150 stores program instructions providing software 1160 that controls the operation of the CPU 1100. Under the control of the software 1160, the CPU 1100 provides or emulates the functions of one or more of the above-mentioned processing instructions. The RAM 1150 also stores program instructions 1170 and data 1180, the program instructions 1170 being instructions applicable to the processor 20 of FIG. 1 and interpreted, emulated or otherwise executed by the CPU 1100 functioning as a virtual machine. The data 1180 is data corresponding to the data 32 of FIG. 1 that is manipulated by the (virtual) execution of the program instructions 1170. 11 configuration thus provides one example of a virtual machine comprising a data processor (such as CPU 1100) executing a computer program including machine-readable instructions (e.g., software 1160), the execution of which causes the data processor to operate as a data processing device of the type described above. Exemplary embodiments are also represented by computer software that, when executed by a computer, causes the computer to perform one or more of the techniques described herein, including the method of FIG. 12 described below, and by a non-transitory machine-readable storage medium storing such computer software.

[0071] Method overview The above techniques may be implemented by processing circuitry (which may comprise or control control circuitry) that causes control circuitry to control the access and selection circuits 210, 220, 230, 240 to access appropriate elements within the storage array.

[0072] In summary, FIG. 12 is a schematic flow chart illustrating a data processing method, which includes: accessing (at step 1200) an array register having at least n×n storage locations, where n is an integer greater than 1; Decoding (at 1210) program instructions; and executing (at Step 1220) the instructions decoded by the decoding step; The decoding step 1210 controls the executing step 1220 to access, in response to the array access instruction, a set of n memory locations, each having a respective array location in an array register, for a vector of n vector elements, the array location accessed for a given vector element of the vector being defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.

[0073] In this application, the term "configured to..." is used to mean that an element of an apparatus has a configuration that is capable of performing a defined operation. In this context, "configuration" refers to a manner of arrangement or interconnection of hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that an apparatus element needs to be modified in any way to provide the defined operation.

[0074] Although exemplary embodiments of the present technology have been described in detail herein with reference to the accompanying drawings, it should be understood that the present technology is not limited to those precise embodiments, and various changes, additions, and modifications can be made by those skilled in the art without departing from the scope and spirit of the technology as defined by the appended claims. For example, various combinations of the features of the dependent claims can be made with the features of the independent claims without departing from the scope of the present technology.< / zy> < / zx> < / hv> < / zat> < / pg> < / zd> < / zc> < / hv> < / hv> < / xm> < / pg> < / zc> < / hv> < / zat> < / xm> < / pg> < / zc> < / hv> < / zat> < / zd> < / zc> < / hv> < / zat> < / zc> < / hv> < / zat> < / pg> < / zd>

Claims

1. 1. A data processing device, comprising:

1. A vector processing circuit for accessing an array register having at least n×n storage locations, n being an integer greater than 1, said vector processing circuit comprising: an instruction decoder circuit for decoding program instructions; an instruction processing circuit that executes the instructions decoded by the instruction decoder circuit; a processing circuit comprising:

1. A data processing apparatus comprising: an instruction decoder circuit for controlling said instruction processing circuitry in response to an array access instruction to access a set of n memory locations, each having a respective array location in said array register, for a vector of n vector elements, wherein the array location accessed for a given vector element of said vector is defined by one or more coordinates associated with said given vector element by one or more parameters of said array access instruction.

2. 2. A data processing apparatus as claimed in claim 1, wherein said array location accessed for said given vector element of said vector is defined by at least a pair of coordinates associated with said given vector element of said vector by a parameter of said array access instruction.

3. 3. A data processing apparatus as claimed in claim 2, wherein said pair of coordinates defines an array position for said given vector element of said vector in each of a first array direction and a second array direction different from said first array direction.

4. 2. A data processing apparatus as claimed in claim 1, wherein the array location accessed for the given vector element of the vector is defined by a coordinate in a first array direction which depends on the vector location of the given vector element, and a coordinate in a second array direction which is different from the first array direction defined by a parameter of the array access instruction.

5. 5. A data processing apparatus as claimed in claim 4, wherein said instruction decoder circuitry is arranged to select said first array direction and said second array direction from two candidate array directions in response to a parameter of said array access instruction.

6. A data processing apparatus according to any one of claims 3 to 5, wherein the second array direction is orthogonal to the first array direction.

7. The array access instruction: a vector store instruction for storing data items into respective locations within said array register; 2. A data processing apparatus as claimed in claim 1, further comprising an instruction selected from said list consisting of vector fetch instructions which fetch data items from respective locations within said array registers.

8. a data processing apparatus comprising a main memory accessible by said vector processing circuit; 8. A data processing apparatus according to claim 7.

9. The array access instruction: a vector store instruction for storing vector elements of an input data vector in respective locations within said array register; 8. A data processing apparatus as claimed in claim 7, further comprising an instruction selected from said list consisting of vector fetch instructions for fetching data items from a set of memory locations in said main memory into respective vector elements of a destination data vector.

10. said vector store instruction being: a first vector fetch instruction for fetching vector elements of an output data vector from respective locations in said array register; 9. A data processing apparatus as claimed in claim 8, further comprising an instruction selected from said list consisting of a second vector fetch instruction for fetching data items from respective locations in said array registers to a set of memory locations in said main memory.

11. A data processing apparatus as claimed in any preceding claim, wherein the instruction processing circuitry controls access of the array registers for each vector element in response to a set of one or more predicates associated with the respective vector element.

12. A data processing apparatus as claimed in any preceding claim, wherein n depends on a vector length applicable to said vector processing circuit.

13. A data processing apparatus as claimed in claim 12, wherein said vector processing circuitry is arranged to select the vector length applicable to said vector processing circuitry.

14. A data processing apparatus as claimed in any preceding claim, comprising two or more array registers for each of the nxn storage locations.

15. 1. A data processing method comprising the steps of: accessing an array register having at least n×n memory locations, where n is an integer greater than 1; Decoding program instructions; executing the instructions decoded by the decoding step; 11. A method of data processing according to claim 10, wherein the decoding step controls the executing step to access a set of n memory locations, each having a respective array location in the array register, for a vector of n vector elements, in response to an array access instruction, the array location accessed for a given vector element of the vector being defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.

16. Computer software which, when executed by a computer, causes the computer to carry out the method of claim 15.

17. 20. A non-transitory machine-readable storage medium storing the computer software of claim 16.

18. 1. A virtual machine comprising a data processor executing a computer program including machine-readable instructions, the execution of the computer program causing the data processor to operate as a data processing device, the data processing device comprising: a vector processing circuit for accessing an array register having at least n×n memory locations, n being an integer greater than 1; an instruction decoder circuit for decoding program instructions; an instruction processing circuit that executes the instructions decoded by the instruction decoder circuit; A vector processing circuit comprising:

2. A virtual machine comprising: a first instruction decoder circuit for controlling said instruction processing circuit to, in response to an array access instruction, access a set of n memory locations, each having a respective array location in said array register, for a vector of n vector elements, the array location accessed for a given vector element of said vector being defined by one or more coordinates associated with said given vector element by one or more parameters of said array access instruction.

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