A common circuit for triangle intersection and instance transformation for ray tracing.

Abstract

Techniques are provided for performing ray tracing operations that include traversing through a bounding volume hierarchy to an instance node, performing instance node transformations using common circuitry, traversing to a leaf node of the bounding volume hierarchy, and performing intersection tests on the leaf node using common circuitry.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 17 / 564,103, filed December 28, 2021, the contents of which are incorporated by reference as if fully set forth herein. [Background technology]

[0002] Ray tracing is a type of graphics rendering technique in which simulated rays are cast to test for object intersections, and pixels are colored based on the results of the ray cast. Ray tracing is more computationally expensive than rasterization-based techniques, but produces more physically accurate results. Improvements to ray tracing behavior are constantly being made.

[0003] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0004] [Figure 1] 1 is a block diagram of an example device capable of implementing one or more features of the present disclosure. [Diagram 2] 2 is a block diagram of the accelerated processing device of FIG. 1 illustrating additional details regarding the execution of processing tasks in the device, according to an example. [Diagram 3] FIG. 1 illustrates a ray tracing pipeline for rendering graphics using ray tracing techniques, according to one example. [Figure 4] FIG. 2 illustrates a bounding volume hierarchy, according to an example. [Diagram 5] FIG. 13 illustrates a coordinate transformation for performing a ray-triangle intersection test, according to an example. [Figure 6] FIG. 13 illustrates a ray-triangle intersection test as a rasterization operation, according to an example. [Figure 7]FIG. 2 illustrates an exemplary two-level acceleration structure. [Figure 8] FIG. 2 illustrates an example ray intersection test unit that includes a multiply-add unit used for both triangle intersection testing and instance transform operations. [Figure 9] 1 is a flow diagram of a method for performing a ray tracing operation, according to an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] Techniques are provided for performing ray tracing operations that include traversing through a bounding volume hierarchy to an instance node, performing instance node transformations using common circuitry, traversing the bounding volume hierarchy to a leaf node, and performing intersection tests on the leaf node using common circuitry.

[0006] 1 is a block diagram of an example device 100 capable of implementing one or more features of the present disclosure. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Device 100 also optionally includes an input driver 112 and an output driver 114. It should be understood that device 100 may include additional components not shown in FIG. 1.

[0007] In various alternatives, the processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, the memory 104 is located on the same die as the processor 102 or is located separately from the processor 102. The memory 104 may include volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache).

[0008] The storage devices 106 include fixed or removable storage devices (e.g., hard disk drives, solid state drives, optical disks, flash drives). The input devices 108 include, but are not limited to, a keyboard, a keypad, a touch screen, a touch pad, a detector, a microphone, an accelerometer, a gyroscope, a biometric scanner, or a network connection (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). The output devices 110 include, but are not limited to, a display device 118, a speaker, a printer, a haptic feedback device, one or more optical, antennae, or network connections (e.g., a wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0009] The input driver 112 communicates with the processor 102 and the input device 108, allowing the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, allowing the processor 102 to send output to the output device 110. It should be noted that the input driver 112 and the output driver 114 are optional components, and that the device 100 operates in the same manner when the input driver 112 and the output driver 114 are not present. The output driver 114 includes an Accelerated Processing Device (APD) 116 coupled to a display device 118. The APD 116 is configured to accept computational and graphics rendering commands from the processor 102, process the computational and graphics rendering commands, and provide pixel output to the display device 118 for display. As described in further detail below, the APD 116 includes one or more parallel processing units configured to perform computations according to the single-instruction-multiple-data (SIMD) paradigm. Thus, although various functions are described herein as being performed by or in conjunction with the APD 116, in various alternative examples, the functions described as being performed by the APD 116 are additionally or alternatively performed by other computing devices having similar capabilities that are not driven by a host processor (e.g., the processor 102) and that are configured to provide (graphical) output to the display device 118. For example, it is contemplated that any processing system that performs processing tasks according to the SIMD paradigm can be configured to perform the functions described herein. Alternatively, it is contemplated that computing systems that do not perform processing tasks according to the SIMD paradigm perform the functions described herein.

[0010] 2 is a block diagram of device 100 showing additional details regarding the execution of processing tasks on APD 116. Processor 102 maintains, in system memory 104, one or more control logic modules for execution by processor 102. The control logic modules include operating system 120, drivers 122, and applications 126. These control logic modules control various aspects of the operation of processor 102 and APD 116. For example, operating system 120 communicates directly with hardware and provides an interface to the hardware for other software executing on processor 102. Driver 122 controls the operation of APD 116, for example, by providing an application programming interface (API) to software executing on processor 102 (e.g., applications 126) to access various features of APD 116. In some embodiments, driver 122 includes a just-in-time compiler that compiles programs for execution by processing components of APD 116 (such as SIMD unit 138, described in more detail below). In other embodiments, a just-in-time compiler is not used to compile the programs, and a regular application compiler compiles the shader programs for execution on the APD 116.

[0011] APD 116 executes commands and programs for selected functions, such as graphic and non-graphic operations that are suitable for parallel and / or out-of-order processing. APD 116 is used to perform graphics pipeline operations, such as pixel operations, geometry calculations, and rendering of images to display device 118, based on commands received from processor 102. APD 116 also performs computational operations not directly related to graphics operations, such as operations related to video, physics simulations, computational fluid dynamics, or other tasks, based on commands received from processor 102.

[0012] APD 116 includes computational units 132 that include one or more SIMD units 138 that perform operations in a parallel manner according to the SIMD paradigm at the request of processor 102. The SIMD paradigm is one in which multiple processing elements share a single program control flow unit and program counter, and thus execute the same program, but execute the program on different data. In one example, each SIMD unit 138 includes 16 lanes, each lane executing the same instruction simultaneously with other lanes in SIMD unit 138, but executing the instruction on different data. Lanes can be switched off with prediction when not all lanes need to execute a given instruction. Prediction can also be used to execute programs with branching control flow. More specifically, for programs with conditional branches or other instructions where the control flow is based on calculations performed by individual lanes, prediction of lanes corresponding to currently not executed control flow paths and serial execution of different control flow paths allows arbitrary control flow. In an embodiment, each of computational units 132 can have a local L1 cache. In an embodiment, multiple computational units 132 share an L2 cache.

[0013] The basic unit of execution within the compute units 132 is the work item. Each work item represents a single instantiation of a program that executes in parallel on a particular lane. Work items can execute simultaneously as a "wavefront" on a single SIMD unit 138. One or more wavefronts are included in a "workgroup," which includes a collection of work items designated to execute the same program. A workgroup is executed by executing each of the wavefronts that make up the workgroup. In the alternative, a wavefront executes sequentially on a single SIMD unit 138, or partially or fully in parallel on different SIMD units 138. A wavefront can be thought of as the largest collection of work items that can execute simultaneously on a single SIMD unit 138. Thus, if commands received from the processor 102 indicate that a particular program should be parallelized to an extent that the program cannot be run simultaneously on a single SIMD unit 138, then the program is split into wavefronts that are either parallelized on two or more SIMD units 138, or serialized on the same SIMD unit 138 (or both parallelized and serialized, as appropriate). The scheduler 136 is configured to perform operations related to scheduling of various wavefronts on the different compute units 132 and SIMD units 138.

[0014] The parallel processing provided by the computation units 132 is well suited to graphics-related operations, such as pixel value calculations, vertex transformations, and other graphics operations. Thus, in some cases, the graphics pipeline 134, which accepts graphics processing commands from the processor 102, provides computation tasks to the computation units 132 for execution in parallel.

[0015] Computation units 132 are also used to perform computational tasks that are not related to graphics or that are not performed as part of the "normal" operation of graphics pipeline 134 (e.g., custom operations performed to supplement the processing performed on the operation of graphics pipeline 134). Applications 126 or other software executing on processor 102 send programs defining such computational tasks to APD 116 for execution.

[0016] Computation units 132 implement ray tracing, which is a technique for rendering a 3D scene by testing intersections between simulated rays and objects in the scene. Much of the work involved in ray tracing is performed by programmable shader programs executing on SIMD units 138 within computation units 132, as described in more detail below.

[0017] 3 illustrates a ray tracing pipeline 300 for rendering graphics using ray tracing techniques, according to an example. The ray tracing pipeline 300 provides an overview of the operations and entities involved in rendering a scene using ray tracing. In some embodiments, the ray generation shader 302, any hit shader 306, closest hit shader 310, and miss shader 312 are shader implementation stages that represent ray tracing pipeline stages whose functions are performed by shader programs executing in the SIMD unit 138. Any of the specific shader programs at each specific shader implementation stage are defined by application-provided code (i.e., by code provided by the application developer that is pre-compiled by the application compiler and / or compiled by the driver 122). In other embodiments, any of the ray generation shaders 302, any hit shaders 306, nearest hit shaders 310, and miss shaders 312 are implemented as software running on any type of processor and performing the operations described herein, circuitry performing the operations described herein, or a combination of hardware circuitry and software running on a processor. An acceleration structure traversal stage 304 performs ray intersection tests to determine whether a ray hits a triangle.

[0018] Ray tracing pipeline 300 refers to the path through which ray tracing operations flow. To render a scene using ray tracing, a rendering orchestrator, such as a program executing on processor 102, specifies a collection of geometric shapes as a "scene." Various objects in the scene are represented as a collection of geometric primitives, which are often triangles but can be any geometric shape. As used herein, the term "triangle" refers to these geometric primitives that make up the scene. The rendering orchestrator renders the scene by specifying a camera position and an image, and requesting that rays be traced from the camera through the image. Ray tracing pipeline 300 performs various operations described herein to determine the color of the rays. The color is often derived from the triangles that the rays intersect. As described elsewhere herein, rays that do not hit a triangle invoke miss shader 312. One possible operation of the miss shader 312 is to color rays with colors from a "skybox," which is an image that is specified as representing a surrounding scene in which no geometry is present (e.g., a scene without geometry renders only the skybox). The color of a pixel in the image is determined based on the intersection point between the ray and the image location. In some examples, after a sufficient number of rays have been traced and the pixels of the image have been assigned colors, the image is displayed on a screen or used in some other manner.

[0019] In some embodiments in which the shader stages of the ray tracing pipeline 300 are implemented in software, the various programmable shader stages (ray generation shader 302, any hit shader 306, nearest hit shader 310, miss shader 312) are implemented as shader programs executing on the SIMD unit 138. The acceleration structure traversal stage 304 is implemented in software (e.g., as a shader program executing on the SIMD unit 138), in hardware, or as a combination of hardware and software. The hit or miss unit 308 is implemented in any technically feasible manner, such as as part of any of the other units, or as a hardware accelerated structure, or as a shader program executing on the SIMD unit 138. The ray tracing pipeline 300, in various embodiments, may be organized partially or fully in software, or partially or fully in hardware, by the processor 102, the scheduler 136, by a combination thereof, or partially or fully by any other hardware and / or software unit. In examples, traversal through the ray tracing pipeline 300 is performed partially or completely by the scheduler 136, either autonomously or under control of the processor 102, or partially or completely by a shader program (such as a bounding volume hierarchy traversal shader program) executing on one or more of the SIMD units 138. In some examples, testing rays against boxes and triangles (inside the accelerated structure traversal stage 304) is hardware accelerated (meaning that a fixed function hardware unit performs those testing steps). In other examples, such testing is performed by software, such as a shader program, executing on one or more of the SIMD units 138. As used herein, when the phrase "the ray tracing pipeline does something" is used, this means that the hardware and / or software implementing the ray tracing pipeline 300 does that thing.Although illustrated as executing on SIMD unit 138 in FIG. 3, it should be understood that in other embodiments, other hardware (e.g., processor 102), with or without SIMD capabilities, may alternatively execute the shader programs of the illustrated ray tracing pipeline 300.

[0020] The ray tracing pipeline 300 operates in the following manner: A ray generation shader 302 is implemented that sets the data of rays to be tested against triangles and calls upon an acceleration geometry traversal stage 304 that tests the rays for intersection with triangles.

[0021] The acceleration structure traversal stage 304 traverses the acceleration structure, which is a data structure that describes the scene volume and objects (such as triangles) in the scene, and tests the ray against triangles in the scene. In various examples, the acceleration structure is a bounding volume hierarchy. In some embodiments, a hit or miss unit 308, which is part of the acceleration structure traversal stage 304, determines whether the results of the acceleration structure traversal stage 304 (which may include raw data such as barycentric coordinates and possible hit times) actually indicate a hit. For triangles that are hit, the ray tracing pipeline 300 triggers the execution of any hit shaders 306. Note that multiple triangles may be hit by a single ray. The acceleration structure traversal stage is not guaranteed to traverse the acceleration structure in order from closest to the ray origin to furthest from the ray origin. The hit or miss unit 308 triggers the execution of the closest hit shader 310 for the triangle closest to the ray origin that the ray hits, or triggers a miss shader if the triangle was not hit.

[0022] It should be noted that any hit shader 306 may "reject" a hit from the ray intersection test unit 304, and thus the hit or miss unit 308 triggers the execution of the miss shader 312 if the hit is not found or accepted by the ray intersection test unit 304. An exemplary situation in which any hit shader 306 may "reject" a hit is when at least a portion of the triangle that the ray intersection test unit 304 reports as a hit is completely transparent. Because the ray intersection test unit 304 only tests geometry and not transparency, for a hit to a triangle that has at least some transparency, any hit shader 306 that is invoked may determine that the reported hit is not actually a hit because it "hit" a transparent portion of the triangle. A typical use of the closest hit shader 310 is to color a material based on the texture of the material. A typical use of the miss shader 312 is to color a pixel with a color set by a skybox. It should be understood that the closest hit shader 310 and miss shader 312 may implement a wide variety of techniques for coloring pixels and / or performing other operations. When these shaders are implemented as programmable shader stages that execute shader programs, different shader programs used for the same application may color pixels in different ways.

[0023] A typical way that the ray generation shader 302 generates rays is with a technique called backwards ray tracing. In backward ray tracing, the ray generation shader 302 generates rays that have their origin at a point on the camera. The point at which the ray intersects a plane defined to correspond to the screen defines a pixel on the screen that is used to determine the ray's color. If the ray hits an object, the pixel is colored based on the closest hit shader 310. If the ray does not hit an object, the pixel is colored based on the miss shader 312.

[0024] Any of the hit shaders 306, the nearest hit shader 310, and the miss shader 312 can spawn unique rays that enter the ray tracing pipeline 300 at ray test points. These rays can be used for any purpose. One common use is to perform environmental lighting or reflections. In one example, when the nearest hit shader 310 is called, it spawns rays in various directions. For each object or light hit by the spawned ray, the nearest hit shader 310 adds lighting intensity and color to the pixel that corresponds to the nearest hit shader 310. Although several examples of how the various components of the ray tracing pipeline 300 can be used to render a scene are described, it should be understood that any of a wide variety of techniques can be used alternatively.

[0025] As mentioned above, determining whether a ray hits an object is referred to herein as a "ray intersection test." A ray intersection test involves firing a ray from an origin and determining whether the ray hits a triangle, and if so, how far from the origin the triangle hits. To increase efficiency, ray tracing tests use a representation of space called a bounding volume hierarchy. This bounding volume hierarchy is the "acceleration structure" mentioned above. In a bounding volume hierarchy, each non-leaf node represents an axis aligned bounding box that bounds the geometry of all of the node's children. In one example, a base node represents the maximum extent of the entire region over which ray intersection tests are performed. In this example, the base node has two children, each of which represents a mutually exclusive axis aligned bounding box that sub-divides the entire region. Each of those two children has two child nodes that represent axis aligned bounding boxes that sub-divide their parent's space, and so on. Leaf nodes represent triangles (or other geometries) over which ray tests can be performed.

[0026] The bounding volume hierarchical data structure allows the number of ray-triangle intersections (which are complex and therefore expensive in terms of processing resources) to be reduced compared to a scenario in which such a data structure is not used and therefore all triangles in the scene need to be tested for the ray. Specifically, if a ray does not intersect a particular bounding box and that bounding box bounds a large number of triangles, all triangles within that box can be eliminated from testing. Thus, ray intersection testing is performed as a series of tests of the ray against axis-aligned bounding boxes, followed by tests against the triangles.

[0027] 4 is a diagram illustrating a bounding volume hierarchy, according to an example. For simplicity, the hierarchy is shown in 2D. However, it should be understood that extension to 3D is straightforward, and the tests described herein are generally performed in three dimensions.

[0028] A spatial representation 402 of the bounding volume hierarchy is shown on the left side of Figure 4, and a tree representation 404 of the bounding volume hierarchy is shown on the right side of Figure 4. In both the spatial representation 402 and the tree representation 404, non-leaf nodes are represented by the letter "N" and leaf nodes are represented by the letter "O". A ray intersection test is performed by traversing through the tree 404, and for each non-leaf node tested, if the box test for that non-leaf node fails, then a branch below that node is eliminated. For leaf nodes that are not eliminated, a ray-triangle intersection test is performed to determine if a ray intersects a triangle at that leaf node.

[0029] In one example, the ray intersects O5 but not any other triangles. A test tests against N1 and determines that the test succeeds. A test tests against N2 and determines that the test fails (because O5 is not in N1). Note that the test eliminates all subnodes of N2 and tests against N3 and that test succeeds. Note that the test tests N6 and N7 and N6 succeeds but N7 fails. Note that the test tests O5 and O6 and O5 succeeds but O6 fails. Instead of testing eight triangle tests, two triangle tests (O5 and O6) and five box tests (N1, N2, N3, N6, N7) are performed.

[0030] The ray-triangle test involves asking if a ray hits a triangle and how long it takes to hit the triangle (time from the ray origin to the intersection point). Conceptually, the ray-triangle test involves projecting the triangle into the ray view space, so that a simpler test can be performed similar to the test of coverage in two-dimensional rasterization of triangles as is commonly performed in graphics processing pipelines. More specifically, the coordinate system is transformed so that the triangle is projected into the ray view space, with the ray pointing downward in the z direction and the x and y components of the ray being zero (although in some variations the ray may point upward in the z direction, or in a positive or negative x or y direction, with the components of the other two axes being zero). The vertices of the triangle are transformed into this coordinate system as well. Such a transformation allows testing for intersection to be performed by simply asking if the x, y coordinates of the ray fall within the triangle defined by the x, y coordinates of the triangle vertices, which is the rasterization operation described above. In effect, the 3D query is transformed into a simpler 2D query, shown in FIG.

[0031] The above transformation is illustrated in Figure 5. Ray 502 and triangle 504 are shown in coordinate system 500 before the transformation. In the transformed coordinate system 510, ray 512 is shown pointing in the -z direction and triangle 514 is also shown in that coordinate system 510.

[0032] 6 illustrates the ray intersection test as a rasterization operation. Specifically, vertices A, B, and C define triangle 514, and vertex T is the origin of ray 512. The test as to whether ray 512 intersects triangle 514 is performed by testing whether vertex T is within triangle ABC. This operation is referred to as a "rasterization" operation because in rasterization, the question is which pixels fall within the triangle, which will be described in more detail below.

[0033] We now provide further details of the ray-triangle test. First, we rotate the coordinate system so that the z-axis is the principal axis of the ray (here, "principal axis" means the axis along which the ray travels fastest). This rotation is done to avoid some edge cases when the z-component of the ray direction is zero, and numerical stability degradation that occurs when the z-component of the ray direction is small. The coordinate system rotation is performed as follows: Note that this coordinate system rotation is arbitrary.

[0034] First, note that a ray is defined by both an origin and a direction. The origin is the starting point of the ray, and the direction indicates the directional range of the ray. The maximum dimension of the ray (x, y, or z) is determined. The maximum dimension is the dimension that has the greatest magnitude. More specifically, a ray has three components x, y, and z that define the ray. The largest of the absolute values ​​of these components is considered to be the maximum dimension.

[0035] Once the maximum dimension is determined, the ray is rotated so that the ray's maximum dimension points in the z direction. If the maximum dimension is z, the ray is unchanged. If the maximum dimension is x, the ray is rotated by setting the x dimension to the old y dimension, the y dimension to the old z dimension, and the z dimension to the old x dimension. If the maximum dimension is y, the ray is rotated by setting the x dimension to the old z dimension, the y dimension to the old x dimension, and the z dimension to the old y dimension. Since a ray is defined by both an origin and a direction, the origin is rotated as well as the direction vector. Additionally, the vertices of the triangle (shown as A, B, and C in FIG. 6) are rotated in the same manner that the vertices of the ray are rotated.

[0036] In the next step, the vertices of the triangle are translated relative to the origin of the ray. More specifically, the translated A vertex is determined by subtracting the ray origin from the old A vertex. The translated B vertex is determined by subtracting the ray origin from the old B vertex. The translated C vertex is determined by subtracting the ray origin from the old C vertex. The translated A, B and C vertices are referred to herein as A, B and C, respectively. tr , B tr and C tr The ray origin is here set to <0,0,0>. It should be understood that the ray direction is relative to the ray origin.

[0037] Next, to simplify the calculation of the intersection points between the ray and the triangle, a linear transformation is applied to the ray and the triangle vertices, allowing the test to be performed in two dimensions instead of three. This linear transformation is done by multiplying each of the triangle vertices by a transformation matrix M. The ray direction does not need to be explicitly transformed by matrix M, since matrix M is constructed such that the transformed ray direction is always <0,0,ray_dir.z>. The ray direction can be transformed in this way because the ray origin is now at <0,0,0> due to the translation step above. Note that ray_dir.z is the z component of the rotated ray direction, ray_dir.x is the x component of the rotated ray direction, and ray_dir.y is the y component of the rotated ray direction. Since the ray origin is <0,0,0>, there is no need to transform the ray origin. Matrix M is:

[0038]

number

[0039] Matrix multiplication is done by multiplying the translated vertices (A tr , B tr , C tr ) to the matrix M, resulting in the new vertex A of the triangle. trf, B trf , C trf Note that the components of a particular vertex are indicated with a subscript -x, -y, or -z. A trf-x =A tr-x * ray_dir.z-ray_dir.x * A tr-z A trf-y =A tr-y * ray_dir.z - ray_dir.y * A tr-z A trf-z =A tr-z B trf-x =B tr-x * ray_dir.z-ray_dir.x * B tr-z B trf-y =B tr-y * ray_dir.z - ray_dir.y * B tr-z B trf-z =B tr-z C trf-x =C tr-x * ray_dir.z-ray_dir.x * C tr-z C trf-y =C tr-y * ray_dir.z - ray_dir.y * C tr-z C trf-z =C tr-z

[0040] Conceptually, the matrix M scales and shears the coordinates such that the ray direction has only a z-component with magnitude ray_dir.z. The x and y components of the ray direction have magnitude 0. With the vertices transformed as above, the ray-triangle test is performed as a 2D rasterization test: is the origin T inside the triangle ABC? Figure 6 shows the A matrix as described above. trf , B trf , C trf 6 shows a triangle 602 with vertices A, B, C corresponding to vertex A, B, C. Ray 604 is shown as point T. Due to the transformations performed on the vertices and rays, the ray points in the -z direction. Furthermore, since the triangle is projected onto a coordinate system with rays pointing in the -z direction, the triangle ray test is reformulated as a test for whether the origin of the ray is within the triangle defined by the x,y coordinates of vertices A, B, C. In other words, the three-dimensional test of whether the ray intersects the triangle has been transformed into a two-dimensional test of whether the origin of the ray is within the triangle. Furthermore, due to the above transformations, the ray origin is at the 2D point (0,0), the intersection of the ray with the triangle (T) is also at the 2D point (0,0), and the distances between the vertices of the triangle, which are AT for vertex A, BT for vertex B, and CT for vertex C, are simply A, B, C since the intersection of the ray with the triangle is at (0,0).

[0041] Next, the barycentric coordinates U, V, W of the triangle (shown in FIG. 6) are calculated as follows: U=area(triangle CBT)=0.5 * (C×B) V=area(triangle ACT)=0.5 * (A×C) W=area(triangle BAT)=0.5 * (B×A)

[0042] Here, "x" denotes the cross product, and A, B, and C are the transformed vertices A and B shown in Figure 6. trf , B trf , C trfThe signs of U, V, and W indicate whether the ray intersects the triangle. More specifically, if U, V, and W are all positive, or if U, V, and W are all negative, then the ray is considered to intersect the triangle because point T is inside the triangle in FIG. 6. If the signs of U, V, and W are different, then the ray is not intersecting the triangle because point T is outside the triangle. If exactly one of U, V, and W is 0, then point T is on a line through the edge corresponding to that coordinate. In this situation, point T is on an edge of triangle 602 if the signs of the other two coordinates are the same, but the point is not on an edge of the triangle if the signs of the other two coordinates are different. If exactly two of U, V, and W are 0, then point T is considered to be on a corner of the triangle. If all of U, V, and W are 0, then the triangle is a zero-area triangle. One additional point is that a point T can be inside a triangle in 2D (shown as a ray intersecting the triangle above), but can miss the triangle in 3D space if the ray is behind the triangle. The sign of t, described below, indicates whether the ray is behind the triangle (and therefore does not intersect the triangle). Specifically, if the sign is negative, the ray is behind the triangle and does not intersect it. If the sign is positive or 0, the ray intersects the triangle.

[0043] In various embodiments, any situation where a point is on an edge or a corner, or where a triangle is a zero-area triangle, may be considered to be either a hit or a miss. In other words, the determination of whether a point on an edge is a hit or a miss and / or the determination of whether a point on a corner is a hit or a miss depends on the particular policy. For example, in some embodiments, all instances where a point is on an edge or a corner are considered to be hits. In other embodiments, all such instances are considered to be misses. In still other embodiments, some such instances (such as point T on an edge facing a particular direction) are considered to be hits and other such instances are considered to be misses.

[0044] Additionally, the time t when the ray hits the triangle is determined. This is done by interpolating the Z values ​​of all triangle vertices using the already calculated barycentric coordinates (U,V,W) of the triangle. First, the z component of point T (the intersection of the ray with the triangle) is calculated.

[0045]

number

[0046]

number

[0047]

number

[0048] It should be noted that although the steps described above are performed with the ray pointing in the -z direction, this direction is arbitrary, and the steps are of course symmetric with respect to any particular direction the ray points.

[0049] FIG. 7 illustrates an exemplary two-level acceleration structure 700. The exemplary acceleration structure 700 serves the same purpose as the bounding volume hierarchy 404 of FIG. 4. More specifically, the acceleration structure 700 includes non-leaf nodes 702 and leaf nodes (in a lower-level acceleration structure 704). The ray tracing pipeline 300 performs ray intersection tests by traversing the acceleration structure 700. Specifically, the ray tracing pipeline 300 tests rays against bounding boxes associated with non-leaf nodes 702, and removes descendants of such nodes if the intersection test fails. For leaf nodes 706, the ray tracing pipeline 300 uses the results of the intersection with such leaf nodes to determine whether the ray hits or misses the associated geometry. In one example, if the ray intersects with the geometry associated with a leaf node, the ray is considered to hit that leaf node, and if the ray does not intersect with the geometry associated with the leaf node, the ray is considered to miss that leaf node.

[0050] The acceleration structure 700 is a two-level acceleration structure that includes an upper level acceleration structure 705 and one or more lower level acceleration structures 704. The upper level acceleration structure 705 includes non-leaf nodes 502 and instance nodes 703. Some of the non-leaf nodes 502 include pointers to instance nodes 703. The instance nodes 703 include pointers to lower level acceleration structures 704. In some embodiments, the upper level acceleration structure 705 includes leaf nodes (similar to leaf nodes 706 of the lower level acceleration structure 704). The lower level acceleration structure 704 includes leaf nodes 706. Some lower level acceleration structures 704 include non-leaf nodes 702 that include pointers to non-leaf nodes 702 or leaf nodes 706.

[0051] As described above, the acceleration structure 700 is a two-level acceleration structure. Thus, the acceleration structure 700 includes an upper level acceleration structure 705 and one or more lower level acceleration structures 704. One advantage of a two-level acceleration structure is that parts of the acceleration structure can be instantiated. Specifically, the acceleration structure 700 can behave as if there were multiple copies or "instances" of a single lower level acceleration structure 704. More specifically, different instance nodes 703 can point to the same lower level acceleration structure 704. Instantiation provides the advantage of requiring less data compared to acceleration structures where instantiation does not occur. In addition to including a pointer to the lower level acceleration structure 704, the instance node 703 also includes information specifying rotation and position transformations for positioning and rotating the lower level acceleration structure 704 in world space.

[0052] The ray intersection testing unit 304 traverses the acceleration structure 700, testing rays against associated geometry in the following manner: The ray intersection testing unit 304 starts with a top node, such as top non-leaf node 702 of a top-level acceleration structure 705. The ray intersection testing unit 304 tests the ray against the bounding box associated with that non-leaf node 702. If the intersection fails, the ray intersection testing unit 304 does not traverse any of the node's children; if the intersection test is successful, the ray intersection testing unit 304 traverses to the node's children. For those children that are traversed, the ray intersection testing unit 304 tests the ray against the child's geometry (e.g., bounding box) and, again based on the outcome of the test, determines whether or not to traverse to the child of the child.

[0053] When the ray intersection testing unit 304 reaches an instance node 703, it applies the transformation associated with the instance node 703 to the ray and then traverses to the lower-level acceleration structure 704 pointed to by that instance node 703. As described above, the instance node 703 specifies transformations, such as a change in position or orientation. These transformations, when applied to a ray, cause the intersection with the ray to be evaluated as if the geometry of the lower-level acceleration structure 704 (including the non-leaf nodes 702 and the leaf nodes 706) had a position and orientation defined by the transformation. These transformations thus allow the same data (the lower-level acceleration structure 704) to represent geometries with different positions and orientations. Applying such a transformation to a ray involves multiplying a matrix representing the transformation by the origin and direction of the ray.

[0054] 8 illustrates an example ray intersection test unit 304 that includes a multiply-add unit 802 used for both triangle intersection testing and instance transform operations. The ray intersection test unit 304 includes one or more input formatting units 801, one or more multiply-add units 802, and one or more instance transform specific circuits 806.

[0055] Part of the triangle intersection test is implemented using multiply-add operations, and part of the instance transformation (multiplying the origin and direction of the ray) is implemented using multiply-add operations. The same circuitry can be used to perform these different multiply-add operations. Furthermore, the input formatting 801 can be used for both operations.

[0056] The triangle intersection test is performed by dividing the vertex A of the transformed triangle by tr , B tr , C tr This involves subtracting the ray origin from the triangle vertices (A,B,C) to obtain .The triangle vertices are then multiplied by the triangle transformation matrix M. For the x and y components of the triangle vertices, this multiplication is shown above as: A trf-x =Atr-x * ray_dir.z-ray_dir.x * A tr-z A trf-y =A tr-y * ray_dir.z - ray_dir.y * A tr-z B trf-x =B tr-x * ray_dir.z-ray_dir.x * B tr-z B trf-y =B tr-y * ray_dir.z - ray_dir.y * B tr-z C trf-x =C tr-x * ray_dir.z-ray_dir.x * C tr-z C trf-y =C tr-y * ray_dir.z - ray_dir.y * C tr-z

[0057] For instance transformation operations, the ray origin and ray direction are determined by the 4 × 3 instance transformation matrix M tr For a ray direction, this calculation can be expressed as:

[0058]

number

[0059] The left side is the transformation matrix and the right side is the ray direction. For the ray origin, the calculation can be expressed as:

[0060]

number

[0061] In general form, multiplication can be expressed as:

[0062]

number

[0063] For the triangle intersection test, the input formatting unit 801 sets the following values: R0=(ray_origin,0) R=(ray_dir.x,ray_dir.y,ray_dir.z,ray_dir.z) v0_rel=v0-R0 v1_rel=v1-R0 v2_rel=v2-R0 D0=(v0_rel.x,-v0_rel.z,v0_rel.y,-v0_rel.z) D1=(v1_rel.x,-v1_rel.z,v1_rel.y,-v1_rel.z) D2=(v2_rel.x,-v2_rel.z,v2_rel.y,-v2_rel.z) Here, v0 is the first vertex of the triangle, v1 is the second vertex of the triangle, and v2 is the third vertex of the triangle. Matrix multiplication is expressed as follows: Ax=D0.x * R.x+D0.y * Ry Bx=D1.x * R.x+D1.y * Ry Cx=D2.x * R.x+D2.y * Ry Ay=D0.z * R.z+D0.w * Rw By=D1.z * R.z+D1.w * Rw Cy=D2.z * R.z+D2.w * Rw where the x and y values ​​represent the x and y components of the transformed A, B, and C vertices of the triangle. As mentioned above, the Z component is not modified by the transformation and therefore does not need to be processed by the multiply-add unit 802. The matrix multiplication is performed by the multiply-add unit 802, and the operations to set R0, R, v0_rel, v1_rel, v2_rel, D0, D1, and D2 are performed by the input formatting unit 801.

[0064] It can be seen that the matrix multiplications for triangle operations and instance transform operations have the same format, i.e., sum of two products. This similarity allows the same hardware to be used for both operations. The input formatting block 801 puts the triangle transform into the same format as for the instance transform, converting subtraction operations into addition operations. Additionally, the multiply-add unit 802 generates partial matrix products for the instance transform, but these partial products are summed in the instance transform specific circuit 806. The input formatting circuit 801 includes some functionality in that the first three components of the vector R are set to the x, y, z components of the ray direction or ray origin. In essence, by manipulating the way in which the inputs are provided to the multiply-add unit 802, the same multiply-add unit 802 can be used for both the ray-triangle intersection test and the instance transform operations. Because multiply-add circuits are much more complex than some other types of circuits, such as adders, reusing these multiply-add units 802 for different operations reduces the amount of circuitry required compared to configurations in which separate multiply-adders are included for the triangle transform and instance transform operations.

[0065] Ray intersection test unit 304 shows two input formatting units 801 and two multiply-add units 802 so that two triangle tests can be performed simultaneously, or instance transformations can be performed simultaneously on ray origins and ray directions, however, in alternative embodiments ray intersection test unit 304 includes any technically feasible number of such units.

[0066] 9 is a flow diagram of a method 900 for performing a ray tracing operation, according to one example. Although described with respect to the systems of FIGS. 1-8, one skilled in the art will recognize that any system configured to perform the steps of method 900 in any technically feasible order falls within the scope of the present disclosure.

[0067] In step 902, the ray tracing pipeline 300 traverses to an instance node 703. As described elsewhere herein, the instance node 703 is a node in an acceleration structure that points to a lower-level acceleration structure 704. The instance node 703 contains transformation information that indicates how to transform the ray for testing against the contents of the lower-level acceleration structure 704. In step 904, the ray tracing pipeline 300 performs the instance node transformation using common circuitry. As described elsewhere herein, the instance node transformation modifies the position and / or orientation of the ray's origin and direction, thereby preparing the ray for traversal of the lower-level acceleration structure 704. Step 904 is performed using common circuitry including the multiply-add unit 802 of the ray intersection test unit 304, which is also used for triangle intersection testing.

[0068] In step 906, the ray tracing pipeline 300 traverses to the leaf nodes 706 of the acceleration structure 700. As described elsewhere herein, these leaf nodes 706 contain geometry descriptions, such as triangle descriptions. In step 908, the ray tracing pipeline 300 performs a ray triangle intersection test using common circuitry. Ray triangle intersection involves multiplication of a transformation matrix by the vertices of a triangle to obtain transformed vertices of the triangle. The multiply-add unit 802 used for this multiplication is the same as that used for the instance transformation.

[0069] Each of the units illustrated in the figure represents a hardware circuit configured to perform the operations described herein, software configured to perform the operations described herein, or a combination of software and hardware configured to perform the steps described herein. For example, the accelerated structure traversal stage 304 is implemented entirely in hardware, entirely in software running on a processing unit (such as the computation unit 132), or a combination thereof. In some examples, the accelerated structure traversal stage 304 is implemented partially as hardware and partially as software. In some examples, the portion of the accelerated structure traversal stage 304 that traverses the bounding volume hierarchy is software running on a processor, and the portion of the accelerated structure traversal stage 304 that performs ray-box intersection tests and ray-triangle intersection tests is implemented in hardware. When a particular stage of the ray tracing pipeline 300 is said to be "invoked," the invocation involves performing a hardware function if the stage is implemented as a hardware circuit, or executing a shader program (or other software) if the stage is implemented as a shader program running on a processor. The input formatting unit 801, the multiply-add unit 802 and the instance transform specific circuitry 806 are implemented as hardwired circuits.

[0070] It should be understood that many variations are possible based on the disclosure herein, and although features and elements have been described above in particular combinations, each feature or element can be used alone without the other features and elements, or in various combinations with or without the other features and elements.

[0071] The provided methods can be implemented in a general purpose computer, processor, or processor core. Suitable processors include, by way of example, general purpose processors, special purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Array (FPGA) circuits, any other type of integrated circuit (IC), and / or state machines. Such processors can be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data including netlists (instructions that can be stored on a computer readable medium). The results of such processing can be a mask work, which is then used in a semiconductor manufacturing process to manufacture a processor implementing aspects of the embodiments.

[0072] The methods or flow charts provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general purpose computer or processor. Examples of non-transitory computer-readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

1. 1. A method for performing a ray tracing operation, comprising: traversing through the bounding volume hierarchy to an instance node; performing instance node transformation using a common circuit; traversing to a leaf node of the bounding volume hierarchy; performing crossover tests on the leaf nodes using the common circuitry. method.

2. The instance node includes a pointer to a lower level acceleration structure.

2. The method of claim 1.

3. The instance node includes position and orientation transformation information.

2. The method of claim 1.

4. and modifying the instance node based on the position and orientation transformation information. The method of claim 3.

5. the instance node transformation includes a first matrix multiplication, and the intersection test includes a second matrix multiplication.

2. The method of claim 1.

6. The first matrix multiplication includes multiplying an instance transformation matrix by a ray origin and a ray direction. The method of claim 5.

7. The second matrix multiplication includes multiplying a transformation matrix by a ray direction. The method of claim 5.

8. The leaf nodes specify the geometry of a triangle.

2. The method of claim 1.

9. The intersection test includes transforming the ray into a coordinate system having x and y components with the origin of the ray at 0; 2. The method of claim 1.

10. 1. A system for performing a ray tracing operation, comprising: A processor; a beam crossing test circuit; The light beam crossing test circuit includes: traversing through the bounding volume hierarchy to an instance node; performing instance node transformation using a common circuit; traversing to a leaf node of the bounding volume hierarchy; performing crossover tests on the leaf nodes using the common circuit; 4. The method of claim 3, system.

11. The instance node includes a pointer to a lower level acceleration structure. The system of claim 10.

12. The instance node includes position and orientation transformation information. The system of claim 10.

13. and modifying the instance node based on the position and orientation transformation information. The system of claim 12.

14. the instance node transformation includes a first matrix multiplication, and the intersection test includes a second matrix multiplication. The system of claim 10.

15. The first matrix multiplication includes multiplying an instance transformation matrix by a ray origin and a ray direction.

15. The system of claim 14.

16. The second matrix multiplication includes multiplying a transformation matrix by a ray direction.

15. The system of claim 14.

17. The leaf nodes specify the geometry of a triangle. The system of claim 10.

18. The intersection test includes transforming the ray into a coordinate system having x and y components with the origin of the ray at 0; The system of claim 10.

19. 1. A system comprising: a ray tracing pipeline configured to require intersection testing to be performed by a ray intersection testing circuit; a beam crossing test circuit; The light beam crossing test circuit includes: traversing through the bounding volume hierarchy to an instance node; performing instance node transformation using a common circuit; traversing to a leaf node of the bounding volume hierarchy; performing crossover tests on the leaf nodes using the common circuit; 4. The method of claim 3, system.

20. The instance node includes a pointer to a lower level acceleration structure.

20. The system of claim 19.

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