Multimedia compression frame-aware cache replacement policy

Abstract

Various embodiments include methods and devices for implementing a criteria-aware cache replacement policy by a computing device. Embodiments may include updating a stale counter, writing a value of a local counter to the system cache associated with a location in the system cache of the data, the value of the stale counter including the value of the stale counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter for the associated data to determine whether the associated data is stale.

Description

[Technical field]

[0001] Related Applications This application claims the benefit of priority from U.S. Non-provisional Patent Application No. 17 / 646,690, filed December 31, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0002] A system cache of a computing device may store data according to one or more replacement policies, such as nMRU (not-most recently used) and capacity-based FIFO (first-in, first-out). The nMRU and FIFO policies are not optimal for various use cases, such as multimedia frame-based clients, where time locality is within frame time boundaries and capacity allocation may vary based on compression ratios. Summary of the Invention

[0003] Various aspects of the present disclosure provide methods, including methods and apparatus for implementing such methods for enforcing a criteria-aware cache replacement policy by a computing device, which may include updating a stale counter; writing a value of a local counter to the system cache associated with a location in the system cache of the associated data, the value of the stale counter including the value of the stale counter at the time the associated data is written to the system cache; and determining whether the associated data is stale using the value of the local counter for the associated data.

[0004] In some aspects, updating the stale counter may include receiving a signal from a client of a computing device configured to indicate whether to update the stale counter, determining whether to update the stale counter based on the signal, and updating the stale counter in response to determining that the stale counter should be updated.

[0005] In some aspects, the signal is a register write command, and receiving the signal from a client of the computing device may include reading a value from a register set by the client, and determining whether to update the stale counter based on the signal may include determining whether to update the stale counter based on the value from the register.

[0006] Some aspects may include setting a value in a register by a client of the computing device based on a time-based criteria.

[0007] Some aspects may include setting a value in a register by a client of the computing device based on event-based criteria.

[0008] Some aspects may include receiving a memory write command, and writing a value of a local counter to a system cache in association with a location in the system cache of associated data, the associated data being data of the write memory command, may occur before updating the stale counter.

[0009] In some aspects, determining whether the associated data is stale using the value of the local counter for the associated data may include calculating a replacement value using the value of the stale counter and the value of the local counter and determining whether the replacement value exceeds a stale threshold, wherein the associated data is determined to be stale in response to determining that the replacement value exceeds the stale threshold.

[0010] Some aspects may include receiving a memory access command and writing data of the memory access command to a system cache at a location where a replacement value is above a stalling threshold, where the data of the memory access command written to the system cache is relevant data.

[0011] Some aspects may include receiving a memory write command, invalidating data at locations where the replacement value is above a stalling threshold, and writing the data of the memory write command to a system cache at the locations having the invalidated data, where the data of the memory write command written to the system cache is the associated data.

[0012] Some aspects may include receiving a memory write access command and, in response to determining that the replacement value does not exceed a staleness threshold, writing data of the memory write access command to a system cache at a location according to another cache replacement policy.

[0013] Further aspects include a computing device including a memory control device configured to perform the operations of any of the methods summarized above. Further aspects include a non-transitory processor-readable storage medium having stored thereon processor-executable software instructions configured to cause a processor to perform the operations of any of the methods summarized above. Further aspects include a computing device having means for achieving the functions of any of the methods summarized above.

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the various embodiments and, together with the general description above and the detailed description below, serve to explain the features of the claims. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a component block diagram illustrating an example computing device suitable for implementing various embodiments. [Diagram 2] FIG. 1 is a component block diagram illustrating an exemplary system-on-chip suitable for implementing various embodiments. [Figure 3A] FIG. 1 is a process component signaling diagram illustrating an example of a criteria-aware cache replacement policy, according to one embodiment. [Figure 3B] FIG. 1 is a process component signaling diagram illustrating an example of a criteria-aware cache replacement policy, according to one embodiment. [Figure 4] FIG. 1 is a memory flow diagram illustrating an example of a criteria-aware cache replacement policy, according to one embodiment. [Diagram 5] FIG. 2 is a memory flow diagram illustrating an example of a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to one embodiment. [Figure 6] FIG. 1 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy for a local counter, according to one embodiment. [Figure 7] FIG. 1 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to one embodiment. [Figure 8] FIG. 1 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to one embodiment. [Figure 9]FIG. 1 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on invalidating data based on the value of a local counter, according to one embodiment. [Figure 10] FIG. 1 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on invalidating data based on the value of a local counter, according to one embodiment. [Figure 11] FIG. 1 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy for a local counter, according to one embodiment. [Figure 12] FIG. 1 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to one embodiment. [Figure 13] FIG. 1 is a process flow diagram illustrating a method for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to one embodiment. [Figure 14] FIG. 1 is a component block diagram illustrating an exemplary mobile computing device suitable for implementing various embodiments. [Figure 15] FIG. 1 is a component block diagram illustrating an exemplary mobile computing device suitable for implementing various embodiments. [Figure 16] FIG. 1 is a component block diagram illustrating an example server suitable for implementing various embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Various embodiments will now be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts. References made to specific examples and implementations are for illustrative purposes only and do not limit the scope of the claims.

[0017] Various embodiments include methods of enforcing a criteria-aware cache replacement policy, and computing devices implementing such methods. Embodiments may include associating data written to a system cache with a local counter. The value of the local counter may include the value of a stale counter at (i.e., at) the time the associated data is written to the system cache. A replacement value for data in the system cache may be calculated using the local value of the associated data and compared to a stale threshold. The value of the local counter of the associated data may be used to determine whether the associated data is stale. Data in the system cache associated with the local counter used to calculate the replacement value may be replaced in response to the replacement value being greater than and / or equal to the stale threshold.

[0018] The term "computing device" is used herein to refer to stationary computing devices including personal computers, desktop computers, all-in-one computers, workstations, supercomputers, mainframe computers, embedded computers (such as in vehicles and other larger systems), computerized vehicles (e.g., passenger vehicles, commercial vehicles, recreational vehicles, military vehicles, partially or fully autonomous ground, air, and / or underwater vehicles such as drones), servers, multimedia computers, and game consoles. The terms "computing device" and "mobile computing device" are used interchangeably herein to refer to any one or all of cellular telephones, smartphones, personal or mobile multimedia players, personal digital assistants (PDAs), laptop computers, tablet computers, convertible laptops / tablets (2-in-1 computers), smartbooks, ultrabooks, netblocks, palmtop computers, wireless email receivers, multimedia Internet-enabled cellular telephones, mobile game consoles, wireless game controllers, and similar personal electronic devices that include memory and a programmable processor.

[0019] For ease and clarity of description, various embodiments are described in terms of code, e.g., processor-executable instructions, but may be equally applicable to any data, e.g., code, program data, or other information stored in memory. The terms "code," "data," and "information" are used interchangeably herein and are not intended to limit the scope of the claims and descriptions to the types of code, data, and information used as examples in describing various embodiments.

[0020] Typically, a system cache of a computing device uses one or more data replacement policies, such as nMRU (not-most recently used) and FIFO (first-in, first-out), to control the memory space in which data is cached. nMRU and FIFO policies are not optimal for various use cases, including, for example, multimedia frame-based clients, where the time locality is within a frame time boundary and the capacity allocation may vary based on the compression ratio. The NMRU replacement policy is insufficient when cache lines accessed from multimedia clients have different access frequencies and are only valid for a certain time frame. FIFO replacement behavior is not guaranteed with self-adaptive partitioning, where the size of a partition of the cache may change over time as the sub-cache is filled with compressed frames.

[0021] Various embodiments address and resolve limitations in conventional cache replacement policies. A client, such as a processor or a process of a software program (e.g., an operating system and / or application) executed by the processor, may signal (e.g., via communication, register write, direct interrupt, etc.) the need to update a stale counter of data in a system cache. For ease of explanation, some examples may be described herein in terms of register writes. However, such examples do not limit the scope of the claims or description to register writes. Those skilled in the art will appreciate that other types or methods of signaling a processor may perform the same or similar functions. Register writes may be issued based on criteria such as time (i.e., time-based criteria), events (i.e., event-based criteria), and / or other metrics. For example, register writes may be issued at the beginning and / or end of a frame of compressed multimedia data, based on frame time boundaries, color fields within a frame of compressed multimedia data, etc. The processor or system cache may associate the value of the stale counter with the data in the system cache as a local counter. For example, a processor or system cache may associate a value of a stale counter in a tag of a system cache line during insertion or use of data in the system cache line. A processor or system cache may associate a local counter containing a value of a stale counter with data when (i.e., at the time) the associated data is written to the system cache. Because the local counter is associated with data in the system cache when the associated data is written to the system cache, the stale counter may indicate stale data by distinguishing data in the system cache, and thus may be used to help identify candidate replacement memory locations for use by a processor or for new write commands.

[0022] The stale threshold may be used by a processor or a system cache to determine whether data in the system cache is stale and can be replaced with the next write of the data to the system cache. The stale threshold may be preconfigured based on a criteria-aware cache replacement policy. A replacement value for data in the system cache may be calculated using the value of a stale counter and a local counter associated with the data and may be compared to the stale threshold to determine whether the associated data is stale and can be replaced with the next write of the data to the system cache.

[0023] Various embodiments provide a cache replacement policy method that can track stale data in a cache such that stale data is more likely to be replaced than non-stale data on the next write of data to the system cache. Identifying stale data using the methods of various embodiments can improve the operation of a computing device by enabling deterministic cache usage and thus improving last-level cache usage and reduced traffic in double data rate (DDR) synchronous dynamic random-access memory (SDRAM).

[0024] 1 illustrates a system including a computing device 100 suitable for use with various embodiments. The computing device 100 may include a system on a chip (SoC) 102 having a central processing unit 104, a memory 106, a communication interface 108, a memory interface 110, a peripheral device interface 120, and a processing device 124. The computing device 100 may further include a communication component 112, such as a wired or wireless modem, a memory 114, an antenna 116 for establishing a wireless communication link, and / or a peripheral device 122. The processor 124 may include any of a variety of processing devices, e.g., several processor cores.

[0025] The term "system on chip" or "SoC" is used herein to generally refer to a set of interconnected electronic circuits including, but not limited to, a processing device, memory, and a communication interface. The processing device may include various different types of processors and / or processor cores, such as a central processing unit (CPU) 104 and / or processors 124 including general purpose processors, central processing unit (CPU) 104, digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), secure processing units (SPUs), intellectual property units (IPUs), subsystem processors of specific components of a computing device such as an image processor for a camera subsystem or a display processor for a display, auxiliary processors, peripheral device processors, single-core processors, multi-core processors, controllers, and / or microcontrollers. The processing device may further incorporate other hardware and combinations of hardware, such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and / or time references. An integrated circuit may be constructed such that components of the integrated circuit reside on a single piece of semiconductor material, such as silicon.

[0026] The SoC 102 may include one or more CPUs 104 and processors 124. The computing device 100 may include more than one SoC 102, thereby increasing the number of CPUs 104, processors 124, and processor cores. The computing device 100 may also include CPUs 104 and processors 124 that are not associated with the SoC 102. Individual CPUs 104 and processors 124 may be multi-core processors. The CPUs 104 and processors 124 may each be configured for a specific purpose, which may be the same or different from other CPUs 104 and processors 124 of the computing device 100. One or more of the CPUs 104, processors 124, and processor cores of the same or different configurations may be grouped together. A group of CPUs 104, processors 124, or processor cores may be referred to as a multi-processor cluster.

[0027] The memory 106 of the SoC 102 may be a volatile or non-volatile memory configured to store data and processor-executable code for access by the CPU 104, processor 124, or other components of the SoC 102. The computing device 100 and / or the SoC 102 may include one or more memories 106 configured for various purposes. The one or more memories 106 may include volatile memories, such as random-access memory (RAM), including DDR memory, implemented as main memory or cache memory. These memories 106 may be configured to temporarily hold data received from data sensors or subsystems, data and / or processor-executable code instructions requested from the non-volatile memory and loaded from the non-volatile memory into the memory 106 in anticipation of future access based on various factors, and / or a limited amount of intermediate processing data and / or processor-executable code instructions generated by the CPU 104 and / or processor 124 that is not stored in the non-volatile memory but is temporarily stored for quick future access. Memory 106 may be configured to at least temporarily store data and processor-executable code that is loaded into memory 106 from another memory device, such as another memory 106 or memory 114, for access by one or more of CPU 104, processor 124, or other components of SoC 102. In some embodiments, any number and combination of memories 106 may include one-time programmable or read-only memory.

[0028] The memory interface 110 and the memory 114 may operate simultaneously to enable the computing device 100 to store and retrieve data and processor-executable code to and from a volatile and / or non-volatile storage medium. The memory 114 may be configured much like an embodiment of the memory 106, such as a main memory, where the memory 114 may store data or processor-executable code for access by one or more of the CPU 104, the processor 124, or other components of the SoC 102. In some embodiments, the memory 114, being non-volatile, may retain information after the computing device 100 is powered off. When power is applied again and the computing device 100 reboots, the information stored on the memory 114 may be available to the computing device 100. In some embodiments, the memory 114, being volatile, may not retain information after the computing device 100 is powered off. The memory interface 110 may control access to the memory 114 and allow the CPU 104 , the processor 124 , or other components of the SoC 102 to read data from and write data to the memory 114 .

[0029] Some or all of the components of computing device 100 and / or SoC 102 may be arranged and / or combined differently while still supporting the functionality of the various embodiments. Computing device 100 may not be limited to one of each of the components, and multiple instances of each component may be included in various configurations of computing device 100.

[0030] 2 illustrates an exemplary SoC suitable for implementing various embodiments. With reference to FIG. 1 and FIG. 2, SoC 200 (e.g., SoC 102 of FIG. 1) may include various combinations of components, including any number and combination of processors 202 (e.g., CPU 104, processor 124 of FIG. 1), L3 cache 216 (e.g., memory 106 of FIG. 1), system cache 218 (e.g., memory 106 of FIG. 1), and / or system memory 224 (e.g., memory 106 of FIG. 1).

[0031] The processor 202 may include any number and combination of processor cores 204a, 204b, 204c, 206a, 206b, 206c. For example, the multi-core processor 202 may have multiple homogeneous or heterogeneous processor cores 204a, 204b, 204c, 206a, 206b, 206c. A homogeneous multi-core processor may include multiple homogeneous processor cores. The processor cores 204a, 204b, 204c, 206a, 206b, 206c of the multi-core processor 202 may be homogeneous in that they may be configured for the same purpose and may have the same or similar performance characteristics. For example, multi-core processor 202 may be a general-purpose processor, and processor cores 204a, 204b, 204c, 206a, 206b, 206c may be homogenous general-purpose processor cores. As another example, multi-core processor 202 may be a graphics processing unit or digital signal processor, and processor cores 204a, 204b, 204c, 206a, 206b, 206c may be homogenous graphics processor cores or digital signal processor cores.

[0032] A heterogeneous multi-core processor may include multiple heterogeneous processor cores. The processor cores 204a, 204b, 204c, 206a, 206b, 206c of the multi-core processor 202 may be heterogeneous in that they may be configured for different purposes and / or have different performance characteristics. The heterogeneity of such heterogeneous processor cores may include different instruction set architectures, pipelines, operating frequencies, etc. An example of such a heterogeneous processor core may include what is known as a "big.LITTLE" architecture, in which a slower, lower power processor core may be combined with a more powerful, power-hungry processor core.

[0033] The processor cores 204a, 204b, 204c, 206a, 206b, 206c may be grouped together as processor core clusters 212, 214. In general, the processor core clusters 212, 214 may include homogenous processor cores within each processor core cluster 212, 214. The processor core clusters 212, 214 may be homogenous or heterogeneous with the other processor core clusters 212, 214. For example, the processor core clusters 212, 214 may be homogenous having the same processor cores as one another. As another example, the processor core clusters 212, 214 may be heterogenous having different processor cores from one another. For ease of explanation, the terms "processor," "processor core," and "processor core cluster" may be used interchangeably herein.

[0034] The processor 202 may further include any number and combination of L2 caches 208a, 208b, 208c, 210a, 210b, 210c (e.g., memory 106 of FIG. 1). For example, each processor core cluster 212, 214 and / or each processor core 204a, 204b, 204c, 206a, 206b, 206c may have a dedicated L2 cache 208a, 208b, 208c, 210a, 210b, 210c. Each L2 cache 208a, 208b, 208c, 210a, 210b, 210c may be designated for read and / or write access by a designated processor core cluster 212, 214 and / or processor core 204a, 204b, 204c, 206a, 206b, 206c. The L2 caches 208a, 208b, 208c, 210a, 210b, 210c may store data and / or instructions and make the stored data and / or instructions available to designated processor core clusters 212, 214 and / or processor cores 204a, 204b, 204c, 206a, 206b, 206c. The L2 caches 208a, 208b, 208c, 210a, 210b, 210c may include volatile memory as described herein with reference to memory 106 of FIG.

[0035] The L3 cache 216, the system cache 218, and the system memory 224 may be shared by and configured for read and / or write access by the processor core clusters 212, 214 and / or the processor cores 204a, 204b, 204c, 206a, 206b, 206c. The L3 cache 216, the system cache 218, and the system memory 224 may store data and / or instructions and make the stored data and / or instructions available to the processor core clusters 212, 214 and / or the processor cores 204a, 204b, 204c, 206a, 206b, 206c. The L3 cache 216, the system cache 218, and / or the system memory 224 may function as buffers for data and / or instructions input to and / or output from the processor 202. L3 cache 216, system cache 218, and system memory 224 may include volatile memory such as described herein with reference to memory 106 of FIG.

[0036] The processor 202 may include a memory controller 220 configured to manage memory accesses to the L2 caches 208a, 208b, 208c, 210a, 210b, 210c, the L3 cache 216, and / or the system cache 218. The memory controller may receive memory access commands from the processor cores 204a, 204b, 204c, 206a, 206b, 206c and grant, enforce, and / or deny memory accesses to the caches 208a, 208b, 208c, 210a, 210b, 210c, 216, 218. The memory controller 220 may be configured to enforce cache maintenance, cache coherency, and / or cache replacement policies. The memory controller 220 may be configured to enforce virtual cache address translation.

[0037] The processor 202 may include any number and combination of registers 222 that can be configured to temporarily store small amounts of data. The registers 222 can be implemented in hardware and / or as memory locations in the caches 208a, 208b, 208c, 210a, 210b, 210c, 216, 218. Any number of registers can be configured to store data individually and / or in combination for a particular purpose associated with the registers 222. For example, the registers can store data configured to indicate to the processor 202 information regarding a particular purpose associated with the registers 222. As another example, an array of registers 222 can store a data vector in which any number and combination of bits can indicate to the processor 202 information regarding a particular purpose associated with the array of registers 222.

[0038] Some or all of the components of SoC 200 and / or processor 202 may be arranged and / or combined differently while still supporting the functionality of the various embodiments. For example, memory controller 220 may be a component of SoC 200 separate from processor 202.

[0039] 3A and 3B illustrate components and signaling for one example of a criteria-aware cache replacement policy, according to various embodiments. With reference to FIGS. 1-3, a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214 of FIG. 2) may implement a client 300 that may issue memory access commands to the system cache 218. For example, the processor may be the client 300. As another example, the processor may execute processes of a software program, which may be the client 300, such as an operating system and / or an application.

[0040] In the example shown in FIG. 3A, the client 300 can issue a memory access command 302, such as a write memory command to a system cache, which can be received by the memory controller 220. The client 300 can also perform a register write 304 to one or more registers 222, which can set a stale counter update value in the register 222. The register 222 can be associated with a stale counter update function for a reference-aware cache replacement policy. The value stored in the register 222 can be configured to indicate to the memory controller 220 whether to update a stale counter (not shown) configured for use by the reference-aware cache replacement policy. For example, the register write 304 can set the stale counter update value to a "1" value, which is configured to indicate to the memory controller 220 to update the stale counter. The client 300 can perform the register write 304 based on a criterion for the reference-aware cache replacement policy. In various embodiments, the criterion can be a time-based criterion, an event-based criterion, or another type of criterion. As an example of a time-based criterion, the client 300 can perform the register write 304 based on a period of time, a number of processor clock cycles, a number of instructions executed, etc. As examples of event-based criteria, the client 300 may perform register writes 304 based on completion, pausing, and / or termination of tasks, processes, and / or applications, starting, resuming, and / or loading of tasks, processes, and / or applications, interrupt signals, error and / or fault signals, etc.As an example of other criteria, the client 300 may perform the register write 304 based on a particular state or change in state, such as a power state, a security state, an availability state, etc., of a processor (e.g., CPU 104, processor 124, processor 202, FIG. 2), a memory (e.g., memories 106, 114, FIG. 1, caches 208a, 208b, 208c, 210a, 210b, 210c, 216, 218, FIG. 2), a peripheral device (e.g., peripheral device 122, FIG. 1), a communication component (e.g., communication component 112), etc. As another example, the client 300 may perform the register write 304 based on a start and / or end of a portion of data, such as a frame of compressed multimedia data based on frame time boundaries, a color field within a frame of compressed multimedia data, etc.

[0041] In response to receiving the write memory command 302, the memory controller 220 may read the register 222 to determine whether to update the stale counter (306). The memory controller 220 may retrieve the value of the register 222 and determine whether the value from the register indicates the memory controller 220 to update the stale counter.

[0042] In response to determining that the value of the register 222 indicates to the memory controller 220 to update the stale counter, the memory controller 220 may update the stale counter (308). The stale counter may include a value stored in a memory that may be readable and write accessible by the memory controller 220 (e.g., memory 106, memory 114 of FIG. 1, L2 caches 208a, 208b, 208c, 210a, 210b, 210c of FIG. 2, L3 cache 216, system cache 218 of FIGS. 2 and 3, register 222). The memory controller 220 may update the stale counter by any mathematical, algorithmic, heuristic, etc. operation, such as by incrementing and / or decrementing the stale counter. In response to determining that the value of the register 222 indicates to the memory controller 220 not to update the stale counter, the memory controller 220 may refrain from updating the stale counter (308).

[0043] Memory controller 220 may read (310) a local counter for data at a location in system cache 218. The local counter value may include a stale counter value stored in association with the associated data being written to system cache 218 in response to a previous write memory command. In one embodiment, memory controller 220 may read one or more local counter values ​​stored with a cache tag for a memory location targeted by a write memory command. In another embodiment, memory controller 220 may read one or more local counter values ​​for a location within a block, partition, the entirety, and / or any other portion of system cache 218.

[0044] The memory controller 220 may use the retrieved value of the local counter to help determine which portion of the system cache 218 should be replaced according to a reference-aware cache replacement policy when implementing a write memory command. In operation 312, the memory controller 220 may calculate a replacement value and compare the replacement value to a stale threshold. For example, the memory controller 220 may use an arithmetic operation to generate the replacement value using the value of the local counter and the stale counter value. For example, the memory controller 220 may subtract the value of the local counter from the value of the stale counter to determine the replacement value. The memory controller 220 may compare the replacement value to the stale threshold to determine whether to replace the data associated with the local counter value. The stale threshold may be a preconfigured value. For example, the stale threshold may be preconfigured based on a reference-aware cache replacement policy. As another example, the stale threshold may be preconfigured based on a size, condition, usage, availability, etc. of the system cache 218. As another example, the stalling threshold may be pre-configured based on the state of the processor and / or computing device (e.g., computing device 100 of FIG. 1), usage, power availability, etc. As another example, the stalling threshold may be pre-configured based on tasks, processes, and / or applications being performed and / or having been performed by the client 300.

[0045] The result of the comparison of the replacement value to the stale threshold may indicate to the memory controller 220 whether a reference-aware cache replacement policy should replace the data associated with the local counter value. For example, in response to the replacement value being equal to or greater than the stale threshold, the memory controller 220 may implement a reference-aware cache replacement policy to replace the data associated with the local counter value with the data of the write memory command. The memory controller 220 may replace the data associated with the local counter value by writing (314) the data of the write memory command to a location in the system cache 218 that stores the data associated with the local counter. If not, the memory controller 220 may write (314) the data of the write memory command to another location in the system cache 218. The memory controller 220 may also write (316) the value of the stale counter to the system cache 218 as a local counter in association with the data of the write memory command written to the system cache 218. For example, the memory controller 220 may write (316) the value of the stale counter to a tag location in the system cache 218 associated with the data of the write memory command written to the system cache 218.

[0046] In the example shown in FIG. 3B , the client 300 may issue a memory access command 302, such as a read memory command to a system cache, which may be received by the memory controller 220. The client 300 may also perform a register write 304 to one or more registers 222, which may set a stale counter update value in the register 222. In response to receiving the read memory command 302, the memory controller 220 may read the register 222 to determine whether to update the stale counter (306). In response to determining that the value of the register 222 indicates the memory controller 220 to update the stale counter, the memory controller 220 may update the stale counter (308). The memory controller 220 may read the data associated with the local counter value by reading (315) the data at a location in the system cache 218 that is associated with the local counter and that stores the data targeted by the read memory command. Memory controller 220 may also write the value of the stale counter as a local counter to system cache 218 in association with the data at the location in system cache 218 targeted by the read memory command (317). For example, memory controller 220 may write the value of the stale counter to a tag location in system cache 218 associated with the data at the location in system cache 218 targeted by the read memory command (317).

[0047] The order of signals 302, 304, 308, 310, 312, 314, 316 in Figure 3A and signals 302, 304, 308, 315, 317 in Figure 3B are examples only, and the order of signals 302, 304, 308, 310, 312, 314, 315, 316, 317 may be performed in a different order. For example, the order of signals 302 and 304, the order of signals 314 and 316, and / or the order of signals 315 and 317 may be reversed. As another example, signals 302 and 304, signals 314 and 316, and / or signals 315 and 317 may be transmitted simultaneously.

[0048] 4 illustrates an example of a memory flow for implementing a criteria-aware cache replacement policy, according to one embodiment. With reference to FIGS. 1-4, a memory controller (e.g., memory controller 220 of FIGS. 2 and 3) may implement write memory commands 410a, 410b, 410c in a system cache 400 (e.g., system cache 218 of FIGS. 2 and 3) and implement stale counter updates 412a, 412b in a stale counter 402. The write memory commands 410a, 410b, 410c may be issued by a client (e.g., client 300) of a computing device (e.g., computing device 100 of FIG. 1).

[0049] The write memory command 410a may be received by the memory controller and prompt the memory controller to write data to the system cache 400. The stale counter 402 when performing the write memory command 410a may be "1". The data of the write memory command 410a may be written to the system cache 400 with a stale counter value of "1" as a local counter associated with the location 404 in the system cache where the data is written.

[0050] Another write memory command 410b may be received by the memory controller, prompting the memory controller to write data to the system cache 400, and the stale counter may be updated (412a) according to a register value read by the memory controller from a register (e.g., register 222 in FIGS. 2 and 3). The register value may be set by a register write (e.g., register write 304 in FIG. 3) performed by the client along with the write memory command 410b. The stale counter 402 when performing the write memory command 410c may be "2". The data of the write memory command 410b may be written to the system cache 400 along with the stale counter value "2" as a local counter associated with the location 406 in the system cache to which the data is written. In this example, the location 406 may be an open location before the data and local counter of the write memory command 410b are written to the location 406. The write memory command 410b may prompt the criteria-aware cache replacement policy to check the system cache 400 for data to be replaced, although replacement may not be implemented in the system cache 400. Replacement may not be implemented for data that does not meet the criteria of the criteria-aware cache replacement policy. For example, the criteria-aware cache replacement policy may determine whether the difference between the local counter for the location 404 in the system cache 400 where the data was written ("1" in this example) and the stale counter 402 ("2" in this example) at the time of the write memory command 410b may be less than a stale threshold.

[0051] Another write memory command 410c may be received by the memory controller, prompting the memory controller to write data to the system cache 400, and the stale counter may be updated according to the register value read by the memory controller (412b). The register value may be set by a register write (e.g., register write 304 of FIG. 3) performed by the client along with the write memory command 410c. The stale counter 402 when performing the write memory command 410c may be "3". The data of the write memory command 410c may be written to the system cache 400 along with a stale counter value of "3" as a local counter associated with the location 404 in the system cache to which the data is written. In this example, the location 404 may be an occupied location before the data and local counter of the write memory command 410c are written to the location 404. The write memory command 410b may prompt the reference-aware cache replacement policy to check the system cache 400 for data to be replaced. In this example, replacement may be performed for some locations 404 and not for other locations 406 in the system cache 400. Replacement may not be performed for data that does not meet the criteria of the criteria-aware cache replacement policy. For example, the criteria-aware cache replacement policy may determine whether the difference between the local counter for the location 406 in the system cache 400 where the data was written ("2" in this example) and the stale counter 402 at the time of the write memory command 410c ("3" in this example) may be less than a stale threshold. Replacement may be performed for data that meets the criteria of the criteria-aware cache replacement policy.For example, a reference-aware cache replacement policy may determine whether the difference between the local counter for location 404 in system cache 400 where data was written ("1" in this example) and the stale counter 402 at the time of write memory command 410c ("3" in this example) may be greater than or equal to a stale threshold. The memory controller may replace the data and local counter for location 404 with the data and stale counter values ​​for write memory command 410c.

[0052] FIG. 5 illustrates an example of a memory flow for implementing a reference-aware cache replacement policy, according to one embodiment. With reference to FIGS. 1-5, a memory controller (e.g., memory controller 220 of FIGS. 2 and 3) can implement a write memory command (Write N) and a read memory command (Read N) in a system cache (e.g., system cache 218 of FIGS. 2 and 3, system cache 400 of FIG. 4). The write memory command and the read memory command can be issued by a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) (e.g., processor 1 and processor 2 of FIG. 5) of a computing device (e.g., computing device 100 of FIG. 1).

[0053] At the time of a write 0 write memory command from processor 1, the stale counter may have a value of "0." The write 0 data may be written to a system cache with the stale counter value "0" as a local counter associated with the write 0 data.

[0054] The Write 0 may be followed by a Read 0 read memory command from processor 2. The memory controller may read the data in the system cache targeted by the Read 0. For example, the memory controller may read the data at the location in the system cache associated with a local counter value of "0."

[0055] Read 0 may be followed by a write 1 write memory command from processor 1. The stale counter may have been updated and may have a value of "1" at the time of write 1. Write 1 may prompt the reference-aware cache replacement policy to check for stale data by comparing a local counter associated with the data in the system cache to a stale threshold. For example, the memory controller may read the local counter from the system cache, calculate a difference between the value of the stale counter and the value of the local counter, and compare the difference to the stale threshold. In response to the difference being less than the stale threshold, the reference-aware cache replacement policy may determine not to replace the data associated with the local counter in the system cache, as in the example of write 1. In this example, the data of write 1 may be written to an open location in the system cache with a stale counter value of "2" as the local counter associated with the data of write 1.

[0056] Write 1 may be followed by a second (i.e., Write 2) write memory command from processor 1. The stale counter may have been updated and may have a value of “2” at the time of Write 2. Write 2 may prompt the reference-aware cache replacement policy to check for stale data by comparing a local counter associated with the data in the system cache to a stale threshold. For example, the memory controller may read the local counter from the system cache, calculate a difference between the value of the stale counter and the value of the local counter, and compare the difference to the stale threshold. In response to the difference being less than the stale threshold, the reference-aware cache replacement policy may determine not to replace the data associated with the local counter in the system cache. In response to the difference being equal to or greater than the stale threshold, the reference-aware cache replacement policy may determine to replace the data associated with the local counter in the system cache. In this example, the data associated with the local counter having a value “0” may be determined to be stale because the difference between the stale counter and the local counter may be equal to or greater than the stale threshold. As a result, the reference-aware cache replacement policy may determine to replace the data associated with the local counter having a value “0”. Because the difference between the stale counter and the local counter is less than the stale threshold, it may be determined that the data associated with the local counter having a value of "1" is not stale. As a result, the reference-aware cache replacement policy may determine not to replace the data associated with the local counter having a value of "2." The data of Write 2 may be written to the open location in the system cache and to the location occupied by the data associated with a local counter value of "0," with a stale counter value of "2" as the local counter associated with the data of Write 2.

[0057] Write 2 may be followed by a Read 1 read memory command from processor 2. The memory controller may read the data in the system cache targeted by Read 1. For example, the memory controller may read the data at the location in the system cache associated with a local counter value of "1."

[0058] Read 1 may be followed by a write 3 write memory command from processor 1. The stale counter may have been updated and may have a value of “3” at the time of write 3. Write 3 may prompt the reference-aware cache replacement policy to check for stale data by comparing a local counter associated with the data in the system cache to a stale threshold. For example, the memory controller may read the local counter from the system cache, calculate a difference between the value of the stale counter and the value of the local counter, and compare the difference to the stale threshold. In response to the difference being less than the stale threshold, the reference-aware cache replacement policy may determine not to replace the data associated with the local counter in the system cache. In response to the difference being equal to or greater than the stale threshold, the reference-aware cache replacement policy may determine to replace the data associated with the local counter in the system cache. In this example, data associated with a local counter having a value “0” or “1” may be determined to be stale because the difference between the stale counter and the local counter may be equal to or greater than the stale threshold. As a result, the reference-aware cache replacement policy may determine to replace the data associated with a local counter having a value “0” or “1”. Because the difference between the stale counter and the local counter may be less than a stale threshold, it may be determined that the data associated with the local counter having a value of "2" is not stale. As a result, the reference-aware cache replacement policy may determine not to replace the data associated with the local counter having a value of "2". However, the reference-aware cache replacement policy may not control all replacement of data in the system cache. For example, a mechanism for writing data to the system cache may be defined such that it may not be perfectly consistent with the reference-aware cache replacement policy under certain circumstances.The data of Write 3 may be written to a location in the system cache occupied by data associated with a local counter value of "0" or "1", along with a stale counter value of "3" as the local counter associated with the data of Write 2. However, the mechanism for writing data to the system cache may write the data in a manner determined by the number of lines in the set. Thus, a situation may arise where Write 3 may replace data that is not stale under a reference-aware cache replacement policy, such as the data associated with a local counter value of "2".

[0059] Write 3 may be followed by a Read 2 read memory command from processor 2. The memory controller may read the data in the system cache targeted by Read 2. For example, the memory controller may read the data at a location in the system cache associated with a local counter value of "2." The data targeted by Read 2 may be partially replaced by the data written to the system cache by Write 3, but in contrast to other cache replacement policies such as not-most recently used (nMRU) and capacity-based first-in, first-out (FIFO), a criteria-aware cache replacement policy allows for a higher hit rate (or lower miss rate) for data in the system cache.

[0060] FIG. 6 illustrates a method 600 for implementing a criteria-aware cache replacement policy, according to some embodiments. With reference to FIGS. 1-6, the method 600 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software (e.g., client 300 of FIG. 3) executing in a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214, client 300 of FIG. 3), or in software. 1 and 2. The method 600 may be implemented in combination with dedicated hardware including a configured processor and other individual components such as various memories / caches (e.g., memory 106, memory 114 of FIG. 1, L2 caches 208a, 208b, 208c, 210a, 210b, 210c of FIG. 2, L3 cache 216, system cache 218 of FIGS. 2 and 3, registers 222, system cache 400 of FIG. 4) and various memory / cache controllers (e.g., memory controller 220 of FIGS. 2 and 3). To encompass alternative configurations possible in various embodiments, the hardware implementing the method 600 is referred to herein as a "client" and a "memory control device."

[0061] At block 602, the client may send a write memory command targeting a system cache (e.g., system cache 218 of FIG. 2 and FIG. 3, system cache 400 of FIG. 4). At block 604, the client may signal a processor (e.g., CPU 104 of FIG. 1, processor 124, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) to update a stale counter of data in the system cache. Signaling to the processor may be accomplished using various types of signal communication, including, for example, a register write to a register (e.g., register 222 of FIG. 2 and FIG. 3), a direct interrupt to the processor, etc. The register may be associated with a stale counter update function for a criteria-aware cache replacement policy. Writing to the register may set a value in the register configured to indicate to the memory control device whether the stale counter should be updated. In some embodiments, the client that sends the write memory command at block 602 and signals the processor to update a stale counter for data in the system cache at block 604 may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or a software program such as an operating system and / or an application (e.g., client 300 of FIG. 3).

[0062] In block 606, the memory control device may receive the write memory command. The memory control device may be configured to manage, control, and / or implement memory access, cache maintenance, cache coherency, and / or cache replacement policies for the system cache. In block 608, the memory control device may implement a criteria-aware cache replacement policy for writing data of the write memory command to the system cache. The memory control device that receives the write memory command in block 606 and implements the criteria-aware cache replacement policy in block 608 may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or a memory controller (e.g., memory controller 220 of FIG. 2 and FIG. 3).

[0063] 7 illustrates a method 700 for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to some embodiments. With reference to FIGS. 1-7, the method 700 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software (e.g., client 300 of FIG. 3) running on a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214, client 300 of FIG. 3), or in software. 7 and 8. The method 700 may be implemented in combination with dedicated hardware including a processor configured and other individual components such as various memories / caches (e.g., memory 106, memory 114, L2 caches 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, system cache 218, registers 222, system cache 400, and other individual components of FIG. 4) and various memory / cache controllers (e.g., memory controller 220, and other components of FIG. 5). To encompass alternative configurations possible in various embodiments, the hardware implementing method 700 is referred to herein as a "memory control device." Blocks 702-714 of method 700 further describe operations that may be performed in block 608 of method 600 described with reference to FIG. 6.

[0064] At block 702, a memory control device may receive a signal to update a stale counter of data in a system cache (e.g., system cache 218 of FIGS. 2 and 3 and system cache 400 of FIG. 4). For example, the memory control device may read a register (e.g., register 222 of FIGS. 2 and 3), receive a direct interrupt, etc., to update the stale counter of data in the system cache. The register may be associated with a stale counter update function for a reference-aware cache replacement policy and may have a value configured to indicate to the memory control device whether to update the stale counter. The value of the register may be set, for example, by writing to the register to update the stale counter of data in the system cache, as described with respect to block 604 of method 600 (FIG. 6). The memory control device may read the value of the register to update the stale counter. In some embodiments, the memory control device that receives the signal to update the stale counter of the data in the system cache at block 702 may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or a memory controller (e.g., memory controller 220 of FIGS. 2 and 3).

[0065] In optional decision block 704, the memory control device may interpret the register value read in block 702 to determine whether the register value indicates that the memory control device should update the stale counter. The value stored in the register may be configured to indicate to the memory control device whether to update the stale counter. For example, the register value may be set to a "1" value to indicate to the memory control device that the stale counter should be updated and set to a "0" value to indicate to the memory control device that the stale counter should not be updated, or vice versa. In some embodiments, the memory control device may read the value of the register to update the stale counter. In some embodiments, the memory control device that determines in optional decision block 704 whether the register value indicates to the memory control device to update the stale counter may be a processor and / or a memory controller.

[0066] After receiving a signal to update the stale counter of the data in the system cache at block 702 or in response to determining that the register value indicates to the memory control device to update the stale counter (i.e., optional decision block 704="yes"), the memory control device may update the stale counter at block 706. In some embodiments, updating the stale counter at block 706 may be performed when (i.e., at the time) the data is written to the system cache. The stale counter may include a value stored in a memory (e.g., memory 106, memory 114 of FIG. 1, L2 caches 208a, 208b, 208c, 210a, 210b, 210c of FIG. 2, L3 cache 216, system cache 218 of FIGS. 2 and 3, register 222, system cache 400 of FIG. 4) that may be readable and write accessible by the memory control device. Updating the stale counter may be performed by any mathematical, algorithmic, heuristic, etc. operation, such as by incrementing and / or decrementing the stale counter. In some embodiments, the memory control device that updates the stale counter at block 706 may be a processor and / or a memory controller.

[0067] In response to determining that the register value indicates to the memory control device not to update the stale counter (i.e., optional decision block 704="no") or after updating the stale counter in block 706, the memory control device may calculate a replacement value for the data associated with the local counter in block 708. In some embodiments, the memory control device that calculates the replacement value for the data associated with the local counter in block 708 may be a processor and / or a memory controller. The local counter may include a value of the stale counter stored in association with data written to the system cache in response to a previous write memory command. In one example, the memory control device may read one or more local counter values ​​stored with a cache tag of a memory location targeted by a write memory command received in block 606 of the method 600 described with reference to FIG. 6. In another example, the memory control device may read one or more local counter values ​​for a location within a block, partition, entirety, and / or any other portion of the system cache.

[0068] The stalling threshold may be a pre-configured value. For example, the stalling threshold may be pre-configured based on a criteria-aware cache replacement policy. As another example, the stalling threshold may be pre-configured based on the size, state, usage, availability, etc. of a system cache. As another example, the stalling threshold may be pre-configured based on the state, usage, power availability, etc. of a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or computing device (e.g., computing device 100 of FIG. 1). As another example, the stalling threshold may be pre-configured based on a task, process, and / or application.

[0069] The memory control device may calculate a replacement value at the stale threshold. For example, the memory control device may use an arithmetic operation to generate the replacement value using the value of the local counter and the stale counter value. For example, the memory control device may subtract the value of the local counter from the value of the stale counter to determine the replacement value.

[0070] In decision block 709, the memory control device may determine whether the replacement values ​​for all data in locations within the block, partition, entirety, and / or any other portion of the system cache are the same. In decision block 709, the memory control device may compare the replacement values ​​calculated in block 708 to each other. For example, the memory control device may determine from the comparison whether the replacement values ​​are equal to each other. In some embodiments, the memory control device that determines in decision block 709 whether the replacement values ​​for all data in locations within the block, partition, entirety, and / or any other portion of the system cache are the same may be a processor and / or a memory controller.

[0071] In response to determining that the replacement values ​​for all data at locations within a block, partition, the entirety, and / or any other portion of the system cache are the same (i.e., decision block 709="yes"), the memory control device may select a cache replacement policy other than a reference-aware cache replacement policy at block 711. For example, the memory control device may select a cache replacement policy such as nMRU, FIFO, random, etc. In some embodiments, the memory control device that selects a cache replacement policy other than a reference-aware cache replacement policy at block 711 may be a processor and / or a memory controller.

[0072] After selecting a cache replacement policy other than the reference-aware cache replacement policy at block 711, the memory control device may receive a write memory command at block 606 of method 600, as described with reference to Figure 6. The memory control device that receives the write memory command at block 606 may be a processor and / or a memory controller.

[0073] In response to determining that the replacement values ​​for all data at locations within the block, partition, entirety, and / or any other portion of the system cache are not the same (i.e., decision block 709="no"), the memory control device may determine whether the replacement value is greater than or equal to a stalling threshold in decision block 710. The memory control device may compare the replacement value calculated in block 708 to a stalling threshold to determine whether to replace the data associated with the local counter value. For example, the memory control device may determine from the comparison whether the replacement value is greater than, equal to, or greater than or equal to the stalling threshold. In some embodiments, the memory control device that determines whether the replacement value is greater than or equal to the stalling threshold in decision block 710 may be a processor and / or a memory controller.

[0074] In response to determining that the replacement value is greater than or equal to the stale threshold (i.e., decision block 710="yes"), the memory control device may, in block 712 of method 700 (FIG. 7), write the data of the write memory command received in block 606 of method 600 (FIG. 6) and the value of the stale counter to the memory at the location where the replacement value is greater than or equal to the stale threshold. The result of the comparison of the replacement value to the stale threshold at decision block 710 may indicate to the memory control device whether a reference-aware cache replacement policy should replace the data associated with the local counter value used to calculate the replacement value in block 708. For example, in response to the replacement value being greater than or equal to the stale threshold, the memory control device may implement a reference-aware cache replacement policy to replace the data associated with the local counter value with the data of the write memory command. The memory control device may replace the data associated with the local counter value by writing the data of the write memory command to a location in the system cache that stores the data associated with the local counter. The memory control device may also write the value of the stale counter as a local counter to the system cache in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the stale counter to memory at block 712 at the location where the replacement value is greater than or equal to the stale threshold may be a processor and / or a memory controller.

[0075] In response to determining that the replacement value is not greater than or equal to the stale threshold (i.e., decision block 710="no"), the memory control device may write the data of the write memory command received in block 606 of method 600 (FIG. 6) and the value of the stale counter to memory at a location according to the criteria in block 714. The criteria used to determine where to write the data of the write memory command and the value of the stale counter to the system cache may be any known criteria, such as a cache placement policy, a cache replacement policy, a cache coherency policy, etc. The memory control device may also write the value of the stale counter to the system cache as a local counter in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the stale counter to memory at a location according to the criteria in block 714 may be a processor and / or a memory controller.

[0076] After writing the data of the write memory command and the value of the stale counter to the memory at the location where the replacement value is greater than or equal to the stale threshold at block 712 or writing the data of the write memory command and the value of the stale counter to the memory at the location according to the criteria at block 714, the memory control device may receive the write memory command at block 606 of method 600, as described with reference to Figure 6. The memory control device that receives the write memory command at block 606 may be a processor and / or a memory controller.

[0077] 8 illustrates a method 800 for implementing a criteria-aware cache replacement policy that replaces data based on the value of a local counter, according to some embodiments. With reference to FIGS. 1-8, the method 800 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software (e.g., client 300 of FIG. 3) running on a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214, client 300 of FIG. 3), or in software. 8 and 9. The method 800 may be implemented in combination with dedicated hardware including a processor configured and other individual components such as various memories / caches (e.g., memory 106, memory 114, L2 caches 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, system cache 218, registers 222, system cache 400, and other individual components of FIG. 4) and various memory / cache controllers (e.g., memory controller 220, and other components of FIG. 5). To encompass alternative configurations possible in various embodiments, the hardware implementing the method 800 is referred to herein as a "memory control device." Blocks 802-814 of the method 800 further describe operations that may be performed in block 608 of the method 600 described with reference to FIG. 6.

[0078] At block 802, the memory control device may calculate a replacement value for the data associated with the local counter. In some embodiments, the memory control device that calculates the replacement value for the data associated with the local counter at block 802 may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or a memory controller (e.g., memory controller 220 of FIGS. 2 and 3). The local counter may include a value of a stale counter stored in association with data written to a system cache (e.g., system cache 218 of FIGS. 2 and 3, system cache 400 of FIG. 4) in response to a previous write memory command. The stale counter may include values ​​stored in memory that may be readable and write accessible by the memory control device (e.g., memory 106, memory 114 of FIG. 1, L2 caches 208a, 208b, 208c, 210a, 210b, 210c of FIG. 2, L3 cache 216, system cache 218 of FIGS. 2 and 3, register 222, system cache 400 of FIG. 4). In one embodiment, the memory control device may read one or more local counter values ​​stored with a cache tag of a memory location targeted by a write memory command received in block 606 of method 600 described with reference to FIG. 6. In another embodiment, the memory control device may read one or more local counter values ​​for a location within a block, partition, the entirety, and / or any other portion of the system cache.

[0079] The stalling threshold may be a pre-configured value. For example, the stalling threshold may be pre-configured based on a criteria-aware cache replacement policy. As another example, the stalling threshold may be pre-configured based on the size, state, usage, availability, etc. of a system cache. As another example, the stalling threshold may be pre-configured based on the state, usage, power availability, etc. of a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or computing device (e.g., computing device 100 of FIG. 1). As another example, the stalling threshold may be pre-configured based on a task, process, and / or application.

[0080] The memory control device may calculate a replacement value at the stale threshold. For example, the memory control device may use an arithmetic operation to generate the replacement value using the value of the local counter and the stale counter value. For example, the memory control device may subtract the value of the local counter from the value of the stale counter to determine the replacement value.

[0081] In decision block 803, the memory control device may determine whether the replacement values ​​for all data in locations within the block, partition, entirety, and / or any other portion of the system cache are the same. In this determination, the memory control device may compare the replacement values ​​calculated in block 802 to each other. For example, the memory control device may determine from the comparison whether the replacement values ​​are equal to each other. In some embodiments, the memory control device that determines in decision block 803 whether the replacement values ​​for all data in locations within the block, partition, entirety, and / or any other portion of the system cache are the same may be a processor and / or a memory controller.

[0082] In response to determining that the replacement values ​​for all data at locations within a block, partition, the entirety, and / or any other portion of the system cache are the same (i.e., decision block 803="yes"), the memory control device may select a cache replacement policy other than a reference-aware cache replacement policy at block 805. For example, the memory control device may select an nMRU or a FIFO cache replacement policy. In some embodiments, the memory control device that selects a cache replacement policy other than a reference-aware cache replacement policy at block 805 may be a processor and / or a memory controller.

[0083] After selecting a cache replacement policy other than the reference-aware cache replacement policy at block 805, the memory control device may receive a write memory command at block 606 of method 600, as described with reference to Figure 6. The memory control device that receives the write memory command at block 606 may be a processor and / or a memory controller.

[0084] In response to determining that the replacement values ​​for all data at locations within the block, partition, entirety, and / or any other portion of the system cache are not the same (i.e., decision block 709="no"), the memory control device may determine whether the replacement value is greater than or equal to a stalling threshold in decision block 804. The memory control device may compare the replacement value calculated in block 802 to a stalling threshold to determine whether to replace the data associated with the local counter value. For example, the memory control device may determine from the comparison whether the replacement value is greater than, equal to, or greater than or equal to the stalling threshold. In some embodiments, the memory control device that determines whether the replacement value is greater than or equal to the stalling threshold in decision block 804 may be a processor and / or a memory controller.

[0085] In response to determining that the replacement value is greater than or equal to the stale threshold (i.e., decision block 804="yes"), the memory control device may, in block 806, write the data of the write memory command received in block 606 of method 600 (FIG. 6) and the value of the stale counter to the memory at the location where the replacement value is greater than or equal to the stale threshold. The result of the comparison of the replacement value to the stale threshold in decision block 804 may indicate to the memory control device whether a reference-aware cache replacement policy should replace the data associated with the local counter value used to calculate the replacement value in block 802. For example, in response to the replacement value being greater than or equal to the stale threshold, the memory control device may implement a reference-aware cache replacement policy to replace the data associated with the local counter value with the data of the write memory command. The memory control device may replace the data associated with the local counter value by writing the data of the write memory command to a location in the system cache that stores the data associated with the local counter. The memory control device may also write the value of the stale counter as a local counter to the system cache in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the stale counter to memory at block 806 at the location where the replacement value is greater than or equal to the stale threshold may be a processor and / or a memory controller.

[0086] In response to determining that the replacement value is not greater than or equal to the stale threshold (i.e., decision block 804="no"), the memory control device may write the data of the write memory command received in block 606 of method 600 (FIG. 6) and the value of the stale counter to memory at a location according to the criteria in block 808. The criteria used to determine where to write the data of the write memory command and the value of the stale counter to the system cache may be any known criteria, such as a cache placement policy, a cache replacement policy, a cache coherency policy, etc. The memory control device may also write the value of the stale counter to the system cache as a local counter in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the stale counter to memory at a location according to the criteria in block 808 may be a processor and / or a memory controller.

[0087] After or as part of writing the data and stale counter value of the write memory command to the memory at the location where the replacement value is equal to or greater than the stale threshold value at block 806 or writing the data and stale counter value of the write memory command to the memory at the location according to the criteria at block 808, the memory control device may receive a signal to update the stale counter of the data in the system cache. For example, the memory control device may read a register (e.g., register 222 of FIGS. 2 and 3), receive a direct interrupt, etc., to update the stale counter of the data in the system cache at block 810. The register may be associated with a stale counter update function for the criteria-aware cache replacement policy and may have a value configured to indicate to the memory control device whether to update the stale counter. The value of the register may be set, for example, by writing to the register to update the stale counter of the data in the system cache as described with respect to block 604 of method 600 with reference to FIG. 6. The memory control device may read the value of the register to update the stale counter. In some embodiments, the memory control device that receives the signal to update the stale counter for data in the system cache at block 810 may be a processor and / or a memory controller.

[0088] In optional decision block 812, the memory control device may determine whether the register value indicates to the memory control device to update the stale counter. The value stored in the register may be configured to indicate to the memory control device whether to update the stale counter. For example, the register value may set the stale counter update value to a "1" value configured to indicate to the memory control device to update the stale counter and a "0" value configured to indicate to the memory control device not to update the stale counter, or vice versa. The memory control device may interpret the register value read in block 810 to determine whether the register value indicates to update the stale counter. In some embodiments, the memory control device may read a value of a register for updating the stale counter. In some embodiments, the memory control device that determines whether the register value indicates to the memory control device to update the stale counter in optional decision block 812 may be a processor and / or a memory controller.

[0089] After receiving a signal to update the stale counter of the data in the system cache at block 810 or in response to determining that the register value indicates to the memory control device to update the stale counter (i.e., optional decision block 812="yes"), the memory control device may update the stale counter at block 814. In some embodiments, updating the stale counter at block 814 may be performed when (i.e., approximately simultaneously with) the data is written to the system cache (e.g., at blocks 806 or 808). Updating the stale counter may be performed by any mathematical, algorithmic, heuristic, etc. operation, such as by incrementing and / or decrementing the stale counter. In some embodiments, the memory control device that updates the stale counter at block 814 may be a processor and / or a memory controller.

[0090] After updating the stale counter at block 814 or in response to determining that the register value indicates to the memory control device not to update the stale counter (i.e., optional decision block 812="No"), the memory control device may receive a write memory command at block 606 of method 600, as described with reference to Figure 6. The memory control device that receives the write memory command at block 606 may be a processor and / or a memory controller.

[0091] 9 illustrates a method 900 for implementing a criteria-aware cache replacement policy that replaces data based on invalidating the data based on the value of a local counter, according to some embodiments. With reference to FIGS. 1-9, the method 900 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software (e.g., client 300 of FIG. 3) running on a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214, client 300 of FIG. 3), or in software. 1 and 2. The method 900 may be implemented in combination with dedicated hardware including a processor configured and other individual components such as various memories / caches (e.g., memory 106, memory 114, L2 caches 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, system cache 218, registers 222, system cache 400, and 4 of FIG. 1 and 2) and various memory / cache controllers (e.g., memory controller 220, and 4 of FIG. 2 and 3). To encompass alternative configurations possible in various embodiments, the hardware performing the method 900 is referred to herein as a "memory control device." Blocks 702-711, 714, 902, 904 of the method 900 describe operations that may be performed as part of the operations in block 608 of the method 600 described with reference to FIG. 6. Blocks 702-711, 714 may be implemented similarly to similarly numbered blocks of the method 700 described with reference to FIG. 7.

[0092] In response to determining that the replacement value is greater than or equal to the stalling threshold (i.e., decision block 710="yes"), the memory control device may invalidate data at the location where the replacement value is greater than or equal to the stalling threshold at block 902. The result of the comparison of the replacement value to the stalling threshold at decision block 710 may indicate to the memory control device whether a reference-aware cache replacement policy should replace data associated with the local counter value used to calculate the replacement value at block 708. For example, in response to the replacement value being greater than or equal to the stalling threshold, the memory control device may implement a reference-aware cache replacement policy to replace data associated with the local counter value with data of the write memory command. The memory control device may invalidate the data using known methods for invalidating data in memory. For example, the memory control device may write a value of a valid / invalid bit associated with a location in a system cache (e.g., system cache 218 of FIGS. 2 and 3, system cache 400 of FIG. 4) associated with the local counter value used to calculate the replacement value at block 708. The value of the valid / invalid bit may be configured to indicate to the memory control device whether the data at the location in the system cache is valid / invalid. In some embodiments, the memory control device that invalidates data at locations where the replacement value is greater than or equal to the stale threshold at block 902 may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or a memory controller (e.g., memory controller 220 of FIGS. 2 and 3).

[0093] In block 904, the memory control device may write the data of the write memory command received in block 606 of method 600 (FIG. 6) and the value of the stale counter to memory at the locations where the data is invalid. The memory control device may read the valid / invalid bits of the locations in the system cache to determine which locations have valid / invalid data. The memory control device may replace the data associated with the local counter value by writing the data of the write memory command to the location in the system cache that stores the data associated with the valid / invalid bits. The memory control device may also write the value of the stale counter to the system cache as a local counter in association with the data of the write memory command written to the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the stale counter to memory at the locations where the data is invalid in block 904 may be a processor and / or a memory controller.

[0094] After writing the data of the write memory command and the value of the stale counter to memory at a location where the data is invalid at block 904 or writing the data of the write memory command and the value of the stale counter to memory at a location according to the criteria at block 714, the memory control device may receive the write memory command at block 606 of method 600, as described with reference to Figure 6. The memory control device that receives the write memory command at block 606 may be a processor and / or a memory controller.

[0095] 10 illustrates a method 1000 for implementing a criteria-aware cache replacement policy that replaces data based on invalidating the data based on the value of a local counter, according to some embodiments. With reference to FIGS. 1-10, the method 1000 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software (e.g., client 300 of FIG. 3) running in a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214 of FIG. 3), or in software. 1 and other individual components such as various memory / caches (e.g., memory 106, memory 114, L2 caches 208a, 208b, 208c, 210a, 210b, 210c, L3 cache 216, system cache 218, registers 222, system cache 400, FIG. 4) and various memory / cache controllers (e.g., memory controller 220, FIG. 2 and FIG. 3). To encompass alternative configurations possible in various embodiments, the hardware implementing method 1000 is referred to herein as a "memory control device." Blocks 802-805, 808-814, 1002, 1004 of method 1000 may describe operations that may be performed as part of block 608 of method 600 described with reference to FIG. 6. Blocks 802-805, 808-814 may be implemented similarly to similarly numbered blocks of method 900 described herein with reference to FIG.

[0096] In response to determining that the replacement value is greater than or equal to the stale threshold (i.e., decision block 804="yes"), the memory control device may invalidate data at the location where the replacement value is greater than or equal to the stale threshold at block 1002. The result of the comparison of the replacement value to the stale threshold at decision block 804 may indicate to the memory control device whether a reference-aware cache replacement policy should replace data associated with the local counter value used to calculate the replacement value at block 802. For example, in response to the replacement value being greater than or equal to the stale threshold, the memory control device may implement a reference-aware cache replacement policy to replace data associated with the local counter value with data of the write memory command. The memory control device may invalidate the data using known methods for invalidating data in memory. For example, the memory control device may write a value of a valid / invalid bit associated with a location in a system cache (e.g., system cache 218 of FIGS. 2 and 3, system cache 400 of FIG. 4) associated with the local counter value used to calculate the replacement value at block 802. The value of the valid / invalid bit may be configured to indicate to the memory control device whether the data at the location in the system cache is valid / invalid. In some embodiments, the memory control device that invalidates data at locations where the replacement value is greater than or equal to the stale threshold at block 1002 may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or a memory controller (e.g., memory controller 220 of FIGS. 2 and 3).

[0097] In block 1004, the memory control device may write the data of the write memory command received in block 606 of method 600 (FIG. 6) and the value of the stale counter to memory at the locations where the data is invalid. The memory control device may read the valid / invalid bits of the locations in the system cache to determine which locations have valid / invalid data. The memory control device may replace the data associated with the local counter value by writing the data of the write memory command to the location in the system cache that stores the data associated with the valid / invalid bits. The memory control device may also write the value of the stale counter as a local counter to the system cache in association with the data of the write memory command written to the system cache. In some embodiments, updating the stale counter by writing the value of the stale counter as a local counter to the system cache in association with the data of the write memory command in block 1004 may be performed when (i.e., at approximately the same time) the data is written to the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data of the write memory command written to the system cache. In some embodiments, the memory control device that writes the data of the write memory command and the value of the stale counter to memory at block 1004 where the data is invalid may be a processor and / or a memory controller.

[0098] 11 illustrates a method 1100 for implementing a criteria-aware cache replacement policy, according to some embodiments. With reference to FIGS. 1-11, the method 1100 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software (e.g., client 300 of FIG. 3) executing in a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214, client 300 of FIG. 3), or in software. and dedicated hardware including other individual components such as various memories / caches (e.g., memory 106, memory 114 of FIG. 1, L2 caches 208a, 208b, 208c, 210a, 210b, 210c of FIG. 2, L3 cache 216, system cache 218 of FIGS. 2 and 3, registers 222, system cache 400 of FIG. 4) and various memory / cache controllers (e.g., memory controller 220 of FIGS. 2 and 3). To encompass alternative configurations possible in the various embodiments, the hardware implementing method 1100 is referred to herein as a "client" and a "memory control device."

[0099] At block 1102, a client may send a read memory command targeting a system cache (eg, system cache 218 of FIGS. 2 and 3, system cache 400 of FIG. 4).

[0100] At block 1104, the client may send a signal to a processor (e.g., CPU 104, processor 124, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300, FIG. 3) indicating that the processor should update stale counters of data in the system cache. The client may signal the processor using various types of signal communication including, for example, a register write to a register (e.g., register 222, FIGS. 2 and 3), a direct interrupt to the processor, etc. The register may be associated with a stale counter update function for a reference-aware cache replacement policy. The write to the register may set a value in the register configured to indicate to the memory control device whether the memory control device should update the stale counters. In some embodiments, the client that sends the read memory command at block 1102 and signals the processor to update a stale counter for data in the system cache at block 1104 may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214, client 300 of FIG. 3) and / or a software program such as an operating system and / or an application (e.g., client 300 of FIG. 3).

[0101] The memory control device may receive the read memory command at block 1106. The memory control device may be configured to manage, control, and / or enforce memory access, cache maintenance, cache coherency, and / or cache replacement policies for the system cache.

[0102] At block 1108, the memory control device may implement a criteria-aware cache replacement policy for writing data of the read memory command to the system cache. The memory control device that receives the read memory command at block 1106 and implements the criteria-aware cache replacement policy at block 1108 may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214, client 300 of FIG. 3) and / or a memory controller (e.g., memory controller 220 of FIGS. 2 and 3).

[0103] 12 illustrates a method 1200 for implementing a criteria-aware cache replacement policy that replaces data based on invalidating the data based on the value of a local counter, according to some embodiments. With reference to FIGS. 1-12, the method 1200 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software (e.g., client 300 of FIG. 3) running in a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214 of FIG. 3), or in software. 1 and dedicated hardware including other individual components such as various memories / caches (e.g., memory 106, memory 114 of FIG. 1, L2 caches 208a, 208b, 208c, 210a, 210b, 210c of FIG. 2, system cache 218 of FIGS. 2 and 3, registers 222, system cache 400 of FIG. 4) and various memory / cache controllers (e.g., memory controller 220 of FIGS. 2 and 3). To encompass alternative configurations possible in various embodiments, the hardware implementing method 1200 is referred to herein as a "memory control device." Blocks 702-706, 1202 of method 1200 describe operations that may be performed as part of the operations in block 1108 of method 1100 described with reference to FIG. 11. Blocks 702-706 may be implemented similarly to similarly numbered blocks of method 700 described with reference to FIG. 7.

[0104] In response to determining that the register value indicates that the memory control device should not update the stale counter (i.e., optional decision block 704="no"), or after updating the stale counter in block 706, the memory control device may read data from the memory at the location targeted by the read memory command received in block 1106 of method 1100 (FIG. 11) and write the value of the stale counter to the memory. The memory control device may read the data at the location in the system cache targeted by the read memory command (e.g., system cache 218 of FIGS. 2 and 3, system cache 400 of FIG. 4). The memory control device may also write the value of the stale counter as a local counter in the system cache in association with the data targeted by the read memory command in the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data targeted by the read memory command in the system cache. In some embodiments, the memory control device that reads data from memory at the location targeted by the read memory command in block 1202 and writes the value of the stale counter to memory may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or a memory controller (e.g., memory controller 220 of FIGS. 2 and 3).

[0105] After reading the data from the memory at the location targeted by the read memory command in block 1202 and writing the value of the stale counter to the memory, the memory control device may receive a write memory command in block 606 of method 600, as described with reference to Figure 6. The memory control device that receives the write memory command in block 606 may be a processor and / or a memory controller.

[0106] 13 illustrates a method 1300 for implementing a criteria-aware cache replacement policy that replaces data based on invalidating the data based on the value of a local counter, according to some embodiments. With reference to FIGS. 1-13, the method 1300 may be implemented in a computing device (e.g., computing device 100 of FIG. 1), in hardware, in software (e.g., client 300 of FIG. 3) running in a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202, processor cores 204a, 204b, 204c, 206a, 206b, 206c of FIG. 2, processor core clusters 212, 214 of FIG. 3), or in software. 1 and dedicated hardware including other individual components such as various memories / caches (e.g., memory 106, memory 114 of FIG. 1, L2 caches 208a, 208b, 208c, 210a, 210b, 210c of FIG. 2, system cache 218 of FIGS. 2 and 3, registers 222, system cache 400 of FIG. 4) and various memory / cache controllers (e.g., memory controller 220 of FIGS. 2 and 3). To encompass alternative configurations possible in various embodiments, the hardware implementing method 1300 is referred to herein as a "memory control device." Blocks 810-814, 1202 of method 1200 describe operations that may be performed as part of the operations in block 1108 of method 1100 described with reference to FIG. 11. Blocks 810-814 may be implemented similarly to similarly numbered blocks of method 800 described with reference to FIG. 8.

[0107] At block 1302, the memory control device may read data from memory at a location targeted by the read memory command received at block 1106 of method 1100 (FIG. 11) and write a stale counter value to the memory. The memory control device may read the data at a location in a system cache (e.g., system cache 218 of FIGS. 2 and 3, system cache 400 of FIG. 4) targeted by the read memory command. The memory control device may also write the value of the stale counter as a local counter in the system cache in association with the data targeted by the read memory command in the system cache. For example, the memory control device may write the value of the stale counter to a tag location in the system cache associated with the data targeted by the read memory command in the system cache. In some embodiments, the memory control device that reads data from memory at the location targeted by the read memory command in block 1302 and writes the value of the stale counter to memory may be a processor (e.g., CPU 104, processor 124 of FIG. 1, processor 202 of FIG. 2, processor cores 204a, 204b, 204c, 206a, 206b, 206c, processor core clusters 212, 214, client 300 of FIG. 3) and / or a memory controller (e.g., memory controller 220 of FIGS. 2 and 3).

[0108] Systems according to various embodiments (including but not limited to those described above with reference to FIGS. 1-13) may be implemented in a wide variety of computing systems, including mobile computing devices, one example of a mobile computing device suitable for use with various embodiments is shown in FIG. 14. The mobile computing device 1400 may include a processor 1402 coupled to a touch screen controller 1404 and internal memory 1406. The processor 1402 may be one or more multi-core integrated circuits designated for general purpose or specific processing tasks. The internal memory 1406 may be volatile or non-volatile memory, and may be secure and / or encrypted, or non-secure and / or non-encrypted, or any combination thereof. Examples of memory types that may be utilized include, but are not limited to, DDR, Low-Power DDR (LPDDR), Graphics DDR (GDDR), WIDEIO, RAM, Static RAM (SRAM), Dynamic RAM (DRAM), Parameter RAM (P-RAM), Resistive RAM (R-RAM), Magnetoresistive RAM (M-RAM), Spin-Transfer Torque RAM (STT-RAM), and Embedded DRAM. The touchscreen controller 1404 and processor 1402 may also be coupled to a touchscreen panel 1412, such as a resistive sensing touchscreen, a capacitive sensing touchscreen, an infrared sensing touchscreen, or the like. Additionally, the display of the mobile computing device 1400 need not have touchscreen capabilities.

[0109] The mobile computing device 1400 may have one or more wireless signal transceivers 1408 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio) and antennas 1410 for transmitting and receiving communications coupled to each other and / or to the processor 1402. The transceivers 1408 and antennas 1410 may be used with the circuitry described above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 1400 may include a cellular network wireless modem chip 1416 that enables communication over a cellular network and is coupled to the processor.

[0110] The mobile computing device 1400 may include a peripheral device connection interface 1418 coupled to the processor 1402. The peripheral device connection interface 1418 may be configured solely to accept one type of connection or may be configured to accept various types of common or proprietary physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. The peripheral device connection interface 1418 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0111] The mobile computing device 1400 may also include a speaker 1414 to provide audio output. The mobile computing device 1400 may also include a housing 1420 constructed from plastic, metal, or a combination of materials that encases all or a portion of the components described herein. The mobile computing device 1400 may include a power source 1422 coupled to the processor 1402, such as a disposable battery or a rechargeable battery. The rechargeable battery may also be coupled to a peripheral device connection port to receive charging current from a source external to the mobile computing device 1400. The mobile computing device 1400 may also include a physical button 1424 to receive user input. The mobile computing device 1400 may also include a power button 1426 to turn the mobile computing device 1400 on and off.

[0112] Systems according to various embodiments (including but not limited to those described above with reference to FIGS. 1-12) may be implemented in a wide variety of computing systems, including a laptop computer 1500, an example of which is shown in FIG. 15. Many laptop computers include a touchpad touch surface 1517 that serves as the computer's pointing device and can therefore receive drag, scroll, and flick gestures similar to those implemented on the computing devices described above equipped with touch screen displays. The laptop computer 1500 typically includes a processor 1502 coupled to volatile memory 1512 and a large capacity non-volatile memory, such as a flash memory disk drive 1513. In addition, the computer 1500 may have one or more antennas 1508 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless data link and / or a cellular telephone transceiver 1516 coupled to the processor 1502. The computer 1500 may also include a floppy disk drive 1514 and a compact disc (CD) drive 1515 coupled to the processor 1502. In a notebook configuration, the computer housing includes a touchpad 1517, a keyboard 1518, and a display 1519, all coupled to the processor 1502. Other configurations of computing devices may include a computer mouse or trackball coupled to the processor (e.g., via a USB input), as is well known, and may also be used with the various embodiments.

[0113] Systems according to various embodiments (including but not limited to those described above with reference to FIGS. 1-12) may be implemented in a fixed computing system, such as any of a variety of commercially available servers. An exemplary server 1600 is shown in FIG. 16. Such a server 1600 typically includes one or more multi-core processor assemblies 1601 coupled to volatile memory 1602 and large capacity non-volatile memory, such as a disk drive 1604. As shown in FIG. 16, multi-core processor assemblies 1601 may be added to the server 1600 by inserting them into a rack of assemblies. The server 1600 may also include a floppy disk drive, compact disk (CD) or digital versatile disc (DVD) disk drive 1606 coupled to the processor 1601. The server 1600 may also include a network access port 1603 coupled to the multi-core processor assembly 1601 for establishing a network interface connection with a network 1605, such as a local area network, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, 5G, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0114] Example implementations are described in the following paragraphs. Although some of the example implementations below are described with respect to example systems, devices, or methods, further example implementations may include the example systems or devices discussed in the following paragraphs implemented as a method of performing operations of the example systems or devices, the example systems, devices, or methods discussed in the following paragraphs implemented by a computing device comprising a processing device configured with processing device executable instructions for performing operations of the example systems, devices, or methods, the example systems, devices, or methods discussed in the following paragraphs implemented by a computing device comprising a processing device configured with processing device executable instructions for performing operations of the example systems, devices, or methods, the example systems, devices, or methods discussed in the following paragraphs implemented by a computing device including means for performing the functions of the example systems, devices, or methods, and the example systems, devices, or methods discussed in the following paragraphs implemented as a non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processor of a computing device to perform operations of the example systems, devices, or methods.

[0115] Example 1. A method of implementing a criteria-aware cache replacement policy by a computing device, the method comprising: updating a stale counter; writing a value of a local counter to the system cache associated with a location in the system cache of the associated data, the value of the stale counter including the value of the stale counter at the time the associated data is written to the system cache; and using the value of the local counter for the associated data to determine whether the associated data is stale.

[0116] Example 2. The method of example 1, wherein updating the stale counter includes receiving a signal from a client of a computing device configured to indicate whether the stale counter should be updated, determining whether the stale counter should be updated based on the signal, and updating the stale counter in response to determining that the stale counter should be updated.

[0117] Example 3. The method of example 1 or 2, wherein the signal is a register write command, receiving the signal from a client of the computing device includes reading a value from a register set by the client, and determining whether to update the stale counter based on the signal includes determining whether to update the stale counter based on the value from the register.

[0118] Example 4. The method of example 3, further comprising setting a value in the register by a client of the computing device based on a time-based criterion.

[0119] Example 5. The method of example 3, further comprising setting a value in the register by a client of the computing device based on an event-based criterion.

[0120] Example 6. A method according to any one of Examples 1 to 5, further comprising receiving a memory write command, and writing a value of a local counter to a system cache in relation to a location in the system cache of associated data, which can be performed before updating the stale counter, and the associated data is data of the write memory command.

[0121] Example 7. The method of any one of Examples 1 to 6, wherein using the value of the local counter of the associated data to determine whether the associated data is stale includes calculating a replacement value using the value of the stale counter and the value of the local counter, and determining whether the replacement value exceeds a stale threshold, and in response to determining that the replacement value exceeds the stale threshold, the associated data is determined to be stale.

[0122] Example 8. The method of example 7, further comprising receiving a memory access command and writing data of the memory access command to a system cache at a location where the replacement value is above a stalling threshold, wherein the data of the memory access command written to the system cache is relevant data.

[0123] Example 9. The method of example 7, further comprising: receiving a memory write command; invalidating data at locations where the replacement value exceeds a stalling threshold; and writing the data of the memory write command to a system cache at the location having the invalidated data, wherein the data of the memory write command written to the system cache is associated data.

[0124] Example 10. A method according to any one of Examples 1 to 9, further comprising: receiving a memory write access command; and, in response to determining that the replacement value does not exceed a stale threshold, writing data of the memory write access command to a system cache at a location according to another cache replacement policy.

[0125] Computer program code or "program code" for execution on a programmable processor to perform operations of various embodiments may be written in a high-level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or a variety of other programming languages. Program code or programs stored on a computer-readable storage medium as used in this application may refer to machine code (such as object code) whose format is understandable by a processor.

[0126] The above method descriptions and process flow diagrams are provided merely as illustrative examples and do not require or imply that the operations of the various embodiments must be performed in the order presented. As will be understood by one of ordinary skill in the art, the order of operations in the above-described embodiments may be performed in any order. Words such as "thereafter," "then," and "next" do not limit the order of operations. These words are used merely to guide the reader through the method description. Furthermore, any reference to a claim element in the singular, for example using the articles "a," "an," or "the," should not be construed as limiting the element to the singular.

[0127] The various exemplary logic blocks, modules, circuits, and algorithmic operations described with respect to the various embodiments may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various exemplary components, blocks, modules, circuits, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0128] The hardware used to implement the various exemplary logic, logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0129] In one or more embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or codes on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operations of the methods or algorithms disclosed herein may be embodied in a processor-executable software module that may reside on a non-transitory computer-readable storage medium or a processor-readable storage medium. A non-transitory computer-readable storage medium or a non-transitory processor-readable storage medium may be any storage medium that may be accessed by a computer or a processor. By way of example and not limitation, such a non-transitory computer-readable medium or a non-transitory processor-readable medium may include RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, operations of a method or algorithm may be present as one or any combination or set of code and / or instructions on a non-transitory processor-readable medium and / or a non-transitory computer-readable medium that may be incorporated into a computer program product.

[0130] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but should be accorded the widest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. 1. A method for implementing a criteria-aware cache replacement policy by a computing device, comprising: updating a stale counter; writing a value of a local counter to a system cache associated with a location in the system cache of associated data, the value of the local counter comprising a value of the stale counter at the time the associated data is written to the system cache; using the value of the local counter of the associated data to determine whether the associated data is stale; A method comprising:

2. The step of updating the stalemate counter comprises: receiving a signal from a client of the computing device configured to indicate whether the stalemate counter should be updated; determining whether the stalemate counter should be updated based on the signal; updating the stale counter in response to determining that the stale counter should be updated; The method of claim 1 , comprising:

3. the signal is a register write command, receiving the signal from the client of the computing device includes reading a value from a register set by the client; determining whether to update the stale counter based on the signal includes determining whether to update the stale counter based on the value from the register. The method of claim 2.

4. The method of claim 3 , further comprising setting the value in the register by the client of the computing device based on a time-based criterion.

5. The method of claim 3 , further comprising setting the value in the register by the client of the computing device based on an event-based criterion.

6. 2. The method of claim 1, further comprising receiving a memory write command, wherein writing the value of the local counter associated with the location in the system cache of the associated data to the system cache occurs before updating the stale counter, and wherein the associated data is data of the write memory command.

7. determining whether the associated data is stale using the value of the local counter of the associated data; calculating a replacement value using the value of the stale counter and the value of the local counter; determining whether the replacement value exceeds a stale threshold, and in response to determining that the replacement value exceeds the stale threshold, the associated data is determined to be stale; The method of claim 1 , comprising:

8. receiving a memory access command; writing data of the memory access command to the system cache at a location where the replacement value is above the stale threshold, the data of the memory access command written to the system cache being the associated data; The method of claim 7 further comprising:

9. receiving a memory write command; invalidating data where the replacement value exceeds the stalling threshold; writing data of the memory write command to the system cache at a location having the invalidated data, the data of the memory write command written to the system cache being the associated data; The method of claim 7 further comprising:

10. receiving a memory write access command; responsive to determining that a replacement value does not exceed the stale threshold, writing data of the memory write access command to the system cache at a location according to a different cache replacement policy; The method of claim 7 further comprising:

11. 1. A computing device comprising:

1. A memory control device, comprising: Update the stalemate counter, writing a value of a local counter to the system cache associated with a location in the system cache of the associated data, the value of the stale counter including a value of the stale counter at the time the associated data is written to the system cache; Using the value of the local counter of the associated data to determine whether the associated data is stale. A memory control device configured to A computing device comprising:

12. The memory control device, receiving a signal from a client of the computing device configured to indicate whether the stalemate counter should be updated; determining whether to update the stalemate counter based on the signal; updating the stalemate counter in response to determining that the stalemate counter should be updated; The computing device of claim 11 , further configured to update the stale counter by:

13. the signal is a register write command, The memory control device, receiving the signal from the client of the computing device by reading a value from a register set by the client; determining whether to update the stalemate counter based on the signal by determining whether to update the stalemate counter based on the value from the register; The computing device of claim 12 further configured to:

14. 14. The computing device of claim 13, further comprising a client configured to set the value in the register based on a time-based criterion.

15. 14. The computing device of claim 13, further comprising a client configured to set the value in the register based on an event-based criterion.

16. The memory control device, Receiving a memory write command; writing the value of the local counter to the system cache associated with the location in the system cache of the associated data prior to updating the stale counter, the associated data being data of the write memory command; The computing device of claim 11 , further configured to:

17. the memory control device using the value of the local counter of the associated data to: calculating a replacement value using the value of the stale counter and the value of the local counter; determining whether the replacement value exceeds a stale threshold, and in response to determining that the replacement value exceeds the stale threshold, determining that the associated data is stale; The computing device of claim 11 , further configured to determine whether the associated data is stale by:

18. The memory control device, Receiving a memory access command; writing data of the memory access command to the system cache at a location where the replacement value is above the stalling threshold, the data of the memory access command written to the system cache being the associated data; 20. The computing device of claim 17, further configured to:

19. The memory control device, Receiving a memory write command; invalidating data where the replacement value exceeds the stalling threshold; writing data of the memory write command to the system cache at a location having the invalidated data, the data of the memory write command written to the system cache being the associated data; 20. The computing device of claim 17, further configured to:

20. The memory control device, receiving a memory write access command; Responsive to determining that the replacement value does not exceed the stale threshold, writing data of the memory write access command to the system cache at a location according to a cache replacement policy that is different from a reference-aware cache replacement policy. The computing device of claim 17 further configured to:

21. 1. A computing device comprising: means for updating a stalemate counter; means for writing a value of a local counter to a system cache associated with a location in the system cache of associated data, the value of the local counter comprising a value of the stale counter at the time the associated data is written to the system cache; means for determining whether the associated data is stale using the value of the local counter of the associated data; A computing device comprising:

22. The means for updating the stalemate counter comprises: means for receiving a signal from a client of the computing device configured to indicate whether the stalemate counter should be updated; means for determining whether the stalemate counter should be updated based on the signal; means for updating the stalemate counter in response to determining that the stalemate counter should be updated; 22. The computing device of claim 21, comprising:

23. the signal is a register write command, the means for receiving the signal from the client of the computing device includes means for reading a value from a register set by the client; the means for determining whether to update the stale counter based on the signal includes means for determining whether to update the stale counter based on the value from the register.

23. The computing device of claim 22.

24. 24. The computing device of claim 23, further comprising means for setting the value in the register by the client of the computing device based on a time-based criterion or for setting the value in the register by the client of the computing device based on an event-based criterion.

25. 22. The computing device of claim 21, further comprising means for receiving a memory write command, wherein means for writing the value of the local counter associated with the location in the system cache of the associated data to the system cache is implemented before updating the stale counter, and the associated data is data of the write memory command.

26. means for determining whether the associated data is stale using the value of the local counter of the associated data, means for calculating a replacement value using the value of the stale counter and the value of the local counter; means for determining whether the replacement value exceeds a stale threshold, wherein in response to determining that the replacement value exceeds the stale threshold, the associated data is determined to be stale; 22. The computing device of claim 21, comprising:

27. means for receiving a memory access command; means for writing data of the memory access command to the system cache at a location where the replacement value exceeds the stalling threshold, the data of the memory access command written to the system cache being the associated data; 27. The computing device of claim 26, further comprising:

28. means for receiving a memory write command; means for invalidating data where the replacement value exceeds the stalling threshold; means for writing data of the memory write command to the system cache at a location having invalidated data, the data of the memory write command written to the system cache being the associated data; 27. The computing device of claim 26, further comprising:

29. means for receiving a memory write access command; means for writing data of the memory write access command to the system cache at a location according to a cache replacement policy different from a reference-aware cache replacement policy in response to determining that a replacement value does not exceed the staleness threshold; 27. The computing device of claim 26, further comprising:

30. A non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a processing device to perform an operation, the operation comprising: updating a stalemate counter; and writing a value of a local counter to a system cache associated with a location in the system cache of associated data, the value of the local counter comprising a value of the stale counter at the time the associated data is written to the system cache; using the value of the local counter of the associated data to determine whether the associated data is stale; 16. A non-transitory processor-readable medium comprising:

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