Package with substrate having post interconnects and solder resist layer with cavities - Patents.com

Abstract

A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least a first dielectric layer, a first plurality of interconnects including a first plurality of post interconnects, and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface, at least a second dielectric layer, a second plurality of interconnects including a second plurality of post interconnects, and a second solder resist layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to and the benefit of nonprovisional application Ser. No. 17 / 579,434, filed in the United States Patent Office on Jan. 19, 2022, the entire contents of which are incorporated by reference herein as if fully set forth below in their entirety, and for all applicable purposes.

[0002] Various features relate to a package having a substrate and an integrated device. [Background technology]

[0003] A package may include a substrate and an integrated device. These components are bonded together to provide a package that can perform various electrical functions. There is a continuing need to provide packages with better performance. There is also a continuing need to reduce the overall size of the package. Summary of the Invention

[0004] Various features relate to a package having a substrate and an integrated device.

[0005] An example provides a package comprising a first substrate comprising at least a first dielectric layer and a first plurality of interconnects, a first integrated device coupled to the first substrate, a second substrate, and a plurality of ball interconnects and a plurality of solder interconnects coupled to the first substrate and the second substrate. The second substrate comprises a first surface and a second surface, at least a second dielectric layer, a second plurality of interconnects comprising a plurality of post interconnects, and a solder resist layer coupled to the second substrate. The second substrate surface faces the first substrate. The solder resist layer includes a cavity. The cavity is located between the first integrated device and the solder resist layer. The plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate. The plurality of ball interconnects and the plurality of solder interconnects are configured to couple the first substrate to the second substrate.

[0006] Another example provides a package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least a first dielectric layer, a first plurality of interconnects including a first plurality of post interconnects, and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface, at least a second dielectric layer, a second plurality of interconnects including a second plurality of post interconnects, and a second solder resist layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer comprises a cavity. The cavity is located between the first integrated device and the second solder resist layer. A plurality of solder interconnects are located between the first substrate and the second substrate, the plurality of solder interconnects being configured to couple the first substrate to the second substrate.

[0007] Another example provides a package comprising a first substrate comprising at least a first dielectric layer and a first plurality of interconnects, a first integrated device coupled to the first substrate, a second substrate, and a means for inter-substrate interconnection coupled to the first substrate and the second substrate. The second substrate comprises a first surface and a second surface, at least a second dielectric layer, a second plurality of interconnects comprising a plurality of post interconnects, and a solder resist layer coupled to the second substrate. The solder resist layer includes a cavity. The cavity is located between the first integrated device and the solder resist layer. The means for inter-substrate interconnection is located between the first substrate and the second substrate. The means for inter-substrate interconnection is configured to couple the first substrate to the second substrate.

[0008] Another example provides a method that includes providing a first substrate comprising at least a first dielectric layer and a first plurality of interconnects. The method bonds a first integrated device to the first substrate. The method bonds a second substrate to the first substrate via the plurality of inter-substrate interconnects such that the plurality of inter-substrate interconnects are located between the first substrate and the second substrate. The second substrate comprises a first surface and a second surface, at least a second dielectric layer, a second plurality of interconnects comprising a plurality of post interconnects, and a solder resist layer bonded to the second substrate surface. The solder resist layer includes a cavity. The cavity is located between the solder resist layer and the first integrated device.

[0009] Various features, nature and advantages may become apparent from the following detailed description when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout. [Brief description of the drawings]

[0010] [Figure 1] 1 is an exemplary cross-sectional side view of a package including a substrate with post interconnects and a solder resist layer having a cavity. [Diagram 2] FIG. 2 is an enlarged cross-sectional side view of a package including a substrate with post interconnects and a solder resist layer having cavities. [Diagram 3] 1 is an exemplary cross-sectional side view of a package including a substrate with post interconnects and a solder resist layer having a cavity. [Figure 4] FIG. 2 is an enlarged cross-sectional side view of a package including a substrate with post interconnects and a solder resist layer having cavities. [Figure 5A] 1A-1C illustrate an exemplary sequence for fabricating a package including a substrate with post interconnects and a solder resist layer having cavities. [Figure 5B] 1A-1C illustrate an exemplary sequence for fabricating a package including a substrate with post interconnects and a solder resist layer having cavities. [Figure 5C] 1A-1C illustrate an exemplary sequence for fabricating a package including a substrate with post interconnects and a solder resist layer having cavities. [Figure 6A] 1A-1C illustrate an exemplary sequence for fabricating a package including a substrate with post interconnects and a solder resist layer having cavities. [Figure 6B] 1A-1C illustrate an exemplary sequence for fabricating a package including a substrate with post interconnects and a solder resist layer having cavities. [Figure 6C] 1A-1C illustrate an exemplary sequence for fabricating a package including a substrate with post interconnects and a solder resist layer having cavities. [Figure 7] FIG. 1 illustrates an exemplary flow chart of a method for making a package including a substrate with post interconnects and a solder resist layer having cavities. [Figure 8] FIG. 1 illustrates an exemplary flow chart of a method for making a package that includes substrates bonded via ball interconnects. [Figure 9] FIG. 1 illustrates an exemplary flow chart of a method for making a package that includes substrates bonded via solder interconnects. [Figure 10A] 1A-1C illustrate an exemplary sequence for fabricating a substrate including post interconnects and a solder resist layer having cavities. [Figure 10B] 1A-1C illustrate an exemplary sequence for fabricating a substrate including post interconnects and a solder resist layer having cavities. [Figure 10C] 1A-1C illustrate an exemplary sequence for fabricating a substrate including post interconnects and a solder resist layer having cavities. [Figure 11] FIG. 1 illustrates an exemplary flow chart of a method for fabricating a substrate including post interconnects and a solder resist layer having cavities. [Figure 12] FIG. 1 illustrates various electronic devices that may incorporate the die, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] In the following description, specific details are provided to provide a thorough understanding of various aspects of the present disclosure. However, those skilled in the art will understand that aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure aspects of the present disclosure.

[0012] The present disclosure describes a package comprising a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, a first integrated device coupled to the first substrate, a second substrate, and a plurality of ball interconnects and a plurality of solder interconnects coupled to the first substrate and the second substrate. The second substrate comprises a first surface and a second surface, at least one second dielectric layer, a second plurality of interconnects comprising a plurality of post interconnects, and a solder resist layer coupled to the second substrate. The second substrate surface faces the first substrate. The solder resist layer includes a cavity. The cavity is located between the first integrated device and the solder resist layer. The plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate. The plurality of ball interconnects and the plurality of solder interconnects are configured to couple the first substrate to the second substrate. The present disclosure describes a package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least a first dielectric layer, a first plurality of interconnects including a first plurality of post interconnects, and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface, at least a second dielectric layer, a second plurality of interconnects including a second plurality of post interconnects, and a second solder resist layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer includes a cavity. The cavity is located between the first integrated device and the second solder resist layer. A plurality of solder interconnects are located between the first substrate and the second substrate. The plurality of solder interconnects are configured to couple the first substrate to the second substrate. As described further below, the package provides high density interconnect routing between the substrates (e.g., high density board-to-board interconnects), which helps provide improved package performance while keeping the package small and thin. Exemplary Package Comprising a Substrate Having Post Interconnects and a Solder Resist Layer Having Cavities

[0013] 1 shows a cross-sectional side view of a package 100 including a substrate having post interconnects and a solder resist layer with cavities. The package 100 may be a package on package (PoP). The package 100 is coupled to a board 106 via a plurality of solder interconnects 110. The board 106 includes at least one board dielectric layer 160 and a plurality of board interconnects 162. The board 106 may include a printed circuit board (PCB).

[0014] The package 100 includes a first substrate 102, a first integrated device 105, and an underfill 152. The first substrate 102, the first integrated device 105, and the underfill 152 can be considered as part of a first package. The first integrated device 105 is coupled to a first surface (e.g., a top surface) of the substrate 102 via a plurality of pillar interconnects 150. The first substrate 102 includes at least one first dielectric layer 120 and a first plurality of interconnects 122. The first integrated device 105 is coupled to the first plurality of interconnects 122 of the first substrate 102 via the plurality of pillar interconnects 150. There may be solder interconnects (not shown) between the plurality of pillar interconnects 150 and the first plurality of interconnects 122. That is, in some implementations, solder interconnects may be used to couple the plurality of pillar interconnects 150 to the first plurality of interconnects 122. The underfill 152 is located between the first integrated device 105 and the first substrate 102. The first substrate 102 includes a solder resist layer 124 and a solder resist layer 126. The solder resist layer 124 is coupled to a first surface (e.g., a top surface) of the first substrate 102. The solder resist layer 126 is coupled to a second surface (e.g., a bottom surface) of the first substrate 102. A plurality of passive devices 130 are coupled to the second surface of the first substrate 102. The passive devices 130 may include capacitors and / or inductors.

[0015] The package 100 includes a second substrate 104 and a second integrated device 107. The second substrate 104 and the second integrated device 107 can be considered as part of a second package. The second integrated device 107 is coupled to a first surface (e.g., a top surface) of the second substrate 104 via a plurality of solder interconnects 170. The second substrate 104 includes at least one second dielectric layer 140 and a plurality of second interconnects 142. As described further below, the plurality of second interconnects 142 can include a plurality of post interconnects. The second integrated device 107 is coupled to the plurality of second interconnects 142 of the second substrate 104 via a plurality of solder interconnects 170. The second substrate 104 includes a solder resist layer 144 and a solder resist layer 146. The solder resist layer 144 is bonded to a first surface (e.g., a top surface) of the second substrate 104. The solder resist layer 146 is bonded to a second surface (e.g., a bottom surface) of the second substrate 104. The solder resist layer 146 includes a cavity. The solder resist layer 146 may include a variable thickness. The second substrate 104 may be an interposer. The second substrate 104 may include two or more metal layers. In some implementations, the second substrate 104 may be fabricated using a modified semi-additive process (mSAP). In some implementations, the first substrate 102 may be fabricated using an embedded trace substrate (ETS) process.

[0016] The second substrate 104 is coupled to the first substrate 102 via a plurality of ball interconnects 109 and a plurality of solder interconnects 190. The plurality of ball interconnects 109 and the plurality of solder interconnects 190 are coupled to (i) the first plurality of interconnects 122 of the first substrate 102 and (ii) the second plurality of interconnects 142 of the second substrate 104. The plurality of ball interconnects 109 may include copper balls. The plurality of ball interconnects 109 and / or the plurality of solder interconnects 190 may be means for inter-substrate interconnection. The plurality of ball interconnects 109 and / or the plurality of solder interconnects 190 may be examples of inter-substrate interconnections. The plurality of solder interconnects 190 serve to couple the plurality of ball interconnects 109 to the interconnects from the first substrate 102 and the interconnects from the second substrate 104. The plurality of solder interconnects 190 can at least partially encapsulate the plurality of ball interconnects 109.

[0017] The first integrated device 105 is located between the first substrate 102 and the second substrate 104. A cavity in the solder resist layer 146 is located above (e.g., above) the first integrated device 105. For example, the cavity may be located between the solder resist layer 146 and the first integrated device 105. A backside of the first integrated device 105 faces the cavity in the solder resist layer 144. The cavity may be located between the solder resist layer 146 and the backside of the first integrated device 105. The cavity may be located in an area of ​​the package that includes the first integrated device 105.

[0018] The package 100 includes an encapsulation layer 108. The encapsulation layer 108 is located between the first substrate 102 and the second substrate 104. The encapsulation layer 108 may encapsulate the first integrated device 105, the plurality of ball interconnects 109, and / or the plurality of solder interconnects 190. The encapsulation layer 108 may be located in a cavity of the solder resist layer 144. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0019] As described further below, the use of cavities (e.g., 250) in the solder resist layer 146, post interconnects (from the plurality of interconnects 142), ball interconnects 109, and / or solder interconnects 190 allows for more interconnections between substrates, which helps improve package performance. For example, the use of cavities (e.g., 250) in the solder resist layer 146, post interconnects (from the plurality of interconnects 142), ball interconnects 109, and / or solder interconnects 190 allows for interconnections between substrates having a smaller pitch (e.g., smaller center-to-center distance between adjacent interconnects), which allows for more interconnections between substrates (thereby increasing the density of the interconnects). The use of cavities in the solder resist layer 146, post interconnects (from the plurality of interconnects 142), ball interconnects 109, and / or solder interconnects 190 allows for thinner packages with smaller gaps between the substrates such that the package can have substrate-to-substrate interconnects with low pitch. This, in turn, helps provide interconnects with high routing density between the substrates. For example, the interconnects between the first substrate 102 and the second substrate 104 can have a pitch of less than 270 micrometers. For example, the interconnects between the first substrate 102 and the second substrate 104 can have a pitch of 150 to 270 micrometers. In some implementations, the number of substrate-to-substrate interconnects (e.g., pin count) between the first substrate 102 and the second substrate 104 can be 300 or more. In some implementations, the number of inter-board interconnects (e.g., pin count) between the first substrate 102 and the second substrate 104 can be up to 400. In some implementations, the number of inter-board interconnects (e.g., pin count) between the first substrate 102 and the second substrate 104 can be 300-400. Reducing the spacing between adjacent interconnects (e.g., adjacent ball interconnects, adjacent solder interconnects) and increasing the number of inter-board interconnects helps to provide high density interconnect routing within the package. High density interconnect routing between the substrates helps to improve the performance of the package.In some implementations, reducing the spacing between adjacent interconnects can reduce the space occupied by the interconnects by as much as 30 percent. In addition to increased routing density, the overall thickness of the package can be reduced by providing a solder resist layer having a cavity, the cavity in the solder resist layer being located above the integrated device. That is, the cavity can be located between the solder resist layer and the backside of the integrated device.

[0020] FIG. 2 shows an expanded view of the package 100. The package 100 includes a solder resist layer 146 that includes a cavity 250. The cavity 250 is filled with the encapsulation layer 108. The solder resist layer 146 includes two portions with different thicknesses. The solder resist layer 146 includes a solder resist layer 146a (e.g., a first portion of the solder resist layer 146) and a solder resist layer 146b (e.g., a second portion of the solder resist layer 146). The solder resist layer 146a has a thickness 240, and the solder resist layer 146b has a thickness 242. The solder resist layer 146a is thicker than the solder resist layer 146b. The thickness 240 is greater than the thickness 242. A gap 282 exists between the solder resist layer 146b and the backside portion of the first integrated device 105. The gap 282 includes a cavity 250 in the solder resist layer 146. The gap 282 is filled with the encapsulation layer 108. A gap 280 exists between the solder resist layer 146a and the solder resist layer 124. The gap 280 is filled with the encapsulation layer 108. In some implementations, the thickness of the gap 282 may be smaller than the thickness of the gap 280. Thus, for example, the vertical gap between the solder resist layer 146b and the backside of the integrated device 105 may be smaller than the vertical gap between the solder resist layer 146a of the second substrate 104 and the solder resist layer 124 of the first substrate 102. In some implementations, a portion of the backside of the integrated device 105 may be located within the cavity 250. Thus, the cavity 250 serves to accommodate the integrated device 105 between the first substrate 102 and the second substrate 104 while reducing the space or gap between the first substrate 102 and the second substrate 104.

[0021] The first plurality of interconnects 142 includes a plurality of post interconnects 142a. The plurality of post interconnects 142a are coupled to the plurality of ball interconnects 109 and the plurality of solder interconnects 190. The plurality of post interconnects 142a have a thickness that is less than a thickness of the solder resist layer 146a. The plurality of post interconnects 142a may be laterally surrounded by the solder resist layer 146a. The first plurality of interconnects 122 includes a plurality of interconnects 122a (e.g., pad interconnects). The plurality of interconnects 122a are coupled to the plurality of ball interconnects 109 and the plurality of solder interconnects 190.

[0022] In some implementations, the plurality of ball interconnects 109 may have a pitch of at least 200-270 micrometers. In some implementations, the plurality of ball interconnects 109 may include as many as 400 ball interconnects laterally surrounding the first integrated device 105. Each of the ball interconnects 109 may represent a separate electrical path between the first substrate 102 and the second substrate 104. This configuration allows for a smaller, thinner package with denser routing between the first substrate 102 and the second substrate 104 while avoiding shorts between adjacent interconnects (e.g., adjacent ball interconnects 109, adjacent solder interconnects 190). As the first substrate 102 and the second substrate 104 are bonded as close as possible to each other, the cavities 250 in the solder resist layer 146 help ensure that the solder resist layer does not directly contact the first integrated device 105.

[0023] In some implementations, to maximize and / or optimize the number of inter-board interconnects between the first substrate 102 and the second substrate 104, the pitch between the inter-board interconnects may need to be reduced to 270 micrometers or less (e.g., 200-270 micrometers). To accomplish this, the vertical gap and / or vertical space between the interconnects (e.g., 122a) from the first substrate 102 and the interconnects (e.g., 142a) from the second substrate 104 may be reduced such that ball interconnects 109 and / or solder interconnects 190 having a smaller size and / or pitch may be used. This may be accomplished by providing post interconnects (from the plurality of interconnects 142), which helps narrow the vertical gap between the interconnects from the first substrate 102 and the second substrate 104, thus allowing for smaller size and / or smaller pitch ball interconnects 109 and / or solder interconnects 190. As the vertical gap between the first substrate 102 and the second substrate 104 is reduced, the first integrated device 105 may butt up against the second substrate 104. To accommodate the first integrated device 105 between the first substrate 102 and the second substrate 104 while still reducing the vertical gap between the first substrate 102 and the second substrate 104, a cavity 250 is formed in the solder resist layer 146 such that the backside of the first integrated device 105 does not directly contact the second substrate 104. In some implementations, the use of post interconnects in the second substrate 104 helps provide a smaller pitch for the solder interconnects between the substrates because the post interconnects of the second substrate 104 and the interconnects of the first substrate 102 are closer together. A smaller pitch between the solder interconnects means that more solder interconnects can be provided in the same area, which means denser routing between the substrates.3 and 4, in some implementations, the use of post interconnects on both the first substrate 102 and the second substrate 104 can help provide an even smaller pitch for the solder interconnects between the substrates, as the post interconnects on each substrate are closer together, meaning that higher density routing between the substrates can be provided.

[0024] Various components of the package 100 may have various thicknesses and / or dimensions. In some implementations, the post interconnects 142a may have a thickness of about 40-50 micrometers. In some implementations, the solder resist layer 146a may have a thickness (e.g., 240) of about 65-80 micrometers. In some implementations, the gap (e.g., 280) between the solder resist layer 124 and the solder resist layer 146a may be about 75-95 micrometers. In some implementations, the ball interconnects 109 may have a diameter of about 100-120 micrometers. In some implementations, the ball interconnects 109 may be optional. Thus, some packages may avoid the use of the ball interconnects 109.

[0025] FIG. 3 shows a cross-sectional side view of a package 300 including a substrate having post interconnects and a solder resist layer with cavities. The package 300 may be a package-on-package (PoP). The package 300 may be similar to the package 100 described in FIG. 1 and FIG. 2. The package 300 avoids the use of ball interconnects while still providing a low profile package with high density routing between substrates (e.g., high density substrate-to-substrate interconnects). The package 300 is coupled to a board 106 via a plurality of solder interconnects 110.

[0026] The package 300 includes a first substrate 302, a first integrated device 105, and an underfill 152. The first substrate 302, the first integrated device 105, and the underfill 152 can be considered as part of a first package. The first integrated device 105 is coupled to a first surface (e.g., a top surface) of the substrate 302 via a plurality of pillar interconnects 150. The first substrate 302 includes at least one first dielectric layer 120 and a first plurality of interconnects 122. The first plurality of interconnects 122 includes a plurality of post interconnects 322. The first integrated device 105 is coupled to the first plurality of interconnects 122 of the first substrate 302 via the plurality of pillar interconnects 150. There may be solder interconnects (not shown) between the plurality of pillar interconnects 150 and the first plurality of interconnects 122. A plurality of solder interconnects may be used to couple the plurality of pillar interconnects 150 to the first plurality of interconnects 122. An underfill 152 is located between the first integrated device 105 and the first substrate 302. The first substrate 302 includes a solder resist layer 324 and a solder resist layer 126. The solder resist layer 324 is coupled to a first surface (e.g., a top surface) of the first substrate 302. The solder resist layer 324 has a thickness that is greater (e.g., thicker) than a thickness of the plurality of post interconnects 322. The plurality of post interconnects 322 may be laterally surrounded by the solder resist layer 324. The solder resist layer 126 is coupled to a second surface (e.g., a bottom surface) of the first substrate 302. A plurality of passive devices 130 are coupled to the second surface of the first substrate 302. The passive devices 130 may include capacitors and / or inductors.

[0027] The package 300 includes a second substrate 104 and a second integrated device 107. The second substrate 104 and the second integrated device 107 can be considered as part of a second package. The second integrated device 107 is coupled to a first surface (e.g., a top surface) of the second substrate 104 via a plurality of solder interconnects 170. The second substrate 104 includes at least one second dielectric layer 140 and a plurality of second interconnects 142. As described further below, the plurality of second interconnects 142 can include a plurality of post interconnects. The second integrated device 107 is coupled to the plurality of second interconnects 142 of the second substrate 104 via a plurality of solder interconnects 170. The second substrate 104 includes a solder resist layer 144 and a solder resist layer 146. The solder resist layer 144 is bonded to a first surface (e.g., a top surface) of the second substrate 104. The solder resist layer 146 is bonded to a second surface (e.g., a bottom surface) of the second substrate 104. The solder resist layer 146 includes a cavity. The solder resist layer 146 may include a variable thickness. The second substrate 104 may be an interposer. The first substrate 302 may include a solder resist layer 324 having a thickness (e.g., 460) that is greater (e.g., thicker) than a thickness of the plurality of post interconnects 322. The second substrate 104 may include two or more metal layers. In some implementations, the second substrate 104 may be fabricated using a modified semi-additive process (mSAP). In some implementations, the first substrate 302 may be fabricated using an embedded trace substrate (ETS) process.

[0028] The second substrate 104 is coupled to the first substrate 302 via a plurality of solder interconnects 190. The plurality of solder interconnects 190 is coupled to (i) the plurality of post interconnects 322 of the first substrate 302 and (ii) the second plurality of post interconnects 142a of the second substrate 104. The plurality of solder interconnects 190 may be a means for inter-substrate interconnection. The plurality of solder interconnects 190 may be an example of a plurality of inter-substrate interconnects.

[0029] The first integrated device 105 is located between the first substrate 302 and the second substrate 104. A cavity (e.g., 250) in the solder resist layer 146 is located above (e.g., above) the first integrated device 105. A backside of the first integrated device 105 faces the cavity of the solder resist layer 146. In some implementations, at least a portion of the backside of the first integrated device 105 may be located within the cavity 250 of the solder resist layer 146.

[0030] The package 300 includes an encapsulation layer 108. The encapsulation layer 108 is located between the first substrate 302 and the second substrate 104. The encapsulation layer 108 may encapsulate the first integrated device 105 and / or the plurality of solder interconnects 190. The encapsulation layer 108 may be located within a cavity of the solder resist layer 146.

[0031] As described further below, the use of cavities in the solder resist layer 146, post interconnects (from the plurality of interconnects 142), the plurality of solder interconnects 190, and the plurality of post interconnects 322 allows for thinner packages with interconnects between the substrates having a low pitch. This, in turn, helps provide interconnects between the substrates with a high routing density (e.g., high density substrate-to-substrate interconnects). For example, the interconnects between the first substrate 302 and the second substrate 104 may have a pitch of less than 270 micrometers. For example, the interconnects between the first substrate 302 and the second substrate 104 may have a pitch of 150 to 270 micrometers. In some implementations, the number of substrate-to-substrate interconnects (e.g., pin count) between the first substrate 302 and the second substrate 104 may be 300 or more. In some implementations, the number of inter-board interconnects (e.g., pin count) between the first substrate 302 and the second substrate 104 can be up to 400. In some implementations, the number of inter-board interconnects (e.g., pin count) between the first substrate 302 and the second substrate 104 can be 300-400. Reducing the spacing between adjacent interconnects (e.g., adjacent solder interconnects) and increasing the number of inter-board interconnects helps to provide high density interconnect routing within the package. High density interconnect routing between the substrates (e.g., high density inter-board interconnects) helps to improve the performance of the package. In some implementations, reducing the spacing between adjacent interconnects can reduce the space occupied by the interconnects by as much as 30 percent. In addition to the increased routing density, the overall thickness of the package can be reduced by providing a solder resist layer with cavities, the cavities in the solder resist layer being located above the integrated device.

[0032] FIG. 4 shows an enlarged view of the package 300. The package 300 includes a solder resist layer 146 that includes a cavity 250. The cavity 250 is filled with the encapsulation layer 108. The solder resist layer 146 includes two portions with different thicknesses. The solder resist layer 146 includes a solder resist layer 146a and a solder resist layer 146b. The solder resist layer 146a has a thickness 240, and the solder resist layer 146b has a thickness 242. The solder resist layer 146a is thicker than the solder resist layer 146b. The thickness 240 is greater than the thickness 242. A gap 282 exists between the solder resist layer 146b and the backside portion of the first integrated device 105. The gap 282 includes the cavity 250 of the solder resist layer 146. The gap 282 is filled with the encapsulation layer 108. A gap 480 exists between solder resist layer 146a and solder resist layer 124. Gap 480 is filled with encapsulation layer 108.

[0033] The first plurality of interconnects 142 includes a plurality of post interconnects 142a. The plurality of post interconnects 142a are coupled to the plurality of solder interconnects 190. The plurality of post interconnects 142a has a thickness that is less than a thickness of the solder resist layer 146a. The plurality of post interconnects 322 has a thickness that is less than a thickness of the solder resist layer 324. The plurality of post interconnects 322 are coupled to the plurality of solder interconnects 190.

[0034] In some implementations, to maximize and / or optimize the number of inter-board interconnects between the first substrate 102 and the second substrate 104, the pitch between the inter-board interconnects may need to be reduced to 270 micrometers or less (e.g., 150-270 micrometers). To achieve this, the vertical gap and / or vertical space between the interconnects (e.g., 122a) from the first substrate 102 and the interconnects (e.g., 142a) from the second substrate 104 may be reduced so that a plurality of solder interconnects 190 having a smaller size and / or smaller pitch may be used. This may be achieved by providing post interconnects (from the plurality of interconnects 142) and post interconnects 322 (from the plurality of interconnects 122), which helps to narrow the vertical gap between the interconnects from the first substrate 102 and the interconnects from the second substrate 104, thus allowing for a smaller size and / or smaller pitch solder interconnects 190. As the vertical gap between the first substrate 102 and the second substrate 104 is reduced, the first integrated device 105 may butt up against the second substrate 104. To accommodate the first integrated device 105 between the first substrate 102 and the second substrate 104 while still reducing the vertical gap between the first substrate 102 and the second substrate 104, a cavity 250 is formed in the solder resist layer 146 such that the backside of the first integrated device 105 does not directly contact the second substrate 104. Below are example dimensions and / or values ​​of various components that help provide a board-to-board interconnect having a pitch of 270 micrometers or less (e.g., 150-270 micrometers). In some implementations, the use of post interconnects in both the first substrate 102 and the second substrate 104 helps provide a smaller pitch for the solder interconnects between the substrates as the post interconnects on each substrate are closer together. A smaller pitch between solder interconnects means that more solder interconnects can be provided in the same area, which means denser routing between boards.

[0035] The various components of the package 300 may have various thicknesses and / or dimensions. In some implementations, the plurality of post interconnects 142a may have a thickness of about 40-50 micrometers. In some implementations, the solder resist layer 146a may have a thickness of about 65-80 micrometers (e.g., 240). In some implementations, the gap (e.g., 480) between the solder resist layer 124 and the solder resist layer 146a may be about 50-70 micrometers. In some implementations, the solder resist layer 324 may have a thickness (e.g., 460) of about 30-50 micrometers. In some implementations, the plurality of solder interconnects 190 may have a diameter of about 50-70 micrometers. In some implementations, the thickness of the gap 282 may be less than the thickness of the gap 480. Thus, for example, the vertical gap between the solder resist layer 146b and the backside of the integrated device 105 may be smaller than the vertical gap between the solder resist layer 146a of the second substrate 104 and the solder resist layer 324 of the first substrate 102. In some implementations, a portion of the backside of the integrated device 105 may be located within the cavity 250. Thus, the cavity 250 serves to accommodate the integrated device 105 between the first substrate 102 and the second substrate 104 while reducing the space or gap between the first substrate 102 and the second substrate 104.

[0036] In some implementations, the above dimensions help provide a package including a plurality of solder interconnects 190 that may have a pitch of approximately 150-270 micrometers. In some implementations, the plurality of solder interconnects 190 may include as many as 400 solder interconnects (e.g., solder balls) that laterally surround the first integrated device 105. Each of the solder interconnects 190 may represent a separate electrical path between the first substrate 302 and the second substrate 104. This configuration allows for a smaller, thinner package with denser routing between the first substrate 302 and the second substrate 104 while avoiding shorts between adjacent interconnects (e.g., adjacent solder interconnects 190). As the first substrate 302 and the second substrate 104 are bonded as close as possible to one another, the cavities 250 in the solder resist layer 146 help ensure that the solder resist layer does not directly contact the first integrated device 105.

[0037] A post interconnect, as used in this disclosure, may be an interconnect whose height (e.g., thickness) is equal to and / or greater than its width and / or diameter. A post interconnect may be bonded to a pad interconnect. A post interconnect may extend perpendicularly from a pad interconnect (e.g., perpendicularly from a surface of the pad interconnect). A post interconnect may be laterally surrounded (e.g., partially or completely) by a solder resist layer. A post interconnect may extend perpendicularly and / or perpendicularly from a surface of a substrate (e.g., first surface, second surface). A post interconnect of a substrate may extend perpendicularly and / or perpendicularly from a surface of the substrate and away from a dielectric layer of the substrate of which the post interconnect is a part. A post interconnect may not be in direct contact with a dielectric layer of a substrate. A post interconnect (e.g., 142a, 322) may be in direct contact with a solder resist layer (e.g., 146a, 324) of a substrate.

[0038] The integrated device (e.g., 105, 107) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or combinations thereof. The integrated device (e.g., 105, 107) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. An integrated device may be an example of an electrical component and / or an electrical device. In some implementations, an integrated device may be a chiplet. Fabrication of chiplets may provide better and / or improved yields (compared to other types of integrated devices), which may lower the overall cost of fabricating chiplets. Different chiplet structures may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chiplets may be used to perform the functionality of one or more chips (e.g., another integrated device). Using several chiplets to perform several functions may reduce the overall cost of the package compared to using a single chip to perform all of the functions of the package.

[0039] The package (e.g., 100, 300) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 100, 300) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 300) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 100, 300) may be configured to transmit and receive signals having different frequencies and / or communication protocols.

[0040] Having described the various packages, the sequence for creating the packages is now described below. Exemplary sequence for making a package comprising a substrate having post interconnects and a solder resist layer having cavities

[0041] In some implementations, making a package includes several processes. Figures 5A-5C show an example sequence for providing or making a package. In some implementations, the sequence of Figures 5A-5C can be used to provide or make package 100. However, the process of Figures 5A-5C can be used to make any of the packages (e.g., 300) described in this disclosure.

[0042] It should be noted that the sequence of Figures 5A-5C may combine one or more steps to simplify and / or clarify the sequence for providing or making a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0043] As shown in FIG. 5A, stage 1 illustrates the state after a substrate 102 is provided. The substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 102 may be fabricated using the methods described in FIGS. 10A-10C. In some implementations, a core substrate (e.g., a substrate including a core layer) is provided.

[0044] Stage 2 shows the state after the first integrated device 105 is bonded to a first surface (e.g., top surface) of the substrate 102. The first integrated device 105 may be bonded to the substrate 102 via a number of pillar interconnects 150 and / or solder interconnects (not shown). A solder reflow process may be used to bond the first integrated device 105 to the substrate 102. Stage 2 also shows an underfill 152 provided and / or formed between the first integrated device 105 and the substrate 102.

[0045] Stage 3 illustrates the state after a substrate 104 is provided. The substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The plurality of interconnects 142 may include post interconnects 142a. The substrate 104 includes a solder resist layer 144 and a solder resist layer 146. The solder resist layer 146 includes a cavity (e.g., 250). The substrate 104 may be fabricated using the method described in FIGS. 10A-10C. In some implementations, a core substrate (e.g., a substrate including a core layer) is provided.

[0046] Stage 4 shows the state after the substrate 104 is bonded to the substrate 102 via the plurality of ball interconnects 109 and the plurality of solder interconnects 190. A solder reflow process can be used to bond the substrate 104 to the substrate 102. The plurality of ball interconnects 109 can be bonded to the substrate 104 before the substrate 104 is bonded to the substrate 102. The substrate 104 is bonded to the substrate 102 such that the first integrated device 105 is located between the substrate 102 and the substrate 104. The first integrated device 105 can be located under a cavity (e.g., 250) in the solder resist layer 146. The plurality of ball interconnects 109 and the plurality of solder interconnects 190 are bonded to (i) the plurality of post interconnects 142a of the second substrate 104 and (ii) the plurality of interconnects 122 of the first substrate 102.

[0047] Stage 5 shows the state after the encapsulation layer 108 is provided between the substrate 102 and the substrate 104, as shown in FIG. 5B. The encapsulation layer 108 may encapsulate the first integrated device 105, the plurality of ball interconnects 109, and / or the plurality of solder interconnects 190. The encapsulation layer 108 may be located in the cavities (e.g., 250) of the solder resist layer 146. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0048] Stage 6 shows the state after the second integrated device 107 has been bonded to a first surface (e.g., top surface) of the substrate 104. The second integrated device 107 may be bonded to the substrate 104 via a number of solder interconnects 170. A solder reflow process may be used to bond the second integrated device 107 to the substrate 104.

[0049] 5C, stage 7 illustrates that the passive devices 130 are coupled to a second surface (e.g., a bottom surface) of the substrate 102. The passive devices 130 may be coupled to the substrate 102 via solder interconnects (not shown). A solder reflow process may be used to couple the passive devices 130 to the substrate 102.

[0050] Stage 8 shows the condition after the plurality of solder interconnects 110 have been bonded to the second surface of the substrate 102. A solder reflow process may be used to bond the plurality of solder interconnects 110 to the substrate 102. Stage 8 may show the package 100. The package 100 may be fabricated piece by piece or may be fabricated integrally as part of one or more wafers and then singulated into individual packages. Exemplary sequence for making a package comprising a substrate having post interconnects and a solder resist layer having cavities

[0051] In some implementations, making the package includes several processes. Figures 6A-6C show an example sequence for providing or making the package. In some implementations, the sequence of Figures 6A-6C can be used to provide or make the package 300. However, the process of Figures 6A-6C can be used to make any of the packages (e.g., 100) described in this disclosure.

[0052] It should be noted that the sequence of Figures 6A-6C may combine one or more steps to simplify and / or clarify the sequence for providing or making a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0053] Stage 1, as shown in FIG. 6A, illustrates the state after a substrate 302 is provided. The substrate 302 includes at least one dielectric layer 120 and a plurality of interconnects 122. The plurality of interconnects 122 includes a plurality of post interconnects 322. The substrate 302 includes a solder resist layer 324 and a plurality of solder resist layers 126. The substrate 302 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The substrate 302 may be fabricated using the methods described in FIGS. 10A-10C. In some implementations, a core substrate (e.g., a substrate including a core layer) is provided.

[0054] Stage 2 shows the state after the first integrated device 105 is bonded to a first surface (e.g., top surface) of the substrate 302. The first integrated device 105 may be bonded to the substrate 302 via a number of pillar interconnects 150 and / or solder interconnects (not shown). A solder reflow process may be used to bond the first integrated device 105 to the substrate 302. Stage 2 also shows an underfill 152 provided and / or formed between the first integrated device 105 and the substrate 102.

[0055] Stage 3 illustrates the state after a substrate 104 is provided. The substrate 104 includes at least one dielectric layer 140 and a plurality of interconnects 142. The substrate 104 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). The plurality of interconnects 142 may include post interconnects 142a. The substrate 104 includes a solder resist layer 144 and a solder resist layer 146. The solder resist layer 146 includes a cavity (e.g., 250). The substrate 104 may be fabricated using the method described in FIGS. 10A-10C. In some implementations, a core substrate (e.g., a substrate including a core layer) is provided.

[0056] Stage 4 shows a state after the substrate 104 is bonded to the substrate 302 via the plurality of solder interconnects 190. A solder reflow process can be used to bond the substrate 104 to the substrate 302. The substrate 104 is bonded to the substrate 302 such that the first integrated device 105 is located between the substrate 302 and the substrate 104. The first integrated device 105 can be located under a cavity (e.g., 250) of the solder resist layer 146. The plurality of solder interconnects 190 are bonded to (i) the plurality of post interconnects 142a of the second substrate 104 and (ii) the plurality of post interconnects 322 of the first substrate 302. The plurality of solder interconnects 190 can be bonded to the substrate 104 first using a solder reflow process, and then the substrate 104 can be bonded to the substrate 302 via the plurality of solder interconnects 190 using a solder reflow process.

[0057] Stage 5 shows the state after the encapsulation layer 108 is provided between the substrate 302 and the substrate 104, as shown in FIG. 6B. The encapsulation layer 108 may encapsulate the first integrated device 105 and / or the plurality of solder interconnects 190. The encapsulation layer 108 may be located in the cavities (e.g., 250) of the solder resist layer 146. The encapsulation layer 108 may include a mold, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0058] Stage 6 shows the state after the second integrated device 107 has been bonded to a first surface (e.g., top surface) of the substrate 104. The second integrated device 107 may be bonded to the substrate 104 via a number of solder interconnects 170. A solder reflow process may be used to bond the second integrated device 107 to the substrate 104.

[0059] 6C, stage 7 illustrates that the passive devices 130 are coupled to a second surface (e.g., a bottom surface) of the substrate 302. The passive devices 130 may be coupled to the substrate 302 via solder interconnects (not shown). A solder reflow process may be used to couple the passive devices 130 to the substrate 302.

[0060] Stage 8 shows the condition after the plurality of solder interconnects 110 have been bonded to a second surface of the substrate 302. A solder reflow process may be used to bond the plurality of solder interconnects 110 to the substrate 302. Stage 8 may show a package 300. The package 300 may be fabricated piece by piece or may be fabricated integrally as part of one or more wafers and then singulated into individual packages. 1 is an exemplary flow diagram of a method for making a package comprising a substrate having post interconnects and a solder resist layer having cavities;

[0061] In some implementations, producing the package includes several processes. Figure 7 shows an example flow diagram of a method 700 for providing or producing a package. In some implementations, the method 700 of Figure 7 can be used to provide or produce the package 100 described in this disclosure. However, the method 700 can be used to provide or produce any of the packages (e.g., 300) described in this disclosure.

[0062] It should be noted that method 700 of Figure 7 may combine one or more processes to simplify and / or clarify the method for providing or making a package. In some implementations, the order of the processes may be changed or modified.

[0063] The method includes (at 705) providing a first substrate (e.g., 102) and a first integrated device (e.g., 105) coupled to a first surface of the first substrate (e.g., 102). The first substrate 102 and the first integrated device 105 can be part of a first package. The first substrate 102 includes at least a first dielectric layer 120 and a first plurality of interconnects 122. In some implementations, the first substrate can include a plurality of post interconnects (e.g., 322). The first substrate 102 can include a solder resist layer 124 and / or a solder resist layer 126. The substrate 102 can be fabricated using the method described in FIGS. 10A-10C. Step 1 of FIG. 5A illustrates and describes an example of a first substrate being provided. Step 2 of FIG. 5A illustrates and describes an example of a first substrate having a first integrated device. Step 1 of Figure 6A illustrates and describes an example of a first substrate being provided. Step 2 of Figure 6A illustrates and describes an example of a first substrate having a first integrated device.

[0064] The method provides (at 710) a second substrate (e.g., 104). The second substrate 104 includes at least one second dielectric layer 140 and a second plurality of interconnects 142. The second plurality of interconnects 142 can include post interconnects (e.g., 142a). The second substrate can include a solder resist layer having a variable thickness. For example, the second substrate can include a solder resist layer having a first thickness and a second thickness. The second substrate can include a solder resist layer having a cavity (e.g., 250). The substrate 104 can be fabricated using the method described in FIGS. 10A-10C. In some implementations, the substrate 104 can be fabricated using mSAP. Stage 3 of FIG. 5A illustrates and describes an example of a second substrate being provided. Stage 3 of FIG. 6A illustrates and describes an example of a second substrate being provided.

[0065] The method includes (at 715) bonding a second substrate (e.g., 104) to a first substrate (e.g., 102) via a plurality of ball interconnects (e.g., 109) and / or a plurality of solder interconnects (e.g., 190). The plurality of ball interconnects 109 and / or the plurality of solder interconnects 190 are examples of inter-substrate interconnects. A solder reflow process can be used to bond the second substrate to the first substrate. Step 4 of FIG. 5A illustrates and describes an example of a second substrate bonded to a first substrate. Step 4 of FIG. 6A illustrates and describes an example of a second substrate bonded to a first substrate.

[0066] The method provides (at 720) an encapsulation layer (e.g., 108) between the first substrate (e.g., 102, 302) and the second substrate (e.g., 104). The encapsulation layer 108 may include mold, resin, and / or epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. At least a portion of the encapsulation layer 108 may be located between the second substrate 104 and the first integrated device 105. Step 5 of FIG. 5B illustrates and describes an example of providing the encapsulation layer. Step 5 of FIG. 6B illustrates and describes an example of providing the encapsulation layer.

[0067] The method includes (at 725) bonding a second integrated device (e.g., 107) to a first surface of a second substrate (e.g., 104) via a plurality of solder interconnects (e.g., 170). A solder reflow process may be used to bond the second integrated device to the first surface of the second substrate 104. Step 6 of FIG. 5B illustrates and describes one example of a second integrated device bonded to the second substrate. Step 6 of FIG. 6B illustrates and describes one example of a second integrated device bonded to the second substrate.

[0068] The method includes (at 730) bonding a passive device (e.g., 130) and a plurality of solder interconnects (e.g., 110) to a second surface of the first substrate (e.g., 102, 302). A solder reflow process may be used to bond the passive device and / or the solder interconnects to the second surface of the first substrate (e.g., 102, 302). Step 7 of FIG. 5C illustrates and describes an example of bonding a passive device to a substrate. Step 7 of FIG. 6C illustrates and describes an example of bonding a passive device to a substrate. Step 8 of FIG. 5C illustrates and describes an example of bonding a solder interconnect to a substrate. Step 8 of FIG. 6C illustrates and describes an example of bonding a solder interconnect to a substrate.

[0069] In some implementations, several packages are made simultaneously. In such cases, the method can singulate the packages (e.g., 100, 300). 1 is an exemplary flow diagram of a method for making a package with substrates bonded via ball interconnects;

[0070] Figure 8 illustrates an example flow diagram of a method 800 for providing or making a package. In some implementations, the method 800 of Figure 8 can be used to provide or make some or all of the packages of Figure 1 described in this disclosure. However, the method 800 can be used to provide or make any of the packages described in this disclosure.

[0071] It should be noted that the method 800 of Figure 8 may combine one or more processes to simplify and / or clarify the method for providing or making the package. In some implementations, the order of the processes may be changed or modified.

[0072] The method provides (at 805) a wafer. The wafer may serve as a substrate on which integrated devices may be formed and / or bonded. In some implementations, other substrates may be bonded to the wafer. The wafer may include silicon. The wafer may serve as a base on which components are built.

[0073] The method forms (at 810) solder interconnects on the wafer. A solder reflow process can be used to form (e.g., bond) the solder interconnects on the wafer.

[0074] The method includes (at 815) preparing one or more integrated devices (e.g., dies) for bonding. Preparing the integrated devices can include fabricating the integrated devices.

[0075] The method provides and prepares (at 820) a first substrate (e.g., substrate 102, bottom substrate) by pre-baking the first substrate. The first substrate may be pre-baked to remove moisture on the first substrate to avoid outgassing during a subsequent thermocompression flip chip bonding process. The method pre-cleans (at 825) the first substrate. The method removes (at 827) any organic solderability preservative (OSP) on the first substrate.

[0076] Once the first substrate is provided and prepared, it can be bonded to the wafer via solder interconnects formed on the wafer.

[0077] The integrated device(s) are bonded (at 830) to the first substrate. For example, the integrated device 105 may be bonded to the substrate 102 via a thermo-compression flip-chip process. An underfill may be provided between the integrated device and the substrate. Stage 2 of Figure 5A illustrates and describes an example of an integrated device bonded to a substrate and an underfill provided between the integrated device and the substrate.

[0078] The method performs (at 835) a plasma clean of the first substrate. The plasma clean can remove contaminants on the surface of the substrate.

[0079] The method pre-cleans (at 840) a second substrate (e.g., substrate 104, top substrate). Stage 3 of FIG. 5A illustrates and describes one example of a second substrate being provided. The method bonds (at 845) ball interconnects (e.g., copper core balls) to the second substrate. The ball interconnects can be bonded to the second substrate 104 via solder interconnects (e.g., 190). A solder reflow process can be used to bond the ball interconnects to the second substrate. The method performs (at 847) singulation of the strip block of the second substrate. This can be done when several substrates are fabricated simultaneously and subsequently singulated.

[0080] The method performs (at 850) flux cleaning of one or more substrates. Flux cleaning can remove oxides from metal of the substrates. Flux cleaning can be performed on the first substrate and / or the second substrate.

[0081] The method then proceeds to (at 855) bond a second substrate (e.g., 104) to the first substrate (e.g., 102) via the ball interconnects. A solder reflow process can be used to bond the second substrate to the first substrate. Step 4 of FIG. 5A illustrates and describes one example of bonding a substrate to another substrate.

[0082] The method includes (at 860) providing an encapsulation layer (eg, 108) between the first substrate and the second substrate. Step 5 of Figure 5B illustrates and describes one example of providing an encapsulation layer between the substrates.

[0083] The method forms (at 865) a solder interconnect or a land side array (LSA) on the first substrate. A solder reflow process can be used to form the solder interconnect. The solder interconnect can be a ball grid array (BGA).

[0084] The method then singulates (at 870) the package into individual packages. This may be done when several packages are fabricated simultaneously. Singulating the packages may include singulating a wafer that includes the first substrate, the integrated device(s), and the second substrate. A mechanical process (e.g., a saw) or a laser may be used to singulate the packages.

[0085] The method performs (at 875) a final test and a final visual inspection of the package. This may include testing the package for proper functioning by attaching probes to the package to determine if it functions as intended. The visual inspection may include visually inspecting the package to see if there are any defects.

[0086] The method performs (at 880) taping and reeling of the packages, which may include wrapping the singulated packages together with tape so that the packages can be properly shipped.

[0087] It should be noted that additional processes may be performed on the package, including coupling other components, such as passive components and / or integrated devices, to the package. Figure 8 shows one example of how the package may be made. Figure 8 is not intended to show the only way the package may be made. 1 is an exemplary flow diagram of a method for making a package comprising substrates bonded via solder interconnects;

[0088] Figure 9 illustrates an example flow diagram of a method 900 for providing or making a package. In some implementations, the method 900 of Figure 9 can be used to provide or make some or all of the packages of Figure 3 described in this disclosure. However, the method 900 can be used to provide or make any of the packages described in this disclosure.

[0089] It should be noted that the method 900 of Figure 9 may combine one or more processes to simplify and / or clarify the method for providing or making the package. In some implementations, the order of the processes may be changed or modified.

[0090] The method provides (at 905) a wafer. The wafer may serve as a substrate on which integrated devices may be formed and / or bonded. In some implementations, other substrates may be bonded to the wafer. The wafer may include silicon. The wafer may serve as a base on which components are built.

[0091] The method forms (at 910) solder interconnects on the wafer. A solder reflow process can be used to form (e.g., bond) the solder interconnects on the wafer.

[0092] The method includes (at 915) preparing one or more integrated devices (e.g., dies) for bonding. Preparing the integrated devices can include fabricating the integrated devices.

[0093] The method provides and prepares (at 920) a first substrate (e.g., substrate 302, bottom substrate) by pre-baking the first substrate. The first substrate may be pre-baked to remove moisture on the first substrate to avoid outgassing during a subsequent thermocompression flip chip bonding process. The method pre-cleans (at 925) the first substrate. The method removes (at 927) any organic solderability preservatives (OSPs) on the first substrate.

[0094] Once the first substrate is provided and prepared, it can be bonded to the wafer via solder interconnects formed on the wafer.

[0095] The integrated device(s) are bonded (at 930) to a first substrate. For example, the integrated device 105 may be bonded to the substrate 102 via a thermo-compression flip-chip process. An underfill may be provided between the integrated device and the substrate. Stage 2 of Figure 6A illustrates and describes an example of an integrated device bonded to a substrate and an underfill provided between the integrated device and the substrate.

[0096] The method performs (at 935) a plasma clean of the first substrate. The plasma clean can remove contaminants on the surface of the substrate.

[0097] The method pre-cleans (at 940) a second substrate (e.g., substrate 104, top substrate). Stage 3 of FIG. 6A illustrates and describes one example of a second substrate being provided. The method forms (at 945) solder interconnects on the second substrate. The solder interconnects (e.g., 190) can be bonded to the second substrate 104 using a paste printing process or using a solder ball attachment process. A solder reflow process can be used to bond the ball interconnects to the second substrate. The method performs (at 947) singulation of the strip block of the second substrate. This can be done when several substrates are fabricated simultaneously and subsequently singulated.

[0098] The method performs (at 950) a flux clean of one or more substrates. The flux clean can remove oxides from the metal of the substrate. The flux clean can be performed on the first substrate and / or the second substrate.

[0099] The method then proceeds to (at 955) bond a second substrate (e.g., 104) to the first substrate (e.g., 102) via the ball interconnects. A solder reflow process may be used to bond the second substrate to the first substrate. Step 4 of FIG. 6A illustrates and describes one example of bonding a substrate to another substrate.

[0100] The method includes (at 960) providing an encapsulation layer (eg, 108) between the first and second substrates. Step 5 of Figure 6B illustrates and describes one example of providing an encapsulation layer between the substrates.

[0101] The method forms (at 965) a solder interconnect or land side array (LSA) on the first substrate. A solder reflow process can be used to form the solder interconnect. The solder interconnect can be a ball grid array (BGA).

[0102] The method singulates (at 970) the package into individual packages. This may be done when several packages are made simultaneously. Singulating the packages may include singulating a wafer that includes the first substrate, the integrated device(s), and the second substrate. A mechanical process (e.g., a saw) or a laser may be used to singulate the packages.

[0103] The method performs (at 975) a final test and a final visual inspection of the package. This may include testing the package for proper functioning by attaching probes to the package to determine if it functions as intended. The visual inspection may include visually inspecting the package to see if there are any defects.

[0104] The method performs (at 980) taping and reeling of the packages, which may include wrapping the singulated packages together with tape so that the packages can be properly shipped.

[0105] It should be noted that additional processes may be performed on the package, including coupling other components, such as passive components and / or integrated devices, to the package. Figure 9 shows one example of how the package may be made. Figure 9 is not intended to show the only way the package may be made. Exemplary Sequence for Preparing a Substrate

[0106] In some implementations, producing a substrate includes several processes. Figures 10A-10C show an example sequence for providing or producing a substrate. In some implementations, the sequence of Figures 10A-10C can be used to provide or produce substrate 104. However, the processes of Figures 10A-10C can be used to produce any of the substrates described in this disclosure, such as substrate 102 and / or substrate 302.

[0107] It should be noted that the sequence of Figures 10A-10C may combine one or more steps to simplify and / or clarify the sequence for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of the processes may be interchanged or substituted without departing from the scope of the disclosure.

[0108] Stage 1, as shown in FIG. 10A , illustrates the state after a carrier 1000 is provided. A seed layer 1001 and interconnects 1002 may be located on the carrier 1000. The interconnects 1002 may be located on the seed layer 1001. A plating process and an etching process may be used to form the interconnects 1002. In some implementations, the carrier 1000 may be provided with a seed layer 1001 and a metal layer that is patterned to form the interconnects 1002. The interconnects 1002 may represent at least some of the interconnects from the plurality of interconnects 142.

[0109] Stage 2 shows the state after a dielectric layer 1020 is formed over the carrier 1000, the seed layer 1001, and the interconnects 1002. A deposition process and / or lamination process can be used to form the dielectric layer 1020. The dielectric layer 1020 can include prepreg and / or polyimide. The dielectric layer 1020 can include a photoimageable dielectric. However, different implementations can use different materials for the dielectric layer.

[0110] Stage 3 shows the state after a number of cavities 1010 have been formed in the dielectric layer 1020. The number of cavities 1010 can be formed using an etching process (eg, a photoetching process) or a laser process.

[0111] Stage 4 shows the state after interconnects 1012 have been formed in and on the dielectric layer 1020, including in and on the plurality of cavities 1010. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0112] Stage 5 shows the state after a dielectric layer 1022 is formed over the dielectric layer 1020 and the interconnects 1012. A deposition and / or lamination process can be used to form the dielectric layer 1022. The dielectric layer 1022 can include prepreg and / or polyimide. The dielectric layer 1022 can include a photoimageable dielectric. However, different implementations can use different materials for the dielectric layer.

[0113] 10B, stage 6 shows the state after a number of cavities 1030 have been formed in the dielectric layer 1022. The number of cavities 1030 can be formed using an etching process (e.g., a photoetching process) or a laser process.

[0114] Stage 7 shows the state after interconnects 1014 have been formed in and on the dielectric layer 1022, including in and on the plurality of cavities 1030. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0115] Stage 8 shows the state after interconnect 1016 is formed on interconnect 1014. Interconnect 1016 may be a post interconnect. A plating process may be used to form interconnect 1016. Plurality of interconnects 1002, plurality of interconnects 1012, and / or plurality of interconnects 1014 may be represented by plurality of interconnects 142. Dielectric layer 1020 and / or dielectric layer 1022 may be represented by at least one dielectric layer 140. At least one dielectric layer 140 may include a photoimageable dielectric. At least one dielectric layer 140 may include a prepreg and / or a polyimide.

[0116] Stage 9 shows the state after the carrier 1000 has been separated (e.g., detached, removed, ground) from the at least one dielectric layer 140 and the seed layer 1001, and portions of the seed layer 1001 have been removed (e.g., etched away), leaving behind a substrate 104 including at least one dielectric layer 140 and multiple interconnects 142.

[0117] Stage 10 illustrates the state after a solder resist layer 144 has been formed on a first surface of the substrate 104 and a solder resist layer 146 has been formed on a second surface of the substrate 104, as shown in Figure 10C. A deposition and / or lamination process may be used to form the solder resist layer 144 and / or the solder resist layer 146.

[0118] Stage 11 shows the state after an additional layer of solder resist has been formed over portions of solder resist layer 146, causing different portions of solder resist layer 146 to have different thicknesses. The additional layer of solder resist is considered part of solder resist layer 146. The additional layer of solder resist forms a cavity 1460 in solder resist layer 146. A deposition and / or lamination process may be used to form the additional solder resist.

[0119] Different implementations may use different processes to form the metal layer(s) and / or the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s). 1 is an exemplary flow diagram of a method for fabricating a substrate;

[0120] In some implementations, producing a substrate includes several processes. Figure 11 shows an example flow diagram of a method 1100 for providing or producing a substrate. In some implementations, the method 1100 of Figure 11 can be used to provide or produce a substrate(s) of the present disclosure. For example, the method 1100 of Figure 11 can be used to produce a substrate 104.

[0121] It should be noted that the method 1100 of Figure 11 may combine one or more processes to simplify and / or clarify the method for providing or fabricating a substrate. In some implementations, the order of the processes may be changed or modified.

[0122] The method provides (at 1105) a carrier (e.g., 1000). Different implementations can use different materials for the carrier 1000. The carrier 1000 can include a seed layer (e.g., 1001). The seed layer 1001 can include a metal (e.g., copper). The carrier can include a substrate, glass, quartz, and / or a carrier tape. Step 1 of FIG. 10A illustrates and describes one example of a carrier having a seed layer provided.

[0123] The method forms and patterns (at 1110) interconnects on the carrier 1000 and the seed layer 1001. A metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer overlies the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 142). Step 1 of FIG. 10A illustrates and describes one example of forming and patterning interconnects on a seed layer and a carrier.

[0124] The method forms (at 1115) a dielectric layer 1020 over the seed layer 1001, the carrier 1000, and the interconnects 1002. A deposition process and / or a lamination process can be used to form the dielectric layer 1020. The dielectric layer 1020 can include prepreg and / or polyimide. The dielectric layer 1020 can include a photoimageable dielectric. Forming the dielectric layer 1020 can also include forming a plurality of cavities (e.g., 1010) in the dielectric layer 1020. The plurality of cavities can be formed using an etching process (e.g., photoetching) or a laser process. Steps 2-3 of FIG. 10A illustrate and describe an example of a dielectric layer and forming cavities in the dielectric layer.

[0125] The method forms (at 1120) interconnects in and on the dielectric layer. For example, interconnects 1012 can be formed in and on the dielectric layer 1020. A plating process can be used to form the interconnects. Forming the interconnects can include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects can also include forming the interconnects in cavities in the dielectric layer. Step 4 of FIG. 10A illustrates and describes one example of forming interconnects in and on the dielectric layer.

[0126] The method forms (at 1125) a dielectric layer 1022 over the dielectric layer 1020 and the interconnects 1012. A deposition process and / or lamination process can be used to form the dielectric layer 1022. The dielectric layer 1022 can include prepreg and / or polyimide. The dielectric layer 1022 can include a photoimageable dielectric. Forming the dielectric layer 1022 can also include forming a plurality of cavities (e.g., 1030) in the dielectric layer 1022. The plurality of cavities can be formed using an etching process (e.g., photoetching) or a laser process. Steps 5-6 of Figures 10A-10B illustrate and describe one example of a dielectric layer and forming cavities in the dielectric layer.

[0127] The method forms (at 1130) interconnects in and on the dielectric layer. For example, interconnect 1014 can be formed in and on dielectric layer 1022. A plating process can be used to form the interconnects. Forming the interconnects can include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects can also include forming the interconnects in cavities in the dielectric layer. Forming the interconnects can include forming post interconnects. Steps 7-8 of FIG. 10B illustrate and describe one example of forming interconnects in and on the dielectric layer, including forming post interconnects.

[0128] The method separates (at 1135) the carrier (e.g., 1000) from the seed layer (e.g., 1001). The carrier 1000 may be removed and / or ground. The method may also remove (at 1135) portions of the seed layer (e.g., 1001). An etching process may be used to remove portions of the seed layer 1001. Step 9 of FIG. 10B illustrates and describes an example of carrier separation and seed layer removal.

[0129] The method may include (at 1140) forming a solder resist layer(s) on a first surface and / or a second surface of the substrate. For example, a first solder resist layer may be formed on the first surface of the substrate, and / or a second solder resist layer may be formed on the second surface of the substrate. The first solder resist layer and / or the second solder resist layer may each have a variable thickness, such that the first solder resist layer and / or the second solder resist layer may have cavities, as described in FIGS. 1-4. That is, a first portion of a solder resist layer may have a first thickness, and a second portion of the same solder resist layer may have a second thickness that is different from the first thickness. Steps 10 and 11 of FIG. 10C illustrate and describe one example of providing and / or forming a solder resist layer having cavities.

[0130] Different implementations may use different processes to form the metal layer(s). In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the metal layer(s). Exemplary Electronic Devices

[0131] FIG. 12 illustrates various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1202, a laptop computer device 1204, a stationary terminal device 1206, a wearable device 1208, or an autonomous vehicle 1210 may include a device 1200 as described herein. The device 1200 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. The devices 1202, 1204, 1206, and 1208 and the vehicle 1210 illustrated in FIG. 12 are merely exemplary. Other electronic devices may also feature device 1200, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices installed in automated vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0132] One or more of the components, processes, features, and / or functions shown in Figures 1-4, 5A-5C, 6A-6C, 7-9, 10A-10C, and 11-12 may be rearranged and / or combined into a single component, process, feature, or function, or may be combined into several components, processes, or functions. Additional elements, components, processes, and / or functions may be further added without departing from the present disclosure. It is also noted that Figures 1-4, 5A-5C, 6A-6C, 7-9, 10A-10C, and 11-12 in this disclosure and corresponding descriptions thereof are not limited to dies and / or ICs. In some implementations, Figures 1-4, 5A-5C, 6A-6C, 7-9, 10A-10C, and 11-12 and corresponding descriptions thereof can be used to manufacture, create, provide, and / or produce a device and / or an integrated device. In some implementations, a device can include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0133] It should be noted that the drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the drawings may not be to scale. In some cases, for purposes of clarity, not all components and / or parts may be shown. In some cases, the position, location, size, and / or shape of various parts and / or components in the drawings may be exemplary. In some implementations, various components and / or parts in the drawings may be optional.

[0134] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the described feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, object A and object C can still be considered to be coupled to each other even though they are not in direct physical contact with each other. Object A that is coupled to object B can be coupled to at least a portion of object B. The term "electrically coupled" can mean that two objects are directly or indirectly coupled together such that an electric current (e.g., signal, power, ground) can travel between the two objects. Two objects that are electrically coupled may or may not propagate a current between the two objects. The use of the terms "first," "second," "third," and "fourth" (and / or anything more than fourth) is arbitrary. Any of the components described may be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component may also be a first component, a second component, a third component, or a fourth component. The terms "encapsulate," "encapsulating," and / or derivatives thereof, mean that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. A component located at the top may be located above a component located at the bottom. A top component may be considered a bottom component and vice versa.As described in this disclosure, a first component being "over" a second component can mean that the first component is above or below the second component, depending on how bottom or top is arbitrarily defined. In another embodiment, the first component may be above (e.g., above) a first surface of the second component, and the third component may be above (e.g., below) a second surface of the second component, where the second surface is opposite the first surface. It is further noted that in the context of one component being above another component, the term "over" as used in this application can be used to mean a component that is on and / or within (e.g., on a surface of or embedded within) the other component. Thus, for example, a first component present on a second component can mean (1) that the first component is present on the second component but not in direct contact with the second component, (2) that the first component is present on (e.g., on the surface of) the second component, and / or (3) that the first component is present within (e.g., embedded within) the second component. A first component located "in" a second component can be partially located within the second component or completely located within the second component. A value that is about X to XX can mean a value between and including X and XX. The value or values ​​between X and XX can be discrete or continuous. The term "about "value X"" or "approximately value X" as used in this disclosure means within a range of 10 percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0135] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include a trace (e.g., a trace interconnect), a via (e.g., a via interconnect), a pad (e.g., a pad interconnect), a pillar, a metallization layer, a redistribution layer, and / or an under bump metallization (UBM) layer / interconnect. In some implementations, an interconnect may include a conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating process, and / or a plating process may be used to form the interconnects.

[0136] It should also be noted that various disclosures contained herein may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Additionally, the order of operations may be rearranged. A process is terminated when its operations are completed.

[0137] In the following, further examples are described to facilitate understanding of the present invention.

[0138] Aspect 1: A package comprising a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, a first integrated device coupled to the first substrate, a second substrate, and a plurality of ball interconnects and a plurality of solder interconnects coupled to the first substrate and the second substrate. The second substrate comprises a first surface and a second surface, at least one second dielectric layer, a second plurality of interconnects comprising a plurality of post interconnects, and a solder resist layer coupled to the second substrate. The second substrate surface faces the first substrate. The solder resist layer includes a cavity. The cavity is located between the first integrated device and the solder resist layer. The plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate. The plurality of ball interconnects and the plurality of solder interconnects are configured to couple the first substrate to the second substrate.

[0139] Aspect 2: The package of claim 1, wherein the plurality of ball interconnects and the plurality of solder interconnects are coupled to a plurality of post interconnects of a second substrate, the plurality of post interconnects being laterally surrounded by a solder resist layer.

[0140] Embodiment 3: The package of embodiments 1 to 2, wherein the plurality of ball interconnects comprises adjacent ball interconnects having a pitch of 270 micrometers or less.

[0141] Example 4: The package of example 3, wherein the plurality of ball interconnects comprises adjacent ball interconnects having a pitch within a range of approximately 200 to 270 micrometers.

[0142] Embodiment 5: A package as described in embodiments 1 to 4, wherein the plurality of ball interconnects includes at least 300 ball interconnects laterally surrounding the first integrated device.

[0143] Aspect 6: The package of aspects 1 to 5, further comprising an encapsulation layer located between the first substrate and the second substrate, a portion of the encapsulation layer located between the solder resist layer and the first integrated device.

[0144] Aspect 7: The package of aspect 6, wherein the encapsulation layer at least partially encapsulates the first integrated device, the plurality of ball interconnects, and the plurality of solder interconnects.

[0145] Aspect 8: A package as described in aspects 1 to 7, wherein the solder resist layer includes a first portion having a first thickness and a second portion having a second thickness, the first portion of the solder resist layer having a first thickness greater than a thickness of the plurality of post interconnects, the second portion of the solder resist layer having a second thickness less than a thickness of the plurality of post interconnects, and the second portion of the solder resist layer is located over the first integrated device.

[0146] Aspect 9: The package of aspects 1 to 8, further comprising a second integrated device bonded to the first surface of the second substrate, wherein a vertical gap between the solder resist layer of the second substrate and a back surface of the first integrated device is smaller than another vertical gap between the solder resist layer of the second substrate and the solder resist layer of the first substrate.

[0147] Example 10: The package of any one of Examples 1 to 9, wherein the plurality of ball interconnects comprises copper core balls (CCBs).

[0148] Aspect 11: A package comprising a first substrate, a first integrated device coupled to the first substrate, a second substrate, and a plurality of solder interconnects coupled to the first substrate and the second substrate. The first substrate comprises at least a first dielectric layer, a first plurality of interconnects including a first plurality of post interconnects, and a first solder resist layer coupled to a first surface of the first substrate. The second substrate comprises a first surface and a second surface, at least a second dielectric layer, a second plurality of interconnects including a second plurality of post interconnects, and a second solder resist layer coupled to a second surface of the second substrate. The second surface of the second substrate faces the first substrate. The second solder resist layer comprises a cavity. The cavity is located between the first integrated device and the second solder resist layer. A plurality of solder interconnects are located between the first substrate and the second substrate, the plurality of solder interconnects being configured to couple the first substrate to the second substrate.

[0149] Aspect 12: The package of aspect 11, wherein a plurality of solder interconnects are coupled to (i) a first plurality of post interconnects of a first substrate and (ii) a second plurality of post interconnects of a second substrate, the first plurality of post interconnects being laterally surrounded by a first solder resist layer, and the second plurality of post interconnects being laterally surrounded by a second solder resist layer.

[0150] Example 13: A package as described in examples 11 to 12, wherein the plurality of solder interconnects comprises adjacent solder interconnects having a pitch of 270 micrometers or less.

[0151] Example 14: The package of example 13, wherein the plurality of solder interconnects comprises adjacent solder interconnects having a pitch within a range of approximately 150 to 270 micrometers.

[0152] Example 15: A package as described in Examples 11 to 14, wherein the plurality of solder interconnects includes at least 300 solder interconnects laterally surrounding the first integrated device.

[0153] Aspect 16: A package described in aspects 11 to 15, further comprising an encapsulation layer located between the first substrate and the second substrate, a portion of the encapsulation layer being located between the second solder resist layer and the first integrated device.

[0154] Example 17: The package of example 16, wherein the encapsulation layer at least partially encapsulates the first integrated device and the plurality of solder interconnects.

[0155] Aspect 18: A package as described in aspects 11 to 17, wherein the second solder resist layer includes a first portion having a first thickness and a second portion having a second thickness, the first portion of the second solder resist layer having a first thickness greater than a thickness of the second plurality of post interconnects, the second portion of the second solder resist layer having a second thickness less than a thickness of the second plurality of post interconnects, and the second portion of the second solder resist layer is located over the first integrated device.

[0156] Aspect 19: The package of aspects 11 to 18, further comprising a second integrated device bonded to the first surface of the second substrate, wherein a vertical gap between the solder resist layer of the second substrate and a back surface of the first integrated device is smaller than another vertical gap between the solder resist layer of the second substrate and the solder resist layer of the first substrate.

[0157] Embodiment 20: The package of embodiments 11 to 19, further comprising a passive device coupled to the first substrate.

[0158] Aspect 21: A package comprising a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, a first integrated device coupled to the first substrate, a second substrate, and a means for inter-substrate interconnection coupled to the first substrate and the second substrate. The second substrate comprises a first surface and a second surface, at least one second dielectric layer, a second plurality of interconnects comprising a plurality of post interconnects, and a solder resist layer coupled to the second substrate. The solder resist layer includes a cavity. The cavity is located between the first integrated device and the solder resist layer. The means for inter-substrate interconnection is located between the first substrate and the second substrate. The means for inter-substrate interconnection is configured to couple the first substrate to the second substrate.

[0159] Example 22: The package of example 21, wherein the means for board-to-board interconnection includes a plurality of ball interconnects and / or a plurality of solder interconnects.

[0160] Embodiment 23: The package of embodiments 21 to 22, wherein the means for inter-board interconnection is coupled to a plurality of post interconnects of the second substrate.

[0161] Example 24: The package of example 23, wherein the first substrate includes a first plurality of interconnects, the first plurality of interconnects having a first plurality of post interconnects, and the means for substrate-to-substrate interconnection is coupled to the first plurality of post interconnects of the first substrate.

[0162] Example 25: The package of any one of Examples 21 to 24, wherein the means for inter-substrate interconnection includes interconnects having a pitch in the range of approximately 150 to 270 micrometers.

[0163] Aspect 26: A method includes providing a first substrate comprising at least a first dielectric layer and a first plurality of interconnects. The method bonds a first integrated device to the first substrate. The method bonds a second substrate to the first substrate via the plurality of inter-substrate interconnects such that the plurality of inter-substrate interconnects are located between the first substrate and the second substrate. The second substrate comprises a first surface and a second surface, at least a second dielectric layer, a second plurality of interconnects comprising a plurality of post interconnects, and a solder resist layer bonded to the second substrate. The solder resist layer includes a cavity. The cavity is located between the solder resist layer and the first integrated device.

[0164] Example 27: The method of example 26, wherein the plurality of board-to-board interconnects comprises a plurality of ball interconnects and / or a plurality of solder interconnects.

[0165] Example 28: The method of Examples 26 to 27, wherein a plurality of inter-substrate interconnects are coupled to a plurality of post interconnects of a second substrate.

[0166] Example 29: The method of example 28, wherein the first substrate includes a first plurality of interconnects, the first plurality of interconnects comprising a first plurality of post interconnects, and the plurality of inter-substrate interconnects are coupled to the first plurality of post interconnects of the first substrate.

[0167] Example 30: The method of any one of Examples 26 to 29, wherein the plurality of inter-substrate interconnects comprises interconnects having a pitch in the range of approximately 150 to 270 micrometers.

[0168] Various features of the present disclosure described herein can be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the aspects of the present disclosure is intended to be illustrative and not intended to limit the scope of the claims. Thus, the present teachings can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. a first substrate comprising at least one first dielectric layer and a first plurality of interconnects; a first integrated device coupled to the first substrate; a second substrate, a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, the second plurality of interconnects comprising a second plurality of post interconnects; a second solder resist layer coupled to the second surface of the second substrate; the second surface of the second substrate faces the first substrate; the second solder resist layer includes a cavity; a second substrate comprising a second solder resist layer, the cavity being located between the first integrated device and the second solder resist layer; a plurality of inter-substrate interconnects coupled to the first substrate and the second substrate, Located between the first substrate and the second substrate, a plurality of inter-substrate interconnects configured to couple the first substrate to the second substrate; package.

2. The package of claim 1, wherein the plurality of inter-board interconnections include a plurality of ball interconnections and a plurality of solder interconnections.

3. The package of claim 1, wherein a plurality of ball interconnections and a plurality of solder interconnections are coupled to the second plurality of post interconnections of the second substrate, and the second plurality of post interconnections are laterally surrounded by the second solder resist layer.

4. The plurality of ball interconnections includes adjacent ball interconnections having a pitch of 270 micrometers or less; 10. The package of claim 1, wherein the plurality of ball interconnects comprises adjacent ball interconnects having a pitch in the range of approximately 200 to 270 micrometers.

5. 10. The package of claim 1, further comprising an encapsulation layer located between the first substrate and the second substrate, a portion of the encapsulation layer located between the second solder resist layer and the first integrated device, the encapsulation layer at least partially encapsulating the first integrated device, the plurality of ball interconnects, and the plurality of solder interconnects.

6. the second solder resist layer includes a first portion having a first thickness and a second portion having a second thickness; the first portion of the second solder resist layer having the first thickness greater than a thickness of the second plurality of post interconnects; the second portion of the second solder resist layer having a second thickness that is less than the thickness of the second plurality of post interconnects; the second portion of the second solder resist layer overlies the first integrated device; The package of claim 1.

7. 2. The package of claim 1, further comprising a second integrated device coupled to the first surface of the second substrate, wherein a vertical gap between the second solder resist layer of the second substrate and a back surface of the first integrated device is smaller than another vertical gap between the second solder resist layer of the second substrate and the first solder resist layer of the first substrate.

8. The package of claim 1, wherein the plurality of ball interconnects include copper core balls (CCBs).

9. the first plurality of interconnects includes a first plurality of post interconnects; the first substrate further comprising a first solder resist layer bonded to a first surface of the first substrate; The package of claim 1 , wherein the plurality of board-to-board interconnects comprises a plurality of solder interconnects.

10. 10. The package of claim 9, wherein the plurality of solder interconnects are coupled to (i) the first plurality of post interconnects of the first substrate and (ii) the second plurality of post interconnects of the second substrate, the first plurality of post interconnects being laterally surrounded by the first solder resist layer, and the second plurality of post interconnects being laterally surrounded by the second solder resist layer.

11. 10. The package of claim 9, wherein the plurality of solder interconnects comprises adjacent solder interconnects having a pitch of 270 micrometers or less, and wherein the plurality of solder interconnects comprises adjacent solder interconnects having a pitch in a range of approximately 150 to 270 micrometers.

12. an encapsulation layer located between the first substrate and the second substrate, a portion of the encapsulation layer located between the second solder resist layer and the first integrated device; The package of claim 9 , wherein the encapsulation layer at least partially encapsulates the first integrated device and the plurality of solder interconnects.

13. the second solder resist layer includes a first portion having a first thickness and a second portion having a second thickness; the first portion of the second solder resist layer having the first thickness greater than a thickness of the second plurality of post interconnects; the second portion of the second solder resist layer having a second thickness that is less than the thickness of the second plurality of post interconnects; the second portion of the second solder resist layer overlies the first integrated device; 10. The package of claim 9.

14. 10. The package of claim 9, further comprising a second integrated device coupled to the first surface of the second substrate, wherein a vertical gap between the second solder resist layer of the second substrate and a back surface of the first integrated device is smaller than another vertical gap between the second solder resist layer of the second substrate and the first solder resist layer of the first substrate.

15. providing a first substrate comprising at least one first dielectric layer and a first plurality of interconnects; coupling a first integrated device to the first substrate; and coupling the second substrate to the first substrate via a plurality of inter-substrate interconnects such that the plurality of inter-substrate interconnects are located between the first and second substrates, wherein the second substrate comprises: a first surface and a second surface; at least one second dielectric layer; a second plurality of interconnects, the second plurality of interconnects comprising a plurality of post interconnects; a solder resist layer coupled to the second surface of the second substrate; the solder resist layer includes a cavity; the cavity is located between the solder resist layer and the first integrated device; method.

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