Bias Source Control and Data Processing

Abstract

A bias supply and plasma processing system are disclosed. A bias supply includes an output node, a feedback node, and a switch network and at least one power supply coupled to the output node and the feedback node. The switch network and at least one power supply are configured in combination to apply an asymmetric periodic voltage waveform and provide a corresponding current waveform at the output node to the feedback node. A measurement component is configured to receive and sample voltage and current signals indicative of a full cycle of the periodic voltage waveform and the corresponding current waveform, and to provide a digital representation of a full cycle of the asymmetric periodic voltage waveform and the corresponding current waveform.

Description

[Technical field]

[0001] The present invention relates generally to power supplies, and more particularly to power supplies for applying voltages for plasma processing. [Background technology]

[0002] Many types of semiconductor devices are fabricated using plasma-based etching techniques. If it is a conductor to be etched, a negative voltage with respect to ground can be applied to the conductive substrate such that across the surface of the substrate conductor, a substantially uniform negative voltage is created that attracts positively charged ions toward the conductor, so that the positive ions that impact the conductor have substantially the same energy.

[0003] However, if the substrate is a dielectric, a constant voltage is ineffective for applying a voltage across the surface of the substrate. However, an alternating current (AC) voltage (e.g., high frequency AC or radio frequency (RF)) can be applied to a conductive plate (or chuck) such that the AC field induces a voltage on the surface of the substrate. During the negative portion of the applied waveform, the surface of the substrate becomes negatively charged, which causes ions to be attracted toward the negatively charged surface during the negative portion of the AC cycle. Also, when the ions collide with the surface of the substrate, the impact removes material from the surface of the substrate, resulting in etching.

[0004] In many cases, it is desirable to have a narrow (or specifically adjustable) ion energy distribution, but applying a sinusoidal waveform to a substrate induces a wide distribution of ion energy, which limits the ability of the plasma process to perform a desired etching profile. Known techniques for achieving a narrow (or specifically adjustable) ion energy distribution can be expensive, inefficient, difficult to control, and / or adversely affect plasma density. As a result, many of these known techniques have not been commercially adopted. Thus, systems and methods are needed to address the shortcomings of current technology and provide other new and innovative features. Summary of the Invention [Means for solving the problem]

[0005] The aspect may be characterized as a bias source for applying a periodic voltage. The bias source comprises a switch network and at least one power source configured in combination to apply an asymmetric periodic voltage waveform and provide a corresponding current waveform. The measurement component is configured to receive and sample voltage and current signals indicative of a full cycle of the periodic voltage waveform and the corresponding current waveform, and provide a digital representation of the full cycle of the asymmetric periodic voltage waveform and the corresponding current waveform. The data processing module is configured to receive the digital representation of the full cycle of the asymmetric periodic voltage waveform and the corresponding current waveform, and to produce a first readback value indicative of ion energy and a second readback value indicative of the ion energy distribution.

[0006] Yet another aspect may be characterized as a method for applying a periodic voltage including applying an asymmetric periodic voltage waveform and providing a corresponding current waveform. The method also includes receiving and sampling voltage and current signals indicative of a full cycle of the periodic voltage waveform and the corresponding current waveform, and providing a digital representation of the full cycle of the asymmetric periodic voltage waveform and the corresponding current waveform. The method also includes processing the digital representation of the full cycle of the asymmetric periodic voltage waveform and the corresponding current waveform to produce a first readback value indicative of an ion energy and a second readback value indicative of an ion energy distribution.

[0007] Another aspect disclosed herein may be characterized as a bias source for applying a periodic voltage. The bias source comprises means for applying an asymmetric periodic voltage waveform and providing a corresponding current waveform. The measurement component is configured to receive and sample a voltage signal and a current signal indicative of a full cycle of the periodic voltage waveform and the corresponding current waveform, and provide a digital representation of the full cycle of the asymmetric periodic voltage waveform and the corresponding current waveform. The bias source also comprises a processor and a non-volatile memory comprising non-transient processor-executable instructions for receiving the digital representation of the full cycle of the asymmetric periodic voltage waveform and the corresponding current waveform, and producing a first readback value indicative of an ion energy and a second readback value indicative of an ion energy distribution. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram depicting an exemplary plasma processing environment in which the bias sources disclosed herein may be utilized.

[0009] [Diagram 2] FIG. 2 is a schematic diagram depicting an exemplary bias supply.

[0010] [Diagram 3] FIG. 3 is a schematic diagram of a side electrical representation of a plasma processing chamber.

[0011] [Figure 4] FIG. 4 depicts graphs and timing diagrams illustrating aspects of a bias supply with two switches.

[0012] [Diagram 5] FIG. 5 illustrates graphs and timing diagrams illustrating aspects of a bias supply with a single switch.

[0013] [Figure 6] FIG. 6 is a block diagram depicting the sampling, readback, and control aspects of the bias supply.

[0014] [Figure 7] FIG. 7 is a schematic diagram depicting the inductance that affects the voltage applied to the plasma chamber relative to the bias supply.

[0015] [Figure 8A] FIG. 8A is a graph illustrating the effect of inductance depicted in FIG.

[0016] [Figure 8B] FIG. 8B is a graph illustrating the results of a method for compensating for the inductance depicted in FIG. 7 and mitigating against the effect depicted in FIG.

[0017] [Figure 9A] FIG. 9A illustrates an example of an asymmetric periodic voltage waveform.

[0018] [Figure 9B] FIG. 9B illustrates an example of an output current associated with the asymmetric periodic voltage waveform illustrated in FIG. 9B.

[0019] [Figure 9C] FIG. 9C depicts the wafer voltage, reconstructed from the voltage waveform of FIG. 9A and the current waveform of FIG. 9B, in accordance with the methods disclosed herein.

[0020] [Figure 10] FIG. 10 is a schematic diagram depicting an embodiment of a bias supply with two power supplies.

[0021] [Figure 11] FIG. 11 is a block diagram depicting a control system for a bias supply, such as the bias supply depicted in FIG. 10, with two power supplies.

[0022] [Figure 12] FIG. 12 includes graphs illustrating an example of an asymmetric periodic voltage waveform and corresponding sheath and wafer voltages consistent with a mode of operating the bias supply of FIG. 10 using the control system of FIG.

[0023] [Figure 13] FIG. 13 includes graphs depicting an example of an asymmetric periodic voltage waveform and corresponding sheath and wafer voltages consistent with another mode of operating the bias supply of FIG. 10 using the control system of FIG.

[0024] [Figure 14A] FIG. 14A is a schematic diagram illustrating an embodiment of the switch network depicted in FIG. 10 with two active switches.

[0025] [Figure 14B] FIG. 14B is a schematic diagram illustrating an embodiment of the switch network depicted in FIG. 10 with one active switch.

[0026] [Figure 15] FIG. 15 is a schematic diagram depicting yet another embodiment of a bias supply with a single power supply.

[0027] [Figure 16] FIG. 16 is a block diagram depicting a control system for a bias supply with a single power supply, such as the bias supply depicted in FIG.

[0028] [Figure 17] FIG. 17 includes graphs depicting examples of operational aspects of the bias supply depicted in FIG. 15 as controlled by the control system of FIG.

[0029] [Figure 18A] FIG. 18A is a schematic diagram illustrating an embodiment of the switch network depicted in FIG. 15 with a single active switch.

[0030] [Figure 18B] FIG. 18B is a schematic diagram depicting another embodiment of the switch network depicted in FIG. 15 comprising a single active switch.

[0031] [Figure 18C] FIG. 18C is a schematic diagram depicting yet another embodiment of the switch network depicted in FIG. 15 comprising a single active switch.

[0032] [Figure 19] FIG. 19 depicts graphs and timing diagrams illustrating aspects of a bias supply comprising the switch network depicted in FIG. 18C.

[0033] [Figure 20] FIG. 20 is a block diagram depicting components that may be utilized to implement the control aspects disclosed herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Detailed Description The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0035] Preliminary Note: The flowcharts and block diagrams in the following figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, some blocks in these flowcharts or block diagrams may represent modules, partitions, or portions of code, which comprise one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially in parallel, or the blocks may sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system, or a combination of special-purpose hardware and computer instructions, that performs the specified functions or actions.

[0036] For purposes of this disclosure, a source generator is one whose energy is primarily directed to generating and sustaining a plasma, while a "bias source" is one whose energy is primarily directed to generating a surface potential to attract ions and electrons from the plasma.

[0037] Described herein are control aspects of bias sources that may be used to apply a periodic voltage function to a substrate support in a plasma processing chamber. Referring initially to FIG. 1, shown is an exemplary plasma processing environment (e.g., a deposition or etching system) in which bias sources may be utilized. The plasma processing environment may include many pieces of equipment coupled directly and indirectly to a plasma processing chamber 101, a volume containing a plasma 102 and a workpiece 103 (e.g., a wafer) and an electrode 104 (which may be embedded in a substrate support). The equipment may include vacuum handling and gas delivery equipment (not shown), one or more bias sources 108, one or more source generators 112, and one or more source matching networks 113. In many applications, power from a single source generator 112 is connected to one or more source electrodes 105. The source generator 112 may be a higher frequency RF generator (e.g., 13.56 MHz to 120 MHz). Electrode 105 generally represents what may be implemented using an inductively coupled plasma (ICP) source, a dual frequency capacitively coupled plasma source (CCP) with a secondary upper electrode biased at another RF frequency, a helicon plasma source, a microwave plasma source, a magnetron, or other independently operated source of plasma energy.

[0038] In variations of the system depicted in FIG. 1, the source generator 112 and source matching network 113 may be replaced or augmented with a remote plasma source. Other variations of the system may also include only a single bias source 108. It should be appreciated that many other variations of the plasma processing environment depicted in FIG. 1 may be utilized. By way of example, and not limitation, U.S. Pat. No. 10,707,055, issued July 7, 2020, and U.S. Pat. No. 10,811,227, issued October 20, 2020, both of which are incorporated by reference in their entirety, disclose various types of system designs.

[0039] Also, while the following disclosure generally refers to plasma-based wafer processing, it should be appreciated that implementations can include any substrate processing in a plasma chamber. In some cases, objects other than substrates can also be processed using the systems, methods, and apparatus disclosed herein. In other words, the present disclosure also applies to plasma processing of any object in a sub-atmospheric pressure plasma processing chamber to affect surface changes, sub-surface changes, deposition, or removal by physical or chemical means.

[0040] 2, shown is an example bias supply 208 that may be utilized to implement the bias supply 108 described with reference to FIG. 1. The bias supply 208 generally represents many variations of bias supplies further described herein for applying a periodic voltage function. Thus, reference to the bias supply 208 generally refers to any of the bias supplies further described herein. As shown, the bias supply 208 includes an output 210 (also referred to as an output node 210), a feedback node 212, a switch network 220, an inductance 214 and a first power supply 216 (also referred to herein as a V supply Also shown is an optional second power supply 218 (referred to herein as V rail In general, bias source 208 functions to apply an asymmetric periodic voltage function between an output node 210 and a feedback node 212. Current delivered to the load through output node 210 is fed back to bias source 208 through feedback node 212, which may be common to the load.

[0041] 2, the bias supply 208 may include a controller that is coupled to the controller and / or that is coupled to the switch network 220. Variations of the switch network 220 (as well as variations with or without the second power supply 218) are also disclosed further herein, but first it is useful to understand the plasma load aspect.

[0042] 3, shown is a schematic diagram electrically depicting a side view of an exemplary plasma load within a plasma processing chamber 101. As shown, the plasma processing chamber 101 has an input 310 (also referred to as an input node 310) to the plasma processing chamber 101 and a sheath voltage V at the surface of a workpiece 103 (also referred to as a wafer substrate 103). s A node representing the chuck capacitance C Ch (including the capacitance of the chuck and the workpiece 103). As a result, the sheath voltage V s The reference to is also referred to herein as the voltage at the surface of the wafer or substrate. In addition, a feedback node 312 (which may be a connection to ground) is depicted. The plasma 102 in the processing chamber is coupled to the sheath capacitance C s , a diode, and a current source. The diode represents the nonlinear diode-like nature of the plasma sheath, which results in rectification of the applied AC field such that a direct current (DC) voltage drop appears between the workpiece 103 and the plasma 102.

[0043] 4 and 5, shown are timing diagrams associated with implementations of bias source 208 having two switches and one switch, respectively. In each of FIGS. 4 and 5, shown are asymmetric periodic voltage waveforms and corresponding current waveforms. As depicted, bias source 208 disclosed herein provides an asymmetric periodic voltage waveform V between output node 210 and feedback node 212. oAs shown, the asymmetric periodic voltage waveform V o has a first portion (times t0-t2) that starts from a first negative voltage and changes to a positive peak voltage during the first portion (at time t1), the asymmetric periodic voltage also changes from the first portion to a third voltage level (at time t3) during a second portion (times t2-t3), the asymmetric periodic voltage waveform including a voltage ramp between the third voltage level and a fourth negative voltage level (at time t4), and has a third portion (times t3-t4).

[0044] As shown in Figures 4 and 5, the asymmetric periodic voltage waveform has a voltage step V between times t2 and t3. step Equipped with V step is the ion at any energy level -E ion During the third portion of the asymmetric periodic voltage waveform, the sheath voltage corresponds to E ion +ΔE ion 4 and 5. Also, what is shown in FIG. 4 and 5 is that at time t reset (between times t0 and t3) and t ramp (between times t3 and t4). As shown, t reset covers the time including both the first and second portions of the asymmetric periodic voltage waveform, and t ramp Also shown in Figures 4 and 5 are examples of compensation currents, with reference to Figure 2. The compensation current I comp may be provided throughout the application of an asymmetric periodic voltage function, I out is the period during the third part of the asymmetric periodic voltage waveform (t ramp Between comp may or may not be equal to

[0045] As discussed further herein, the fundamental period (t0-t4) of the asymmetric periodic voltage waveform may be adjusted to adjust the spread of ion energies. As shown in Figures 4 and 5, a complete current cycle occurs between times t0 and t3 during the first and second portions of the asymmetric periodic voltage waveform. Also, the time between complete current cycles is the time t between t3 and t4. ramp Aspects of the present disclosure include a current I out Adjust the ion current I ion Another aspect of the present disclosure addresses the issue of methods for adjusting the level and distribution of ion energy in a plasma chamber.

[0046] In a variation of bias supply 208 with two switches, as shown in Figure 4, a first portion of the asymmetric periodic voltage waveform may transition to a second portion of the asymmetric periodic voltage waveform (between times t1 and t2), and in a variation of bias supply 208 with one switch, as shown in Figure 5, t1 may be equal to t2 and the first portion of the asymmetric periodic voltage waveform may end (and the second portion may start) at a positive peak voltage level.

[0047] Further details of both the single-switch and two-switch bias supplies are disclosed further herein, however, Figures 4 and 5 provide a basis for the variation control methodologies and various structural variations, which are disclosed further herein.

[0048] 4 shows the switching sequence of the first switch S1 and the second switch S2, the current I out , the voltage V at the output node 210 of the bias supply 208 out , sheath voltage V s (also shown in FIG. 3), and the corresponding ion energy distribution function (IEDF), depicted as ion flux versus ion energy.

[0049] As shown in FIG. 4, the first switch S1 and the second switch S2 are connected to each other to supply the output current I out may be controlled such that the output current I completes a full current cycle between times t0 and t3. During the start of the current cycle at t0, the output current I out But Level-I o From t1, the current is controlled to reach a positive peak current value, and then at t2, the current is controlled to reach a positive peak current value, o Then, at t2, the output current I out But at t3, -I o -I before decreasing back to o From -I, the current is controlled to increase in the opposite direction (opposite the positive peak current value) to a peak value. More specifically, during the positive portion of the current cycle (when the first switch S1 is closed and the second switch S2 is open), the current increases to a peak positive value and then decreases to -I o During the negative portion of the complete current cycle (time t2 to t3), the current increases to a negative peak value and then decreases to -I o decreases to.

[0050] As shown in FIG. 4, the first switch S1 and the second switch S2 may be controlled using an adjustable dead time, which is the time from t1 to t2 (after switch S1 is opened from a closed position and before switch S2 is closed).

[0051] As depicted in FIG. 4, controlling the dead time is reset Allows control of t reset vs. ramp Adjusting the ratio of t reset Control of the fundamental switching frequency allows the fundamental switching frequency to be controlled (eg, remain below a level that affects the plasma density within the plasma processing chamber 101).

[0052] Another aspect of control that can be achieved using the bias supply 208 disclosed herein is ion current compensation. More specifically, the length of the dead time, tramp The length of and / or the period (t0 to t4) of the periodic voltage function may be controlled to control the level of ionic current compensation. ramp , Dead Time, and / or Level I o is the ion current I ion I o =I ion -(CCh+Cstr1)*slope and I comp =I ion -(CCh+Cstr0+Cstr1)*slope (slope is the output voltage V out , where .gamma. is the slope of the gradient .gamma..times ...

[0053] As shown in Figure 4, when the ion current is overcompensated, the sheath voltage V s (and the voltage at the surface of the workpiece 103) between times t3 and t4 (t ramp t3 and t4). There is also a distribution of ion energies due to the range of sheath voltages between times t3 and t4. However, the ion current is proportional to the sheath voltage V s (and the voltage at the surface of the workpiece 103) between times t3 and t4 (t ramp It should be appreciated that the metric may be undercompensated so as not to be too negative during the time frame.

[0054] In addition, the sheath voltage V s is substantially constant between times t3 and t4. out It is also possible to adjust the slope of the beam, which results in a very narrow distribution of ion energies.

[0055] Dead time and t ramp By adjusting both the frequency of the periodic voltage waveform, t ramp , and the frequency of the periodic voltage waveform. rampIt is also contemplated that the time may be shortened while still being shortened or lengthened.

[0056] Referring to FIG. 5, shown are waveforms depicting the electrical aspects of the bias supply 208 and the plasma processing chamber 101 when the switch network 220 is implemented with a single switch. As shown in FIG. 5, the switch network provides an output current I out But -I o From the peak value, -I o and in the opposite direction, to the peak value, and then to -I o It should be appreciated that the peak value of the current in the first half of the current cycle may be different than the peak value of the current in the second half of the current cycle.

[0057] 6, shown is a block diagram depicting general aspects of measurement, readback, and control. Shown are bias supply 208, measurement component 620, and digital control section 622. In general, measurement component 620 receives and samples a signal indicative of a power-related parameter value and provides a digital representation of the power-related parameter value to digital control section 622. For example, the power-related parameter may be the current provided to output node 210 and the voltage V between output node 210 and feedback node 212. out Although not required, the feedback node may be a ground connection.

[0058] The measurement component 620 may receive and sample signals from one or more bias source signal lines 624. The bias source signal lines 624 may include the I comp The current signal line 626 may carry a signal indicative of bias supply parameters, such as temperature, temperature, and other parameters. The current signal line 626 may carry an output current I o , and voltage line 628 may provide an analog signal indicative of the voltage V at the output of the bias supply. outAn analog signal may be provided to indicate the power-related signal (I o and V out In response to receiving the asymmetric periodic voltage waveform V out , output current waveform i out and / or i comp A complete digital representation of the

[0059] An aspect of many variations of the measurement component 620 is that the complete voltage and current waveforms are captured, which provides improved visibility of the output of the bias supply and also enables improved control aspects as disclosed further herein.

[0060] Although not required, the metrology component 620 may be implemented in part by a field programmable gate array, and the digital control section may be implemented by one or more processors executing code stored in a non-transitory medium (to provide the functionality of the digital control section 622). However, other combinations of hardware, software, and firmware may be used to implement the metrology component 620 and the digital control section 622.

[0061] As shown, the asymmetric periodic voltage waveform V out , output current i out and / or i comp The digital representation of V may be provided to a data reporting component 631, which may be a user interface (e.g., a touch screen display). In addition, the asymmetric periodic voltage waveform V out , output current i out and / or i comp The digital representation of V is provided to a data processing module, which further calculates the asymmetric periodic voltage waveform V out , output current i out and / or i compand process the digital representation of the sheath voltage v s , and E ion , V step , ΔE ion , the output voltage slope (e.g., the slope of the third portion of the asymmetric periodic voltage waveform), and / or the slope deviation factor K s etc. may provide a readback of one or more other parameter values.

[0062] Slope deviation coefficient K s can be calculated as follows: [ka] In the formula, the slope w is the slope of the wafer / sheath voltage from t3 to t4.

[0063] Or alternatively, the slope deviation coefficient may be calculated to satisfy the following equation: [ka]

[0064] Slope deviation coefficient K s is the ion current I ion Compensation current I comp For example, K s When is equal to zero, the compensation current provides perfect compensation, and K s >0, then I comp overcompensates the ion current, and K s <0, the compensation current I comp is the ion current I comp Undercompensate.

[0065] As shown, the readback values ​​(e.g., depicted as Readback1 and Readback2) may also be used as part of the feedback control. As shown, a first comparator 638 may calculate the difference between a first set point, Setpoint1, and a first readback value, Readback1, to produce a first error signal, Error1. Also, a second comparator 640 may calculate the difference between a second set point, Setpoint2, and a second readback value, Readback2, to produce a second error signal, Error2. As shown, the error signals (Error1 and Error2) are fed to one or more compensators 632, which may provide control signals (Ctrl_knob1 and Ctrl_knob2) to the bias supply 208, as further described herein.

[0066] Also shown within the digital control section 622 is a timing parameter estimator 634, which determines the output waveform V out and the output current I out In one aspect, the timing parameter estimator 634 detects when there is zero current through the switches of the bias supply to reduce switching related losses. The timing parameter estimator 634 also receives a digital representation of t reset (shown in FIGS. 4 and 5) may be determined, and t reset The values ​​for t are reported via the data reporting component 631. reset The values ​​for may be provided to the data processing module 630.

[0067] The digital control section 622 also includes a gate drive signal generator 636 configured to provide gate drive signals to the switches (S1, S2) of the bias supply 208 in response to a pulse width control signal 637 from the timing parameter estimator 634 and / or in response to a control signal 639 output by the one or more compensators 632. While many types of switches are controlled by electrical gate drive signals, it is also contemplated that optical control signals may also be used. For example, the gate drive signal generator 636 may provide an optical signal.

[0068] Another aspect of the capabilities of the data processing module 630 is its ability to compensate for inductance between the output 210 of the bias supply 208 and the input 310 to the plasma chamber. With reference to FIG. 7, shown is a lumped element inductance 740 (also referred to as stray inductance 740) that represents the inductive element between the output 210 of the bias supply 208 and the input 310 to the plasma chamber. In many implementations, the digital representation of the asymmetric periodic voltage waveform (output by the measurement component 620) may be adjusted, for example, by the data processing module 630 to compensate for the stray inductance 740 (to obtain an adjusted digital representation of the asymmetric periodic voltage waveform). By compensating for the inductance 740, the V at the input 310 to the plasma chamber may be adjusted to 100 V at the input 310 to the plasma chamber. step can be calculated, a wafer voltage value can be calculated, and an ion energy value E ion can be calculated.

[0069] As shown in FIG. 8A, due to inductance 740, the voltage V out1 is the voltage V applied at the output node 210 of the bias supply 208. out As a result, the data processing module 630 can obtain the voltage V out1 may be configured to estimate [ka] In the formula, L stray is the inductance 740. In the presence of noise and parasitic ringing, V out and I out It should be noted that the signals may be filtered within the measurement component 620 and / or digitally filtered within the data processing module 630 before any calculations are performed.

[0070] As shown in FIG. 8B, the estimated voltage V out1 closely matches the actual voltage at the chamber input 310.

[0071] In addition, E ion can be calculated more accurately by taking into account the inductance. [ka]

[0072] The wafer voltage may also be more accurately reconstructed by compensating for the inductance 740. Referring to Figures 9A and 9B, shown are examples of output voltages and currents associated with operation of the bias supply 208. Figure 9C also shows a measurement of the actual wafer voltage compared to a reconstructed wafer voltage that is reconstructed using the data from Figures 9A and 9B.

[0073] For example, the reconstructed wafer voltage V w may be determined as follows: [ka] In the formula, C stray1 is the lumped element capacitance that represents the capacitance from the output of the bias source 208 to the input 310 of the chamber 101 (including the capacitance of the connector and the filter capacitance).

[0074] 9C also shows the closeness of the reconstructed wafer voltage to the actual measured wafer voltage. Note that in some implementations, a complete reconstruction of the wafer waveform can be obtained by capturing the entire current and voltage waveforms (as described with reference to FIG. 6).

[0075] 10 and 11, shown are examples of bias supply 208 (comprising two power supplies) and corresponding control systems, respectively. More specifically, FIG. 10 illustrates an embodiment of a bias supply 208 (comprising two power supplies) with a first power supply (V supply ) 216 and a second power supply (V rail supply 11 is a block diagram depicting an example of a control aspect that may be utilized in connection with a two-source configuration such as that depicted in FIG 10. The switch network 220 may comprise a variety of different topologies, including one or two switches, and as shown, the switch network 220 couples to the bias source 208 at node 1050 (coupled to the positive output of the second power supply 218), at node 212 (coupled to the negative output of the second power supply 218), and at output node 210.

[0076] As shown in FIG. 11, the control system includes two control “knobs”: supply and V rail This approach may be used to control the DC voltage of the compensation current i comp (to control the width of the distribution of ion energies), and V rail In contrast to previous approaches, where the first power supply 216 (V supply ) and the voltage of the second power supply (V rail ) may be controlled based on a general relationship: [ka]

[0077] In this control approach, the first set point is the ion energy set point, E ion_set and the second set point is the spread (also called distribution) of ion energies, Δ Eion_set (E ion_set and Δ Eion_set 4), and the data processing module 630 receives from the measurement component 620, out and V out Based on the digital representation of E ion and Δ Eion As shown, a first comparator 638 may calculate a first set point, E ion_set and E ion A second comparator 640 may generate a first error signal, Error1, based on the difference between the calculated value of Eion_set and Δ Eion A second error signal, Error 2, may be generated based on the difference between the calculated values ​​of

[0078] Alternatively, the first set point (to set the ion energy value) is V step The first set point may be a slope set point (to set the slope of the fourth portion (time between t3 and t4) of the asymmetric periodic voltage waveform), or the second set point may be a slope deviation factor set point (to set the slope deviation factor K s The data processing module 630 may be configured to set the i out and V out Based on the digital representation of V step and the slope or slope deviance coefficient K s In this alternative, the first comparator 638 may calculate a first set point (e.g., V step Set point) and V stepA second comparator 640 may generate a first error signal, Error1, based on the difference between a second set point (either a slope set point or a slope deviation factor set point) and the calculated value of the slope or the slope deviation factor K s A second error signal, Error 2, may be generated based on the difference between the calculated values ​​of

[0079] As shown, the control system may include two compensators associated with the two control loops: a first compensator 1132A and a second compensator 1132B. The first compensator 1132A also receives a first error signal, Error 1, and a signal V supply_set and may control the first power supply 216. The second compensator 1132B receives a second error signal, Error 2, and generates a signal V rail_set to control the second power supply 218. In some variations, the gate drive signal generator 636 may be set with a fixed switching time for the first switch of the bias supply 208 (and the second switch in the two-switch bias supply). In other variations, the timing parameter estimator 634 may provide a pulse width signal such that the gate drive signal generator 636 may close the switch of the bias supply 208 and provide zero current switching. Each of the compensators 1132A, 1132B may be realized by a proportional-integral-derivative (PID) controller, and in some variations, the bandwidth of the first compensator 1132A is set to be different from the bandwidth of the second compensator 1132B, which allows the two control loops associated with each of the compensators 1132A, 1132B to be decoupled. For example, the sampling rate of each control loop may be set to a different rate to result in different bandwidths. As another option, a single control loop associated with MIMO compensator 632, as generalized in FIG. 6, can be used with multiple inputs (generally shown as Error 1 and Error 2 in FIG. 6) and multiple outputs, where Ctrl_knob1 and Ctrl_knob2 in FIG. 6 are V supply_set and V rail_setmay be also possible.

[0080] 12 and 13, shown are examples of how the first power supply 216 and the second power supply 218 may be controlled. More specifically, in the graph shown in FIG. 12, the second power supply 218 (V rail ) is fixed at −2,000 V, and three examples of asymmetric periodic voltage waveforms are depicted when the first power supply 216 is set at 4,500 V, 5,000 V, and 5,500 V. Also shown are three wafer voltage V(w) waveforms corresponding to the three asymmetric periodic voltage waveforms.

[0081] In Fig. 13, shown are three example graphs where the voltage of the first power supply 216 is set at 5,500V and the voltage of the second power supply 218 is set at 300V, -200V, and -700V. Also shown are three wafer voltage V(w) waveforms corresponding to the three asymmetric periodic voltage waveforms. While Figs. 12 and 13 are provided merely as examples of the ability to provide desired ion energy values ​​and ion energy distributions using the first power supply 216 and the second power supply 218, it should be appreciated that in many variations, both the first power supply 216 and the second power supply 218 are variable power sources that can be adjusted and controlled using the control system depicted in Fig. 11.

[0082] 14A and 14B, shown are examples of switch networks that may be used in connection with the two-source configuration of FIG. 10. Referring first to FIG. 14A, switch network 1420A is a two-switch network that couples to bias source 208 at node 1050, feedback node 212, and output node 210. Also shown for reference within the switch network is node 1460. As depicted, switch network 1420A includes a first switch S1 arranged in series with a first diode D1 between node 1050 and node 1460. The cathode of diode D1 is coupled to node 1460, and the anode of diode D1 is coupled to switch S1. Switch network 1420A also includes a second switch S2 (arranged in series with a second diode D2) between feedback node 212 and node 1460. The anode of diode D2 is coupled to node 1460 and the cathode of diode D2 is coupled to switch S2. In addition, inductor L1 is positioned between node 1460 and output node 210.

[0083] In operation, the switches (S1 and S2) are configured to generate an asymmetric periodic waveform V depicted in FIG. 4, as described with reference to FIG. out and the output current I out It should be appreciated that because switch S1 and diode D1 are arranged in series, the order of switch S1 and diode D1 may be swapped. Similarly, because switch S2 and diode D2 are arranged in series, the order of switch S2 and diode D2 may be swapped.

[0084] In many implementations, the switches disclosed herein are realized by field effect switches such as metal oxide semiconductor field effect transistors (MOSFETs), and in some implementations, the switches are realized by silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) or gallium nitride metal oxide semiconductor field effect transistors (GaN MOSFETs). As another example, the switches may be realized by insulated gate bipolar transistors (IGBTs). In these implementations, the gate drive signal generator 636 may comprise an electrical driver known in the art configured to apply an electrical drive signal to the switch in response to a signal from the timing parameter estimator 634 and / or one or more compensators 632. It is also contemplated that the drive signal may be transmitted via an optical line to carry an optical switching signal. The switch may also switch in response to an optical signal and / or an optical signal that is converted to an electrical drive signal.

[0085] It should be appreciated that each of the switches depicted herein generally represents one or more switches that can be closed and opened, respectively, to connect and disconnect a current path. For example, each of the switches may be realized by multiple switches arranged in series (for improved voltage capability), multiple switches arranged in parallel (for improved current capability), or each of the switches may consist of multiple switches arranged in a series-parallel combination (for improved voltage and / or current capability). In these variations, one skilled in the art will appreciate that each switch may be driven by a corresponding drive signal in a synchronized manner.

[0086] It should also be appreciated that any of the diodes depicted herein may be implemented with multiple diodes. For example, any diode may be implemented with multiple series connected diodes (to improve voltage capability), with multiple diodes arranged in parallel (to improve current capability), or may consist of multiple diodes arranged in a series-parallel combination (for improved voltage and / or current capability).

[0087] 14B, shown is another embodiment of the switch network 220 depicted in FIGS. 2 and 10. As shown, the switch network 1420B comprises a first current path (for current iS1) between the node 1050 and the output node 210. The first current path comprises a series combination of a switch S1, a diode D1, and an inductor L1. In addition, the switch network 1420B comprises a second current path (for current iD2) (between the output node 210 and the feedback node 212), which comprises a second diode D2 and an inductive element L2.

[0088] In operation, switch S1 in switch network 1420B, as shown in FIG. 5, outputs the asymmetric periodic waveform V out and the output current I out It should be appreciated that the order in which switch S1, diode D1, and inductor L1 are positioned (between node 1050 and output node 210) may be swapped (because switch S1, diode D1, and inductor L1 are arranged in series).

[0089] 15 and 16, shown are a schematic (depicting the bias supply 208 with the first power supply 216 as a single power supply) and a block diagram, respectively, depicting a control system for the bias supply 208. As shown, the control system for the single source configuration is such that the second compensator 1132B controls the frequency setpoint signal F sw_setThe control system is similar to the control system for the two source configuration (described with reference to FIG. 11 ) except that the first power supply 216 provides a bias voltage to control the frequency of switching of the bias supply 208. As shown in FIG. 17 , the switching frequency is related to the voltage applied by the first power supply 216 to obtain the desired ion energy value E ion and the desired ion energy distribution ΔE ion may be used to provide

[0090] 18A, shown is a schematic diagram illustrating a switch network 1820A, which is an embodiment of the switch network 220, comprising two switches, a first switch S1 and a second switch S2. In the variation depicted in FIG. 18A, a series combination of a first switch S1 and a first diode D1 is arranged between a feedback node 212 of the bias supply 208 and a node 1862. In addition, a series combination of a second switch S2 and a second diode D2 is arranged between a node 1862 of the bias supply 208 and the feedback node 212. As shown in FIG. 18A, a first diode D1 is arranged between the first switch S1 and a node 1862, with its anode coupled to the first switch S1 and its cathode coupled to the node 1862. A second diode D2 is arranged between the second switch S2 and the node 1862, with its cathode coupled to the second switch S2 and its anode coupled to the node 1862. In this arrangement, the cathode of the first diode D1 is coupled to the anode of the second diode D2 at the node 1862.

[0091] In operation, the first diode D1 conducts when the first switch S1 is closed, and the second diode D2 conducts when the second switch D2 is closed. The first switch S1 and the second switch S2 also conduct an asymmetric periodic voltage waveform V out and the output current i out(shown in FIG. 4). Although not depicted, it should be appreciated that the position of the first switch S1 and the position of the first diode D1 may be interchanged. Similarly, the position of the second switch S2 and the position of the second diode D2 may be interchanged.

[0092] 18B, shown is a schematic diagram depicting switch network 1820B, which is another embodiment of switch network 220, comprising a single switch, namely S1. As shown, a first inductor L1 is coupled between node 1870 and output node 210. Switch S1 is also coupled between node 1870 and feedback node 212. A diode D1 is coupled in parallel with switch S1 between node 1870 and feedback node 212. In operation, switch S1 is opened and closed, and a periodic asymmetric voltage function V out and the output current I out For example, application of an asymmetric periodic voltage waveform closes switch S1, resulting in an output current I out -I o From the peak value, -I o After switch S1 is opened, the current increases in the opposite direction to a peak value, -I o To reduce losses, the timing parameter estimator 634 optionally estimates the output current i out I o Detects when the output current i out I o , the gate drive signal generator 636 may provide a signal to cause switch S1 to open.

[0093] 18C, shown is a schematic diagram depicting a switch network 1820C, which is another embodiment of the switch network 220, comprising a single switch: S1. As shown, the switch network 1820C comprises a first current path (for current iS1) between the feedback node 212 and a node 1872. The first current path comprises a series combination of a switch S1, a diode D1, and an inductor L1. In addition, the switch network 1820C comprises a second current path (for current iD2) (between the node 1872 and the feedback node 212), which comprises a second diode D2 and an inductive element L2. As shown, a cathode of the diode D2 is coupled to the feedback node 212, and a third inductor L3 is positioned between the node 1872 and the output node 210.

[0094] In operation, switch S1 in switch network 1820C generates an asymmetric periodic voltage waveform V between output node 210 and feedback node 212 from time t0 to time t4, as shown in FIG. out Also depicted in FIG. 19 is a sheath voltage V, which corresponds to an asymmetric periodic voltage. s As shown, the asymmetric periodic voltage waveform V out is a sheath voltage V, which is generally negative to attract ions to impinge on the surface of the workpiece and enable etching of the workpiece 103. s Achieve this.

[0095] When the switch S1 is closed at time t0, a current path (comprising the switch S1, the diode D1, and the inductor L1) connects the feedback node 212 to the node 1872, and the unidirectional current iS1 starts to increase from zero current at time t0, increasing the asymmetric periodic voltage V out(with respect to feedback node 212) begins to move (over the first portion 1951 of the periodic voltage waveform) from a first negative voltage 1952 to a positive peak voltage 1956. As shown, current iS1 increases to a peak value and then decreases to zero at time t1 when switch S1 is opened. As shown, iD2 increases in a ramp-like manner when switch S1 is closed such that current iD2 is non-zero when switch S1 is opened at time t1.

[0096] As depicted, the current iS1 through the first current path drops to zero and the asymmetric periodic voltage drops from a positive peak voltage 1956 when switch S1 is opened. Also, after switch S1 is opened (during the second portion 1953 of the asymmetric waveform), the unidirectional current iD2 increases to a peak through the second current path (through the second diode D2) and then drops to zero current flow at time t1-time t3. As shown, the increase and drop in the unidirectional current iD2 occurs while the asymmetric periodic voltage changes from the positive peak voltage 1956 to a third negative voltage level 1958 (during the second portion 1953). As depicted, between times t0-t3, the first portion 1951 of the asymmetric periodic voltage increases due to the sheath voltage V s 1950 to a positive voltage to repel positive charge (which accumulates on the surface of the work piece, while the surface of the work piece is held at a negative voltage), and the second portion 1953 of the asymmetric periodic voltage achieves the desired ion energy value 1960. To achieve the ion flux, the sheath voltage V s to the desired negative voltage (or range of voltages).

[0097] As depicted, the unidirectional current iD2 rises and then falls back to the zero current level, after which the asymmetric periodic voltage V out becomes more negative (as a negative voltage ramp) during a fourth portion 1961 until switch S1 is closed again at time t4. As depicted, the compensation current I comp may be provided during the cycles of the asymmetric periodic voltage to compensate the ion current in the plasma chamber 101. For example, a compensation current Icomp If not, the sheath voltage V s may gradually change and become more positive during the fourth portion of the asymmetric periodic voltage, which would produce a wider distribution of ion energies, which may not be desirable. However, in some variations, the compensation current I comp may be set to intentionally over- or under-compensate the ion current in the plasma chamber 101 to produce a wider distribution of ion energies. In the mode of operation depicted in FIG. comp is the asymmetric periodic voltage V o During the fourth portion 661 of the s to provide.

[0098] It should be appreciated that the order in which switch S1, diode D1, and inductor L1 are positioned (between feedback node 212 and node 1872) may be changed (because switch S1, diode D1, and inductor L1 are arranged in series). In addition, the order in which L2 and D2 are arranged may be swapped.

[0099] To maintain a narrow ion energy distribution (IED) width, the switching frequency is increased at higher ion currents and lower ion energies. Note that changing the switching frequency also affects the ion energy (eV) level, requiring adjustment of the first power supply 216 to keep constant ion energy. The multiple-input multiple-output (MIMO) control system shown in FIG. 6 can still be implemented in this system configuration, with the control variables being: [ka] wherein the two control knobs are [ka] Alternatively, two separate single-input single-output (SISO) control loops can be implemented, as shown in FIG. ionThe first power supply source controls only the E ion The two control loops may be separated by having different bandwidths. This can be achieved by appropriately adjusting the PID compensator coefficients or by setting the sampling rates of the two control loops differently. The latter option reduces the computational effort in the digital control system.

[0100] 6, 11, and 16, shown are block diagrams depicting aspects of sampling, readback, and control methods for bias supply 208. Aspects of these methods are achieved by using an asymmetric periodic voltage waveform V out (at output node 210, to feedback node 212) and the corresponding output current waveform I out and providing a digital representation of the asymmetric periodic voltage waveform and the corresponding current waveform. Voltage and current signals indicative of the periodic voltage waveform and the corresponding current waveform are received and sampled (e.g., by the measurement component 620) to provide a digital representation of the asymmetric periodic voltage waveform and the corresponding current waveform. The digital representation of the asymmetric periodic voltage waveform and the corresponding current waveform are processed (e.g., by the data processing module 630) to produce a first readback value indicative of the ion energy and a second readback value indicative of the ion energy distribution. Depending on the implementation, as described above, the data processing module 630 may provide parameter values ​​that are utilized in one or more control loops to control desired attributes of the asymmetric periodic voltage waveform, the output current, the ion energy, and the ion energy distribution, for example, but not limited to, the asymmetric periodic voltage waveform, the output current, the ion energy, and the ion energy distribution.

[0101] The methods and other variations of the methods described herein may be embodied directly in hardware, in processor executable code encoded in a non-transitory tangible processor-readable storage medium, or in a combination of the two. With reference to FIG. 20, for example, what is shown is a block diagram depicting physical components that may be utilized to realize the control aspects disclosed herein. As shown, in this embodiment, a display 1312 and a non-volatile memory 1320 are coupled to a bus 1322, which is also coupled to a random access memory ("RAM") 1324, a processing portion (including N processing components) 1326, a field programmable gate array (FPGA) 1327, and a transceiver component 1328, including N transceivers. Although the components depicted in FIG. 20 represent physical components, FIG. 20 is not intended to be a detailed hardware diagram, and thus many of the components depicted in FIG. 20 may be realized by a general structure or distributed among additional physical components. Additionally, it is contemplated that other existing and yet to be developed physical components and architectures may also be utilized to implement the functional components described with reference to FIG.

[0102] The display 1312 generally operates to provide a user interface for a user, and in some implementations the display is realized by a touch screen display. In general, the non-volatile memory 1320 is a non-transient memory that functions to store (e.g., persistently store) data and processor executable code (including executable code associated with steps that effect the methods described herein). In some embodiments, for example, the non-volatile memory 1320 includes boot loader code, operating system code, file system code, and non-transient processor executable code to facilitate execution of the methods of biasing a substrate using a bias source 208 described herein.

[0103] In many implementations, the non-volatile memory 1320 is realized by a flash memory (e.g., NAND or ONENAND memory), although it is contemplated that other memory types may be utilized as well. While it may be possible to execute code from the non-volatile memory 1320, executable code in the non-volatile memory is typically loaded into RAM 1324 and executed by one or more of the N processing components in the processing portion 1326.

[0104] The N processing components, in association with the RAM 1324, generally operate to execute instructions stored in the non-volatile memory 1320 to enable execution of the algorithms and functions disclosed herein. It should be appreciated that while several algorithms are disclosed herein, some of these algorithms are not represented in the flow charts. Processor executable code for effecting the methods described herein may be stored persistently in the non-volatile memory 1320 and executed by the N processing components associated with the RAM 1324. As one skilled in the art would appreciate, the processing portion 1326 may include a video processor, a digital signal processor (DSP), a microcontroller, a graphics processing unit (GPU), or other hardware processing components or a combination of hardware and software processing components (e.g., an FPGA or FPGAs including digital logic processing portions).

[0105] Additionally or alternatively, non-transient FPGA configuration instructions may be persistently stored in non-volatile memory 1320 and accessed (e.g., during boot-up) to configure a field programmable gate array (FPGA) to implement the algorithms disclosed herein.

[0106] The input components 1330 include a power-related signal (e.g., an output current I out and voltage V out Although not required, in some implementations, the FPGA 1327 may sample the power-related signal and receive the output current I out and the output voltage V out In some embodiments, the processing component 1326 (in conjunction with the processor executable instructions stored in the non-volatile memory 1320) is used to implement the data processing modules, comparators, and compensators disclosed herein. Additionally, the input component 1330 may receive phase information and / or synchronization signals between the bias source 108 and the source generator 112 indicative of one or more aspects of the environment in the plasma processing chamber 101 and / or the synchronized control between the source generator and the single switch bias supply. The signals received at the input component may include, for example, from synchronization signals, power control signals for various generators and power supply units, or control signals from a user interface. Those skilled in the art will readily appreciate that any of a variety of types of sensors, such as, but not limited to, directional couplers and voltage-current (VI) sensors, may be used to sample power parameters such as voltage and current, and signals indicative of the power parameters may be generated in the analog domain and converted to the digital domain.

[0107] The output components generally operate to provide one or more analog or digital signals to provide gate drive signals for opening and closing the switches. The output components may also control the power supplies described herein.

[0108] The depicted transceiver component 1328 includes N transceiver chains that may be used to communicate with external devices over wireless or wired networks. Each of the N transceiver chains may represent a transceiver associated with a particular communication scheme (e.g., Wifi, Ethernet, Profibus, etc.).

[0109] As will be appreciated by those skilled in the art, aspects of the present disclosure may be embodied as a system, method, or computer program product. Thus, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may all generally be referred to herein as a "circuit," "module," or "system." Additionally, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

[0110] As used herein, the recitation of "at least one of A, B, and C" or "at least one of A, B, or C" is intended to mean "any of A, B, C, or any combination of A, B, and C." The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bias supply for applying a periodic voltage, comprising: An output node; A feedback node; a switch network and at least one power supply coupled to the output node and the feedback node, the switch network and the at least one power supply configured in combination to apply an asymmetric periodic voltage waveform and provide a corresponding current waveform at the output node to the feedback node, each cycle of the asymmetric periodic voltage waveform including a first portion starting from a first negative voltage and changing to a positive peak voltage during a first portion, the asymmetric periodic voltage also changing from the first portion to a third voltage level during a second portion, the asymmetric periodic voltage waveform including a third portion including a voltage ramp between the third voltage level and a fourth voltage level; a measurement component configured to receive and sample voltage and current signals indicative of a full cycle of the periodic voltage waveform and the corresponding current waveform, and to provide a digital representation of a full cycle of the asymmetric periodic voltage waveform and a full cycle of the corresponding current waveform; a data processing module configured to receive a digital representation of a complete cycle of the asymmetric periodic voltage waveform and a complete cycle of the corresponding current waveform and to produce a first readback value indicative of ion energy and a second readback value indicative of an ion energy distribution; A bias supply source comprising:

2. 2. The bias supply of claim 1, wherein the first portion transitions into the second portion or the first portion ends and the second portion starts from the positive peak voltage.

3. The first readback value is the ion energy or voltage step V between the peak positive voltage level and the third voltage level. ｓｔｅｐ 10. The bias supply of claim 1, comprising one of:

4. The bias supply of claim 1 , wherein the second readback value comprises one of a deviation factor or a slope of the voltage ramp indicative of an ion energy distribution.

5. 2. The bias supply of claim 1, wherein the data processing module is configured to obtain an ion energy value using an adjusted digital representation of the asymmetric periodic voltage waveform adjusted to compensate for inductance between the output node and a chuck coupled to the output node.

6. The data processing module reduces the V at a chamber input by compensating for an inductance between the output node and a chuck coupled to the output node. ｓｔｅｐ The bias source of claim 1 configured to obtain a calculation of:

7. 2. The bias supply of claim 1, wherein the data processing module is configured to obtain a wafer voltage value using an adjusted digital representation of the asymmetric periodic voltage waveform adjusted to compensate for inductance.

8. Two power sources; two control loops, a first of the two control loops using the first readback value to control a first of the two power supplies, and a second of the two control loops using the second readback value to control a second of the two power supplies; The bias supply of claim 1 , comprising:

9. 9. The bias supply of claim 8, wherein the two control loops are separated by a difference in the bandwidth of each of the control loops.

10. Two power sources; a single control loop with two inputs comprising a first readback value and said second readback value; The bias supply of claim 1 , comprising:

11. A single power supply; two control loops, a first of the two control loops controlling a voltage of the single power supply and a second of the two control loops controlling a time of the voltage ramp; The bias supply of claim 1 , comprising:

12. 12. The bias supply of claim 11, wherein the two control loops are separated by a difference in the bandwidth of each of the control loops.

13. A single power supply; a single control loop for controlling the voltage of said single power supply and the time of said voltage ramp; The bias supply of claim 1 , comprising:

14. 1. A method for applying a periodic voltage, comprising: applying an asymmetric periodic voltage waveform to a feedback node at an output node and providing a corresponding current waveform, each cycle of the asymmetric periodic voltage waveform including a first portion starting from a first negative voltage and changing to a positive peak voltage during a first portion, the asymmetric periodic voltage also changing from the positive peak voltage to a third voltage level during a second portion, the asymmetric periodic voltage waveform comprising a third portion including a voltage ramp between the third voltage level and a fourth voltage level; receiving and sampling voltage and current signals indicative of a full cycle of the periodic voltage waveform and the corresponding current waveform to provide a digital representation of a full cycle of the asymmetric periodic voltage waveform and a full cycle of the corresponding current waveform; processing a digital representation of a complete cycle of the asymmetric periodic voltage waveform and a complete cycle of the corresponding current waveform to produce a first readback value indicative of ion energy and a second readback value indicative of an ion energy distribution; A method comprising:

15. 15. The method of claim 14, wherein the first portion transitions into the second portion or the first portion ends and the second portion begins from the positive peak voltage.

16. Processing a digital representation of a complete cycle of the asymmetric periodic voltage waveform and a complete cycle of the corresponding current waveform includes processing and determining an ion energy or voltage step V between the positive peak voltage level and the third voltage level. ｓｔｅｐ 15. The method of claim 14, comprising generating the first readback value comprising one of:

17. 15. The method of claim 14, wherein processing the digital representations of a complete cycle of the asymmetric periodic voltage waveform and a complete cycle of the corresponding current waveform comprises processing to produce the second readback value comprising one of a deviation coefficient or a slope of the voltage ramp indicative of an ion energy distribution.

18. 15. The method of claim 14, comprising obtaining an ion energy value using an adjusted digital representation of the asymmetric periodic voltage waveform adjusted to compensate for inductance between the output node and a chuck coupled to the output node.

19. By compensating for the inductance between the output node and a chuck coupled to the output node, V at the chamber input ｓｔｅｐ The method of claim 14, comprising calculating:

20. 15. The method of claim 14, comprising obtaining a wafer voltage value using an adjusted digital representation of the asymmetric periodic voltage waveform that is adjusted to compensate for stray inductance.

21. operating two control loops, a first of the two control loops using the first readback value to control a first of the two power supplies, and a second of the two control loops using the second readback value to control a second of the two power supplies; 15. The method of claim 14, comprising:

22. 22. The method of claim 21, wherein the two control loops are separated by a difference in the bandwidth of each of the control loops.

23. 15. The method of claim 14, comprising operating a single control loop with two inputs comprising a first readback value and the second readback value.

24. operating two control loops, a first of the two control loops controlling a voltage of a single power supply source and a second of the two control loops controlling a time of the voltage ramp; 15. The method of claim 14, comprising:

25. 25. The method of claim 24, comprising isolating the two control loops by operating them at different bandwidths.

26. 15. The method of claim 14, comprising operating a single control loop that controls the voltage of a single power supply and the time of the voltage ramp.

27. A bias supply for applying a periodic voltage, comprising: An output node; A feedback node; means for applying an asymmetric periodic voltage waveform to the feedback node and providing a corresponding current waveform at the output node, each cycle of the asymmetric periodic voltage waveform including a first portion starting from a first negative voltage and changing to a positive peak voltage during a first portion, the asymmetric periodic voltage also changing from the positive peak voltage to a third voltage level during a second portion, the asymmetric periodic voltage waveform comprising a third portion including a voltage ramp between the third voltage level and a fourth voltage level; a measurement component configured to receive and sample voltage and current signals indicative of a full cycle of the periodic voltage waveform and the corresponding current waveform, and to provide a digital representation of a full cycle of the asymmetric periodic voltage waveform and a full cycle of the corresponding current waveform; A processor and a non-volatile memory, the non-volatile memory comprising non-transient processor-executable instructions, the instructions comprising: receiving a digital representation of a complete cycle of the asymmetric periodic voltage waveform and a complete cycle of the corresponding current waveform; producing a first readback value indicative of an ion energy and a second readback value indicative of an ion energy distribution; a processor and non-volatile memory having instructions for performing A bias supply source comprising:

28. 28. The bias supply of claim 27, wherein the first portion transitions into the second portion or the first portion ends and the second portion begins from the positive peak voltage.

29. The first readback value is the ion energy or voltage step V between the peak positive voltage level and the third voltage level. ｓｔｅｐ 30. The bias supply of claim 27, comprising one of:

30. 28. The bias supply of claim 27, wherein the second readback value comprises one of a deviation factor or a slope of the voltage ramp indicative of an ion energy distribution.

31. 28. The bias supply of claim 27, wherein the instructions comprise instructions for obtaining an ion energy value using an adjusted digital representation of the asymmetric periodic voltage waveform adjusted to compensate for inductance between the output node and a chuck coupled to the output node.

32. The command reduces V by compensating for inductance between the output node at the chamber input and a chuck coupled to the output node. ｓｔｅｐ 30. The bias supply of claim 27 comprising instructions for obtaining a calculation of:

33. 30. The bias supply of claim 27, wherein the instructions comprise instructions for obtaining a wafer voltage value using an adjusted digital representation of the asymmetric periodic voltage waveform that is adjusted to compensate for stray inductance.

34. The means for applying comprises two power supplies; the instructions comprise instructions for creating two control loops, a first of the two control loops using the first readback value to control a first of the two power supplies, and a second of the two control loops using the second readback value to control a second of the two power supplies.

28. The bias supply of claim 27.

35. 35. The bias supply of claim 34 comprising instructions for isolating the control loops by a difference in their respective bandwidths.

36. The means for applying comprises two power supplies; the instructions comprise instructions for creating a single control loop with two inputs comprising a first readback value and the second readback value; 28. The bias supply of claim 27.

37. the means for applying comprises a single power supply; the instructions comprising instructions for creating two control loops, a first of the two control loops controlling a voltage of the single power supply and a second of the two control loops controlling a time of the voltage ramp.

28. The bias supply of claim 27.

38. 38. The bias supply of claim 37, wherein the instructions comprise instructions for isolating the control loops by a difference in their respective bandwidths.

39. A single power supply; a single control loop for controlling the voltage of said single power supply and the time of said voltage ramp; 28. The bias supply of claim 27 comprising:

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