Electronic bias control signals for electron-assisted materials processing

Abstract

A system and method are presented for material processing using precisely controlled wafer-scale waves of electrons in a DC plasma. The surface floating potential of a substrate placed on a stage in the positive column of the DC plasma is adjusted and maintained at a reference potential. A periodic bias signal referenced to the reference potential is capacitively coupled to the stage to control the surface potential of the substrate according to an activation phase that provides kinetic energy to free electrons in the DC plasma to activate target bonds on the substrate surface, a neutralization phase that repels the free electrons from the substrate surface, and an initialization phase that restores the initial state of the surface floating potential.

Description

[Technical field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. Application No. 17 / 668,301, filed February 9, 2022, and entitled "Electron Bias Control Signals for Electron Enhanced Material Processing," the contents of which are incorporated herein by reference. Additionally, this application claims priority to U.S. Application No. 17,524,330, filed November 11, 2021, and entitled "DC Plasma Control for Electron Enhanced Material Processing" (Attorney Docket No. P2641-US), the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates generally to systems and methods for controlling free electrons in a DC plasma reaction chamber used for materials processing, and more particularly to generating a waveform for a bias signal to control the kinetic energy of the free electrons to generate wafer-scale waves of precisely controlled electrons in a DC plasma at room temperature (or other temperatures, if desired). [Background technology]

[0003] For example, the manufacture of integrated circuits involves processing corresponding substrates in a direct current plasma reaction chamber, where electrons and / or ions are accelerated towards the substrate surface to initiate reactions that physically change the substrate surface. In some cases, and primarily due to the relatively small mass of electrons compared to ions, substrate processing via electrons may be preferred to reduce damage to the substrate surface beyond the targeted physical changes expected by the processing step itself.

[0004] In some cases, plasma processing may involve placing a substrate in a region of a direct current plasma reaction chamber such that the exact value of the substrate's surface floating potential is not known. Thus, a bias signal externally applied to the substrate may impart a free electron energy in a region of the plasma close to the surface of the substrate that does not correlate with the electron energy threshold / level of the (atomic) material present at the surface of the substrate.

[0005] The above-referenced U.S. Application Serial No. 17,524,330, the entire disclosure of which is incorporated herein by reference, describes a method and system for precisely and selectively controlling the value of the surface floating potential of a substrate, and thus allowing precise and selective control of the energy levels of atoms at the surface of the substrate. The teachings of the present disclosure utilize such precise and selective control of the atomic energy levels at the substrate surface to generate waveforms whose timing and amplitude correspond to signals used to bias free electrons in a DC plasma chamber to generate wafer-scale waves that specifically target the atomic energy levels at the substrate surface. Summary of the Invention

[0006] Systems and methods are disclosed for material processing using precisely controlled wafer-scale waves of electrons in a DC plasma at room temperature (or other temperatures as desired). In this disclosure, such material processing, in which the kinetic energy of free electrons in the DC plasma can be precisely controlled to precisely (and selectively) target the electron energy levels of atoms at the surface of the substrate being processed, is referred to as electron enhanced material processing (EEMP).

[0007] According to a first embodiment of the present disclosure, a direct-current (DC) plasma system for substrate processing is disclosed, comprising: a DC plasma reaction chamber configured to contain a DC plasma generated between an anode and a cathode of the DC plasma reaction chamber; a substrate support stage disposed in a region of the DC plasma reaction chamber containing a positive column of the DC plasma; a means for presetting a floating potential at a surface of the substrate support stage to a reference potential; and a bias signal generator capacitively coupled to the substrate support stage, the bias signal generator configured to generate a periodic bias signal having a voltage referenced to the reference potential, the periodic bias signal including an activation phase having a positive voltage, a neutralization phase having a negative voltage, and an initialization phase having a zero voltage.

[0008] According to a second embodiment of the present disclosure, a method for treating a surface of a substrate is disclosed, the method comprising the steps of: placing a substrate on a support stage in a region of a direct current plasma reaction chamber configured to generate a positive column of direct current plasma; generating a direct current plasma; presetting a floating potential of the substrate surface to a reference potential; and capacitively coupling a periodic bias signal having a bias voltage referenced to the floating potential to the support stage, the periodic bias signal including an activation phase having a positive voltage based on a known reaction threshold voltage of a target chemical bond involving an electron of an atom of the substrate surface, a neutralization phase having a negative voltage, and an initialization phase having a zero voltage.

[0009] Further aspects of the present disclosure are set forth in the specification, drawings and claims of this application. [Brief description of the drawings]

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of the exemplary embodiments, serve to explain the principles and embodiments of the disclosure. [Figure 1A] 1 is a simplified schematic diagram of a DC plasma reaction chamber that can be used in a DC plasma processing system. [Figure 1B] 1B is a graph showing the change in the (electrical) potential of the plasma during operation of the DC plasma reaction chamber of FIG. 1A. [Figure 1C] 1B shows a simplified schematic diagram of a DC plasma processing system including a (substrate) stage positioned in the region of the DC plasma reaction chamber of FIG. 1A. [Figure 1D] 1D illustrates an exemplary biasing of a stage of the DC plasma processing system of FIG. 1C via an external bias signal generator. [Figure 1E] 1D shows an exemplary bias signal generated by the external bias signal generator of FIG. 1D and the corresponding potential generated at the stage surface. [Figure 1F] 3 shows exemplary energy levels of atoms at the surface of the stage. [Figure 2A] 1 shows a simplified schematic diagram of a DC plasma processing system according to one embodiment of the present disclosure, including a means for controlling a surface potential of a stage. [Figure 2B] 2B is a graph showing control of a surface potential of a stage of the DC plasma processing apparatus of FIG. 2A. [Figure 2C] 2B is a graph illustrating adjustment of a surface potential of a stage relative to a reference ground potential of the DC plasma processing system of FIG. 2A. [Figure 3A] 1 shows a simplified schematic diagram of a DC plasma processing system according to one embodiment of the present disclosure, comprising a means for controlling a surface potential of a stage and a means for measuring the surface potential. [Figure 3B] FIG. 3B shows a simplified schematic diagram of a DC plasma processing system according to an embodiment of the present disclosure, based on the system of FIG. 3A with the addition of means for automatic control of the surface potential. [Figure 4A] FIG. 3C is a simplified schematic diagram of a DC plasma processing system according to an embodiment of the present disclosure based on the system of FIG. 3B with the addition of stage biasing means. [Figure 4B] 4B illustrates exemplary bias signals supplied to a stage of the DC plasma processing system of FIG. 4A and the corresponding potentials developed at the surface of the stage. [Figure 4C]3 shows exemplary energy levels of atoms at the surface of the stage. [Diagram 5] 2 is a process chart illustrating various steps of a method according to one embodiment of the present disclosure for treating a surface of a substrate. [Figure 6] 6A-C are graphs showing the reaction rates of electron-enhanced material processing (EEMP) for different materials according to the present disclosure. [Figure 7] 6A-C are graphs depicting waveforms of EEMP bias signals for processing different materials, according to some exemplary embodiments of the present disclosure. [Figure 8A] 1 is a graph illustrating an idealized waveform of an EEMP bias signal. [Figure 8B] 1 is a graph showing a practical waveform of an EEMP bias signal. [Figure 8C] 1 is a graph showing an analog waveform under a capacitive load condition. [Figure 9A] 8C is a graph showing a digitized waveform for producing the practical waveform of FIG. 8B and a corresponding digitized waveform with predistortion. [Figure 9B] 9B is a graph illustrating an analog waveform generated from the predistorted digitized waveform of FIG. 9A under capacitive loading conditions. [Figure 10A] 4 is a graph illustrating gain versus frequency for a band-limited linear power amplifier according to an embodiment of the present disclosure and for a conventional power amplifier; [Figure 10B] 10B is a graph illustrating an analog waveform generated from the predistorted digitized waveform of FIG. 9A through the band-limited linear power amplifier of FIG. 10A under capacitive load conditions. [Figure 11] 4 is a process chart illustrating various steps of a method for treating a surface of a substrate according to another embodiment of the present disclosure.

[0011] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] FIG. 1A shows a simplified schematic diagram of a prior art DC plasma reaction chamber (110) that may be used in a DC plasma processing system. The bias of the DC plasma reaction chamber (110) may be provided by a DC voltage source (150) coupled between an anode A and a cathode C of the DC plasma reaction chamber (110). During operation, a glow discharge (plasma) may be formed in the chamber (110) based on the interaction of the gas with electrons of the current flowing between the anode A and the cathode C. This generates free ions and free electrons in the chamber. The operating principle of such a DC plasma reaction chamber (110) is well known to those skilled in the art, and therefore the relevant details will be omitted in this disclosure.

[0013] 1A, the glow discharge formed in the chamber (110) may include glow regions (G1, G2, G3, G4) that emit significant light and dark regions (D1, D2, D3, D4) that may not emit light. Such regions may represent different operating characteristics of the DC plasma reaction chamber (110), including, for example, temperature and electrical potential.

[0014] FIG. 1B illustrates the plasma (electrical) potential V along the axial (longitudinal) direction X of the chamber (110) during operation. PP As shown in FIG. 1B, the plasma potential V PP is the value V representing the potential applied to the cathode C by the DC voltage source (150 in FIG. 1A). C , the value V represents the potential applied to the anode A by the DC voltage source (150 in FIG. 1A). A For example, as shown in FIG. 1D below, the value V A is zero volts (e.g., reference ground), and the value V C It should be noted that is negative (eg, negative for values ​​in the range of about 0 (zero) to 500 volts).

[0015] Continuing to refer to FIG. 1B, the potential V in the regions (e.g., D1, G1, D2) close to the cathode C and the region (e.g., G4) close to the anode A isPP The rapid fluctuations in may correspond to regions of higher operating temperature in the chamber (110). The other region G3, also called the positive column, has a fairly uniform / constant potential, V PP For example, as shown in FIG. 1B, the region along the axis X of the chamber (110) is a region of low operating temperature [X G31 , X G32 Considering that the positive column region G3 includes the segment [X G31 , X G32 ] across the plasma potential V PP The variation of is minimal, in other words, the segment [X G31 , X G32 ] potential V PP can be considered to be constant. Therefore, as shown in Figure 1B, the segment [X G31 , X G32 ] plasma potential V pp is the value V G3 The lower operating temperature and constant potential value of the plasma in the positive column region G3 allows such region to be used for substrate processing, as shown in Figures 1C and 1D.

[0016] FIG. 1C shows a simplified schematic diagram of a DC plasma processing system (100C) including a (substrate) stage S located in the positive column region G3 of the DC plasma reaction chamber (110). The stage S may be designed to support a flat substrate and therefore may include a top flat / planar surface. The stage S shown in FIG. 1C is electrically isolated (not connected to an external potential) and therefore is not connected to the plasma potential V, as is well known to those skilled in the art. PP In the presence of S is generated, and the potential V S is the surface floating potential V FP This is called the (surface) floating potential V FP and the plasma potential V PP The relationship between the area [X G31 , X G32] at the plasma potential V PP is V G3 and the floating potential V FP is the plasma potential V G3 (plasma potential V G3 is negative with respect to

[0017] The floating potential V shown in the graph of FIG. FP can be attributed to a "plasma sheath" that develops in the presence of stage S. As known to those skilled in the art, any wall or barrier in the plasma will develop a negative potential with respect to the bulk of the plasma. As a result, an equilibrium potential drop occurs between the bulk of the plasma and the wall or barrier. Such a potential drop is confined to a small region of space adjacent to the wall or barrier due to a charge imbalance that develops between the plasma and the wall or barrier. This layer of charge imbalance has a finite thickness, characterized by the Debye Length, and is called the "plasma sheath" or "sheath." Such a layer is a few Debye lengths thick, a value that depends on various properties of the plasma. When the dimensions of the bulk plasma (e.g., chamber 110) are, for example, much larger than the Debye length, the Debye length depends on the plasma temperature and electron density. For certain DC plasma operating conditions supported by the teachings of the present disclosure (e.g., EEMP systems near to and moderately above room temperature), the Debye length is on the order of a few millimeters (e.g., less than 10 millimeters), and the potential V G3 and V FP , is on the order of a few volts (e.g., less than 10 volts). It should be noted that the plasma sheath can occur in the presence of any wall or barrier, whether conductive or not. Thus, once a substrate (whether conductive or insulating) is positioned on the stage S, it is exposed to the same floating potential V as described above with reference to FIG. 1C. FP may occur on the surface of the substrate.

[0018] FIG. 1D illustrates an example biasing of stage S of the DC plasma processing system of FIG. 1C via an external bias signal generator (180) that is capacitively coupled to stage S by a capacitor C. In the example configuration (100D) shown in FIG. 1D, a potential V A is zero volts (e.g., tied to a reference ground, Gnd). Additionally, as shown in FIG. 1D, a bias signal V applied to stage S by an external bias signal generator (180) B can be referenced to a reference ground potential Gnd. In some prior art implementations, the bias signal V B may be DC coupled to stage S, however the teachings of the present disclosure strictly prohibit such DC coupling to the stage to avoid a discharge path for DC current through any intermediate point within the chamber (110) which could significantly change the operating conditions within the chamber (110).

[0019] In the DC plasma processing system shown in FIG. 1D, the bias signal V B is the potential seen by free electrons and / or ions near the stage S, or the substrate, if present (e.g., the surface potential V S ) can be used to control the energy of the free electrons and / or ions to a material-specific level required for (optimal) processing of the substrate. For example, as shown in the left graph of FIG. 1E, a bias signal V generated by an external bias signal generator (e.g., 180 in FIG. 1D) can be used to control the energy of the free electrons and / or ions to a material-specific level required for (optimal) processing of the substrate. B starts from zero and grows to a voltage amplitude of V B1 As shown in the top right graph of FIG. 1E, during processing step (a), the voltage amplitude V B1 is applied (e.g., AC-coupled) to stage S, the voltage amplitude V B1 is the surface floating potential V FPa is added to (or subtracted if negative), and a surface potential V S However, the free electrons and / or ions are at the plasma potential V PPaTherefore, the free electrons and / or ions see a plasma potential V PPa Surface potential V exceeds S For example, as shown in the top right graph of FIG. 1E, the (kinetic) energy of free electrons and / or ions is Potential difference V KEa =(V B1 -ΔV FPa ), where: ΔV FPa , =(V PPa -V FPa ).

[0020] For example, different differential ΔV FPb , =(V PPb -V FPb ) may result in different plasma potentials V PPb , or different floating potentials V FPb Considering the process step (b) represented by the graph on the lower right side of FIG. 1E, which may have different operating conditions from those of the process step (a) including the same applied voltage amplitude V B1 , different (kinetic) energies of the free electrons and / or ions are obtained. The teachings of the present disclosure eliminate variations in the operating conditions in the chamber (e.g., 110 in FIG. 1D) and / or compensate for such variations, for example, to allow precise control of the energy of the free electrons (and / or ions). It should be noted that variations in the operating conditions are expected when considering different types of processes (e.g., (a) and (b) in FIG. 1E) performed in the chamber (110), including, for example, etching the substrate with different reactive gases, cleaning the substrate, or other processes that may alter and / or remove composition / material from the surface of the substrate. It should be noted that, as known to those skilled in the art, different operating conditions for performing different types of processes may further include corresponding variations and / or adjustments to any one of the DC plasma current, temperature, gas mixture, or flow rates in the chamber (110).

[0021] When the substrate is placed on the surface of the stage S, the bias signal V BThe kinetic energy of the free electrons and / or ions obtained by the application of V accelerates them towards the surface of the substrate and may cause them to collide with the substrate, releasing their kinetic energy to atoms at the surface of the substrate. However, those atoms are not able to reach the potential at which they exist, in other words the floating potential, V FP The various energy levels of such atoms for the process type (a) described above with reference to FIG. 1E are based on the energy levels E of the nuclei of the atoms at the substrate surface. n , the energy level E of the electrons bound to the nuclei of the atoms on the substrate surface B , and the energy level E of the electron in the orbital of the electron bound to the nucleus on the substrate surface e , as shown in Figure 1F.

[0022] As can be seen in Figure 1F, the nuclear energy level E n is the (negative) potential V FPa and the electron energy level E e is the (negative) electric potential (E n +E B In other words, to excite an atom to a level that breaks the bond between the electron and the nucleus, the electron must reach the energy level E e Therefore, if we consider a plasma that is processed only through free electrons, the potential difference V KEa =(V B1 -ΔV FPa ) is the bias signal V B The kinetic energy of the free electrons supplied by the application of e must be equal to or greater than . However, E e =(E n +E B ), and E n is the a priori unknown floating potential V FPa Because it is based on the energy level E e It may be impossible to precisely control the kinetic energy of the free electrons in order to target them precisely.

[0023] Floating potential (e.g., V in Figure 1F) FPa ) may be empirically and / or experimentally determined for a given process in stable operating conditions of a direct current plasma chamber, but inconsistencies and / or lack of repeatability of such operating conditions may invalidate the determined floating potential. Furthermore, since different types of processes result in essentially different floating potentials, the task of precisely controlling the kinetic energy of the free electrons to precisely target the energy levels of atoms on the substrate surface may not be feasible. As a result, in some prior art implementations, atoms on the substrate surface may be imparted with kinetic energy substantially greater than the energy levels of the targeted atoms, and thus may not be selective (since atoms of different materials / compositions having different energy levels may equally experience sufficient energy levels to break orbital bonds). Electron-assisted material processing (EEMP) according to the teachings of the present disclosure overcomes such shortcomings, thus enabling precise control of the kinetic energy of the free electrons to precisely and selectively target the energy levels of atoms on the substrate surface.

[0024] 2A shows a simplified schematic diagram of a DC plasma processing system (200A) according to one embodiment of the present disclosure, comprising means (250, 260) for controlling the surface potential of the stage S when electrically isolated. In other words, these means (250, 260) control the floating potential V FP As shown in FIG. 2A, the means (250, 260) includes an adjustable DC voltage source (250) coupled to the anode A of the DC plasma reaction chamber (110) and a DC current source (260) coupled to the cathode C of the DC plasma reaction chamber (110). Thus, the potential VA of the anode A can be controlled to be in the range of zero volts or more (positive) with respect to a reference earth (Gnd at zero volts), and the (drain) current Ip flowing between the anode A and the cathode C through the reaction chamber (110) can be set by the DC current source (260). Thus, the potential V of the cathode C can be controlled to be in the range of zero volts or more (positive) with respect to a reference earth (Gnd at zero volts), and the (drain) current Ip flowing between the anode A and the cathode C through the reaction chamber (110) can be set by the DC current source (260). Cis not forced by an external DC voltage source (e.g., 150 in FIG. 1D), but rather (floats) to the adjustable potential V of anode A. A and settles to a (negative) voltage based on the set current Ip. Such a configuration allows the floating potential V to be increased while maintaining the set current Ip through the reaction chamber (110) constant in order to establish and maintain a higher level of process stability and optimization. FP This allows the user to control / adjust the

[0025] FIG. 2B illustrates the surface potential V of the stage S of the DC plasma processing system (200A) described above with reference to FIG. 2A. FP In particular, FIG. 2B shows two graphs, differentiated by the use of solid or dashed lines, each graph showing two different voltages (V A1 , V A2 ) across the longitudinal extension X of the chamber (110) relative to the plasma potential V PP As can be seen in Figure 2B, the voltage V A1 to voltage V A2 A positive step increase in the anode potential to +ΔV 12 For floating potential (V FP1 , V FP2 ) and cathode potential (V C1 , V C2 ) is the same positive step, +ΔV 12 In fact, as shown in Figure 2B, the plasma potential V PP For the whole of 12 In other words, the range [X C , X A For any longitudinal coordinate X in PP (X) is the step increase, +ΔV 12 A similar behavior applies to the negative step variation applied to anode A by the adjustable DC voltage source (250). In other words, the control of the potential of anode A by the adjustable DC voltage source follows the plasma potential V PP and therefore the floating potential VFP and the voltage V at the top of stage S S As will be described later in this disclosure, such linearity is important while operating a DC plasma chamber for different types of material processing, as well as the floating potential V FP This can be used in an EEMP system according to the present teachings to implement a closed-loop control subsystem that automatically controls the value of to a preset value (e.g., zero volts).

[0026] Figure 2C shows the anode voltage V A1 FIG. 2B shows two graphs similar to the one discussed above with reference to FIG. 2B, including the special case where V is equal to zero volts (solid line). As can be seen in FIG. 2B, the floating potential voltage in such a case is a negative value V FP1 and therefore the plasma potential V PP Furthermore, as can be seen in FIG. 2C, a positive step increase in the anode potential, +ΔV 13 =(V A1 -V FP1 ), the floating potential is equal to zero volts, V FP3 According to one embodiment of the present disclosure, the floating potential V FP Such zeroing of may allow for precise control of the kinetic energy of free electrons in a DC plasma to precisely (and selectively) target the energy levels of atoms at the surface of the substrate (whether conductive or insulating) being processed. In other words, referring back to FIG. 1F, the energy level E of the nuclei of the atoms targeted / selected for processing may be n The a priori unknown floating potential that determines the floating potential V FP On the other hand, as shown in FIG. 4B below, this causes the energy level E e , the kinetic energy level of free electrons in a DC plasma (e.g., V in Fig. 1F) KEa ), and the bias voltage V applied to stage S B allows all the potentials to be referenced to the same known and fixed reference, the zero volt potential Gnd. FPIt should be noted that while the provision of a known level of may be provided by zeroing such potential as described above, such zeroing should not be considered as limiting the scope of the present disclosure, as other pre-set / adjusted non-zero values ​​of the floating potential may similarly function as reference potentials for precisely controlling the kinetic energy of free electrons in a DC plasma in order to precisely (selectively) target the energy levels of atoms at the surface of the substrate (whether conductive or insulating) being processed.

[0027] FIG. 3A shows a means for controlling the surface potential of the stage S (250, 260 in FIG. 2A) and a surface potential V S (For example, floating potential, V FP ) measuring means (R, 311, V in FIG. 3A) R 3 shows a simplified schematic diagram of a direct current plasma processing system (300A) according to an embodiment of the present disclosure, comprising a surface potential V S Means for measuring (R, 311, V R ), or in other words, the floating (surface) potential above the stage V FP Means for measuring (R, 311, V R ) represents an improvement over the system (200A) described above with reference to FIG. 2A. FP By enabling such measurement, adjustment of the DC voltage source (250) as described above with reference to FIGS. 2A-2C can be made to the surface potential V FP This may be done while monitoring / measuring the floating potential V, including for example setting such potential to zero (VFP=0 volts). FP This allows for precise control of the amount of heat generated.

[0028] With continued reference to FIG. 3A, the means (R, 311, V R) includes a reference plate R that is located in the DC plasma chamber (110) in the same (longitudinal coordinate) segment [XG31, XG32] as the stage S. The reference plate R may be made of any conductive material that can withstand the (internal) operating conditions of the chamber (110) and may have any planar shape, including, for example, planar shapes according to a square, rectangle, circle, pentagon, trapezoid or others. The reference plate R is located in the same area as the plate S and therefore has the same approximately constant plasma potential V PP Since the reference plate R is located in the region of FP In other words, the (surface) potential V on the reference plate R R By measuring the potential V, the floating potential at stage S can be determined. An insulated conductive wire (311) attached to reference plate R is connected to a potential V R to measurement electronics (e.g., transducers) located outside of the chamber (110). It should be noted that such measurement electronics should not provide a DC current path to the plasma through plate R.

[0029] With continued reference to FIG. 3A, the location of the reference plate R may be any longitudinal extension of the chamber (110) within the segments [XG31, XG32] that is technically feasible and practical. The chamber (110) may include an access door adjacent to the stage S on one side of the chamber (110), and in some exemplary embodiments, the reference plate R may be located against or near a wall of the chamber (110) opposite the access door and the stage S. Furthermore, according to exemplary embodiments, the center of the reference plate R and the center of the stage S (e.g., the intersection of the two segments of the stage T as shown in the figure) may be included in a line perpendicular to the axial direction (e.g., centerline, direction of longitudinal extension) of the chamber (110). Applicants of the present disclosure have proposed a method for tracking the floating potential of the stage S using a means (R, 311, V R ) was confirmed to be highly accurate.

[0030] FIG. 3B illustrates the surface potential V on stage S based on the system (300A) of FIG. FP 1 shows a simplified schematic diagram of a DC plasma processing system (300B) according to an embodiment of the present disclosure, with the addition of a means (320, CT) for automatic control of the floating potential V at stage S while operating the DC plasma chamber for different types of processes. FP The control electronics (320) is configured to incorporate a closed-loop control system that automatically controls the value of V to a preset value (e.g., zero volts). In particular, as shown in FIG. 3B, the control electronics (320) controls the (surface) potential V of the reference plate R via the coupling provided by the insulated conductive wire (311). R is taken as an input, and the voltage V supplied to the anode A is A , and thus generates a control (error) signal CT to regulate the floating potential V in stage S, as described above with reference to FIGS. 2A-2C. FP The control (error) signal CT is connected to a floating potential V, e.g. zero volts. FP The control electronics (320) may be generated with respect to a desired target / preset value of V. Those skilled in the art are familiar with design techniques for implementing control electronics (320), which are outside the scope of this disclosure. In particular, those skilled in the art are familiar with the use of operational amplifiers or error amplifiers in such control electronics (320), the input of which is connected to a potential V R , and the floating potential V FP to a desired target / preset value (e.g., zero volts) and generate an error signal (e.g., CT) based on the difference in the inputs.

[0031] FIG. 4A shows a biasing means (C S FIG. 4 shows a simplified schematic diagram of a direct current plasma processing system (400A) according to one embodiment of the present disclosure based on the system of FIG. 3B with the addition of bias means (C , 480). S , 480) is a capacitor C SIn other words, the bias signal V generated at the output of the bias signal generator (480) is B is the capacitor C S The bias signal generator (480) capacitively couples the bias signal V to the stage S via a bias voltage VV, as previously described in this disclosure. As previously described in this disclosure, such capacitive coupling allows for the elimination of any direct current paths to or from the DC plasma chamber (110), thereby preventing any undesired perturbation of the operating conditions of the chamber (110). The bias signal generator (480) adjusts the bias signal V according to desired characteristics including, for example, amplitude, frequency, duty cycle, and / or rising / falling edges / slope. B It should be noted that the stage S may include a programmable waveform generator configured to output a waveform of a bias signal V B to the stage S. S 3), and a second portion of the stage (e.g., a horizontal support plate), which may include conductive and / or insulating materials.

[0032] FIG. 4B illustrates an exemplary bias signal V applied to stage S of the DC plasma processing system (400A) of FIG. 4A. B1 , and the corresponding surface potential V generated on the surface of the stage S. S As will be clearly understood by those skilled in the art, the graph shown in FIG. FP 1E )。 Therefore, in view of (or in contrast to) the above description with reference to FIG. 1E, the (kinetic) energy of free electrons and / or ions attracted to the surface of the stage S or a substrate thereon is determined by the potential difference V KE =(V B1 -ΔV FP ) and ΔV FP =(V PP -V FP) Therefore, in practical substrate processing applications using a DC plasma chamber, ΔV FP The value of V KE (e.g., the energy level E of the target electron in FIG. 4C) e Since the approximate value V KE =V B1 is believed to be reasonable, which in turn provides a bias signal V provided to stage S for performing electron-enhanced material processing (EEMP) according to the teachings of the present disclosure that precisely and selectively targets the energy levels of atoms (e.g., bound electrons) at the surface of the substrate. B1 This allows for simple and easy generation of

[0033] With further reference to FIGS. 4A and 4B, the excitation of the energy levels of atoms at the surface of the stage S or at the surface of a substrate disposed on the stage S is primarily due to the surface potential V S Note that the excitation of the energy levels may be based on the instantaneous change in the bias voltage V. B1 This can be achieved immediately at the end of the transition to , in other words, at the end of the ramp shown in FIG. 4B.

[0034] 4C illustrates exemplary energy levels of atoms at the surface of stage S of the DC plasma processing system (400A) of FIG. 4A. FIG. 4C illustrates the floating potential V, according to the description above with reference to FIGS. 2A-2C, further based on a reference plate R according to the description above with reference to FIG. 3A, further based on an (optional) closed loop control system provided by the control electronics (320) according to the description above with reference to FIG. 3B, and further based on capacitive coupling of a bias signal VB provided by the bias signal generator (480) according to the description above with reference to FIG. 4A. FP Based on the zeroing of KE This application highlights the advantages of electron-enhanced materials processing (EEMP) according to the teachings of the present disclosure, which allows for precise and selective targeted adjustment of the surface area of ​​a material.

[0035] 5 is a process chart (500) illustrating various steps of a method according to an embodiment of the present disclosure for treating a surface of a substrate. As shown in FIG. 5, such steps include: placing a substrate support stage in a region of a DC plasma reaction chamber configured to generate a positive column of DC plasma according to step (510); generating DC plasma by coupling an adjustable DC voltage source and a DC current source to an anode and a cathode of the DC plasma reaction chamber, respectively, according to step (520); generating a floating potential on the surface of the substrate support stage based on the generating step according to step (530); adjusting the potential of the anode via the adjustable DC voltage source while maintaining the DC current between the anode and the cathode constant via the DC current source according to step (540); and setting the floating potential to the potential of the reference ground of the adjustable DC voltage source based on the adjusting and maintaining step according to step (550).

[0036] 6A-6C are graphs illustrating the reaction kinetics of electron-enhanced material processing (EEMP) according to the present disclosure for different (categories / types / classes) of materials, including single crystal or two-dimensional (2D) materials, such as semiconductor or insulator materials (FIG. 6A), metals and metal alloys (FIG. 6B), and composite materials, such as polymers, composites, nanomaterials, or three-dimensional (3D) materials (FIG. 6C). In this case, the reaction, or target reaction, is determined by the bias signal V applied to a stage (e.g., S in FIG. 4A). B , which can be referred to as the breaking of chemical bonds (e.g., bonds between electrons and atomic nuclei) of atoms of a material at the surface of a substrate placed on a stage (e.g., S in FIG. 4A) in response to a level of . As is evident from such a graph, the reaction rate RR is proportional to the reaction threshold voltage V RTH , reaction cut-off voltage V RCO , and the reaction threshold voltage V RTHV It should be noted that for each material or type of material, such characteristic voltages may be different and are generally part of a priori acquired knowledge base. For example, the V RTHis the V of the metal material (e.g., Figure 6B) RTH , or V of the composite material (e.g., FIG. 6C) RTH and the V of the crystalline material (e.g., FIG. 6A). RTHV is the V of a metal material (e.g., FIG. 6B) or a complex material (e.g., FIG. 6C). RTHV may differ from.

[0037] It should be noted that 2D materials compatible with electron-enhanced material processing (EEMP) according to the present disclosure include, for example, graphene, boron nitride, molybdenum disulfide, tungsten diselenide, or platinum diselenide, nanomaterials compatible with EEMP according to the present disclosure include, for example, carbon nanotubes, nanosilver particles, titanium oxide particles, or quantum dots, and 3D materials compatible with EEMP according to the present disclosure include, for example, any 3D structure formed of materials including polymers, collagen fibers, or metals such as titanium, or 3D printed polymer / polymer, polymer / carbon, or polymer / metal microstructures. Single crystals compatible with EEMP according to the present disclosure include, for example, semiconducting single crystals such as group IV silicon, germanium, group III-V gallium arsenide, gallium nitride, silicon carbide, indium gallium arsenide, group II-VI zinc selenide, and quantum well stacks containing alternating II-VI and / or III-V compound semiconductors. Single crystals compatible with EEMPs according to the present disclosure further include semiconducting single crystals such as, for example, quartz, sapphire, or diamond. Polymers compatible with EEMPs according to the present disclosure include, for example, polypropylene, polyethylene, polyetheretherketone, polycarbonate. Composites compatible with EEMPs according to the present disclosure include, for example, polymers containing metal particles, carbon particles, carbon fibers, or carbon nanotubes. The materials and structures listed here should be considered non-limiting with respect to the material compatibility list for EEMPs according to the present teachings, and this list may grow as new materials / structures and corresponding bond energies and reaction energies that may be targeted by the present EEMPs are obtained, for example, through advanced methods for computer simulation of chemical bonds.

[0038] Continuing with reference to FIGS. 6A-6C, for example, as described above with reference to FIG. 4B, when a substrate is placed on a stage (e.g., S in FIG. 4A), a floating potential (e.g., V in FIG. 4B) is applied to the substrate. FP ) can be adjusted (controlled) to a known potential (e.g., zero volts or other). Thus, the energy levels of the atoms at the substrate surface assume the same potential (e.g., as the ground state) and no reaction may be observed at the substrate surface, or in other words, the reaction rate RR of the target bonds (in the ground state) is zero, as shown in Figures 6A-6C. B As increases, the reaction rate RR of the target bonds remains zero, and then a small (e.g., small) number of target bonds slowly begin to react, or in other words, when a small number of target bonds reach their respective excited states, the reaction cutoff voltage V RCO The bias voltage V B is the reaction threshold voltage V RTH When the bias voltage V reaches B With further increase in , the reaction rate RR increases with a (substantially) constant slope, which increases with increasing bias voltage V B is the reaction threshold voltage V RTHV This continues until the reaction threshold voltage V RTH and the reaction threshold voltage V RTHV Between these, the reaction rate RR increases until (almost) all of the target bonds react. As shown in Figures 6A-6C, the reaction threshold shift voltage V RTHV Beyond the bias voltage V B Increasing the bias voltage V B When the bias voltage V decreases, the reaction rate RR becomes similar to the graphs shown in Figures 6A to 6C. B is the reaction cut-off voltage V RCO When the reaction rate R drops to a level below , the reaction rate R drops to zero as all of the target bonds on the substrate surface return to their ground states.

[0039] As is clear from the graphs in FIGS. 6A to 6C, the voltage V RTH and V RTHV The (substantially) constant slope of the reaction rate RR between or the difference between the two voltages may be a function of the material used for the (surface of) the substrate being treated. In particular, the voltage V RTH and V RTHV The difference from the surface potential can be due to atomic level defects on the surface of single crystal materials such as semiconductors or insulators (e.g., FIG. 6A), atomic level defects and associated grain boundaries on the surface of metals, metal alloys or nanomaterials (e.g., FIG. 6B), or the presence of three-dimensional (3D) structures in polymers, composites or other 3D materials (e.g., FIG. 6C). As will be described later in this disclosure, the teachings of the present disclosure provide a method for controlling the activation (or deactivation) of a reaction governed by the reaction rate RR, for example, the graphs shown in FIGS. 6A-6C, by using voltage levels V specifically targeted to the material used for the substrate. B In particular, specific waveforms for each material shown in the graphs of reaction rates RR in Figures 6A, 6B, and 6C are shown in Figures 7A, 7B, and 7C, respectively.

[0040] 7A-7C are graphs illustrating waveforms of EEMP bias signal V(t) according to some exemplary embodiments of the present disclosure for processing different materials. In particular, FIG. 7A illustrates a waveform for processing a single crystal material such as a semiconductor or insulator, FIG. 7B illustrates a waveform for processing a metal, metal alloy, or nanomaterial, and FIG. 7C illustrates a waveform for processing a polymer, composite, or three-dimensional material. Such graphs may be used to illustrate ideal voltage levels (e.g., V) of bias signal V(t) for use in the EEMP process according to the present disclosure described above. B , V BN ), which represents the potential V FP to a known level, such as zero volts or other fixed known level, and FP Voltage / potential level relative to (e.g., V B It should be noted that the method may include the step of energizing the free electrons in the DC plasma with a

[0041] Each graph in FIG. 7A to FIG. 7C shows the time course of a (periodic) bias signal V(t), T EEMP The EEMP process of the material on the surface of the substrate is carried out over a predefined number of cycles, T EEMP , the different EEMP processes (e.g., having different RR characteristics) can be implemented by using different layers of material in the substrate and / or different operating conditions and / or potentials V(t) of the DC plasma reaction chamber. FP can be performed sequentially on the same substrate, taking into account (controlled / preset) levels of

[0042] Continuing to refer to FIGS. 7A-7C, according to one embodiment of the present disclosure, a cycle T of the waveform of the bias signal V(t) is EEMP are three different phases (e.g., time intervals, time segments) ΔT that include voltage levels above zero volts (or a reference voltage level), below zero volts, and equal to zero volts, respectively. BP , ΔT BN , and ΔT BZ In other words, the time interval ΔT BP During this time, the level V of the bias signal V(t) B is strictly greater than zero volts (or a reference voltage level) for a time interval ΔT BN During this time, the level V of the bias signal V(t) BN is strictly less than zero volts and for the time interval ΔT BZ During this time, the level of the bias signal V(t) is equal to zero volts.

[0043] According to one embodiment of the present disclosure, the duration T of the cycle of the waveforms shown in FIGS. EEMPmay be in the range of 1 μs to 10 μs, or in other words, the frequency of the bias signal V(t) may be in the range of 100 KHz to 1 MHz. According to further embodiments of the present disclosure, the waveform of the bias signal V(t) may be DC-free, or in other words, the integral over a cycle of the waveforms shown in FIGS. 7A-7C may have a value of zero. Such DC-free characteristic of the waveforms according to the present teachings may be achieved by controlling the preset / controlled local surface potential (e.g., V FP In other words, the DC-free nature of the waveform may allow for maintaining the average local surface potential of the substrate during application of the bias signal V(t) substantially equal to the voltage levels (e.g., V B , V BN ) can be applied to the substrate surface. FP For a voltage V FP 7A to 7C. In other words, the potential V FP Note that this can be adjusted by substituting the value of

[0044] According to one embodiment of the present disclosure, the time interval ΔT BP , ΔT BN , and ΔT BZ The length of each of the time intervals ΔT can be based on the type of material (at the surface) of the substrate, including the corresponding reaction rate RR, as described above with reference to FIGS. BP The length of the time interval ΔT BNThe ratio to can be in the range of (about) 1 / 10 to (about) 1 / 1. For example, in the case of crystalline materials (e.g., FIG. 7A), the ratio can be about 10 / 65 (±10%), in the case of metallic materials (e.g., FIG. 7B), the ratio can be about 1 / 2 (±10%), and in the case of composite materials (e.g., FIG. 7C), the ratio can be about 1 / 1 (±10%). Furthermore, as shown in FIGS. 7A-7C, the overall cycle length T EEMP The length of the time interval for BZ According to a non-limiting embodiment of the present disclosure, the ratio of the time interval ΔT BZ The length of is the total period T EEMP may be based only on the time interval ΔT BP and ΔT BN may be independent of the length of each of the

[0045] For the exemplary, non-limiting case shown in FIGS. 7A-7C, the time interval (ΔT BP , ΔT BN , ΔT BZ ) the total cycle length T EEMP The ratio of to can be (e.g., ±10%), for crystalline materials (e.g., FIG. 7A), about (10 / 100, 65 / 100, 25 / 100), for metallic materials (e.g., FIG. 7B), about (25 / 100, 50 / 100, 25 / 100), and for composite materials (e.g., FIG. 7C), about (37.5 / 100, 37.5 / 100, 25 / 100). Figures 7A-7C show a cycle T with a length of 4 μs (frequency 250 KHz). EEMP However, as noted above in this disclosure, such lengths may be in the range of 1 μs to 10 μs (e.g., frequencies between 100 KHz and 1 MHz) and should not be considered as limiting the scope of this disclosure.

[0046] Continuing to refer to the waveforms in Figures 7A-7C, the phase ΔT BPDuring the period, the waveform applies a bias voltage V(t) to a (positive) level (e.g., V ) to activate a (targeted) EEMP reaction at the substrate surface based on collisions of energized (free) electrons with targeted bonds at the substrate surface (e.g., surface materials including single crystal for FIG. 7A, metal for FIG. 7B, and composite for FIG. 7C). B According to one embodiment of the present disclosure, the (high) level V of the bias voltage V(t) can be set to B The length of time that the phase ΔT is maintained must be long enough to keep the energized (free) electrons on the substrate surface and react with the target bonds. Such a length is determined by the phase ΔT BP (Part of) the rising or falling slope included in (e.g., when the bias voltage (V(t)) reaches the target high level V B It should be noted that the period (not shown) may not be included.

[0047] Furthermore, phase ΔT BN During this time, the waveforms of FIGS. 7A-7C drive the bias signal V(t) to a (negative) level V(t) in order to deactivate the EEMP reaction on the substrate surface and also to discharge (e.g., repel) any free electrons from the substrate surface, thereby neutralizing the charge on the substrate. BN Phase ΔT BN During this time, the kinetic energy is BN It should be noted that the energized free ions may be imparted to the free ions in the DC plasma by , so that the energized free ions may move slowly towards the substrate surface and thereby further participate in the neutralization of the substrate. Furthermore, it should be noted that due to their low energy level, the energized free ions may not (and should not) react with the bonds of the substrate surface. The voltage level V of the bias signal V(t) BN The magnitude of is therefore high enough (e.g., more negative) for the free ions to move slowly, and the phase ΔT BN The duration of the voltage level V BN Magnitude and phase ΔT BPIn combination with the duration of V(t), V(t) may be sufficiently long to cause suppression (or control) of the DC component of the bias signal V(t).

[0048] Phase ΔT BZ During this time, the waveforms of FIGS. 7A to 7C show that the voltage level of the bias signal V(t) is zero (or a floating potential V FP Therefore, the phase ΔT BZ is the bias signal V(t) for each cycle T EEMP may be used to restore a similar initial bias condition of the substrate at the start of FP This may allow for a more stable and accurate process (EEMP) when compared to other prior art processes. Therefore, based on the description provided, the cycle T describing the waveform of the bias signal V(t) is EEMP Each phase ΔT BP , ΔT BN , and ΔT BZ can be referred to as the active (EEMP) response phase, the (EEMP) neutralization phase, and the (EEMP) initialization phase, respectively, the latter two phases being inactive phases with respect to the targeted (EEMP) response.

[0049] Figure 8 shows the active phase ΔT BP Further timing details describing each portion of the waveform in (e.g., time interval t BR , t BH , and t BR 7A-7C, in particular for a time interval t BR is the change in bias signal V(t) from its starting value at the beginning of the phase (e.g., V(t)=0) to the target high level V B The transition time can be specified to reach the time interval t BH is the target high level V(t) of the bias signal V(t). B and a time interval tBF is the bias signal V(t) during the active phase ΔT BP In other words, we can specify a transition time to return to the starting value (e.g., V(t)=0) at the end of a time interval t BR is the starting value at a higher level V B A rising (e.g., leading) edge slope of the bias signal V(t) to reach BF may define the falling (eg, trailing) edge slope of the bias signal V(t) to return to the starting value.

[0050] With continued reference to FIG. 8A, time interval t BH During this time, the bias signal V(t) is RTH A high level V that exceeds (is greater than) B 6A-6C, the target binding is, for example, in the time interval t BH Each excited state can be reached as long as the duration of the active phase ΔT is long enough to keep the energized (free) electrons on the substrate surface to react with the target bonds. BP The length of the time interval t BH The ratio of V(t) may be in the range of about 1 / 4 (e.g., ±10%) to about 3 / 4 (e.g., ±10%). Thus, a periodic bias signal V(t) having a frequency of 250 KHz and thus a cycle length T equal to 4 μs is EEMP Consider the case of performing EEMP processing of a single crystal material (e.g., as shown in Figs. 6A and 7A above), the length of the time interval t BH can be in the range of about 0.1 μs to about 0.3 μs.

[0051] With further reference to FIG. 8A, the bias signal V(t) is in an active phase ΔT BP As the reaction threshold voltage V RTH The level of the bias signal V(t) that exceeds BRSimilarly, if the bias signal V(t) arrives during a portion of the time interval t BH As the voltage decreases at the end of RTH The level of the bias signal V(t) that exceeds BF 8A is effectively seen by free electrons in a DC plasma. In the ideal case, the level of the bias signal V(t) is therefore RTH A time interval t that is greater than or equal to BR and t BF may be included in the determination (or interpretation) of the graph of reaction rate RR described above with reference to Figures 6A-6C. However, the time interval t BR and t BF Since the slope of the rising and falling edges defined by B may be in the range of 10 volts to about 200 volts), a portion of which may be considered irrelevant / unimportant compared to the minimum time required to keep energized (free) electrons on the substrate surface to react with target bonds.

[0052] FIG. 8B is a graph illustrating a practical waveform of an EEMP bias signal. Such a waveform represents a practically achievable waveform that can be modeled from the ideal waveform described above with reference to FIG. 8A. In particular, the practical waveform of FIG. 8B is shown to have a corresponding steady state level (e.g., V B , V BN , zero volts). Such realistic waveforms may be generated by electronics that may include a power amplifier (e.g., coupled to and / or part of the bias signal generator of FIG. 4A ) whose output is coupled to a load under perfect match conditions. However, such perfect match conditions are not provided by the capacitive load (e.g., stage S of FIG. 4A ) in DC plasma processing according to the present disclosure, and thus the steady state level (e.g., V B , V BNBefore the input voltage settles to a fixed voltage (0 volts), signal reflections including ringing and associated distortions can be expected.

[0053] The ringing shown in FIG. 8C occurs at the target high level V B The active phase ΔT before settling BP Between and the target low level V BN Neutralization phase before settling at ΔT BN The ringing of the bias signal V(t) during BU ) during the active phase. As shown in FIG. BP is the overshoot voltage V BOS Targeting high levels of V B and the undershoot voltage V BUS Targeting high levels of V B The spread of uncertain voltages below V BU Those skilled in the art will appreciate that the undershoot voltage V BUS The level of the bias signal V(t) is the threshold voltage V RTH The overshoot voltage V BOS The level of the bias signal V(t) is the reaction threshold voltage V' of non-target bonds that may be present on the substrate surface. RTH Therefore, the spread of uncertain voltage V BU It will be clearly understood that during the activation phase, activation of the EEMP target response can be disrupted. On the other hand, during the neutralization phase ΔT BN The ringing in the active phase ΔT does not significantly affect the EEMP process because the free ions are kept well below the reaction energy of any ion-driven reactions (e.g., thermochemical reactions). BP Reduction of the ringing shown in FIG. 8C, including the ringing in, may be provided by predistortion (eg, distortion compensation) of the bias signal V(t).

[0054] FIG. 9A shows a digitized waveform (WF, digital samples marked with circles) for generating the practical waveform of FIG. 8B and the corresponding predistorted digitized waveform (WF P 8B is a graph showing digital samples of the predistorted digitized waveform WF (digital samples WF denoted by squares). In particular, generation of the practical waveform of FIG. 8B may be provided by uploading the corresponding digital samples WF of the digitized waveform to a digital signal generator whose output may be provided to a power amplifier (e.g., coupled to or part of the bias signal generator of FIG. 4A). Similarly, generation of the corresponding practical waveform with predistortion may be provided by uploading the corresponding digital samples WF of the predistorted digitized waveform to a digital signal generator whose output may be provided to a power amplifier (e.g., coupled to or part of the bias signal generator of FIG. 4A). P may be provided by uploading the signal to a digital signal generator.

[0055] With continued reference to FIG. 9A, predistortion may be achieved by providing a practical predistortion waveform (e.g., WF 100) that may provide a reduced amount of ringing when subjected to a capacitive load condition of a stage (e.g., S in FIG. 4A) as shown in FIG. 9B. P ) can be used to modify / equalize the slope / transition of the digitized waveform with predistortion. As shown in FIG. 9B, the use of predistortion reduces the overall active phase ΔT BP During this time, the bias signal level V(t) is the target threshold voltage V RTH Any non-target reaction threshold voltage V' RTH The spread of the uncertainty voltage V BU Such predistortion can cause a decrease in the bias signal V(t) to reach the targeted high level V B The desired length of the time interval t BH In other words, the predistortion may result in a waveform that includes a time interval t BH The length can be maintained.

[0056] FIG. 10A is a graph representative of gain versus frequency for a band-limited linear power amplifier according to an embodiment of the present disclosure (e.g., graph G1) and a graph representing gain versus frequency for a conventional power amplifier (e.g., graph G2). According to one embodiment of the present disclosure, a band-limited linear power amplifier used for EEMP processing may include a flat gain G1 within 0.75 dB in the frequency range of 10 KHz to 10 MHz as shown in FIG. 10A. This operating (passband) range of the band-limited linear power amplifier includes any corresponding (higher frequency) harmonics that may be reflected from capacitive loads, as well as some of the ringing shown in FIGS. 8C and 9B (e.g., uncertainty voltage spread, V BU The bias signal V(t) is selected having regard to the 100 KHz to 1 MHz frequency range of operation so as to reduce any corresponding (higher frequency) harmonics that may produce distortion of the signal, including

[0057] FIG. 10B shows the predistorted digitized waveform WF of FIG. 9A through the band-limited linear power amplifier of FIG. 10A under capacitive load conditions. P 9B is a graph showing an analog waveform generated from the waveform shown in FIG. 9B. In particular, when compared to the waveform described above with reference to FIG. 9B, the spread of uncertain voltages V BU A decrease in is observed, indicating a larger process window for controlling / manipulating the targeted EEMP response. It should be noted that the waveform in FIG. 9B can be reproduced by a conventional power amplifier whose gain vs. frequency G2 is shown in FIG. 10A. In particular, as shown in FIG. 10A, the cutoff frequency f of the conventional power amplifier C2 is the cutoff frequency f of the band-limited linear power amplifier according to the present teachings. C1 may be substantially larger than the bias voltage V(t) and may pass higher frequency harmonics of the bias signal V(t) and thus cause such harmonics to be reproduced as distortion.

[0058] Fig. 11 is a process chart (1100) showing various steps of a method according to an embodiment of the present disclosure for processing a surface of a substrate. As shown in Fig. 11, such steps include placing a substrate on a support stage in a region of a DC plasma reaction chamber configured to generate a positive column of DC plasma according to step (1110), generating a DC plasma according to step (1120), presetting a floating potential of the substrate surface to a reference potential according to step (1130), and capacitively coupling a periodic bias signal having a bias voltage referenced to the floating potential to the support stage according to step (1140), the periodic bias signal including an activation phase having a positive voltage referenced to a known reaction threshold voltage of a target chemical bond of atoms on the surface of the substrate, a neutralization phase having a negative voltage, and an initialization phase having a zero voltage.

[0059] A number of embodiments of the present disclosure have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the disclosure. Accordingly, other embodiments are within the scope of the following claims.

[0060] The above examples are provided to those of ordinary skill in the art as a complete disclosure and description of how to make and use the embodiments of the present disclosure, and are not intended to limit the scope of what the inventors regard as their disclosure.

[0061] Modifications of the above-described modes for implementing the methods and systems disclosed herein that are obvious to one skilled in the art are intended to be within the scope of the following claims. All patents and publications mentioned in this specification are indicative of the level of skill of those skilled in the art to which this disclosure pertains. All references cited in this disclosure are incorporated by reference to the same extent as if each reference was individually incorporated by reference in its entirety.

[0062] It is to be understood that the present disclosure is not limited to a particular method or system, as such may vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting. As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the content clearly dictates otherwise. The term "plurality" includes two or more references unless the content clearly dictates otherwise. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

Claims

1. 1. A direct current (DC) plasma system for processing a substrate, comprising: a DC plasma reaction chamber configured to contain a DC plasma generated between an anode and a cathode of the DC plasma reaction chamber; a substrate support stage disposed within the DC plasma reaction chamber in a region containing a DC plasma positive column; a means for controlling the floating potential of the surface of the substrate support stage to a reference potential; and a bias signal generator capacitively coupled to the substrate support stage and configured to generate a periodic bias signal having a voltage referenced to the reference potential, the periodic bias signal comprising: an active phase having a positive voltage; a neutralization phase having a negative voltage; and An initialization phase with zero voltage; The bias signal generator includes: A direct current plasma system comprising:

2. 2. The DC plasma system of claim 1, wherein the positive voltage is a preset voltage based on a known reaction threshold voltage of the target chemical bonds of atoms on a surface of a substrate disposed on the substrate support stage.

3. 2. The DC plasma system of claim 1, wherein the positive voltage is equal to or greater than the reaction threshold voltage of the target chemical bonds of atoms on the substrate surface disposed on the substrate support stage.

4. 4. The DC plasma system of claim 3, wherein the positive voltage is less than a reaction threshold voltage of non-target chemical bonds of atoms on the substrate surface.

5. 4. The direct current plasma system of claim 3, wherein the positive voltage is strictly greater than the reaction threshold voltage of the target chemical bonds of atoms for a duration in the range of 1 / 4 to 3 / 4 of the total time length of the active phase.

6. 4. The DC plasma system of claim 3, wherein the negative voltage has a magnitude low enough to keep the energy levels of free ions in the positive column below the reaction energy levels of all chemical bonds of atoms at the substrate surface.

7. 7. The DC plasma system of claim 1, wherein the DC component of the periodic bias signal is zero.

8. 8. The DC plasma system of claim 7, wherein the frequency of the periodic bias signal is in the range of 100 KHz to 1 MHz.

9. 9. The direct current plasma system of claim 8, wherein the ratio of the length of time of the activation phase to the length of time of the neutralization phase is in the range of 1 / 10 to 1 / 1.

10. 10. The DC plasma system of claim 9, wherein the ratio of a length of time of the initialization phase to a length of time of one cycle of the periodic bias signal is about 1 / 4.

11. 10. The DC plasma system according to any one of claims 1 to 9, wherein the target chemical bonds are atoms of a material that is either a) a single crystal, b) a metal, c) a composite material or a three-dimensional material.

12. 12. The DC plasma system of claim 11, wherein the single crystalline or two-dimensional material comprises a semiconductor or insulator material.

13. 13. The direct current plasma system of claim 12, wherein the ratio of the length of time of the activation phase to the length of time of the neutralization phase is about 1 / 10.

14. 12. The DC plasma system of claim 11, wherein the target chemical bonds are atoms of a metal or metal alloy; and the ratio of the length of time of the activation phase to the length of time of the neutralization phase is about 1 / 2; DC plasma system.

15. 12. The DC plasma system of claim 11, wherein the composite material comprises any of a polymer, a composite, or a three-dimensional material.

16. 16. The direct current plasma system of claim 15, wherein the ratio of the length of time of the activation phase to the length of time of the neutralization phase is about 1 / 1.

17. 18. The DC plasma system of any one of claims 1 to 17, wherein the periodic bias signal includes a predistortion configured to reduce ringing during the active phase.

18. 19. The DC plasma system of claim 1, wherein the bias signal generator comprises a digital signal generator configured to receive digital samples including distortion compensation for generating the periodic bias signal.

19. 20. The DC plasma system according to claim 1, the bias signal generator further comprising a band-limited linear power amplifier configured to receive an output of the digital signal generator and generate the periodic bias signal; the band-limited linear power amplifier includes a gain that is flat within 0.75 dB in the frequency range of 10 KHz to 10 MHz; the band-limited linear power amplifier is configured to substantially block harmonics of the periodic bias signal; DC plasma system.

20. In the DC plasma system according to any one of claims 1 to 20, the means for controlling the floating potential comprises: a reference plate made of a conductive material arranged in a region of the DC plasma reaction chamber containing the positive column of the DC plasma, the reference plate being arranged such that a first surface potential developed on a surface of the reference plate is equal to a second surface potential developed on a surface of the substrate support stage, the first surface potential and the second surface potential being equal to the floating potential; and control electronics configured to measure the first surface potential and responsively adjust the potential of an anode to adjust the second surface potential to the reference potential; A direct current plasma system.

21. A method for treating a substrate surface, comprising treating said substrate through a DC plasma system according to any one of claims 1 to 21.

22. 1. A method for treating a substrate surface, comprising: placing a substrate on a support stage within a region of a direct current plasma reaction chamber configured to generate a positive column of a direct current plasma; generating the DC plasma; presetting a floating potential of the substrate surface to a reference potential; and capacitively coupling a periodic bias signal having a bias voltage referenced to the floating potential to the support stage, the periodic bias signal comprising: an activation phase having a positive voltage based on a known reaction threshold voltage of a target chemical bond of atoms on the substrate surface; a neutralization phase having a negative voltage; and An initialization phase with zero voltage; a step of capacitively coupling to the support stage; A method comprising:

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