Efficient image data delivery for an array of pixel driver memory cells - Patents.com

Abstract

A backplane design for delivering image data in an efficient manner to memory cells forming part of the pixel drivers includes a speed-matched word line design and column data register release signal delivery design, and a complementary bit line delivery design that is speed-matched to row decoder signal circuits that operate to pull the word line drivers into a state to enable the memory circuitry of that row to receive data from the row driver of each row. Because the circuit designs are substantially identical, the speed matching is effective over a range of operating temperatures.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of U.S. Patent Application No. 18 / 067,267, filed December 16, 2022, which is a continuation-in-part of U.S. Patent Application No. 17 / 354,419, filed June 22, 2021 (now U.S. Patent No. 11,538,431), which claims the benefit of U.S. Provisional Patent Application No. 63 / 045,252, filed June 29, 2020, all of which are incorporated by reference in their entireties herein.

[0002] This application is a continuation of U.S. Patent Application No. 17 / 568,831, filed January 5, 2022, which is a continuation-in-part of U.S. Patent Application No. 17 / 354,419 (now U.S. Patent No. 11,538,431), filed June 22, 2021, which claims the benefit of U.S. Provisional Patent Application No. 63 / 045,252, filed June 29, 2020, all of which are incorporated by reference in their entireties herein.

[0003] Technical Field The present disclosure relates to the efficient delivery of image data to pixel driver memory cells in the form of a single bit of data corresponding to a bit plane required to establish a modulation state for the duration of the bit plane, and more particularly to the delivery of image data to pixels of a pulse width modulated display. [Background technology]

[0004] The use of semiconductor backplanes as components for spatial light modulators is well known in the art. Microdisplays used to generate images observed by human viewers have been on the market for over 20 years and are well documented in the published and patent literature. Later applications have emerged in telecommunications devices where phase-matched spatial light modulators can be used to direct coherent light beams to desired locations using appropriate kinoforms (phase masks) implemented by modulating a liquid crystal layer. The backplane technology used for both classes of devices is often identical. Large format liquid crystal silicon microdisplays are particularly valuable. Silicon microdisplay liquid crystals are found in projection systems for business conference support, and in projectors for digital cinema. Large format phase-matched spatial light modulators (SLMs) based on the same silicon design can be used to expand the number of input beams that can be directed to different output ports of a telecommunications router.

[0005] Liquid crystal silicon devices have been implemented using silicon backplane designs based on memory elements. In an early example, Dr. Timothy Drabik, in his doctoral dissertation, Optically Interconnected Parallel Processor Arrays (Georgia Institute of Technology, Atlanta, GA, December 1989) (hereafter Drabik 1989), p. 125, discloses the use of SRAM as the basis for a pulse-width modulated 64 x 64 liquid crystal array, commonly referred to as a liquid crystal on silicon device or LCOS device. Drabik 1989 specifies that the SRAM can be written either by using byte-wide arithmetic, which can write a byte of data containing 8 bits to the eight memory cells of a selected row, or by using a row page mode, which can write all eight bytes of a row containing 64 memory cells when the selected row line (word line) is held high. Those skilled in the art of electronic design will recognize that byte wide mode requires that individual columns be addressable, whereas row page mode does not specifically require that capability, although row page mode is certainly compatible with that means of addressing data to columns.

[0006] Elsewhere in Drabik 1989, the paper notes in the same page two specific aspects of SRAMs implemented with the goal of accelerating their speed of operation. The first is the row page mode mentioned above, as it reduces the number of times a row's word line must be pulled high from eight to one. The second is the addition of an inverter circuit to isolate the six-transistor SRAM of each pixel driver from the incoming load from the pixel driver mirror. Drabik 1989 reports that this allows the retention time required to set the state of the SRAM circuit to be reduced from a few microseconds (μsec) to a few nanoseconds (nsec). Applicant notes that efforts to reduce the time required to accomplish a required action, such as writing data, have been ongoing since the early days of liquid crystal-on-silicon displays and spatial light modulators.

[0007] Applicant has previously developed a 4096x2400 aspect ratio (128x75 ratio) backplane composed of square pixel drivers with 3.74 micrometer (μm) pitch in both the horizontal and vertical directions. The target process for this development is a 130 nanometer (nm) process using copper circuitry and transistors under an aluminum pixel mirror, optionally with an intervening layer to prevent unwanted interactions between the two different metal layers. The pixel mirror not only functions to reflect light, but is driven by a voltage supplied by the underlying circuitry that corresponds to the desired modulation. The image diagonal of the array on the backplane is 0.70 inches (0.70"). One limitation of this resolution and process choice is that the maximum voltage range that can be spanned across the pixel mirrors is approximately 4 volts. A span of 5 volts or more is much more desirable, especially for phase-matched devices where the liquid crystal cell must be thicker, since the required phase modulation range is at least twice that required for amplitude-matched displays. This voltage limitation arises from the library of transistors available within the selected process, and the need to keep the pixel driver array area to an area range approximately equal to the square of the pixel display pitch. Furthermore, the row driver height and column driver width must be compatible with the pixel pitch in that dimension.

[0008] Applicant currently has U.S. Patent No. 7,443,374, the entire contents of which are incorporated by reference, which discloses pixel driver designs including a 6-transistor SRAM and other elements implemented in 250 nm, 180 nm, and 130 nm processes (see especially Figures 5-8, including the correction to Figure 6). There are other pixel drivers that may benefit from the present invention. For example, the pixel driver described in U.S. Patent No. 6,005,558, the entire contents of which are incorporated herein by reference, also relies on a one-bit SRAM memory cell to establish the modulation state of the pixel driver. The pixel driver of U.S. Patent No. 6,005,558 and the pixel driver of U.S. Patent No. 7,443,374 have roughly the same effect on the associated liquid crystal layer, but otherwise achieve this through substantially different means. Other pixel drivers that rely on one-bit SRAM or DRAM devices may benefit from the implementations described herein.

[0009] In this application, the terms wire, conductor, and line are presumed to mean a conductive medium such as aluminum, copper, or polysilicon, although other conductive mediums are within the scope of this disclosure. The use of the term terminal means a conductive medium that operates to connect to a node of a circuit element, such as a source, gate, or drain of a logic gate or transistor, or to the bulk of a semiconductor. The terms word line, wordline, and WLINE are all used by those skilled in the art and should be considered equivalent to one another. The terms row driver and wordline driver should be considered equivalent to one another. The terms bit line, bitline, and column line should be considered equivalent to one another. The terms column driver and bitline driver should be considered equivalent to one another. Summary of the Invention

[0010] It is therefore an object of the embodiments described herein to improve backplanes forming part of a display system by reducing the time required to load a plane of data into the backplane's pixel drivers. In particular, a device design that can reduce setup and hold time requirements compared to other designs allows data to be written to the storage elements of each pixel driver more quickly, and also allows the entire pixel driver array to be written more quickly. This means a higher overall data rate than would otherwise be possible. [Brief description of the drawings]

[0011] [Figure 1A] FIG. 2 shows a functional block diagram of a spatial light modulator backplane. [Figure 1B] 1 shows an electrical schematic diagram of an SRAM memory cell associated with a pixel driver array. [Figure 1C] FIG. 2 illustrates a functional block diagram of a portion of a row decoder circuit that operates to activate word lines of selected rows of SRAM memory associated with a pixel driver array. [Figure 1D] 1 shows a functional block diagram of a column driver that operates to configure complementary bit lines of a column of an SRAM memory associated with a pixel driver array. [Figure 1E] 1 shows a functional block diagram of a column driver that operates to configure complementary bit lines of a column of an SRAM memory associated with a pixel driver array. [Figure 2A] 1 shows a plan view of a memory cell of an SRAM memory annotated with a representation of the propagation delay. [Figure 2B] A 2x2 block of pixels showing path length differences is shown. [Diagram 3] 1 shows an equivalent circuit for the resistance and capacitance of a segment of a conductor in a semiconductor. [Figure 4A]1 shows a block diagram of a set of row release segments of a display, the set operative to provide release signals to AND gates of row drivers of the set; [Figure 4B] 1 shows a block diagram of a single row free segment of a display, the single row free segment operative to provide a free signal to an AND gate of a row driver of the segment; [Figure 4C] FIG. 2 shows a simplified block diagram of a pair of bit lines that together with a column driver and trigger circuit controller form part of an array of dummy pixel drivers. [Figure 4D] 1 illustrates a detailed block diagram of one tap circuit operative to deliver a release trigger signal to multiple AND gates. [Figure 5A] FIG. 2 shows a block diagram of a set of column release segments of a display, the set operative to provide release signals to circuit elements of a column driver of the set; [Figure 5B] FIG. 2 shows a block diagram of a single column release segment of a display, the single column release segment operative to provide release signals to circuit elements of a column driver of the segment; [Figure 5C] 1 illustrates a diagram of word lines and other circuit elements of a dummy driver array of a pixel driver that operates to send a trigger pulse to the bit line drivers to disable the release of stored data onto the bit lines. [Figure 5D] 1 shows a diagram of a section of a circuit that operates to receive a trigger pulse delivered via a dummy word line and deliver a trigger pulse to a column driver to release the data stored in the column driver onto the bit lines of that column. [Figure 6A] FIG. 1 is a block diagram of an arrangement of wordlines on a backplane divided into four vertical sections, each modulated by a different display controller. [Figure 6B] FIG. 6B is a block diagram of the right side of the block diagram of FIG. 6A with added detail. [Figure 6C]FIG. 1 is a block diagram of a pixel driver for a 2×2 array in which even and odd rows are modulated independently of each other. [Figure 6D] 1 illustrates an equivalent circuit for the resistance and capacitance of a segment of a conductor in a semiconductor, where the resistance and capacitance of a first portion of the segment differs from the resistance and capacitance of a second portion of the segment. [Figure 7A] FIG. 13 is a block diagram of the left half of an array of pixel drivers that includes two vertical sections of pixel drivers modulated by separate display controllers. [Figure 7B] FIG. 13 is an illustration of a time delay for delivery of data to a memory element of a pixel driver. [Figure 7C] FIG. 13 is an illustration of the time delay in a section of the display that is located further from its bit line drivers than other sections. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] A backplane may be configured with an array of pixel drivers (sometimes referred to as a pixel driver array) to drive pixels within a pixel contained in a display (a pixel display). The array of pixel drivers may include many individual pixel drivers. A pixel display (containing micro light emitting diodes (LEDs) or other emitters) is often coupled to the array of pixel drivers. The area of ​​the pixel display may coincide with the area of ​​the array of pixel drivers. An image may be displayed by driving individual pixels associated with the image through word lines (aligned in rows) and bit lines (aligned in columns) in the backplane, for example. For individual pixels in a display to properly display an image, it is important to deliver the image associated with the image of the individual pixels at the proper time using one or more pixel drivers. Additionally, it is important to drive the word lines and intersecting bit lines simultaneously with image data for the individual pixels in the pixel display.

[0013] A technical problem with known backplanes is that the backplanes cannot simultaneously drive wordlines and bitlines at very high speeds (e.g., frequencies) and / or with tight timing tolerances. Known backplanes often have buffer circuits (e.g., arrays of inverters, etc.) and / or timing circuits outside the pixel driver array that have metal lines, semiconductor device diffusions, connections to transistors, etc. that are subject to variations due to semiconductor processing, temperature, undesirable stray inductance, etc. In particular, components outside the pixel driver array of the backplane may respond differently to variations than components inside the pixel driver array of the backplane. Due to these variations, the timing, frequency, etc. of known backplanes are slowed down to widen the timing window to drive pixel displays with image data in a desired manner. In particular, the respective mismatch in the effects of variations on components inside and outside the pixel driver array of the backplane may require, for example, a widening of the timing window of the backplane in order for the backplane to properly drive the corresponding pixel displays. In other words, the timing windows are adjusted to account for discrepancies in the respective effects of variations on components inside and outside the pixel driver array of the backplane associated with the pixel display.

[0014] The technical solution described herein (sometimes referred to as resistive-capacitive (RC) tracking) includes a backplane circuit configured to eliminate mismatching effects of variations in the backplane due to semiconductor processing, temperature, undesired stray inductance, etc. on components inside and outside the backplane, specifically the pixel driver array. This is sometimes referred to as RC tracking because variations (due to semiconductor processing, temperature, etc.) of components outside the pixel driver array track variations of components inside the pixel driver array. Because the components outside the pixel driver array can be identical (mirrored) to the components inside the pixel driver array (except for being disabled or deactivated), the RC characteristics can be matched or mirrored between the components outside and inside the pixel driver array. Specifically, the backplane circuitry includes an array (or a portion thereof) of dummy pixel drivers (e.g., data storage elements such as static random access memories (SRAMs) associated with one or more pixel drivers) aligned along a bit line direction (which may be referred to as dummy bit lines) outside the pixel driver array (e.g., pixel driver array region) and within a word line path of the pixel driver array (e.g., within a row select path of the word line path). The backplane circuitry also includes an array (or a portion thereof) of dummy pixel drivers (e.g., data storage elements such as static random access memories (SRAMs) associated with one or more pixel drivers) aligned along a word line direction (which may be referred to as dummy bit lines) outside the pixel driver array (e.g., pixel driver array region) and within a bit line path of the pixel driver array (e.g., within a data load trigger path of the bit line path). In some implementations, the array of dummy pixel drivers may include only a portion (e.g., copied portion) of the actual (or active) pixel drivers (e.g., only the data storage elements (or disabled versions (e.g., deactivated versions) of the data storage elements) of the pixel drivers).These arrays of dummy pixel drivers (e.g., dummy bit line pixel driver arrays, dummy word line pixel driver arrays) that are outside of the pixel driver array (e.g., the active pixel driver array) and are used to transmit image data to pixels using the pixel driver array mirror the configuration of the word lines and bit lines in the pixel driver array. By doing this, variations in semiconductor processing, temperature, etc. that affect backplane components outside the pixel driver array that drive the word lines and bit lines inside the pixel driver array can affect the actual word lines and bit lines inside the pixel driver array as well as the backplane components outside the pixel driver array.

[0015] At least one technical effect of the configurations described herein is that a backplane can use a pixel driver array at very high speeds and / or with tight timing tolerances to drive a pixel display, even in the presence of variations. In particular, variations that may affect the pixel driver array will similarly affect components of the backplane outside the pixel driver array, and the timing tolerances will change with the variations. The operating windows of components inside and outside the pixel driver array of the backplanes described herein do not need to be expanded to account for variations in the backplane components outside the pixel driver array, and variations in the components of the actual pixel driver array (e.g., word lines, bit lines) to operate at high speeds and / or with tight timing tolerances.

[0016] Further details relating to the array and timing of the dummy pixel drivers are described in connection with at least Figure 2A. Components contained within the pixel driver array and external to the pixel driver array of the backplane are described in at least Figures 1A-1E.

[0017] 1A shows a functional block diagram including the data transfer section of a spatial light modulator (SLM) 100. The SLM 100 includes a pixel driver array 101, a left row decoder and driver assembly 105l, a right row decoder and driver assembly 105r, a left write signal control section 106l, a right signal control section 106r, a column data register array 104, a control block 103, and a wire bond pad block 102. The wire bond pad block 102 is configured to allow contact with an FPCA (flexible printed circuit assembly) or other suitable connection means to receive data and control signals over lines from an SLM controller (not shown). The data and control signal lines include a clock signal line 111, an opcode signal line 112, a serial input / output signal line 113, a bidirectional temperature signal line 114, and a parallel data signal line 115. In FIG. 1A , the left row decoder and driver assembly 105l, the right row decoder and driver assembly 105r, and / or the column data register array 104 may include one or more dummy pixel drivers (e.g., dummy data storage elements associated with a pixel driver) in accordance with embodiments described herein.

[0018] A bidirectional clock signal line 111 provides a clock signal from an external control device (not shown) that operates in conjunction with the clock to deliver data to the SLM. In one embodiment, both rising and falling clock edges are used.

[0019] A serial input / output line 113 provides data from an external control device (not shown) which operates to configure the SLM to a required operating condition. A bidirectional temperature signal line 114 provides data from an external control source (not shown) to set a temperature measurement circuit (not shown) within the SLM to a desired operating condition and to transmit information from the temperature measurement circuit to the external control source.

[0020] The wire bond pad block 102 receives image data and control signals and passes these signals to the control block 103. The control block 103 receives the image data and passes the image data to the column data register array 104. The row address information is sent to the row decoder left 105l and row decoder right 105r. In one embodiment, only one row decoder is used for the entire array. In one embodiment, the value of the opcode line 112 determines whether the data received on the parallel data signal lines 115 is address information indicating the row to which data is to be loaded or address information indicating the data to be loaded into the row. In one embodiment, the row address information appears first in the time ordered sequence and acts as a header followed by the data for that row. In the context of this application, the word "address" is most often a noun used to communicate the location of the row to be written. The location may be communicated as an offset from a baseline row location (address) or it may be the absolute location of the row to be written. This is similar to the way random access memory devices such as SRAMs are written to or read from. The use of column addressing, also used in random access memory devices, may be envisaged, although other mechanisms such as shift registers are also envisaged. The use of shift registers to enable writing of data to rows of the array is also envisaged.

[0021] The row decoder and driver assembly left 105l and row decoder and driver assembly right 105r include a set of circuits that operate to pull the word lines of a row decoded using row driver circuits (not shown) high so that data for that row can be transferred from the column data register array 104 to storage elements residing in the pixel drivers of a selected row of the pixel driver array 101. In one embodiment, the row decoder and driver assembly left 105l applies signals that operate to pull the word lines high for the left half of the display, and the row decoder and driver assembly right 105r pulls the word lines high for the right half of the display. In one embodiment, the output of the row decoder. In one embodiment, the circuitry of the row decoder and driver assemblies 105l and 105r includes an AND gate in each row (not shown) that operates to receive a trigger signal from a circuit (not shown) that receives a signal from the row decoder circuit and operates to deliver a trigger signal to all AND gates of all rows. Only the AND gate of the selected row receives two high signals and delivers a high signal output. In one embodiment, the row decoder and driver assemblies 105l and 105r include voltage level shifting circuits.

[0022] Blocks 106l and 106r represent trigger release circuits that operate to deliver, for each pixel driver of a selected row, a trigger signal for pulling the word line in the selected row high, and a separate trigger signal for releasing the data stored in the memory cell of the bit line driver to the complementary bit line. In one embodiment, the signal from the trigger release circuits 106l and 106r forms one input to an AND gate (not shown) that has as a second input a signal from the row decoder logic blocks 105l and 105r. This provides greater temporal control over the timing of pulling the word line high. The trigger release circuits 106l and 106r can also be considered release timing circuits.

[0023] FIG. 1B illustrates one embodiment of a data storage element 120 forming part of a pixel driver. In other words, the data storage element 120 illustrated in FIG. 1B can be associated with or included in one or more pixel drivers of the pixel driver array 101 illustrated in FIG. 1A. The data storage element 120 is preferably a CMOS static RAM (SRAM) latch device. Such devices are well known in the art. See DeWitt U. Ong, Modern MOS Technology, Process, Devices, & Design, 1984, Chapter 9, Section 5 (hereinafter Ong 1984), the details of which are fully incorporated herein by reference. See also Drabik 1989, page 126, Figure 7.11, cited above. A static RAM is one that retains data as long as power is applied, but the clock is not running. FIG. 1B illustrates the most common implementation of an SRAM memory cell, in which six transistors are used. MOSFET transistors 128, 129, 130, and 131 are n-channel transistors, while MOSFET transistors 132 and 133 are p-channel transistors. In this particular design, word line 121, when held high, applies a voltage to the gates of pass transistors 128 and 129 via terminals 122 and 123, respectively, (B POS )124 line and (B NEG ) 125 line remains in a precharged high state or is discharged to a low state by the flip-flop (i.e., transistors 132, 133, 130, and 131). Differential sensing of the state of the flip-flop is then possible in read mode. When writing data to a selected cell, the (B POS )124 and (B NEG ) 125 is forced high or low by additional write circuitry including column drivers (not shown). The low side is the most effective side for causing the flip-flop to change state. POS The data on 124 is asserted via terminal 126 to the source of pass transistor 128,NEG The data on 125 is asserted to the source of pass transistor 129 via terminal 127. The gate voltage applied to transistors 131 and 133 via conductor 134 is asserted to the drain of the transistor and to the source of transistor 130 via conductor 139. The gate voltage applied to transistors 130 and 132 via conductor 137 is applied to the drain of transistor 133 and to the source of transistor 131 via conductor 138. In one embodiment of the present application, two output ports 134 and 137 are required to relay to the rest of the pixel driver circuitry whether the SRAM data set is in an "on" or "off" state. In some embodiments, only one output port is required. Line (B POS )124 and (B NEG ) 125 are commonly referred to as bit lines or bitlines.

[0024] Data storage element 120 receives a V DDAR and V on bus 136. SS Connected to V DDAR is the V of the array DD It is common practice to use lower voltage transistors for peripheral circuits such as backplane I / O circuits and control logic for a variety of reasons, including reduced EMI and the reduced circuit size this allows. Other voltage differentials may be implemented for a variety of reasons too numerous to mention briefly.

[0025] Six-transistor SRAM cells are desirable in CMOS-type design and manufacture because they require the least amount of detailed circuit design and process knowledge and are the safest with respect to noise and other effects that may be difficult to estimate before silicon is available. Furthermore, current processes are dense enough to allow for large static RAM arrays. These types of storage elements are therefore desirable in the design and manufacture of liquid crystal silicon display devices as described herein. However, other types of static RAM cells, such as four-transistor RAM cells that use NOR gates, as well as those that use dynamic RAM cells rather than static RAM cells, are contemplated by the embodiments described herein.

[0026] The convention in examining the output ports of an SRAM is to refer to the outputs as complementary signals S_pos or S POS and S_neg or S NEG The output of data storage element 120 is shown as connecting the gates of transistors 133 and 131 via conductor 134. By convention, this side of an SRAM is usually called the S NEG The gates of transistors 132 and 130, connected via conductor 137, are typically referred to as S POS Either side can be used to provide a data source. In the case of the above-cited U.S. Patent No. 7,443,374, both sides are used with additional circuitry to select one or the other of the two outputs depending on the DC balance state.

[0027] In some implementations, data storage element 120 may include other circuit elements, such as drivers, inverters, etc. Such circuit elements may be coupled to conductors 138 and / or conductors 139, for example.

[0028] In some implementations, the data storage element 120 may be included in a dummy bit line (e.g., in a row select path) and / or a dummy word line (e.g., in a data load trigger path). In other words, the data storage element 120 may be included in a dummy bit line to be or simulate a pixel driver (or at least a portion thereof) and / or in a dummy word line to be or simulate a pixel driver (or at least a portion thereof).

[0029] When included in a dummy bit line and / or a dummy word line, the data storage element 120 shown in FIG. 1B can be modified to be inoperable. When modified to be inoperable, the data storage element 120 may be referred to as a disabled data storage element or a deactivated data storage element. In other words, a disabled data storage element may be disabled such that the data storage element cannot be programmed or cannot store information (e.g., cannot be used as a storage element). For example, the word line 121 can be coupled to ground or VSS such that the data storage element does not function properly as an SRAM device. As another example, the terminal 122 (coupled to the gate of the pass transistor 128) can be coupled to ground or VSS such that the data storage element does not function properly as an SRAM device. As yet another example, the bus 135 can be coupled to ground or VSS such that the data storage element does not function properly as an SRAM device. In some implementations, the word line 121, the terminal 122, and / or the bus 135 can be coupled to ground or VSS such that the data storage element does not function properly as an SRAM device. However, the RC characteristics of the disabled data storage element will be the same as the RC characteristics of an active SRAM device or active data storage element 120 .

[0030] FIG. 1C shows a block schematic diagram of row drivers 140a, 140b of a device that includes multiple rows of SRAM memory cells (not shown) or similar memory cells, each forming part of a pixel driver. Row drivers of DRAM circuits are similar to row drivers 140a, 140b. Row drivers 140a, 140b may also be referred to as word line drivers. An array of row drivers, such as row driver 140a, may be included in or function as a row selection path, such as the path shown and described in connection with FIG. 2A. The illustrated row drivers 140a, 140b are shown as driving two rows. Many additional rows are possible. In one product, applicants have 2464 rows, each with an individual row driver. Row drivers 140a, 140b include row decoder logic 141, AND gates 116a and 116b, voltage level shifters 142a and 142b, and inverters 143a and 143b. The row decoder logic 141 operates to select every single row of an array of SRAM memory cells, such as those associated with pixel drivers in pixel drive array 101 of Figure 1A, based on address information provided to the backplane. In one embodiment, address information identifying the row to which data is to be written is provided along with the data to be written to that row.

[0031] Row decoder logic 141 may be one of several types of row decoders well known in the art of random access memory (RAM) design. Row decoder logic 141 is connected to a voltage source (not shown) via conductor 144. The voltage source is V DD or a different voltage source V DD_IO or a third type of voltage source, V, selected by the designer. DD_RD In one embodiment, the voltage supply of the row selector is lower than the voltage supply present in the pixel driver array. The row decoder 141 is connected to the V SS Connected to the common V SS However, different circuit sections have different V DD It is common practice for voltage to be used across sections of a device.

[0032] Generally, row decoders are limited to four NAND gates because the more NAND gates used, the more electrically complex and unacceptably slow the resulting circuit becomes. To achieve the functionality required across a large number of rows, the decoding is then split into pre-decoders that provide input to a series of decoder circuits. This is well known and proven, so will not be repeated here. See, for example, VLSI-Design of Non-Volatile Memories, G. Camardo, et al, pp. 185-188, especially the bottom of page 187, Springer Verlag, Berlinet al, 2005 (hereafter Campardo 2005).

[0033] The row decoder logic 141 operates to provide voltages as inputs to AND gate 116a, and to AND gate 116b, and to all other rows from the entirety of the rows of the SRAM. Only one AND gate receives a high voltage from the row decoder circuit, indicating that the row is the selected row. All AND gates, whether 116a, 116b, or another AND gate not shown here, are also connected to a trigger source (not shown) by a trigger gate line 117 (sometimes called an enable line). When the trigger gate line 117 receives a high voltage, indicating a trigger, that voltage is applied to all AND gates. Only the AND gates of the selected row fully meet the requirements of the AND gate logic and deliver an on-state voltage to their output. The addition of the AND gates reduces any uncertainty regarding the timing of the triggering of the word lines (WLINEs). In one embodiment, AND gates 116a, 116b, and all other AND gates (not shown) include pairs of pass transistors in series.

[0034] In one embodiment, the AND gates 116a and 116b are replaced by a logic circuit after the logic circuit 165 of the column driver 160 of FIG. 1D. The logic circuit 165 can be either a level-sensitive D-flip-flop or an edge-sensitive D-latch. AND gates, D-flip-flops, and D-latches are all types of logic circuits. Appropriate inverters, voltage level shifters, and other small mirror circuits (not shown) may be required to reach the required voltage polarities and voltage levels.

[0035] In one embodiment, the output of AND gate 116a is connected to voltage level shifter 142a via terminal 119a. The output of AND gate 116b is connected to voltage level shifter 142b via terminal 119b. Similarly, each of the remaining AND gates is connected to a voltage level shifter via a voltage conducting means such as a terminal, conductor, or wire. The use of voltage level shifters is preferred when a section of a device, such as an array of memory cells that operates to drive pixels in a pixel display, requires a particular voltage range that may differ from the input / output circuitry or periphery.

[0036] Voltage level shifter 142a receives a signal from AND gate 116a via terminal 119a, and voltage level shifter 142b receives a signal from AND gate 116b via terminal 119B. All other voltage level shifters (not shown) each receive a signal from their respective AND gate via a terminal. All these signals are 0 except for the signal from the one selected row. The voltage level shifters 142a, 142b and all other voltage level shifters (not shown) associated with the row drivers are connected to V DD_WL (V DDThe outputs of voltage level shifters 142a and 142b are connected to inverters 143a and 143b, respectively. The outputs of all other voltage shifters (not shown) that form part of the row driver are similarly connected to inverters. The output of inverter 143a is asserted on conductor 148a and the output of inverter 143b is asserted on conductor 148b. All other inverters (not shown) are similarly asserted on a conductor and on a feedback conductor. In one embodiment, conductor 148a, conductor 148b and all other similarly driven conductors are the word lines (WLINEs) of the array of pixel drivers.

[0037] In one embodiment of each row driver, a voltage level shifter is provided whose source is connected to the voltage source V DD_WL and its drain connected to the output of the AND gate. In that same embodiment, each inverter includes a p-channel transistor in series with an n-channel transistor, the input to each transistor being a signal from the row driver AND gate to the gates of both transistors, and the source of the p-channel transistor is connected to V DD_WL and the drain of the n-channel transistor is connected to ground (V SS ). The output of the inverter is connected to a word line and to the gate of a p-channel transistor of a voltage level shifter (not shown). A detailed description of voltage shifters and their use in row drivers is given in Campardo 2005 (cited above) pp. 184-187. Voltage level shifter designs that operate to shift voltages down and up are within the scope of the present invention.

[0038] In one embodiment, the output of the level shifter is a voltage V DD_AR Lower voltage (V DD_ARRAY). Operating the word lines at less than their maximum possible voltage provides an effective means of lowering the overall power of the array, thereby reducing any residual heating that may result. This may require that pass transistors in the memory circuits of the pixel driver array, similar to pass transistors 128 and 129 of data storage element 120 (FIG. 1B), be adapted to conduct when that voltage is applied to their gates.

[0039] The capacitance to the word lines (WLINE) places a strong load on the row driver design. Inverters 143a and 143b act to buffer row drivers 140a, 140b from the effects of high capacitance loads. The nature of the capacitance to the word lines is explained in more detail with respect to FIG.

[0040] As shown in FIG. 1C, when included in a dummy bit line (e.g., in a row select path), the row drivers 140a, 140b can be connected to an array of dummy drivers 198a (e.g., an array of dummy drivers 198a including disabled data storage elements). As mentioned above, the disabled data storage elements may be at least modified versions of the data storage elements 120 shown in FIG. 1B. The array of dummy drivers 198a is shown in dashed lines because these elements are optionally included with the row drivers 140a, 140b when included in a dummy bit line. The array of dummy drivers 198a introduces an RC characteristic along the trigger gate lines 117 (which may also be referred to as enable lines), for example, when in a row select path (or dummy bit line) that mirrors the RC characteristic of the bit lines in a pixel driver array (e.g., pixel driver array 101 shown in FIG. 1C). The array of dummy drivers 198a may be substantially identical to the configuration of the bit lines, except that they are disabled (e.g., have data storage elements disabled) so that the RC characteristics of the array of dummy drivers 198a replicate as closely as possible the RC characteristics of the active bit lines in the active pixel driver array.

[0041] In this exemplary implementation, row drivers 140a, 140b (which may be referred to as a set or section of row drivers) are connected at tap 197a-1 from an array of dummy drivers 198a (e.g., dummy bit line drivers). In this implementation, an inverter is optionally connected between tap 197a-1 and row drivers 140a, 140b. Row drivers 140a, 140b and the array of dummy drivers 198a may be located outside of an active pixel driver array (e.g., pixel driver array 101 shown in FIG. 1A). Another section of row drivers (not shown) may be connected to the array of dummy drivers 198a via tap 197a-2. Row drivers 140a, 140b may be included in a section of row drivers that includes two or more row drivers.

[0042] Figure 1C shows an array of dummy drivers 198b parallel to the array of dummy drivers 198a. One or more sections of row drivers (not shown) can be tapped from the array of dummy drivers 198b. An implementation of an array of dummy drivers (e.g., a parallel array of dummy drivers) and a section of a row driver associated with (e.g., outside of) a pixel driver array tapped from the array of dummy drivers (described in Figure 1C) is described in more detail at least in Figure 7B.

[0043] 1D illustrates a column driver 160. The column driver 160 includes memory cells 163 operative to store bits of data, an optional voltage level shifter 164 operative to shift a peripheral voltage to a bit line voltage, and logic circuitry 165 operative to receive the data voltage and assert complementary voltages through intermediate circuitry to data output terminals 168 and 177 in response to a data clock signal asserted on terminal CLK 166. In one embodiment, the data clock signal asserted on terminal CLK 166 is a trigger signal transmitted from a trigger control circuit (not shown) on the backplane. Other names for the clock CLK are release REL and enable EN.

[0044] Memory cell 163 receives and stores bits of image data for a plane of image data from an external source. The stored data is asserted at terminal 175, which asserts the data value to voltage level converter 164. Voltage level converter 164 asserts a converted data voltage level at terminal 174, which asserts the data voltage to data terminal D of logic circuit 165. In one embodiment, voltage shifter circuit 164 is replaced with a straight conductor. In one embodiment, logic circuit 165 is a circuit with two stable states. The voltage asserted at data terminal D is asserted at Q, and its complement is asserted at terminal Q. - (Q with overline). The voltage asserted at terminal Q is asserted at output terminal 167. - is unused. Output terminal 167 then asserts the value of terminal Q to inverter 161a. The output of inverter 161a is asserted to the input of inverter 161b, whose output holds the same logical value as the input to inverter 161a. Together, inverters 161a and 161b form a buffer which acts to isolate column driver 160 from the capacitive load present on the complementary bit line. The output of inverter 161b is asserted to bit line 168 and to the input to inverter 176. The output of inverter 176 is asserted to bit line 177, which logically forms a complementary bit line pair with bit line 168.

[0045] Logic circuit 165 allows system level control over the timing of the release of image data onto the bit lines of the drive columns of the array of active pixel drivers. Several types of circuits provide the required functionality. Two circuits that are particularly suitable are the D-latch and the D-flip-flop. (The letter D in the two circuit names can stand for either Data or Delay. Both names refer to the same circuit characteristics.) Not all sources distinguish between latches and flip-flops. In this application, the distinction between D-latch and D-flip-flop is maintained.

[0046] The D latch has a data input node D, a clock node CLK, and output nodes Q and Q. - When CLK is high, the data asserted at D is the data value asserted at Q, and its complement is Q. - If the value asserted on D changes while CLK is high, then Q and Q - The asserted value also changes.

[0047] In contrast, the D flip-flop is a clock edge sensitive circuit. The input and output nodes are the same as a D latch, except that when a rising clock edge is detected, the data value asserted at input D is asserted at Q, and its complement is asserted at Q. - If the data value asserted at input D later changes, Q and Q - The output asserted to does not change until another rising clock edge is detected. A falling clock edge has no effect on the output. However, there are similar circuits that trigger on a falling clock edge but not on a rising clock edge. For this application, the clock edge for enabling the circuit is assumed to be a rising edge with the understanding that alternative implementations fall within the scope of this disclosure. For further reference, 14-Flip-flops.pdf (author unknown) Class presentation for CSE370, Lucch 14, University of Washington, 2008, pages 2-5 provides useful information.

[0048] In one embodiment, the logic circuit 165 may be replaced with an AND gate, such as AND gate 116a or 116b of the word line driver assembly 140a, 140b of FIG. 1C. An exemplary column driver 160 with AND gate 169 is shown in FIG. 1E. The operation of AND gate 169 is similar to that of the D-latch version described for logic circuit 165 of FIG. 1D. In fact, both are logic circuits, similar to the D-flip-flop described above. AND gate 169 (and other AND gates in the column driver (not shown) collocated with column driver 160) are also connected to a trigger source (not shown) by a trigger gate line 118 (sometimes called an enable line). Appropriate inverters, voltage level shifters, and other minor circuitry (not shown) may be required to arrive at the required voltage polarity and voltage levels.

[0049] One problem that frequently arises in array design is propagation delay, also known as path propagation delay. As mentioned above, applicants have developed an array with over 9.8 million pixels (4096 x 2400). The intersection of each row with each column represents two unique paths.

[0050] As shown in FIG. 1E, when included in a dummy word line (e.g., in a data load trigger path), the column driver 160 (or multiple column drivers) can be connected to an array of dummy drivers 199a (e.g., an array of dummy drivers 199a including disabled data storage elements). As mentioned above, the disabled data storage elements may be at least modified versions of the data storage elements 120 shown in FIG. 1B. The array of dummy drivers 199a is shown in dashed lines because these elements are optionally included with the column driver 160 when included in a dummy word line. The array of dummy drivers 199a introduces an RC characteristic along the trigger gate line 118 (which may also be referred to as an enable line), for example, when in a data load trigger path (or dummy word line) that mirrors the RC characteristic of a word line in a pixel driver array (e.g., the pixel driver array 101 shown in FIG. 1A). The array of dummy drivers 199a may be substantially identical to the configuration of the word lines, except that they are disabled (e.g., have data storage elements disabled) so that the RC characteristics of the array of dummy drivers 199a replicate as closely as possible the RC characteristics of the active word lines in the active pixel driver array.

[0051] In this exemplary implementation, the column driver 160 (which may be included in a set or section of column drivers (not shown)) is connected at tap 196a-1 from an array of dummy drivers 199a (e.g., dummy word line drivers). In this implementation, an inverter is optionally connected between tap 196a-1 and the column driver 160. The column driver 160 and the array of dummy drivers 199a may be located outside the active pixel driver array (e.g., pixel driver array 101 shown in FIG. 1C). Another section of column drivers (not shown) may be connected to the array of dummy drivers 199a via tap 196a-2. The column driver 160 may be included in a section of column drivers that includes multiple column drivers.

[0052] Figure 1E shows an array of dummy drivers 199b parallel to the array of dummy drivers 199a. One or more sections of column drivers (not shown) can be tapped from the array of dummy drivers 199b. An implementation of an array of dummy drivers (e.g., a parallel array of dummy drivers) and a section of a column driver associated with (e.g., outside of) a pixel driver array tapped from the array of dummy drivers (illustrated in Figure 1E) is described in more detail at least in Figure 7B.

[0053] As shown in FIG. 2A, the first path is a row select path 261 (also called a dummy bit line) coupled with a word line 262 for a row, hereafter referred to as word line path 260. The row select path 261 is a first portion of the word line path 260, and the word line 262 is a second portion of the word line path 262. The row select path 261 is disposed outside the pixel driver array 150 (e.g., outside the area of ​​the pixel driver array 150). The row select path 261 is aligned along the bit line direction (the vertical direction shown in FIG. 2A). The row select path 261 may include an array of dummy drivers and row drivers, for example, as shown in FIG. 1C. Several types of circuits are known that allow for the selection of a single row of a memory device. Often, the row is specified by an address location that causes a row decoder to select that particular row before a signal is sent to the row to pull the word line 262 high. The output of the row decoder enters an AND gate configured to receive a separate trigger signal that is delivered to all AND gates that can receive the row decoder output. The word line 262 itself forms a second portion of the word line path 260, including the physical distance from the row driver (e.g., row driver 140a shown in FIG. 1C) along the word line 262 to the target pixel driver 280. All trigger signal generation circuits (also referred to as trigger initiation circuits 250) may function as release timing circuits.

[0054] The second path is the bit line path 270. The bit line path 270 includes a data load trigger path 271 (e.g., a first portion of the bit line path) that delivers a voltage to a circuit in the bit line driver that releases data stored in the bit line driver to the array of the display, and a complementary bit line (e.g., bit line 272, which is a second portion of the bit line path) to the target pixel driver 280. In other words, the data load trigger path 271 is the first portion of the bit line path 270, and the bit line 272 is the second portion of the bit line path 270. The data load trigger path 271 is disposed outside the pixel driver array 150 (e.g., outside the area of ​​the pixel driver array 150). The data load trigger path 271 may also be referred to as a dummy word line. The data load trigger path 271 is aligned along the word line direction (horizontal direction shown in FIG. 2A). The data load trigger path 271 may include, for example, an array of dummy drivers and column drivers shown in FIG. 1E.

[0055] 2A, for purposes of illustrating propagation delays, a pixel driver array 150 (e.g., an SRAM array) is shown that is m columns wide by n rows high. In this example, the trigger signals (from trigger initiate circuit 250) for the release of image data onto the bit lines (e.g., bit line 272) and for activating circuitry associated with the row driver to pull word line 262 high are presumed to originate at the trigger initiate circuit 250 proximate the lower left corner of driver array 150 at coordinates (0,0).

[0056] It should be understood that the trigger signal may originate at multiple locations from one or more trigger initiation circuits (e.g., trigger initiation circuit 250). For example, a first location may be proximate a lower left corner of pixel driver array 150 in a trigger initiation circuit (similar to trigger initiation circuit 250), a second location may be proximate a lower right corner of pixel driver array 150 in a trigger initiation circuit, where the lower left trigger initiation circuit in the first location may process the left half of pixel driver array 150, and the lower right trigger initiation circuit in the second location may process the right half of pixel driver array 150. In some implementations, the trigger signal may originate from a location above pixel driver array 150, the upper left corner of pixel driver array 150, and / or the upper right corner of pixel driver array 150.

[0057] Considering the word line path above, the time from when a trigger signal is sent from the trigger initiation circuit 250 along the row select path (e.g., a first portion of the word line path) to an AND gate adjacent to coordinate (0,0) until the trigger signal reaches an AND gate adjacent to coordinate (0,y) is denoted as TR1. TR1 represents the time it takes for the trigger signal to propagate along the row select path from a point adjacent to coordinate (0,0) to coordinate (0,y). Using distance to represent time is appropriate because the propagation delay along the row select path has uniform characteristics when the circuitry carrying the signal in that portion of the row select path is uniform and repeatable.

[0058] The second part of the word line path is the word line. The word lines of an array of SRAM type memory cells are connected to the gates of pass transistors, such as transistors 128 and 129 of data storage element 120 of FIG. 1B. The resistance of the word line and the capacitance of the word line and its connections to the pass transistors define the RC characteristics of the word line and therefore the propagation delay of the word line. The RC characteristics of the word line may be different from the RC characteristics of the line along which the trigger signal propagates, which is used as an input to the AND gates in each row driver.

[0059] If the pixel driver pitch in the x direction is uniform X units of distance horizontally across the display, and the pixel driver pitch in the y direction is uniform Y units of distance vertically on the display, then a pixel driver position (x,y) is at a physical position relative to the origin at (0,0) that is x times X units of distance horizontally and y times Y units of distance vertically. The choice of distance units is arbitrary, but most modern pixel drivers are specified in microns, or millionths of a meter, from center to center.

[0060] The same considerations can be applied to other display shapes, such as parallelograms, provided that opposing sides, such as a diamond, are of equal length and parallel. The same considerations can also be applied in a modified form to displays that have a pixel driver format that is anamorphic in one of the major axes, the main difference being that the pixel driver pitch in that axis is not uniform, necessitating the use of other types of distance calculations, such as lookup tables.

[0061] There are other delays inherent in logic components such as AND gates, voltage level shifters, and inverters, such as that of row driver 140a in Figure 1C. These delays are of uniform characteristics for each row and do not vary from row to row, making the delays predictable in that all pixel drivers in all rows have the same delays from their sources inherent to them.

[0062] As an example, consider a pixel driver at coordinate (x,y) in FIG. 2A. The pixel driver in the row immediately below is located at coordinate (x,y-1), and the pixel driver in the row immediately above is located at coordinate (x,y+1). The time it takes for a signal to propagate from (0,y) at the left edge of the array to coordinate (x,y) is the same as the time it takes for the signal to propagate from coordinate (0,y-1) to coordinate (x,y-1) and the time it takes for the signal to propagate from coordinate (0,y+1) to coordinate (x,y+1). The time it takes for the signal to propagate from coordinate (0,0) to coordinate (0,y) is longer than the time it takes for the signal to propagate from coordinate (0,0) to coordinate (0,y-1), but is less than the time it takes for the signal to propagate from coordinate (0,0) to coordinate (0,y+1). This arises from the difference in path length along the Y axis.

[0063] The time from when the trigger signal to the column driver to release complementary data onto the bit lines is initiated by the trigger initiation circuit 250 to its arrival at the column driver, and the time from the release of the data from the column driver to the data reaching the target pixel driver 280(x,y) in the array both take a variable amount of time, the variation depending primarily on the length of the row select and word line paths and the individual RC (resistance and capacitance) characteristics of the circuits that form the two segments it propagates through.

[0064] The first portion of the bit line path that brings the trigger signal from the trigger initiation circuit 250 to the column driver extends from coordinates (0,0) to (x,0) along the data load trigger path that is along the X-axis of the array 150. The time it takes for the signal to propagate that distance along the data load trigger path is denoted as TB1. The duration of TB1 is determined by the RC characteristics of the data load trigger path (e.g., the conductors of the data load trigger path) along which the trigger signal propagates. The RC characteristics are in turn determined by the physical characteristics of the data load trigger path, including resistive and capacitive coupling components, and the physical characteristics of any transistor nodes along the path, including primarily capacitive coupling components. This can be thought of as a network. In some implementations, the actual voltage of the trigger signal does not affect the RC characteristics of the network.

[0065] The second part of the bit line path, delivering the bit line data to the target pixel driver 280, begins when the bit line data is released from the column driver. There is an inherent delay within the column driver that is the same for all columns. The propagation delay from when the data is released onto the bit line of the target pixel driver 280 until the data reaches the target pixel driver 280 on the selected bit line depends on the bit line characteristics, i.e., RC delay, as well as the distance from the column driver to the target pixel driver. For analysis purposes, the time delay is referred to as TB2. TB2 is the time it takes for the bit line data to propagate along the bit line from coordinate (x,0) to coordinate (x,y) of the target pixel driver 280.

[0066] In some implementations, the additional delays due to various logic circuits can be summarized as TB3 (not shown) and treated as a constant value that is independent of the location of the pixel driver. The total delay due to the propagation delay from the trigger source to the target pixel driver 280, TB TOT (not shown) is TB TOT=TB1+TB2+TB3. The word line path begins with a path from the second trigger start (trigger start circuit 250) that delivers a trigger signal up the side of the display along the row select path from coordinate (0,0) to coordinate (0,y). The row select path is slightly outside the array but parallel to the Y axis as shown. The time it takes for the trigger signal to propagate along this row select path (which is the first part of the word line path) is TR1. The duration of TR1 is determined by the RC characteristics of the line that the trigger pulse propagates along to reach the row driver at coordinate (0,y), as described above. The second part of the word line path is the word line itself. The word line on the selected row is pulled high when the trigger signal reaches an AND gate that forms part of the row driver. The propagation time, TR2, is determined by the RC characteristics of the word line.

[0067] In some implementations, the additional delays due to various logic circuits can be summarized as TR3 (not shown) and treated as a constant value that is independent of the location of the pixel driver. The total delay TR due to the propagation delay from the trigger source to the target pixel driver 280 TOT (not shown) is TR TOT =TR1+TR2+TR3.

[0068] 2A, the physical length associated with path TB1 added to the length of path TB2 is substantially equal to the physical length associated with path TR1 added to the length of TR2. Another feature is that the physical length associated with TR1 is substantially equal to the physical length associated with TB2, and the physical length associated with TR2 is substantially equal to the physical length associated with TB1.

[0069] Note that the RC characteristics associated with the TR1 path do not necessarily match the RC characteristics associated with the TR2 path, and the RC characteristics associated with the TB1 path do not necessarily match the RC characteristics associated with the TB2 path. If both the RC characteristics and physical length associated with a first circuit are substantially equal to the RC characteristics and physical length associated with a second circuit, then the propagation delays along the two circuits will be substantially equal.

[0070] Based on the above observation that the physical path length associated with TR1 is substantially equal to the physical path length associated with TB2, it follows that the propagation delays associated with the two physical paths may result in similar propagation delays if the RC characteristics of the two physical paths are substantially the same. The same considerations regarding RC characteristics apply to the path length associated with TR2 and the path length associated with TB1. The difficulty is to identify a means by which the total length of the circuitry carrying the trigger signal to the row decoder can be RC matched to the bit lines that function as the circuitry for carrying data to the pixel drivers of the selected row.

[0071] This, and similar considerations regarding the path lengths associated with the trigger signals to the column drivers and the RC matching between the word lines from the row decoder to the target pixel driver 280(x,y) are addressed in this application. In other words, stated differently, it is important that the equation TR1+TR2=TB1+TB2 is substantially satisfied. The design procedure disclosed in this application supports achieving that result.

[0072] RC matching is the subject of significant development efforts in semiconductor device design. Much of the research is directed toward design techniques and practices that reduce the effects of any mismatch in RC matching. While useful for many pure memory designs, techniques such as splitting a word line into many sub-word lines are less useful in the field of displays based on memory elements at each pixel driver, where the goal is to write an entire row of data to the display as quickly as possible, rather than writing a single word to a portion of a row.

[0073] In the embodiment shown in FIG. 2A, the dummy pixel driver (or portion thereof) (e.g., disabled data storage elements 198a, 198b) is included in the row select path 261 of the word line path 260, and the dummy pixel driver (or portion thereof) (e.g., disabled data storage element 198) is included in the data load trigger path 271 of the bit line path 270. The row select path 261 may include an array of row drivers with disabled data storage elements (e.g., row driver 140a with disabled data storage element 198a shown in FIG. 1C). The data load trigger path 271 may include an array of column drivers with disabled data storage elements (e.g., column driver 160 with disabled data storage element 198 shown in FIG. 1E).

[0074] Since the dummy pixel driver (which is a disabled copy of an actual pixel driver or an active pixel driver) is included in the row select path 261 of the word line path 260, the propagation time TR1 of the trigger signal along the row select path 261 is substantially equal to the propagation time TB2 of the trigger signal along a bit line (e.g., an actual pixel driver) included in the pixel driver array 150. Thus, the dummy pixel driver included in the row select path 261 of the word line path 260 has an RC characteristic that mirrors the RC characteristic of the bit line (e.g., an actual (or active) pixel driver in the bit line) included in the pixel driver array 150. Also, since the dummy pixel driver (which is a disabled copy of an actual pixel driver or an active pixel driver) is included in the data load trigger path 271 of the bit line path 270, the propagation time TB1 of the trigger signal along the data load trigger path 271 is substantially equal to the propagation time TR2 of the trigger signal along a word line (e.g., an actual pixel driver) included in the pixel driver array 150. Thus, the dummy pixel drivers included in the data load trigger path 271 of the bit line path 270 have RC characteristics that mirror the RC characteristics of the word lines (e.g., the actual (or active) pixel drivers in the word lines) included in the pixel driver array 150. Thus, the equation TR1+TR2 (e.g., word line path 260)=TB1+TB2 (e.g., bit line path 270) is substantially satisfied.

[0075] In one embodiment following the system of FIG. 6A (described below), the display controller may be located away from the corners of the array. Additionally, the word lines associated with that display controller may also pass through a section of the pixel driver to reach the portion of the array where the word lines actually connect to the pixel driver's memory circuitry. These locations add up the time it takes for the word lines to pull high at a particular point on the array, but the added time can be taken into account, and the time added due to the requirement to pass through another section of the pixel driver remains constant for pixel drivers in that portion of the array. Once the signal reaches the nearest pixel driver, the difference in time to propagate across the pixel drivers in that portion of the display is determined by the RC characteristics of the word lines in that section.

[0076] FIG. 2B shows a 2×2 block of pixels 260 including pixel (x,y) 261, pixel (x+1,y) 262, pixel (x,y+1) 263, and (x+1,y+1) 264 forming part of the pixel display 150 of FIG. 2A. The depiction emphasizes that the path lengths to each pixel differ to some extent. Using pixel 261 at coordinates (x,y) as the origin, pixel 262 is on the same row as pixel 261 but is one pixel further away from the row driver (not shown) on the left edge of the array. Pixel 263 is located one row directly above pixel 261, thereby increasing its distance from the column driver (not shown) at the origin of the portion of pixel display 150. Pixel 264 is located in the row above pixel 261 and is one pixel away from the left edge of the portion of pixel display 150. Pixels 262 and 263, shown as square pixels, may appear to have the same path lengths, although other pixel aspect ratios are possible. In one embodiment, the pixels may be rectilinear but not square (not shown). In this case, the portion of the pixel display 150 and the row and column drivers must all fit within the respective row and column spacing. In one embodiment, the pixels may be hexagonal (not shown). In a hexagonal array, pixels in adjacent rows are typically offset from each other by one-half column, but the underlying pixel driver array may be rectilinear. A more specific implementation of FIG. 2A is shown at least in FIG. 7B.

[0077] FIG. 3 shows an equivalent circuit 170 of the resistance and capacitance characteristics of a segment of a conductor forming part of a semiconductor, based on the circuit of Campardo 2005, page 183, figures 9-10, cited above. Resistors 171a, 171b and 171c each represent the part of resistance for a segment of equivalent circuit 170. For a conductor of resistance R, resistors 171a, 171b and 171c each have a distributed resistance of R / 3. Arrows 178 indicate the direction of current flow. It is well known that the resistance of a conductor is proportional to its length and inversely proportional to its cross section. Each type of conductor has a resistivity p, specified in Ω-m (ohm-meter). The resistivity of aluminum at 20°C is 2.7×10 -8 Ω-m, while the resistivity of copper at the same temperature is 1.7×10 -8 The formula for calculating resistance R in ohms (Ω) for the above calculation is R=pL / A, where L is the length of the conductor and A is the cross-sectional area of ​​the conductor. A more commonly used metric is sheet resistance, given as R□. The three dimensions of a conductor in a VLSI semiconductor are nominally the length L, the width W, and the height H. The height H is the thickness of the conductor layer above the layer below. The cross-sectional area is A=W×H. For most processes, the height H is a constant value and can be divided by p to create R□=p / H, called the resistance per square.

[0078] Capacitors 172a, 172b, 172c and 172d, each connected to a common ground 173, represent the distributed capacitance in the conductor represented by equivalent circuit 170. For equivalent circuit 170 with a net capacitance of C, the capacitance of capacitors 172b and 172c is taken to be C / 3 and the capacitance of end capacitors 172a and 172d is taken to be C / (2*3) or C / 6. Arrows 270 indicate the direction of propagation of the signal on the conductor.

[0079] In general, a conductor can be represented as an equivalent circuit including n resistive elements and n+1 capacitive elements. The resistance of each resistor is R / n, and the capacitance of all capacitive elements 2 to n is considered to be equal to C / n. The capacitance of equivalent capacitors 1 and n+1 is considered to be equal to C / 2n.

[0080] The capacitance in a conductor in a semiconductor has several components that contribute to the total capacitance. One component, called the areal capacitance, is based on a parallel plate model where conductors at different levels in the semiconductor are separated by a dielectric medium. Another component is called the fringe field capacitance. Its importance arises from reducing the width W of a conductor to the point where its height H is greater than its width W in newer processes with finer design rules. The subject is complex and has been the subject of a considerable amount of advanced research. See Digital Integrated Circuit, A Design Perspective, 2004, pp. 211-215. nd Ed., Rabaey, et al., Pearson du Duc, Delhi, 2002, pp. 136-138 (hereinafter Rabaey 2002), the entire contents of which are incorporated herein by reference.

[0081] Additional sources of capacitance on a conductor are its interconnections with other circuit elements, such as various connections to transistors. One example is described in Lecture Notes, Static Random Access Memory - SRAM, Dr. Lynn Fuller, November 18, 2016, Rochester Institute of Technology, pages 12-13 (hereinafter Fuller 2016), the entire contents of which are incorporated by reference. Lecture Notes Fuller 2016 specifies that the word line of an SRAM receives a contribution to the total capacitance at each memory cell through two pass transistors connected to it, such as pass transistors 128 and 129 in FIG. 1B of the present application, and the word line is connected to the gates of those transistors. The exact nature of the connections that a conductor makes to other components directly affects the capacitance C at that conductor and therefore the propagation delay associated with that conductor.

[0082] 4A-5D show implementations (some variations) of the example described in connection with at least FIGS. 1A-2B and 7A-7C. FIG. 4A shows a release signal delivery circuit 180 that operates to deliver a release signal to AND gates of row drivers, such as AND gates 116a and 116b of row drivers 140a, 140b shown in FIG. 1C of the present application. The release signal delivery circuit 180 includes an array of dummy pixel drivers 181a, 181b, and 181c, sample circuits 182a, 182b, and 182c, also known as sense circuits, and conductor terminals 183a, 183b, and 183c. Modeling in a CAD design tool revealed that it is preferable to replicate the entire pixel driver array in the dummy pixel drivers to match the C capacitance contributed by the active pixel driver array, including the bit lines and word lines.

[0083] The array of dummy pixel drivers 181a, 181b, and 181c each includes a number of dummy pixel drivers that are identical to the active pixel drivers, each having the same interconnections, such as word lines and bit lines (not shown), as the active pixel drivers of the array of pixel drivers. The sample circuits 182a, 182b, and 182c are not found in the active pixel drivers of the array of pixel drivers. The sample circuits 182a, 182b, and 182c detect the rising edge of a trigger signal on one of the bit lines (not shown) of the dummy pixel drivers 181a, 181b, and 181c. The sample circuits 182a, 182b, and 182c include a rising edge detector circuit and a circuit that operates to hold an output signal high for a period of time after a rising edge on the sampled bit line is detected. Another name is a sense circuit. The main requirement is that the rising edge of the sense circuit can turn on again when the next rising edge is detected, but does not remain on for the entire time from one rising edge to the next. In one embodiment, sense circuits 182a, 182b, and 182c also detect the level of the trigger signal and turn off the output of each sense circuit when the level of the trigger signal falls below a certain level. The outputs of sense circuits 182a, 182b, and 182c are asserted on conductors 183a, 183b, and 183c, respectively. Conductors 183a, 183b, and 183c each connect at multiple terminals, such as terminal 184 (one shown), to multiple AND gates (not shown) that form part of a row driver, such as AND gates 116a and 116b in FIG. 1C. Arrow 247 indicates the direction of propagation of the release signal in the array of dummy pixel driver segments 181a, 181b, and 181c. Arrow 251c indicates the direction of propagation in conductor 183c, arrow 251b indicates the direction of propagation in conductor 183b, and arrow 251a indicates the direction of propagation in conductor 183a. The trigger signal source originates in other circuitry (not shown) located below release signal delivery circuit 180.

[0084] The array of dummy pixel drivers 181a, 181b, and 181c operates as a continuous unit. A trigger signal on one of the bit lines of a segment of the dummy pixel driver array 181c propagates from bottom to top, then continues to propagate on one of the bit lines of the dummy pixel driver array 181b, and then on one of the bit lines of the dummy pixel driver array 181a. The bit lines (not shown) of the array of dummy pixel driver segments 181a, 181b, and 181c form continuous conductors with no intervening circuits or breaks between the segments 181a, 181b, and 181c within the individual bit lines. The bit lines connect to the gates of pass transistors (not shown), such as the pass transistors 128 and 129 of the data storage element 120 shown in FIG. 1C. Additionally, at relatively regular intervals, a tap (not shown) on one of the bit lines asserts the value on that bit line (not shown) to an input to a sense circuit, such as sense circuits 182a, 182b, and 182c.

[0085] FIG. 4B shows a segment 190 of a release signal delivery circuit, which represents one segment of a row release signal circuit similar to the release signal delivery circuit 180 of FIG. 4A. The segment 190 includes a dummy pixel driver 191, a sense circuit 192, also known as a sample circuit, a conductor 193, and a number of terminals 194 (one shown) for connecting the conductor to a same number of AND gates forming part of a same number of row drivers (not shown) similar to the row driver 140a of FIG. 1C. Preferably, the array of dummy pixel drivers is collinear with the array of normal pixel drivers (not shown). Arrow 249 indicates the direction of propagation of the release trigger signal within the dummy pixel driver array segment 191. Arrow 248 indicates the direction of propagation of the release signal asserted by the circuit element 192 to the conductor 193.

[0086] The structure of segment 190 is important. The propagation direction of the release trigger signal in dummy pixel driver array segment 190 starts at the bottom and proceeds up as indicated by arrow 249. Sense circuit 192 samples the state of the trigger release signal in dummy pixel driver array 191 and releases a pulse on conductor 193 corresponding to the state of the trigger release signal. The trigger signal propagates through the bit lines (not shown) of dummy pixel driver array 191 at a rate determined by the RC characteristics of the bit lines and the capacitance of the circuit elements attached to the bit lines. The output of circuit elements 192 propagates on conductors 193 at a rate corresponding to the RC characteristics of conductors 193 and the capacitance of the circuit elements (AND gates) attached to conductors 193. The lengths of dummy pixel driver array 191 and conductors 193 are nearly identical, the only difference arising from the need for a gap between one conductor and the next, as in the case of conductors 183a and 183b in FIG. 4A.

[0087] If the pixel driver, whether dummy or active, is 6.4 μm × 6.4 μm, the length of the conductor attached to the 32 AND gates is W length = 6.4 μm × 31 = 198.4 μm = 0.1984 mm. The length of the bit line that extends across the 32 pixel drivers is B length = 6.4 μm × 32 = 204.8 μm = 0.2048 mm. The difference is not significant because the trigger generated by the sense circuit does not need to propagate beyond the row driver of the top row of that conductor. The difference in RC characteristics between a bit line over that distance and a conductor over a similar distance to drive 32 row drivers may result in a difference of less than 0.1%. Simulations show that the mismatch between the propagation delay of the bit lines (not shown) in the array of dummy pixel drivers 191 and the propagation delay of conductor 193 is not cumulative because a limited number of rows are driven from each tap and the tapped bit lines run parallel to the conductors.

[0088] FIG. 4C shows a bit line and column driver circuit 230 of an array of dummy pixel drivers including bit line pair 235p and 235n. Pixel driver elements other than the bit lines have been omitted for clarity. A trigger initiation circuit 231 controls the timing and generation of trigger pulses and asserts trigger pulses on conductors 232. Conductor 232 operates to assert trigger pulses to column driver 234 via terminal 233. The column driver is similar to that of FIG. 4A or 4C to that of FIG. 1D. The data configuration of column driver 234 can be set in memory cells (not shown) that form part of column driver 234 in response to signals from trigger signal control and generation circuit 231. In one embodiment, the data state of the memory cells of column driver 234 can be switched during operation to change the state of the voltage asserted on bit line 235P, thereby acting as a control for the timing of the trigger signal on that bit line. Both bitlines 235p and 235n are driven with complementary data to match the capacitance of the normal bitlines of the active pixel drivers.

[0089] If multiple word lines and word line driver circuits exist for each row, then there may be a separate bit line and column driver circuit similar to bit line and column driver circuit 230 for each word line driver circuit.

[0090] The voltage asserted to the bit string 235p is asserted to the sense circuit 237a via the terminal 236a, to the sense circuit 237b via the terminal 236b, to the sense circuit 237c via the terminal 236c, to the sense circuit 237d via the terminal 236d, to the sense circuit 237e via the terminal 236e, to the sense circuit 237f via the terminal 236f, and to the sense circuit 237g via the terminal 236g. The outputs of the sense circuits 237a to 237g are asserted in order to the output terminals 238a to 238g, respectively. The sense circuits may also be called sample circuits. Each of output terminals 238a, 238b, 238c, 238d, 238e, 238f, and 238g is asserted to a conductor similar to conductor 193 of Figure 4B, which also asserts a voltage to terminals of AND gates of multiple row drivers (not shown) similar to row drivers including some of row drivers 140a of Figure 1C. In one embodiment, multiple bit line pairs are implemented for multiple columns of an array of dummy pixel drivers (not shown). Arrow 243 indicates the direction of propagation of the trigger signal on bit line 235p.

[0091] FIG. 4D shows a detailed block diagram of a single tap circuit 280 after the single tap circuit 190 of FIG. 4B. The tap circuit 280 includes complementary bit lines 281p and 281n of an array of dummy pixel drivers (not shown), a tap 282, a sense circuit 283, conductors 284, terminals 285a-285g, column driver AND gates 286a-286g, and output terminals 287a-287g. The complementary bit lines 281p and 281n operate to deliver release trigger signals from a control unit (not shown). All trigger signals are released on the bit lines 281p. In an initial state, the bit lines 281n are held high while the bit lines 281p are held low. When the trigger signals are released on the bit lines 281p, the trigger signals are held high and the bit lines 281n switch to low. This ensures that the RC characteristics of bit lines 281p and 281 match those of the pair of bit lines in the active array, and therefore have substantially the same propagation delay. Tap 282 delivers a signal corresponding to the state of bit line 281p to sense circuit 283. Sense circuit 283 functions to drive conductor 284 with a signal conditioned to be delivered to a number of row drivers, as described above with respect to FIG. 4A. Terminal 285a delivers the output of sense circuit 283 to two-port AND gate 286a, which forms part of row driver 140a shown in FIG. 1C. A second input to two-port AND gate 286a comes from a row decoder unit (not shown), as described above with respect to FIG. 1C. Similarly, terminals 285b, 285c, 285d, 285e, 285f, and 285g deliver the output of sense circuit 283 to one port of two-port AND gates 286b, 286c, 286d, 286e, 286f, and 286g, the other ports of which are connected to a row decoder unit (not shown). The outputs of AND gates 286a-286g are asserted at output terminals 287a-287g, respectively. In one embodiment, terminals 287a-287g assert the outputs of AND gates 286a-286g at the inputs of a voltage level shifter that forms part of a row driver (not shown).In one embodiment, terminals 287a-287g assert the outputs of AND gates 286a-286g at the inputs of inverters that form part of row drivers (not shown). Each row driver asserts its output to a word line (not shown). Only one row is selected by the row decoder circuitry, so only one word line is held high. Arrows 288 and 289 indicate the direction of signal propagation on bit line 281p and on conductor 284, respectively. Conductor 284 is parallel to bit line 281p in the same propagation direction for a relatively small number of rows, so the net propagation delay on bit line 281p is similar to the net propagation delay on conductor 284.

[0092] Figure 5A shows three segments 201a, 201b, and 201c of dummy pixel drivers and associated circuitry 200 that operates to provide trigger signals to an associated array of column drivers (not shown) to release data stored in memory cells onto the bit lines of the associated array of column drivers (not shown), such as column driver 160 of Figure 1D, and column driver 162 of Figure 4C. The word lines (not shown) of the array of dummy pixel drivers are used as a means to deliver signals to the associated set of column drivers that initiate the release of complementary data onto the bit lines of the array of active pixel drivers. The word lines of segments 201a, 201b, and 201c form a continuous word line across all sections.

[0093] The taps on each of segments 201a, 201b, and 201c of the array of dummy pixel drivers are connected to circuit elements 202a, 202b, and 202c, respectively, so that the signal present on the tapped word line of segment 201a is asserted at circuit element 202a, the signal present on the tapped word line of segment 201b is asserted at circuit element 202b, and the signal present on the tapped word line of segment 201c is asserted at circuit element 202c. In one embodiment, circuit elements 202a, 202b, and 202c may be sense elements similar to sense elements 237a-237g of Figure 4C. The outputs of circuit elements 202a, 202b, and 202c are asserted to conductors 203a, 203b, and 203c, respectively. In one embodiment, the tapped word lines of segments 201a, 201b, and 201c are different word lines of an array of dummy pixel drivers.

[0094] Conductors 203a, 203b, and 203c each assert the output received from circuit elements 202a, 202b, and 202c to a series of column drivers (not shown) via a series of terminals 204 (one shown). In one embodiment, each of the terminals 204 is connected to the CLK 166 of a corresponding column driver 162 of Figure 4C. In one embodiment, each of the terminals 204 is connected to a corresponding gate of a load switch 152 of the column driver circuit 150 of Figure 1D.

[0095] The direction of propagation on segments 201a, 201b, and 201c is indicated by arrow 241 adjacent to the array of dummy pixel drivers. The direction of propagation of the tapped signal on conductors 203a, 203b, and 203c is indicated by arrows 242a, 242b, and 242c, respectively. Conductor 203a is approximately half a pixel driver to a full pixel driver shorter than segment 201a, conductor 203b is approximately half a pixel driver to a full pixel driver shorter than segment 201b, and conductor 203c is approximately half a pixel driver to a full pixel driver shorter than segment 201c. The difference in length serves to allow conductors 203a, 203b, and 203c to be substantially collinear without being electrically connected. A signal asserted on conductor 203a by circuit element 202a delays the propagation of a trigger signal asserted on a word line of segment 201a by a uniform factor determined by the propagation delay due to circuit element 202a. This same delay is induced by circuit elements 202b and 202c because the circuit elements are identical. Because all column drivers in the array of active pixel drivers (not shown) are triggered by circuitry identical to circuit 202a, the propagation delay across all conductors similar to conductor 203a includes a delay factor substantially equal to the propagation delay due to circuit element 202a.

[0096] FIG. 5B shows a single segment 210 of the array of dummy pixel drivers 211 and associated circuitry after the three segments of FIG. 5A. The segment 210 includes an array of dummy pixel drivers 211, a tap on a word line operative to deliver a signal to an input of a circuit element 212, a conductor 213 operative to receive a signal from an output of the circuit element 212, and a number of terminals 214 (one shown). In one embodiment, the circuit element 212 is a sense circuit. Each of the terminals 214 operates to assert a signal on the conductor 213 on a column driver (not shown), such as those shown in FIGS. 4A and 4C. In one embodiment, each of the terminals 214 is connected to the CLK 166 of a corresponding column driver 162 of FIG. 4C. In one embodiment, each of the terminals 214 is connected to a corresponding gate or other release mechanism of a load switch (not shown), such as the logic circuit 165 of the column driver circuit 160 of FIG. 1D.

[0097] The structure of segment 210 is important. The direction of propagation of a release trigger signal using dummy pixel driver array segment 210 starts at the left side of the array of dummy pixel drivers 211 and moves to the right as indicated by the arrow. The trigger signal propagates through the word lines (not shown) of the array of dummy pixel drivers 211 at a rate corresponding to the RC characteristics of the dummy word lines. A tap on a word line (not shown) in the array of dummy pixel drivers asserts a trigger signal to circuit element 212, which in turn asserts its output to conductor 213. The tapped signal propagates on conductor 213 at a rate corresponding to the RC characteristics of conductor 213 and the capacitance of the circuit elements in the column driver attached across a number of terminals 214 (one shown).

[0098] Conductor 213 is parallel to and substantially coplanar with the word lines in the array of dummy pixel drivers, so that there is not extensive mismatch between conductor 213 and the word lines. The above discussion from FIG. 4B regarding the length of the physical lines applies in this case. What is important is that the length is relatively short and that the series of taps is regular, although not necessarily evenly spaced. Thus, the tapped signal propagates a relatively short distance on conductor 213 after a new tap propagates on the new conductor, as described above for conductors 203c, 203b, and 203a in FIG. 5A. This ensures that no propagation differences accumulate across the word lines in the array of dummy pixel drivers 210, as compared to the signals asserted at terminals 214 (one shown).

[0099] Arrow 244 indicates the direction of propagation along the word lines in the array of dummy pixel drivers. Arrow 245 indicates the direction of propagation of the trigger signal from circuit element 212 on conductor 213. Circuit element 212 has its own propagation delay which is a fixed delay and is the same for all circuits for delivering a trigger pulse to the column drivers.

[0100] 5C shows a simplified diagram 220 of dummy word lines 223a and 223b operating to deliver trigger signals to a set of column drivers (not shown) via a set of taps 224a-224h on dummy word line 223a. Dummy word line 223B is held low at all times to provide a capacitive load comparable to that on word lines in an array of active pixel drivers (not shown), where only one word line is high and the surrounding word lines are low.

[0101] In an embodiment in which the array of pixel drivers is divided into vertical segments with the rows of each section serviced by a separate row decoder circuit, the column driver circuits for the columns of each section are served by separate circuits arranged similarly to that of the component in simplified drawing 220.

[0102] Row drivers 222a and 222b of an array of dummy pixel drivers, such as the array of dummy pixel drivers 211 of Figure 5B, are configured to initiate the trigger pulses required to release the data stored in the column drivers, such as the column drivers of Figures 4A and 4C, as described above. The trigger timing control unit 221 delivers signals via conductors 227 to the row drivers 222a and 222b to initiate high trigger pulses on the dummy word lines 223a and 223b. In one embodiment, the dummy word line 223b is hardwired to a low state.

[0103] Taps 224a, 224b, 224c, 224d, 224e, 224f, 224g, and 224h tap dummy word line 223a in an array of dummy pixel drivers, such as the array of dummy pixel drivers 211 of Figure 5B. Word line 223b is held low. In one embodiment, word line 223b is hardwired to a low state.

[0104] Arrow 246 indicates the direction of propagation of signals released by trigger control unit 221. Row drivers 222a and 222b assert values ​​on dummy word lines 223a and 223b of the array of dummy pixel drivers in response to signals received from trigger control unit 221. Arrow 252 indicates the direction of propagation of the value asserted on dummy word line 223a.

[0105] The logic behind holding the adjacent word lines low is that in the active pixel driver array, only one word line is high and all other word lines remain low. This creates a boundary condition that needs to be replicated in the dummy pixel driver array in order for the capacitive load to match that of the active pixel driver array and therefore match the RC characteristics and therefore the propagation delay of the word lines of the active array.

[0106] In the implementation described herein, it is contemplated that more than two rows of dummy pixel drivers may be circuited to deliver signals to release data stored in multiple column drivers via multiple word lines of the dummy pixel drivers. In one embodiment, the taps may occur on a set of parallel word lines with at least one intervening word line held low. Word lines between the tapped parallel word lines are held low. The choice of splitting into a first set and a second set of taps depends on the requirements of the particular display. If the display operates as a unified system, the splitting may be simple. If the split is into four major vertical stripes, each stripe being approximately one-quarter of a column, a different design is required. If the split is into four quadrants including top left, top right, bottom left, and bottom right, yet another design is required. All can be achieved in one design at the cost of significant complexity.

[0107] FIG. 5D shows a detailed block diagram of a segment 290 of the column driver data release circuit after FIG. 5B. Segment 290 includes dummy word lines 291a and 291b, taps 298, sense circuit 292, conductors 293, and column drivers 295a-295h. Dummy word lines 291a and 291b work together to form a circuit that substantially matches the RC characteristics of the word lines of an array of active pixel drivers (not shown), thereby matching the propagation delay between the dummy word line and the word lines of the array of active pixel drivers. Dummy word line 291a is pulled high by a signal from a trigger timing control unit, such as unit 221 described in FIG. 5C. Dummy word line 291b is present to ensure that the capacitive load on word line 291a is properly matched to the word lines pulled high on the array of dummy pixel drivers (not shown). The state of dummy word line 291a at a given point is asserted to sense circuit 292 via terminal 298. The sense circuit detects the state of dummy word line 291a and, with any necessary signal conditioning, asserts a corresponding signal on conductor 293. In one embodiment, sense circuit 292 detects the leading edge of the signal sensed on dummy word line 291a.

[0108] The signal asserted on conductor 293 is asserted via terminals 294a-294h to respective column drivers 295a-295n. In response to the asserted state at their respective terminals 294a-294h, column drivers 294a-294h release the data stored in their memory on complementary bit lines 296a-296h, respectively. Each of bit lines 296a-296h represents a pair of complementary bit lines, as described in FIG.

[0109] Arrows 297 indicate the direction of propagation both on the dummy word line 291a and on the conductor 293. The propagation delay on the dummy word line 291a may differ from the propagation delay on the conductor 293 because the RC of the two lines are not identical. The propagation difference may not be significantly different over a relatively short period of time. By using multiple taps on the dummy bit line, it is possible to make the line length equivalent to 32 or 64 pixel driver pitch lengths. For a pixel driver pitch of 8.0 μm, this is 0.256 mm or 0.512 mm, respectively. Even with a small RC mismatch, over such short distances, significant propagation delays do not accumulate.

[0110] 6A shows an arrangement in which four controller devices 329LN, 329LF, 329RF, and 329RN control a single backplane 320. The array of pixel drivers in backplane 320 is divided into four vertical sections, each section having a controller associated with it. The convention in this application is that LN means near on the left, LF means far on the left, RF means far on the right, and RN means near on the right. The use of near and far refers to the relative distance to the row address circuitry found in the left row decoder and word line driver 322L or the relative distance to the row address circuitry found in the right row decoder and word line driver 322R.

[0111] The vertical sections include a near independent section on the left of pixel driver 321LN, a far independent section on the left of pixel driver 321LF, a far independent section on the right of pixel driver 321RF, and a near independent section on the right of pixel driver 321RN, referred to as sections. It is possible for the widths of sections 321LN, 321LF, 321RF, and 321RN to be substantially equal, but it is not necessary for the vertical sections to be substantially or strictly equal. Engineering considerations may require that the vertical sections are not all equal. Also, it is possible for engineering reasons to not have the width of the left section combining 321LN and 321LF equal to the width of the right section combining 321RN and 321RF. It is noted that none of the independent sections of pixel drivers 321LN, 321LF, 321RF, and 321RN overlap any of the other independent sections of pixel drivers 321LN, 321LF, 321RF, or 321RN.

[0112] The complete image data for the array of pixel drivers is received by image data pre-processor 330 via bus 331. Image data pre-processor 330 processes the incoming image data, separates it into data for left near section 321LN, left far section 321LF, right far section 321RF, and right near section 321RN, and delivers the data to display controller 329LN, display controller 329LF, display controller 329RF, and display controller 329RN via terminals 332LN, 332LF, 332RF, and 332RN, respectively. Display controller 329LN, display controller 329LF, display controller 329RF, and display controller 329RN process the data and schedule it to be written to the rows where the data is needed. All display controllers 329LN, 329F, 329RF, and 329RN, and pre-processor 330 operate from the same master clock, set by a crystal control circuit (not shown) or similar device. This does not keep the display controllers precisely synchronized, since each display controller synchronizes to the master clock signal with its individual digital phase-locked loop running slightly asynchronously to the other digital phase-locked loops. Each display controller also receives a Vsync (vertical synchronization) signal from circuitry associated with the image data pre-processor 330. Vsync keeps the frame rate of each image section synchronized with the frame rates of all other image sections. Typically they are within one or two clock cycles, which has negligible effect on image quality between vertical sections.

[0113] In one embodiment, the data transferred by each display controller to its column data registers is not confined to the boundaries of each independent segment of the pixel driver associated through the row select assembly.

[0114] There are other ways to develop and implement a display controller assembly. In one approach, all required display controllers are designed and implemented in a single semiconductor device. While this may make some aspects easier to implement, the integrated approach shown here offers some advantages in terms of yield due to the smaller silicon size of the individual display controllers. Also, the approach of striped displays to a backplane is compatible with either approach to the display controller.

[0115] A device called a single display controller or a display controller assembly, where each display controller controls a section of the display, may be comprised of several separate elements, such as multiple semiconductor elements, within the spirit of the present invention.

[0116] Row decoder and word line driver 322L includes a row decoder and word line driver pair, one for display controller 329LM and one for display controller 329LF. Display controller 329LN delivers word line address and row trigger control signals to row decoder and word line driver 322L via lines 334LN. At the same time, display controller 329LN delivers image data for the addressed row onto a set of bit line drivers via conductors 333LN for the left near section 321LN (not shown). The relative timing requires that the data for all pixel drivers of an addressed row be in place before the word line driver pulls the word line for that segment of the row high. Propagation delays can be taken into account as long as the speed of propagation up the display across the display ensures that the complementary bit line for that column is in its data state at that row before the word line pulls high at that point in the row.

[0117] Display controller 329LF delivers word line address and row trigger signals via lines 334LF to the second of two row decoder and word line driver circuits in row decoder and word line driver 322L. Simultaneously, display controller 329LF delivers image data for the addressed row to the set of bit line drivers via conductors 333LF. The same considerations regarding propagation delays that are addressed in display controller 329LN apply to display controller 329LF.

[0118] Row decoder and word line driver 322R includes a pair of row decoder and word line driver circuits followed by row decoder and word line driver 322L circuits. Display controller 329RF delivers word line address and row trigger signals via lines 334RF to one of the pair of row decoder and word line driver circuits in row decoder and word line driver 322R. Display controller 329RF delivers image data for the far right section 321RF to the bit line driver via conductors 333RF under the timing conditions described above.

[0119] Display controller 329RN delivers word line address and row trigger signals over lines 334RN to the second of the two row decoder and word line driver circuits in row decoder and word line driver 322R. Display controller 329RN delivers image data for right near section 321RN over conductors 333RN under the timing conditions described above.

[0120] In one embodiment, display controllers 329LN, 329LF, 329RF, and 329RN operate physically separated trigger circuits that are similar in function and location.

[0121] When row decoder and word line driver 322L receives a row address from display controller 329LN on the first row decoder and word line driver circuit, the word line of the row corresponding to the address is held in a state that allows the memory circuit operated by that word line to receive data via the bit line when a trigger signal is received via the same connection. Dashed line 325LN represents the word line of the first row of the near left section 321LN, and dashed line 326LN represents the word line of the second row of the near left section 321LN. Because section 321LN is near the row decoder and word line driver, word line 325LN and word line 326LN do not extend into far left section 321LF. For reasons of constant metal density, dummy metal structures are placed in far left section 321LF to improve the planarity of the multiple dies forming the backplane, a consideration of importance for liquid crystal devices and other devices.

[0122] When the row decoder and word line driver 322L receives a row address from the display controller 329LF on the second row decoder and word line driver circuit, the row corresponding to the address is held high when a trigger signal is received through the same connection. The word line 323LN passes under the left near section 321LN without making an electrical connection to reach the word line 323LF connected to the SRAM memory cell of each pixel driver in the left far section 321LF. The same considerations apply to the word line segments 324LN and 324LF.

[0123] The RC value of word line 323LN coupled to word line 323LF will be larger than the RC value of 326LN due to the resistance associated with the length of 324LN passing under nearby section 321LN on the left, but that must also be taken into account if the sections are not of equal width. The RC characteristics are part of the definition of the propagation delay in propagating a word line change from low to high and back to low.

[0124] Similar considerations apply for word lines 325RN and 326RN, both of which connect to a row of pixel drivers in the right near section 321RN. Similarly, word line 323RN passes under the right near section 321RN to connect to word line segment 323RG that connects to SRAM memory cells in pixel drivers that form a row of the right far section 321RF. The same considerations apply for word line segment 324RN that connects to word line segment 324RF.

[0125] FIG. 6B shows a more detailed block diagram of the right half of the system of FIG. 2A. The enlarged view includes display controller 329RF, display controller 329RN, and partial backplane 320R. Partial backplane 320R includes right far section 321RF, right near section 321RN, row decoder and word line driver (right far section 322RF), and row decoder and word line driver (right near section) 322RN. The relative positions of row decoder and word line driver 322RF and row decoder and word line driver 322RN are chosen for ease of illustration. They may in fact be developed in different layers and stacked vertically, depending on the number of metal layers of the backplane semiconductor. Other arrangements are possible.

[0126] The far right section 321RF includes bit line driver 335RF, even row pixel driver 328RF, and odd row pixel driver 327RF. The near right section 321RN includes bit line driver 335RN, even row pixel driver 328RN, and odd row pixel driver 327RN. The odd row 339 includes pixel driver 327RF and pixel driver 327RN, and the even row 340 includes pixel driver 328RF and pixel driver 328RN. For clarity, dashed line 337 represents the boundary between the pixel driver of odd row 339 and the pixel driver of even row 340. The dashed line 338 represents the boundary between the pixel driver of even row 340 and bit line driver 335RF and bit line driver 335RN.

[0127] Display controller 329RF delivers image data to bit line driver 335RF via conductor 333RF. Conductor 333RF substantially includes multiple parallel data paths. Display controller 329RF transmits row address information to row decoder and word line driver 322RF via conductor 334RF. In one embodiment, another trigger signal is transmitted via conductor 334RF to pull the word line high when timing is critical. This can be implemented using an AND gate (not shown) with two input ports and one output. The selected row receives one input from the row decoder and a second input from the trigger signal, with the output connected to the word line. Only one AND gate has a high input on both input ports, which causes the output of the AND gate to pull the word line high.

[0128] Digital controller 329RN delivers image data to bit line driver 335RN via conductor 333RN. Conductor 333RN substantially includes multiple parallel data paths. Display controller 329RN transmits row address information to row decoder and word line driver 322RN via conductor 334RN. In one embodiment, another trigger signal is transmitted via conductor 334RN to pull the word line high when timing is critical. This can be implemented using an AND gate with two input ports and one output. The selected row receives one input from the row decoder and a second input from the trigger signal and output on the word line. Only one AND gate has a high input on both input ports, which causes the output of the AND gate to pull the word line high.

[0129] Pixel driver 327RF is part of odd row 339 in far right section 321RF. In an actual embodiment, far right section 321RF may include 500-1000 or more pixel drivers, although other numbers of pixel drivers are not excluded. Similar considerations may apply to pixel driver 327RN, pixel driver 328RF, and pixel driver 328RN.

[0130] The far row decoder and word line driver 322RF operates to drive a set of two word lines in each row. Word line segment 323RN passes under pixel driver 327RN in odd row 339 and connects to word line segment 327RF, where word line segment 323RN contacts the SRAM memory cells of pixel driver 327RF. The near row decoder and word line driver 322RN drives word line segment 325RN, which contacts the SRAM memory cells of pixel driver 327RN.

[0131] Row decoder and word line driver 322RF operates to drive word line segments 324RN which pass under pixel drivers 328RN of even rows 340, where they make contact with the SRAM memory cells of pixel drivers 328RF.

[0132] In one embodiment, word line segments 223RN and 223RF and word line segment 225RN of odd row 239 are pulled high at substantially the same time, somewhat accounting for different propagation delays. Alternatively, word line segments 224RN and 224RF and word line segment 226RN of even row 240 are pulled high at substantially the same time, somewhat accounting for different propagation delays. The selection of the row whose word line is pulled high depends on address data sent to row decoders and word line drivers 222RF and 222RN.

[0133] For display applications producing images for human viewing, it is best to keep the near and far sections on the same schedule. This helps control the occurrence of visual artifacts due to causes such as lateral field effects. In other applications, it may be advantageous to arrange the near and far sections on different schedules.

[0134] 6C illustrates an additional way in which the time required to write an array can be reduced. Display system 360 includes four pixel drivers 341a, 341b, 342a, and 342b arranged in a 2x2 matrix format. Display system 360 further includes row decoders and word line drivers 353 and 354, bit line drivers 343a, 343b, 343c, and 343d, and a display controller 344. It should be understood that an actual arrangement will have many more rows and columns than shown here.

[0135] Pixel drivers 341a and 341b form the odd row of pixel drivers, and pixel drivers 342a and 342b form the even row of pixel drivers. Row decoder and word line driver 353 drives word lines 355 associated with odd row pixel drivers 341a and 341b. Row decoder and word line driver 354 drives word lines 356 associated with even row pixel drivers 342a and 342b.

[0136] The bit line driver 343a supplies complementary binary image data to the SRAM memory cells of the pixel driver 341a on the odd rows via complementary bit lines 347a and 347b. The bit line driver 343c supplies complementary binary image data to the SRAM memory cells of the pixel driver 341b on the odd rows via complementary bit lines 349a and 349b. The complementary bit lines 347a and 347b and the complementary bit lines 349a and 349b pass under the pixel drivers 342a and 342b located on the even rows.

[0137] Bit line driver 343b supplies complementary binary image data to the SRAM memory cells of pixel driver 342a on the even rows via complementary bit lines 348a and 348b. Bit line driver 343d supplies complementary binary image data to the SRAM memory cells of pixel driver 342b on the even rows via complementary bit lines 350a and 350b. Complementary bit lines 348a and 348b as well as complementary bit lines 350a and 350b pass under pixel drivers 341a and 341b located on the even rows. It should be understood that additional even rows may be positioned above the odd rows of pixel drivers 341a and 341b.

[0138] Data for odd numbered rows is provided by terminals 359a and 359c over bus lines 357 to bit line drivers 334a and 334c. Data for even numbered rows is provided by terminals 359b and 359d over bus line 358 to bit line drivers 334b ​​and 334d. Bus lines 351 and 352 include multiple parallel lines used to transmit address data for selected rows to row decoders and word line drivers 353 and 354, respectively. In one embodiment, bus lines 351 and 352 include word line trigger signal conductors that control the timing of the operation to pull the word lines high.

[0139] FIG. 6D shows a depiction of the RC characteristic 370 of the word line after word line segment 323RN is coupled with word line segment 323RF of detailed block diagram 320R of FIG. 6B. Vector 378 represents the propagation direction of the row select signal on the word line. Resistor 371a represents resistance and capacitor 372a represents the parasitic capacitance of word line segment 323RN passing under the near section 321RN on the right side of detailed block diagram 320R. Note that all shown capacitances are connected to ground 373. Other grounding configurations may be possible, since the parasitic capacitance of word line segment 323RN may be affected not by a ground plane, but by another nearby conductor at a different potential.

[0140] Capacitors 372b, 372c, and 372d represent capacitances at nodes where word line segment 323RF crosses a circuit element, such as pass transistors 128 and 129 of the six-transistor data storage element 120 of FIG. 1B. It is generally expected that the capacitance due to interactions at a node will be substantially larger than the parasitic capacitance due to the presence of other nearby circuit elements, although there are exceptions to this that depend on the details of the semiconductor manufacturing process and the design rules associated with the chosen process. Modern semiconductor computer-aided design (CAD) software tools allow detailed evaluation of silicon designs to be performed before they are manufactured and tested.

[0141] The values ​​of the resistance R of a segment of a conductor that can be calculated are given in the description of FIG. 3 and are repeated here in a simplified form. The applicant refers the reader to that text. As mentioned above, all conductors in the same layer of a semiconductor process are usually made of the same material, such as aluminum or copper, and therefore have similar resistivity σ and height H. The length L and width W can vary, but if the resistivity σ and width W are the same, the resistance per unit length will be the same. One way in which the resistance of a given unit length of wire can be reduced is by enlarging the width W. Care must be taken when doing this, since a reduction in resistance R may be accompanied by an increase in stray capacitance C, which may result in less than the desired reduction in the RC characteristics of the conductor. This, in turn, will limit or eliminate any acceleration of the signal propagation speed in such lines.

[0142] A useful goal is to reduce the time it takes for a word line select signal to propagate along a word line, following the above-mentioned word line including word line segment 323RN coupled with word line segment 323RF. Word line segment 323RN does not interact with memory circuitry in near section 321RN on the right side of the pixel driver, but word line segment 323RF does interact with memory circuitry in far section 321RF on the right side of the pixel driver. Word line segment 325RN interacts with memory circuitry in near section 321RN on the right side. The word line selected for this example addresses one row of many rows that may all be addressed in a similar manner.

[0143] The time it takes to propagate across the right near section 327RN on word line segment 325RN is determined by the RC characteristics of the line. The signal from word line segment 325RN does not propagate to the right far section 321RF because the memory circuits on the same row of the right far section 321RF are controlled by the signal on word line segment 323RF received through word line segment 323RN, as described above.

[0144] In one embodiment, word line segment 323RN that does not interact with memory circuitry on its row of right near section 321RN is routed near word line segment 325RN. This may be a desired design choice for a number of reasons unrelated to capacitance, such as the desire to maintain a constant metal density in the individual layers of semiconductor to maintain their planarity, an important consideration for liquid crystal devices such as liquid crystal silicon light modulators.

[0145] Applicant has developed several backplanes of different sizes in different processes with an active resolution of 4096 columns by 2400 rows. By applying the four display controller scheme disclosed herein and also using an even-row-odd-row scheme, the nominal size of the display that each display controller subchannel must handle is effectively a manageable 1024 width by 1200 height. As a result, the final requirement is four pairs of display controller subchannels which is effectively eight subchannels.

[0146] Data and signal propagation delays on the backplane are most significant when using older processes with aluminum wiring, especially when the parts are large in terms of integrated circuits. Applicant has filed a separate patent application which describes means for minimizing delays within the backplane by speed matching the bit lines to the word line controls and speed matching the word line delays to the bit line trigger signals.

[0147] 7A shows a depiction of the left side of a display 400 having four vertical sections of pixel drivers. The left display side 400 includes the leftmost vertical section of pixel driver 401LN and the left side of the center vertical section of pixel driver 401LF. The left display side 400 further includes a display controller 402LN operative to control the vertical section of pixel driver 401LN, a display control 402LF operative to control the vertical section of pixel driver 401LF, a row of bit line drivers 412LN operative to deliver complementary operational bit line data to the pixels of the vertical section of pixel driver 401LN, and a row of bit line drivers 412LF operative to deliver bit line data to the pixel drivers of the vertical section of pixel driver 301LF. All segments may reside on the same physical semiconductor assembly. The left display side 400 includes a row decoder and word line driver assembly 404LN that operates to drive the word lines of a selected row in the vertical section of the pixel driver 401LN, and a word line driver assembly 404LF that operates to drive the word lines of a selected row in the vertical section of the pixel driver 401LF.

[0148] Display controller 402LN and display controller 402LF receive row address and row data information for their respective vertical sections from an image data pre-processor, such as image data pre-processor 330 of FIG. 6A. Each display controller controls its vertical section of pixel drivers independent of adjacent display controllers. The display controllers are programmed to operate similarly with respect to the rows being written and are synchronized to the same clock. As a result, adjacent vertical sections operate normally within a few clock cycles of each other.

[0149] Image data for a given row in the vertical section of pixel driver 301LN is loaded by display controller 402LN via terminal 410LN onto row bit line drivers 406LN1 and 406LN2 of bit line driver 412LN for the pixel drivers in the vertical section of pixel driver 401LN. The pixel drivers associated with bit line driver 406LN1 include pixel drivers 1Na, 1Nb, 1Nc, 1Nd, and 1Ne, and the pixel drivers associated with bit line driver 306LN2 include pixel drivers 2Na, 2Nb, 2Nc, 2Nd, and 2Ne. Bit line driver 406LN1 loads the bit line data for the selected pixel driver onto complementary bit line 413LN1, respectively B pos Or B neg , is marked with a + (plus) sign or a - (minus) sign. The bit line driver 406LN2 loads the bit line data of the selected pixel driver onto the complementary bit line 413LN2. As mentioned above, the complementary bit lines are marked with a + or - sign.

[0150] Image data for a given row having a vertical section of pixel driver 401LF is loaded by display controller 402LF onto bit line drivers 406LF1 and 406LF2 of rows of bit line driver 412LF for pixel drivers of the vertical section of pixel driver 401LF via terminals 410LF. The pixel drivers associated with bit line driver 406LF1 include pixel drivers 1Fa, 1Fb, 1Fc, 1Fd, and 1Fe, and the pixel drivers associated with bit line driver 406LF2 include pixel drivers 2Fa, 2Fb, 2Fc, 2Fd, and 2Fe. Bit line driver 406LF1 loads the bit line data of the selected pixel driver onto complementary bit line 413LF1, respectively B POS Or B NEG3. The bit line driver 306LF2 loads the bit line data of the selected pixel driver onto the complementary bit line 313LF2. As mentioned above, the complementary bit lines are marked with a + (plus) sign or a - (minus) sign.

[0151] The left display side 400 includes rows 405a, 405b, 405c, 405d, and 405e, each of which includes a near row decoder and word line driver on the left side of row decoder and word line driver assembly 404LN, a far row decoder and word line driver on the left side of word line driver assembly 404LF, two pixel drivers in the near left vertical section, and two pixel drivers in the far left vertical section. For example, row 405a includes a near left row decoder and word line driver LNa, a left row decoder and word line driver LFa, pixel drivers 1Na and 2Na in near left section 401LN, and pixel drivers 1Fa and 2Fa in near left section 401LF. Rows 405b, 405c, 405d, and 405e are organized identically with their components.

[0152] The left display side further includes a trigger signal circuit 403LN and a trigger signal circuit 403LF. The trigger signal circuit 403LN receives a signal or set of signals from the display controller 402LN via a bus 409LN. The trigger signal circuit 403LN releases bit line trigger signals via a bus line 408LN and releases row select and word line high signals via a bus line 407LN. In one embodiment, the trigger signal circuit 403LN forms part of the display controller 402LN. The trigger signal circuit 403LF receives a signal or set of signals from the display controller 302LF via a bus 409LF. The trigger signal circuit 403LF releases bit line trigger signals via a bus line 408LF and releases row select and word line high signals via a bus line 407LF. In one embodiment, the trigger signal circuit 403LF forms part of the display controller 402LF.

[0153] The row select and word line high trigger signals delivered to the row decoder and word line driver assembly 304LN via bus 307LN cause the following actions to be performed: The row decoder logic of one of the row decoders and word line drivers LNa, LNb, LNc, LNd, and LNe goes high in response to the row select signal delivered to the row decoder and word line driver assembly 304LN. In a first embodiment, the output of the word line driver for each row is applied to an input of a two-input AND gate (not shown). The word line trigger signal is applied to the other input of each of the AND gates. Only the selected row receives inputs from both the row select decoder logic and the word line trigger signal, allowing the output of the AND gate to hold its word line high. In one embodiment, the row decoder logic pulls the word line high without the word line trigger signal.

[0154] Word line driver LNa drives word line 411a, which provides word line signals to memory circuits of pixel drivers 1Na and 2Na in the vertical section of pixel driver 401LN. Word line 411a does not extend into the vertical section of pixel driver 401LF. Similarly, word line driver LNb drives word line 411b, which provides word line signals to memory circuits of pixel drivers 1Nb and 2Nb in the vertical section of pixel driver 401LN. Word line drivers LNc, LNd, and LN3 drive word lines 411c, 411d, and 411e, respectively, which provide word line signals to memory circuits of pixel drivers in their respective rows.

[0155] The row select and word line high trigger signals delivered via bus 407LF to the row decoder and word line driver assembly 404LF cause the following actions to be performed: The row decoder logic of one of the row decoders and word line drivers LFa, LFb, LFc, LFd, and LFe goes high in response to the row select signal provided to the row decoder and word line driver assembly 404LF. In a first embodiment, the output of the word line driver of each row is applied to an input of a two-input AND gate (not shown). The word line trigger signal is applied to the other input of each of the AND gates. Only the selected row receives inputs from both the row select decoder logic and the word line trigger signal, allowing its word line to be held high. In one embodiment, the row decoder logic pulls the word line high without the presence of a trigger signal or an AND gate.

[0156] Word line driver LFa drives word line 441a, which provides word line signals to memory circuits of pixel drivers 1Fa and 2Fa in the vertical section of pixel driver 401LF. Word line 414a passes under the pixel drivers in the vertical section of pixel driver 401LN without making an electrical connection. Similarly, word line driver LFb drives word line 414b, which provides word line signals to memory circuits of pixel drivers 1Fb and 2Fb in the vertical section of pixel driver 401LF. Word line drivers LFc, LFd, and LFe drive word lines 414c, 414d, and 414e, respectively, which provide word line signals to memory circuits of pixel drivers in their respective rows.

[0157] Trigger circuit 403LN delivers a bit line driver trigger signal to bit line drivers 406LN1 and 406LN2 of the row of bit line driver circuit 412LN. This releases the data previously loaded into bit line drivers 406LN1 and 406LN2 by display controller 402LN. The data and its complement are loaded onto complementary bit line 413LN1 by bit line driver 406LN1 and onto complementary bit line 413LN2 by bit line driver 406LN2.

[0158] The trigger circuit 403LF delivers a bit line driver trigger signal to the bit line drivers 406LF1 and 406LF2 of the row of the bit line driver circuit 412LF. This releases the data previously loaded into the bit line drivers 406LF1 and 406LF2 by the display controller 402LF. The data and its complement are loaded onto the complementary bit line 413LF1 by the bit line driver 306LF1 and onto the complementary bit line 413LF2 by the bit line driver 406LF2.

[0159] Control of the wordline and bitline timing is essential for efficient operation of the backplane. In general, the bitline at a particular pixel driver of a selected row must be loaded with that pixel driver's complementary data before that wordline is pulled high. It is also important that the previous wordline that was held high must be turned off before the data of the new pixel driver of the next selected row reaches the pixel driver of the old row. Turning off the wordline of the old row can be accomplished by either removing the wordline trigger signal if one is required, or by selecting a new row in the absence of a wordline release signal.

[0160] For purposes of illustrating propagation delay, an m-column wide by n-row high SRAM array 420 is shown in Figure 7B. Figure 7B illustrates how the dummy pixel driver array shown and described in connection with at least Figures 1C and 1E can be implemented in connection with pixel driver array 150.

[0161] In this exemplary implementation, row select path 261 (of word line path 260) includes several parallel dummy pixel driver arrays 261A-2, 261B-2, and 261C-2 (e.g., each including disabled data storage elements). For simplicity, only three dummy pixel driver arrays 261A-2, 261B-2, and 261C-2 are shown. The dummy pixel driver arrays 261A-2, 261B-2, and 261C-2 have lengths equal to the lengths of the bitlines in pixel driver array 150 to replicate the RC characteristics of the bitlines in pixel driver array 150.

[0162] Sections (or segments) of row drivers 261A-1, 261B-1, 261C-1 (which correspond to portions of word lines A, B, and C (marked with double-headed arrows) of pixel driver array 150) are tapped from dummy pixel driver arrays 261A-2, 261B-2, and 261C-2, respectively. Sections of row drivers 261A-1, 261B-1, 261C-1 and dummy pixel driver arrays 261A-2, 261B-2, and 261C-2 are located outside of pixel driver array 150. As a specific example, dummy pixel driver array 261A-2 can be used with a section of row driver 261A-1 (e.g., row drivers 140a, 140b shown in FIG. 1C) tapped from dummy pixel driver array 261A-2 (e.g., dummy pixel driver array 198a shown in FIG. 1C) to drive word line A (marked with a double-sided arrow). The section of row driver 261A-1 corresponds to word line A. Similarly, a section of row driver 261B-1 is tapped from dummy pixel driver array 261B-2, and a section of row driver 261C-1 is tapped from dummy pixel driver array 261C-2. Although the connections are not shown in FIG. 7B, the sections of row drivers 261A-1, 261B-1, 261C-1 are configured to connect to and drive various word lines in pixel driver array 150.

[0163] The dashed arrows indicate one potential path for the trigger signal TRA through the dummy pixel driver array 261A-2 and sections of the row driver 261A-1 to drive the word line associated with the pixel of interest 280 at word line A. As shown in FIG. 7B, the dummy pixel driver arrays 261A-2, 261B-2, 261C-2 are aligned as closely as possible to the pixel driver array 150 so that the RC characteristics can be matched as closely as possible. The dummy pixel driver arrays 261A-2, 261B-2, 261C-2 are disposed between the pixel driver array 150 and sections (or segments) of the row drivers 261A-1, 261B-1, 261C-1.

[0164] 7B includes row drivers that are tapped only along the dummy pixel driver array 261A-1 portion of the row select path 261, which can reduce RC effects (compared to including row drivers along the entirety of the dummy pixel driver array 261A-1). Specifically, the row drivers 261A-1 are tapped only along the top of the dummy pixel driver array 261A-1 (to drive word line A at the top of the pixel driver array 150), and no row drivers are tapped along the bottom of the dummy pixel driver array 261A-1. Instead, for example, the dummy pixel driver array 261C-2 has a row driver 261C-1 along the bottom of the dummy pixel driver array 261C-1 (to drive word line C at the bottom of the pixel driver array 150).

[0165] As an example of loading that can be implemented for a configuration such as that shown in Figure 7B, each of the eight sections of the eight row drivers can be tapped (to drive a total of 64 word lines) to one of 16 dummy pixel drive arrays (arranged in parallel as shown in Figure 7B). Thus, each one of the 16 dummy pixel driver arrays can be tapped eight times with eight different sections of the row driver (only one tap per dummy pixel driver array and one section of the row driver is shown in Figure 7B). This configuration can drive 1024 different word lines within the pixel driver array.

[0166] Also, in this exemplary implementation, the load data trigger path 271 (of the bit line path 270) includes several parallel dummy pixel driver arrays 271D-2, 271E-2, and 271F-2 (e.g., each including disabled data storage elements). For simplicity, only three dummy pixel driver arrays 271D-2, 271E-2, and 271F-2 are shown. The dummy pixel driver arrays 271D-2, 271E-2, and 271F-2 have lengths equal to the lengths of the word lines in the pixel driver array 150 to replicate the RC characteristics of the word lines in the pixel driver array 150.

[0167] Sections (or segments) of column drivers 271D-1, 271E-1, 271F-1 (corresponding to portions of word lines D, E, and F (marked with double-sided arrows) of pixel driver array 150) are tapped from dummy pixel driver arrays 271D-1, 271E-2, and 271F-2, respectively. Sections of column drivers 271D-1, 271E-1, 271F-1, and sections of dummy pixel driver arrays 271D-2, 271E-2, and 271F-2 are disposed outside of pixel driver array 150. As a specific example, dummy pixel driver array 271D-2 can be used with a section of column driver 271D-1 (e.g., column driver 160 shown in FIG. 1E) tapped from dummy pixel driver array 271D-2 (e.g., dummy pixel driver array 199a shown in FIG. 1E) to drive word line D (marked with double-sided arrow). A section of column driver 271D-1 corresponds to word line D. Similarly, a section of column driver 271E-1 is tapped from dummy pixel driver array 271E-2, and a section of column driver 271F-1 is tapped from dummy pixel driver array 271F-2. Although connections are not shown in FIG. 7B , the sections of column drivers 271D-1, 271E-1, 271F-1 are configured to connect to and drive various bit lines in pixel driver array 150.

[0168] The dashed arrows indicate one potential path for the trigger signal TRB through the dummy pixel driver array 271D-2 and sections of the column driver 271D-1 to drive the bit line associated with the pixel 280 of interest at bit line D. As shown in FIG. 7B, the dummy pixel driver arrays 271D-2, 271E-2, 271F-2 are aligned as closely as possible to the pixel driver array 150 so that the RC characteristics can be matched as closely as possible. The dummy pixel driver arrays 271D-2, 271E-2, 271F-2 are disposed between the pixel driver array 150 and sections (or segments) of the column drivers 271D-1, 271E-1, 271F-1.

[0169] 7B includes column drivers that are tapped only along the dummy pixel driver array 271D-1 portion of the load data trigger path 271, which can reduce RC effects (compared to including row drivers along the entirety of the dummy pixel driver array 271D-1). Specifically, the row drivers 271D-1 are tapped only along the top of the dummy pixel driver array 271D-1 (to drive bit lines D in the right portion of the pixel driver array 150), and no column drivers are tapped along the left portion of the dummy pixel driver array 271D-1. Instead, for example, the dummy pixel driver array 271F-2 has a column driver 271F-1 along the left portion of the dummy pixel driver array 271F-1 (to drive word lines F in the left portion of the pixel driver array 150).

[0170] As an example of loading that can be implemented for a configuration such as that shown in Figure 7B, eight sections of eight column drivers can each be tapped (to drive a total of 64 bit lines) to one of 16 dummy pixel drive arrays (arranged in parallel as shown in Figure 7B). Thus, each one of the 16 dummy pixel driver arrays can be tapped eight times with eight different sections of the column driver (only one tap per dummy pixel driver array and one section of the column driver is shown in Figure 7B). This configuration can drive 1024 different bit lines within the pixel driver array.

[0171] FIG. 7C shows the case where the display is divided into vertical sections 441 and 442. Any of the features described in relation to FIG. 2 or FIG. 7B can be applied and included in FIG. 7C. In this case, the SRAM array 440 again includes an array of pixel drivers with m columns by n rows, each including a memory cell. The dividing line between the vertical sections 441 and 442 is a vertical dashed line 445 between coordinates (m',0) and (m',n), where M is a prime number m. If m'=m / 2, the width of the two vertical sections is equal. For engineering or other reasons, one vertical section may be wider than the other vertical section within the scope of the invention. In one embodiment, the display includes four vertical sections, of which the example shows the left half. The example emphasizes one pixel driver at coordinates (x,y), but it should be understood that pixel drivers at all coordinates must work as examples in order for the solution to be a general solution.

[0172] The calculations in this example are an extension of those developed for Figure 2A. The difference is in the presence of an extended section on the word line below the vertical section where the word line does not interact with the pixel driver above it, and a similarly long section on the word line caused by the display controller for that vertical section that needs to reach the left edge of the display. The latter is necessary because the area containing the array of pixel drivers must be continuous and cannot have gaps in it to accommodate other types of circuitry.

[0173] The general approach in this embodiment is to make the time it takes for a word line high signal to propagate from the word line driver at coordinate (0,y) to the target pixel driver at coordinate (x,y) equal the time it takes for a bit line trigger signal to propagate from the circuitry near coordinate (0,0) to the bit line driver at coordinate (x,0). The second part of the current approach is to make the time it takes for a word line trigger signal to propagate from the circuitry near coordinate (0,0) to the row decoder and word line select circuitry at coordinate (0,y) substantially equal the time it takes for complementary bit line data to propagate up complementary bit line 443 to the target pixel driver at coordinate (x,y).

[0174] 7c, in one embodiment, originates from a circuit near the lower left corner of array 340, at coordinates (0,0). The coordinates should be considered to represent rows and columns of array 340.

[0175] Signal TR1 represents the propagation time of the word line trigger signal. The word line trigger signal, which takes time TR1 to propagate, originates in a circuit located near coordinate (0,0) and is delivered to an AND gate (not shown) in the row decoder and word line circuit of each row. A second input to the AND gate is a signal from the row decoder circuit of the row select circuit. Since only one row is selected, only one AND gate has its logic satisfied and holds the word line of that row high.

[0176] In one embodiment, an AND gate is not used, but a tri-state buffer is used instead. The tri-state buffer has one input, which is the data from the word line decode, and an enable signal, which in this case is the row decoder and the word line trigger signal. Before the word line trigger signal is asserted at the enable terminal, the output of the tri-state buffer floats. Then the driver for the unselected row is low and the driver for the selected row is high. This performs roughly the same logical function as an AND gate, but does not continuously drive the word line on.

[0177] When the word line driver output is pulled high, the word line signal propagates down the word line 444 starting at coordinate (0,y). The first segment takes a time TR4 to propagate across the vertical portion 441 of the array 440. The word line 444 does not interact with any of the pixel drivers in the vertical section 441, but the word line 344 interacts with all of the pixel drivers in the vertical section 442, creating a condition in which the RC characteristics of the word line 444 with the vertical section 441 are different from the RC characteristics of the portion of the word line 444 in the vertical section 442. It is assumed that the capacitance in the vertical section 441 is lower than the capacitance of the section of the word line 444 in the vertical section 442, but this is less important than the possibility that the RC time constants in the two vertical sections may be different. The portion of the word line 344 in the vertical line 342 actually extends to coordinate (m,y). The termination at coordinate (x,Y) is to facilitate the remaining discussion of the propagation delay.

[0178] The total time it takes for the word line signal to reach coordinate (x,y), T TOT_WLINE The components are TR1, the time it takes for the word line trigger signal to reach the selected row, TR3, the time it takes to satisfy the AND gate logic, TR4, the propagation time across vertical section 341, and TR2, the time it takes to reach coordinate (x,y) within vertical line 342. This is known as T TOT_WLINE =TR1+TR2+TR3+TR4.

[0179] Releasing the bit line data onto the complementary bit line for delivery to the pixel driver on the selected row creates a second timing issue that must be taken into consideration: A bit line trigger signal is generated in circuitry near coordinate (0,0) and propagates to a bit line driver (not shown) at coordinate (x,0). The complementary data propagates on bit line 443 to coordinate (x,y) where it can be loaded into the SRAM memory cell located at that coordinate.

[0180] In one embodiment, the output of a bit line memory data cell is asserted with a tri-state buffer. The tri-state buffer has one data input, which is the pixel driver data from the bit line memory cell, and an enable signal in the form of a bit line trigger signal. Before the bit line trigger signal is asserted at the enable terminal, the output of the tri-state buffer floats. This effectively prevents new bit line data from encountering a word line that is still high from a previous row write sequence. All bit line drivers in all of the various embodiments of the present disclosure may operate in this manner.

[0181] In order for the bit line trigger signal propagation delays TB4 and TB1 to match the propagation delays TR4 and TR2 on the word line 444, the bit line trigger signal must match the RC time constant of the section of the word line 344 that passes under vertical section 441 and the RC time constant of the section of the word line 344 that passes under vertical section 442. In other words, TR4=TB4 and TR 2= It's TB1.

[0182] Since all pixel drivers serving the word line 344 are in the vertical section 342 and all signals directed to pixel drivers in the vertical section 342 must pass through the vertical section 341, the propagation time TR4 of the word line 444 through the vertical section 341 is unchanged. As a result, the bit line trigger signal propagation time in the region parallel to the vertical section 341 should also be unchanged. In one embodiment, TR4≠TB4, and in fact TR4≧TB4. The imbalance may result from using a straight line that is not parallel to the vertical section 341. Additional delay elements placed elsewhere may compensate for the imbalance in that case.

[0183] The portion of the word line 444 that serves as a pixel driver for the vertical portion 442 interacts with all pixel drivers found along the row y associated with coordinate (x,y). The time TR2 it takes for the word line signal to propagate from coordinate (m',y), the point where it enters the vertical section 442, to coordinate (x,y), should be the same as the time TB1, which is the time it takes for the bit line trigger signal to propagate from a point adjacent to coordinate (m',0) to coordinate (x,0), the location of the bit line driver. The situation where the shortened bit line driver trigger circuit delivers the trigger signal along some, if not all, of the parallel trigger circuits at the bottom of the vertical section 441 is conceivable and can be addressed by compensating for the delays caused by other circuits.

[0184] The most efficient way to match the propagation delay is to match the RC characteristics and length of the word line 444 at the bit line trigger signal line. Applicant notes that using the same type of circuitry at both locations will result in similar RC characteristics, provided that the capacitance at the two circuits remains substantially the same. In the case of the word line 444, the design requirements of the word line are determined by design, while the design requirements of the bit line trigger circuitry used to deliver the bit line signal are more flexible. By designing using a circuit similar to the word line to deliver the bit line trigger signal to the bit line driver, the propagation characteristics of the two circuits should be substantially similar. The regular shape of the pixel driver array supports this implementation.

[0185] For the propagation of complementary bit line data on the bit lines, a similar scheme can be adopted for the propagation of the word line trigger signal. The structure of the complementary bit line 443 is determined by the data requirements of the SRAM memory cells and by the pitch of the pixel drivers. Again, the same structure can be used to deliver the word line release signal to the row decoder and word line drive circuitry. This case is simpler since the bit line circuitry 443 only propagates through active pixel drivers and may interact with pixel drivers on any row, but in the given example only interacts with word line signals that are high.

[0186] Example 1: A backplane forming part of a display system operative to drive an array of pixel drivers, said backplane comprising a plurality of rows and a plurality of columns of pixel drivers, each pixel driver comprising a memory circuit operative to hold a bit of image data, each pixel driver operative to apply a drive waveform in response to a state of the image data in the memory circuit, said backplane further comprising at least one row decoder for each row of the array of pixel drivers, each row decoder operative to drive a single word line circuit arranged on a single row segment to select the memory circuit of the pixel driver to receive data via a bit line, a number of row segments for each row equal to the number of row decoders for each row, a set of row decoder circuits comprising at least one row decoder circuit for each row of pixel drivers arranged along a side of the array of pixel drivers, a row decoder control circuit located near the row decoder circuit and proximate to a bottom row of the array of pixel drivers, configured to control the row decoder circuit to determine which row is to receive data. a row decoder circuit which releases a signal determining which row segment is selected to receive data from the column driver when it is determined to be selected, the row decoder circuit passing a signal to a word line driver to enable the word line to be driven to a state in which the memory circuits of the row segment connected to the word line are put into a state to receive data from the column driver via bit lines, the data to be loaded into the pixel drivers of the row selected by the word line is stored by data processing circuitry in memory circuits each forming part of a column driver circuit of a set of column driver circuits, the column driver control circuits being located near the same corner of the array of pixel drivers at which location the row decoder control circuitry sends a signal to a logic circuit to assert a value on the memory circuit of the column driver to the bit line, the circuitry through which the column driver control circuitry sends a signal to assert the value on the memory circuit of the column driver on the bit line is substantially RC matched to and substantially coextensive with the word line circuitry of the array of pixel drivers such that the propagation delay of the two circuits isa backplane that is substantially matched over any selected similar distance on the two circuits;

[0187] Example 2: The backplane of Example 1, wherein the circuit through which the column driver control circuit sends a trigger signal to the column driver circuit matches a layout of the selected word line circuit and at least one adjacent unselected word line circuit.

[0188] Example 3: A backplane as described in Example 2, wherein the word line driver circuit comprises a memory circuit, an optional level shifter, and a bistable logic circuit operative to receive an input from the level shifter, receive a second input from a trigger signal circuit, and assert an output to an associated word line.

[0189] Example 4: A backplane as described in Example 3, wherein the trigger signal circuit through which the column driver control circuit sends a trigger signal to the column driver circuit comprises a series of conductor circuits that respectively tap the circuits on which the trigger signal is asserted and deliver those signals to the second inputs of a plurality of bistable logic circuits, the conductor circuits being substantially parallel to the circuits through which the column driver control circuit sends a trigger signal propagating in the same direction.

[0190] Example 5: A backplane as described in example 4, wherein each of the conductor circuits tapping the circuit to which the trigger signal is sent comprises a sample circuit disposed between a tap point on the circuit at which the trigger signal is asserted and a series of points on the conductor circuit where it connects to the second input of the bistable logic circuit, the sample circuit comprising a rising edge detector circuit element and an output circuit operative to hold an output high for a period sufficient to allow the column driver circuit to assert its output to a bit line, but short enough to ensure that the bistable logic circuit will not have a signal present at its second input when next data is written to the memory circuit of the column driver.

[0191] Example 6: The backplane of Example 1, wherein the word line driver circuit operative to control the word lines of a single row segment comprises a logic circuit operative to release a signal when two valid inputs are received, an optional voltage level shifter, and an optional isolation inverter circuit, the two inputs to the logic circuit being a signal from the row decoder circuit for the row and a release signal received via a conductor from a release timing circuit, thereby enabling the output of the selected row to place the word lines controlled by the word line driver circuit in a state where the memory circuits of the pixel drivers attached to that word line are in a state to receive asserted data via bit lines from a group of column drivers associated with those bit lines.

[0192] Example 7: The backplane of example 6, wherein the logic circuit comprises one of an AND gate, a level-sensitive D flip-flop, or an edge-sensitive D latch.

[0193] Example 8: A backplane as described in Example 6, wherein the conductors from the release timing circuit for the word line driver comprise a main conductor and a plurality of shorter parallel conductors that connect to the main conductor at tap points where the shorter conductors connect to the main conductor and connect to inputs to a subset of the logic circuits, at least a plurality of which form part of a word line driver circuit, the shorter conductors being substantially parallel to the main conductor and conducting current thereon in substantially the same direction as the direction of current in the main conductor.

[0194] Example 9: The backplane of example 7, wherein each of the plurality of shorter parallel conductors comprises a sample circuit disposed between the tap point on the main conductor and the input to the subset of the logic circuits.

[0195] Example 10: A backplane as described in Example 6, wherein the conductors on which the release signals are received are bit lines of at least one column of a dummy pixel driver substantially identical to the active pixel drivers and bit lines of an active array, and the release signals to a dummy column driver circuit are controlled and generated by a control circuit that operates to assert a timing release signal in the memory circuit of a dummy column driver circuit substantially identical to the active column driver circuit, and the memory circuit is set to a data state configured such that a signal propagating on the conductor meets the input requirements of the logic circuit for the release of that signal.

[0196] Example 11: A backplane as described in Example 10, wherein the memory circuit of the dummy column driver is configured such that the memory circuit is always in an on state, and when the release signal is received from the control circuit at the dummy column driver circuit, the conductor receives the release signal which is delivered to one input of each of the logic circuits of the associated word line driver circuit.

[0197] Example 12: The backplane with at least one row decoder for each row of the array of pixel drivers, comprising at least two row decoder circuits for each row of the array of pixel drivers, each row decoder circuit operative to drive a single word line circuit segment arranged on a section of a single row to select the memory circuits of the pixel drivers of that section operated by the word line to receive data via bit lines, each row of the array of pixel drivers comprising a similar number of pixel drivers, the rows of the array of pixel drivers being vertically divided into non-overlapping sections having distinct vertical boundaries, the number of vertical sections corresponding to the number of row decoder circuits, all pixel drivers of all rows being located in one and only one section, all pixel drivers of each row segment within each section being operated by a single word line driver controlled by a single row decoder circuit, each row being controlled by an equal number of row decoder circuits in the same position relative to an edge of the array of pixel drivers, each row of the array of pixel drivers comprising at least two row decoder circuits, each row decoder circuit operative to drive a single word line circuit segment arranged on a section of a single row to select the memory circuits of the pixel drivers of that section operated by the word line to receive data via bit lines, each row of the array of pixel drivers comprising a similar number of pixel drivers, the rows of the array of pixel drivers being vertically divided into non-overlapping sections having distinct vertical boundaries, the number of vertical sections corresponding to the number of row decoder circuits, all pixel drivers of all rows being located in one and only one section, all pixel drivers of each row segment within each section being operated by a single word line driver controlled by a single row decoder circuit, a first row decoder of the at least two row decoders disposed proximate an edge of the pixel driver array, a second row decoder of the at least two row decoders for each row of the pixel driver array disposed proximate a first row decoder circuit of the at least two row decoder circuits with the at least two row decoder circuits between the second row decoder of the at least two row decoder circuits and an edge of the pixel driver array, each of the at least two row decoders for each row connecting to word lines of different segments of that row via an intervening word line driver, the first row decoder circuit of the at least two row decoder circuits disposed proximate the edge of the pixel driver array controls a word line operative to control the memory circuit of an associated row of a first vertical section of the pixel driver array, and the second row decoder circuit of the at least two row decoder circuits disposed proximate the first row decoder circuit of the at least two row decoder circuits disposed proximate the edge of the pixel driver arraya second word line operative to control the memory circuitry of a row of a second vertical section of the array of pixel drivers, one of the first and second vertical sections of the array of pixel drivers adjacent to the edge of the pixel driver array and the other of the first and second vertical sections of the array of pixel drivers adjacent to an opposite edge of the other vertical section of pixel drivers, the word line of the row of the vertical section of the array of pixel drivers adjacent to the edge of the array of pixel drivers controlling a state of the memory circuitry of that vertical section, and the word line of the row of the vertical section of the array of pixel drivers adjacent to the opposite edge of the vertical section of the array of pixel drivers adjacent to the edge of the array of pixel drivers controlling a state of the memory circuitry of that vertical section, respectively, a first word line segment passing through the first vertical section without interacting with the memory circuitry of that pixel driver and a second word line segment passing through the second vertical section and controlling the state of the memory circuitry of that pixel driver. and a second word line segment electrically connected to the non-interacting first word line segment which controls the state of the memory circuit of a row of the vertical section of pixel drivers; a separate row decoder control circuit is present for each set of row decoder circuits operative to control the state of the memory circuit of a row of the vertical section of pixel drivers, each separate row decoder circuit receives a signal from the row decoder control circuit of its set of row decoder circuits which determines which row is selected for data to be written into the memory circuit of the pixel driver of that row controlled by the word line control circuit by the word line driver controlled by the row decoder circuit; upon detecting that it has been selected, each row decoder circuit passes a signal to its associated word line driver to enable it to drive its associated word line segment to a state in which the memory circuit connected to that word line segment is put into a state to receive data via a bit line; and data to be loaded onto the pixel driver of the row segment selected by the word line is controlled by a data processing circuit,2. The backplane of claim 1, wherein: the pixel driver circuits are loaded into memory circuits forming part of a set of column driver circuits, the column driver control circuits are located near a bottom of the array of pixel drivers in a corner position such that the column driver circuits can deliver release signals to logic circuits enabling the column driver circuits to assert the data values ​​on the memory circuits of the column drivers to the bit lines, the circuitry for each column driver control circuit sending a signal to its associated column driver circuit to assert the value on the memory circuit of the column driver circuit to the bit lines is substantially RC matched to the word line circuitry of the array of pixel drivers of the array of pixel drivers, such that the propagation delays of the two circuits are substantially matched over any selected distance.

[0198] Example 13: A backplane as described in Example 12, wherein the circuitry by which each of the column driver control circuits sends a trigger signal to its respective control driver circuit matches the layout of the selected word lines of the respective word line circuits associated with the same section of the array of pixel drivers.

[0199] Example 14: A backplane as described in Example 13, wherein each of the word line driver circuits comprises a memory circuit, an optional level shifter or alternatively a conductor, and a bistable logic circuit operative to receive an input from the optional level shifter or conductor, to receive a second input from a trigger signal circuit, and to assert an output onto one of a plurality of inverter circuits in series.

[0200] Example 15: The backplane of Example 12, wherein each word line driver circuit operative to control responsive word lines of a single row segment comprises a logic circuit operative to release a signal when two valid inputs are received, an optional voltage level shifter or direct conductor, and an optional isolation inverter circuit, the two inputs to the logic circuit being a signal from the row decoder circuit of the row and a release signal received via conductors from a release timing circuit, thereby enabling the output of the selected word line driver circuit to place the word lines controlled by the word line driver circuit into a state in which the memory circuits of the pixel drivers attached to those word lines receive asserted data via bit lines from the group of column drivers associated with those bit lines.

[0201] Example 16: The backplane of Example 15, wherein the logic circuit comprises one of an AND gate, a D flip-flop circuit responsive to a signal level, or a D latch responsive to the edge of the signal applied thereto.

[0202] Example 17: The backplane of example 1, wherein the word line high signal operates at a voltage lower than an upper supply voltage of the array of pixel drivers.

[0203] Example 1A: An apparatus comprising: a target pixel driver in a pixel driver array; a row select path and a word line path including a word line, the row select path including a plurality of row drivers and a first plurality of dummy pixel drivers, the apparatus further comprising a data load trigger path and a bit line path including a bit line, the word line and the bit line intersect at the target pixel driver in the pixel driver array, and the data load trigger path includes a column driver and a second plurality of dummy pixel drivers.

[0204] Example 2A: The apparatus of example 1A, wherein the first plurality of dummy pixel drivers are adapted to mirror a configuration of the word lines.

[0205] Example 3A: The apparatus of any of Examples 1A or 2A, wherein the first plurality of dummy pixel drivers are simulated by a plurality of disabled data storage elements.

[0206] Example 4A: The apparatus of example 3A, wherein the plurality of disabled data storage elements are adapted to introduce an RC characteristic along an enable line to a trigger source of the trigger initiation circuit.

[0207] Example 5A: The apparatus of example 4A, wherein the RC characteristic along the enable line is determined as an RC characteristic of the data load trigger path.

[0208] Example 6A: The apparatus of example 1A, wherein the column driver includes a disabled data storage element.

[0209] Example 7A: The device of any of Examples 1A-6A, wherein the row select paths are aligned orthogonally to the word lines and parallel to the bit lines.

[0210] Example Implementation 8A: The apparatus of any of Examples 1A-7A, wherein the word line follows the row select path in the word line path and the bit line follows the data load trigger path in the bit line path.

[0211] Example 9A: The apparatus of any of Examples 1A-8A, wherein the row select path is disposed outside the pixel driver array, and the word line is disposed within the pixel driver array.

[0212] Example 10A: The apparatus of any one of Examples 1A to 9A, wherein the data load trigger path is disposed outside the pixel driver array, and the bit line is disposed within the pixel driver array.

[0213] Example 11A: The apparatus of any of Examples 1A-10A, wherein the row select path in the word line path is aligned parallel to the bit lines.

[0214] Example 12A: The apparatus of any of Examples 1A-11A, wherein the data load trigger path in the bit line path is aligned parallel to the word line.

[0215] Example 13A: The apparatus of any of Examples 1A to 12A, further comprising a trigger initiation circuit configured to transmit image data via the word line path and the bit line path.

[0216] Example 14A: The apparatus of any of Examples 1A-13A, wherein the row selection path includes a first row selection path portion parallel to a second row selection path portion.

[0217] Example 15A: The apparatus of example 14A, wherein the first row select path portion includes a section of a row driver having a dummy pixel driver and a section of a dummy pixel driver without a row driver.

[0218] Example 16A: The apparatus of any of Examples 1A-15A, wherein the row select path and the data load trigger path are included in a backplane associated with the pixel driver array.

[0219] Example 17A: The device of any of Examples 1A to 16A, wherein the pixel driver array comprises a plurality of word lines, a plurality of bit lines, and an array of dummy pixel drivers adapted to mirror the configuration of the plurality of word lines and the plurality of bit lines.

[0220] The implementations described herein enable the development of large arrays of pixel drivers based on memory elements that have a predictable delay from the start of writing the pixel driver to writing both the bit line and the word line pixel drivers by using design techniques to reduce the time discrepancy between the time of arrival of the rising word line and the time of arrival of the data being written to the bit line. The design techniques described herein, when implemented, result in precise time tracking for all pixel drivers in the array, not just for a small subset of one location.

[0221] Other applications of the design techniques described herein are contemplated within the scope of the embodiments described herein.

[0222] Various implementations of the systems and techniques described herein can be realized in digital electronic circuitry, integrated circuits, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementation in one or more computer programs executable and / or interpretable by a programmable system including at least one programmable processor, which may be special-purpose or general-purpose, coupled to receive data and instructions from the storage system, and to transmit data and instructions to the storage system.

[0223] These computer programs (also known as programs, software, software applications, or code) include machine instructions for a programmable processor and may be implemented in high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and / or device (e.g., magnetic disks, optical disks, memory, programmable logic circuits (PLDs)) used to provide machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0224] To provide interaction with a user, the systems and techniques described herein are implemented on a computer having a display device (e.g., a CRT or LCD monitor) for displaying information to a user, and a keyboard and pointing device (e.g., a mouse or trackball) by which the user can provide input to the computer. Other types of devices can also be used to provide interaction with a user, for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback), and input from the user can be received in any form, including acoustic, verbal, or tactile input.

[0225] The individually described systems and techniques can be implemented in a computing system that includes back-end components (e.g., as a data server), or that includes middleware components (e.g., an application server), or that includes a front-end component (e.g., a client computer having a graphical user interface or a web browser through which a user can interact with an embodiment of the systems and techniques described herein), or in a combination of such back-ware, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communications network). Examples of communications networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0226] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0227] In this specification and the appended claims, the singular forms "a," "an," and "the" do not exclude plural references unless expressly stated otherwise. Furthermore, conjunctions such as "and," "or," and "and / or" are inclusive unless the context clearly dictates otherwise. For example, "A and / or B" includes A alone, B alone, and A and B. Furthermore, the connecting lines or connectors shown in the various figures presented are intended to represent example functional relationships and / or physical or logical couplings between the various elements. Many alternative or additional functional relationships, physical connections, or logical connections may be present in a practical device. Furthermore, unless an element is specifically described as "essential" or "critical," no article or component is essential to the practice of the embodiments disclosed herein.

[0228] Terms such as, but not limited to, about, substantially, generally, etc. are used herein to indicate that an exact value or range is not required or need not be specified. As used herein, the above terms have a readily and immediately applicable meaning to one of ordinary skill in the art.

[0229] Additionally, use of terms such as up, down, top, bottom, side, end, front, back, etc. herein are used with reference to the orientation currently considered or illustrated, and it is to be understood that when they are considered with respect to another orientation, such terms must be correspondingly modified.

[0230] Although certain exemplary computer-implemented methods, apparatus, and articles of manufacture are described herein, the scope of coverage of this patent is not limited thereto. It is to be understood that the terminology used herein is for the purpose of describing particular aspects, and is not intended to be limiting. On the contrary, this patent covers all methods, apparatus, and articles of manufacture that fairly fall within the scope of the claims of this patent.

[0231] In one aspect, a non-transitory computer-readable medium stores instructions that, when executed by a processor at a receiving computing device, cause the receiving computing device to perform any of the methods disclosed herein.

[0232] In one aspect, a computing device may be configured with at least one processor and a memory storing instructions that, when executed by the at least one processor, perform any of the methods disclosed herein.

Claims

1. An apparatus comprising: a target pixel driver in a pixel driver array; a row select path and a word line path including word lines, the row select path including a plurality of row drivers and a first plurality of dummy pixel drivers, the apparatus further comprising:

11. An apparatus comprising: a bit line path including a data load trigger path and a bit line, the word line and the bit line intersecting at the target pixel driver in the pixel driver array, the data load trigger path including a column driver and a second plurality of dummy pixel drivers.

2. The apparatus of claim 1 , wherein the first plurality of dummy pixel drivers are adapted to mirror a configuration of the word lines.

3. 3. The apparatus of claim 1, wherein the first plurality of dummy pixel drivers are simulated by a plurality of disabled data storage elements.

4. The apparatus of claim 3 , wherein the plurality of disabled data storage elements are adapted to introduce an RC characteristic along an enable line to a trigger source of a trigger initiation circuit.

5. The apparatus of claim 4 , wherein the RC characteristics along the enable line are determined as the RC characteristics of the data load trigger path.

6. The apparatus of claim 1 , wherein the column driver comprises a disabled data storage element.

7. The apparatus of any preceding claim, wherein the row select paths are aligned orthogonally to the word lines and parallel to the bit lines.

8. An apparatus as claimed in any preceding claim, wherein the word lines follow the row select path in the word line paths and the bit lines follow the data load trigger path in the bit line paths.

9. An apparatus according to any preceding claim, wherein the row select paths are arranged outside the pixel driver array and the word lines are arranged within the pixel driver array.

10. The apparatus of any one of claims 1 to 9, wherein the data load trigger path is arranged outside the pixel driver array, and the bit lines are arranged within the pixel driver array.

11. The apparatus of any preceding claim, wherein the row select paths within the word line paths are aligned parallel to the bit lines.

12. The apparatus of any preceding claim, wherein the data load trigger path in the bit line path is aligned parallel to the word line.

13. The apparatus of any preceding claim, further comprising a trigger initiation circuit configured to transmit image data over the word line paths and the bit line paths.

14. An apparatus according to any preceding claim, wherein the row selection path comprises a first row selection path portion parallel to a second row selection path portion.

15. 15. The apparatus of claim 14, wherein the first row select path portion includes a section of a row driver having a dummy pixel driver and a section of a dummy pixel driver without a row driver.

16. An apparatus according to any preceding claim, wherein the row select path and the data load trigger path are contained within a backplane associated with the pixel driver array.

17. 17. The apparatus of claim 1, wherein the pixel driver array comprises a plurality of word lines, a plurality of bit lines, and an array of dummy pixel drivers adapted to mirror the configuration of the plurality of word lines and the plurality of bit lines.

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