Method for enhancing lithographic patterning using semiconductor stress film tailoring - Patents.com

Abstract

An aspect of the present disclosure provides a method for optimizing wafer shape. For example, the method may include receiving a wafer having a working surface for fabricating one or more devices thereon and a back surface opposite the working surface, measuring the wafer to determine a curvature measurement of the wafer, and forming a first stressor film on the back surface. The first stressor film may be responsive to light of a first wavelength in that exposure to light of the first wavelength modifies an internal stress of the first stressor film. The method may further include exposing a pattern of light of the first wavelength to the first stressor film to modify the internal stress of the first stressor film. The pattern of light of the first wavelength corresponds to the curvature measurement.

Description

[Technical field]

[0001] Incorporation by Reference This disclosure claims the benefit of U.S. Provisional Patent Application No. 63 / 306,585, filed February 4, 2022, entitled "METHOD TO ENHANCE LITHOGRAPHY PATTERN CREATION USING SEMICONDUCTOR STRESS FILM TUNING," and U.S. Nonprovisional Patent Application No. 17 / 890,766, filed August 18, 2022, entitled "METHOD TO ENHANCE LITHOGRAPHY PATTERN CREATION USING SEMICONDUCTOR STRESS FILM TUNING," which are incorporated by reference in their entireties herein.

[0002] The present disclosure relates to semiconductor manufacturing, and more particularly to wafer curvature, bow and overall wafer shape. [Background technology]

[0003] The description of the background art provided herein is intended to generally present the background art of the present disclosure. The inventors' work and described aspects of the present disclosure that would not otherwise be recognized as prior art at the time of filing to the extent described in this Background Art section are not expressly or implicitly admitted as prior art to the present disclosure.

[0004] Semiconductor manufacturing involves several different steps and processes. One typical manufacturing process is known as photolithography (also called microlithography). Photolithography uses radiation, such as ultraviolet or visible light, to create fine patterns in semiconductor device designs. Semiconductor manufacturing techniques, including photolithography, etching, film deposition, surface cleaning, metallization, etc., can be used to construct a variety of semiconductor devices, such as diodes, transistors, and integrated circuits.

[0005] Exposure systems (also called exposure tools) are used to implement photolithography techniques. Exposure systems typically include an illumination system, a reticle (also called photomask) or spatial light modulator (SLM) that creates the circuit pattern, a projection system, and a wafer alignment stage that aligns a semiconductor wafer covered with a photosensitive resist. The illumination system illuminates an area of ​​the reticle or SLM with a (preferably) rectangular slot illumination field. The projection system projects an image of the illuminated area of ​​the reticle pattern onto the wafer. For accurate projection, it is important to expose the light pattern onto a relatively flat or planar wafer, preferably with a height deviation of less than 10 microns. Summary of the Invention [Means for solving the problem]

[0006] Aspects of the present disclosure provide a method for achieving an optimal wafer shape. For example, the method may include receiving a wafer having a working surface for fabricating one or more devices thereon and a back surface opposite the working surface, measuring the wafer to determine a curvature measurement of the wafer, and forming a first stressor film on the back surface. The first stressor film may be responsive to a first wavelength of light in that exposure to the first wavelength of light modifies an internal stress of the first stressor film. The method may further include exposing the first stressor film to a pattern of the first wavelength of light to modify the internal stress of the first stressor film, the pattern of the first wavelength of light corresponding to the curvature measurement. In an embodiment, the first stressor film may be formed while holding the peripheral edge of the wafer.

[0007] In an embodiment, measuring the wafer to determine the wafer curvature measurement may be performed prior to forming the first stressor film, hi another embodiment, measuring the wafer to determine the wafer curvature measurement may be performed after forming the first stressor film.

[0008] In an embodiment, the work surface of the wafer may have one or more devices fabricated thereon, and the method may further include forming a protective layer on the work surface of the wafer to protect the devices. For example, measuring the wafer to determine the wafer curvature measurement may be performed after forming the protective layer. As another example, measuring the wafer to determine the wafer curvature measurement may be performed before forming the protective layer. In another embodiment, the wafer is inverted so that the protective layer can contact the wafer chuck when forming the first stressor film.

[0009] In an embodiment, the method may further include performing one or more lithographic patterning processes on the work surface of the wafer, hi another embodiment, the method may further include removing the first stressor film after performing the lithographic patterning processes.

[0010] In an embodiment, the method may further include forming a second stressor film on the first stressor film. The second stressor film may be responsive to the second wavelength of light in that exposure to the second wavelength of light modifies the internal stress of the second stressor film. The method may further include exposing the second stressor film to a pattern of the second wavelength of light to modify the internal stress of the second stressor film, the pattern of the second wavelength of light corresponding to the curvature measurement. For example, measuring the wafer to determine the curvature measurement of the wafer may be performed after forming the second stressor film.

[0011] In an embodiment, the method may further include forming a stressed film on a backside of the wafer, and forming the first stressor film on the backside may include forming the first stressor film on the stressed film. In another embodiment, the method may further include removing a portion of the stressed film and replacing the removed portion with a stressed layer. In some embodiments, the stressed layer may have a different stress type than the stressed film.

[0012] Aspects of the present disclosure also provide a system for achieving optimal wafer shape. For example, the system may include a curvature measurement device, a stressor film forming device, a light generator, and a controller coupled to the curvature measurement device, the stressor film forming device, and the light generator. The curvature measurement device may be configured to measure the wafer to determine a curvature measurement value of the wafer. The wafer may have a working surface for fabricating one or more devices thereon and a back surface opposite the working surface. The stressor film forming device is configured to form first and second stressor films. The first and second stressor films may be responsive to the first and second wavelengths of light, respectively, in that exposure to the first and second wavelengths of light modifies internal stresses of the first and second stressor films, respectively. The light generator may be configured to generate patterns of the first and second wavelengths of light. The controller may be configured to control the curvature measuring device to measure the wafer to determine a curvature measurement value of the wafer; control the stressor film forming device to sequentially form first and second stressor films on a back side of the wafer; and control the light generator to generate a pattern of light at a first wavelength and / or a pattern of light at a second wavelength and transfer the pattern of light at the first wavelength and / or the pattern of light at the second wavelength onto the first stressor film and / or the second stressor film, wherein the pattern of light at the first wavelength and the pattern of light at the second wavelength correspond to the curvature measurement value.

[0013] In an embodiment, the system may further include a lithography module coupled to the controller. The lithography module may be configured to be controlled by the controller to form a stressed film on the backside of the wafer, remove a portion of the stressed film, and replace the removed portion of the stressed film with a stressed layer. For example, the stressed layer may have a different stress type than the stressed film.

[0014] In an embodiment, the controller may be configured to control the stressor film forming device to form the first stressor film or the first and second stressor films on the stressed film. In another embodiment, the controller may be configured to first control the stressor film forming device to form the first stressor film or the first and second stressor films on the backside of the wafer, and then control the curvature measuring device to measure the wafer to determine a curvature measurement value of the wafer.

[0015] It should be noted that this summary section does not specify every embodiment and / or every inherently novel aspect of the present disclosure or claimed invention. Rather, this summary provides only a preliminary discussion of various embodiments and corresponding points of novelty over the prior art. For additional details and / or anticipated aspects of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.

[0016] Various embodiments of the present disclosure, proposed by way of example, will now be described in detail with reference to the following figures, in which like numbers refer to like elements, and in which: [Brief description of the drawings]

[0017] [Figure 1A] The primary and secondary curvature of the wafer is shown. [Figure 1B] The primary and secondary curvature of the wafer is shown. [Figure 1C] The primary and secondary curvature of the wafer is shown. [Diagram 2] FIG. 1 is a functional block diagram of an exemplary system for achieving optimal wafer shape, in accordance with some embodiments of the present disclosure. [Diagram 3] 1 illustrates an exemplary method used to optimize a wafer shape of a semiconductor structure according to a first embodiment of the present disclosure. [Figure 4] 1 illustrates an exemplary method used to optimize a wafer shape of a semiconductor structure according to a first embodiment of the present disclosure. [Diagram 5] 1 illustrates an exemplary method used to optimize a wafer shape of a semiconductor structure according to a first embodiment of the present disclosure. [Figure 6] 1 illustrates an exemplary method used to optimize a wafer shape of a semiconductor structure according to a first embodiment of the present disclosure. [Figure 7] 1 illustrates an exemplary method used to optimize a wafer shape of a semiconductor structure according to a first embodiment of the present disclosure. [Figure 8] 1 illustrates an exemplary method used to optimize a wafer shape of a semiconductor structure according to a first embodiment of the present disclosure. [Figure 9] 1 illustrates an exemplary method used to optimize a wafer shape of a semiconductor structure according to a first embodiment of the present disclosure. [Figure 10] 1 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a second embodiment of the present disclosure. [Figure 11] 1 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a second embodiment of the present disclosure. [Figure 12] 1 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a second embodiment of the present disclosure. [Figure 13] 1 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a second embodiment of the present disclosure. [Figure 14] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a third embodiment of the present disclosure. [Figure 15] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a third embodiment of the present disclosure. [Figure 16] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a third embodiment of the present disclosure. [Figure 17] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a third embodiment of the present disclosure. [Figure 18] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a third embodiment of the present disclosure. [Figure 19] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a third embodiment of the present disclosure. [Figure 20] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a fourth embodiment of the present disclosure. [Figure 21] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a fourth embodiment of the present disclosure. [Figure 22] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a fifth embodiment of the present disclosure. [Diagram 23] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a fifth embodiment of the present disclosure. [Figure 24] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a fifth embodiment of the present disclosure. [Diagram 25] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a fifth embodiment of the present disclosure. [Figure 26] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a sixth embodiment of the present disclosure. [Figure 27] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a sixth embodiment of the present disclosure. [Figure 28] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a sixth embodiment of the present disclosure. [Figure 29] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a sixth embodiment of the present disclosure. [Diagram 30] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a sixth embodiment of the present disclosure. [Diagram 31] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a seventh embodiment of the present disclosure. [Diagram 32] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a seventh embodiment of the present disclosure. [Diagram 33] 13 illustrates an exemplary method used to optimize wafer shape of a semiconductor structure according to a seventh embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] To achieve the highest resolution using laser or EMS λ (electromagnetic spectrum wavelength) sensitive lithography emulsions on the mask to define areas to be blocked or open for subsequent pattern transfer or implantation, the wafer surface needs to be optimally shaped prior to the photo / lithography process. The techniques disclosed herein include stress modification of films on the wafer to achieve target curvature or correction. The techniques herein can use any type of photosensitive wavelength / lithography type in the electromagnetic spectrum (some examples are photolithography, electron beam lithography, direct laser writing lithography, and x-ray lithography).

[0019] The techniques disclosed herein define several process flows to achieve an optimal starting wafer shape (using semiconductor stress film tuning or by tuning its lattice) prior to the photo process used on the working surface of the wafer. The process flows herein include, as one option, providing a disposable stress tuning film on the backside of the wafer. Another option is to leave the stress tuning film in place for subsequent processing, for use in some cases where low temperature processing is possible for some steps.

[0020] Lithographic films can be used to pattern with a mask or by direct writing with features of the lithographic stress film. One unique aspect of the present invention is that the deposited lithographic film can have compressive, tensile or neutral stress as deposited as a lithographic emulsion sensitive to a particular laser or EM wavelength. Thus, microstressed regions can be defined by masking and etching the deposited film or by direct writing (or an option) of areas where selective compressive / neutral / tensile regions are desired. The process can also be replicated using two different deposition methods (i.e., one sensitive to a first laser wavelength and the other to a second laser wavelength) to eliminate wafer curvature after laser processing.

[0021] Techniques herein include wafer stress modification techniques to correct wafer bow and curvature to improve wafer overlay. Stress film deposition can be performed with the wafer face up or face down as an option for all process flows for all flows that have the option of clamping the wafer.

[0022] Microfabrication of semiconductor structure 100 begins with a flat substrate or wafer 110, such as the one shown in FIGS. 1A-1C. During microfabrication of semiconductor structure 100, multiple processing steps are performed, which may include depositing material on substrate 110, removing material, implanting dopants, annealing, baking, etc. The different materials and structure formations 120 thus formed induce internal stresses in substrate 110, which result in curvature of semiconductor structure 100, which in turn affects overlay, typically resulting in overlay errors of various magnitudes. For example, FIGS. 1A and 1B show how the different materials and structure formations 120 induce compressive or tensile stresses, respectively, in substrate 110, which results in a primary curvature with a curvature measurement indicating a height deviation in the z-direction from a reference plane (not shown). As another example, FIG. 1C shows a secondary curvature of substrate 110, with two curvature measurements each identifying a positive and negative z-direction height deviation.

[0023] If an area of ​​the substrate 110 initially contains compressive or tensile stress, an opposite type of stress can be applied to the local nano-stress area. The techniques herein can use laser-sensitive lithographic films to generate stress. Certain films can respond to actinic radiation to change the type and magnitude of their stress. Other films can be patterned using an etch mask. For example, a stressor film is deposited and then a photoresist layer is deposited on the stressor film. The photoresist layer is patterned and developed, resulting in a relief pattern or etch mask. This etch mask is used to etch the underlying stressor film, thereby releasing or inducing stress depending on the etch mask.

[0024] FIG. 2 is a functional block diagram of an exemplary semiconductor processing system 200 for achieving optimal wafer shape according to some embodiments of the present disclosure. For example, the system 200 may include a metrology instrument (e.g., a curvature measurement device 210) configured to measure a substrate or wafer (e.g., the substrate 110 shown in FIG. 1) to determine a curvature measurement value of the wafer. In an embodiment, the curvature measurement device 210 may use optical mechanisms (e.g., using a scanning laser technique), acoustic mechanisms, and other mechanisms to measure height deviations in the z direction across the surface of the wafer, store the height deviations by (x,y) coordinates, and determine multiple sub-curvature measurements (x,y) of the curvature measurement value. The height deviations in the z direction may be mapped with various resolutions depending on the type of metrology instrument used and / or the desired resolution. The curvature measurements (and sub-curvature measurements as well) may include raw curvature data or may be expressed as a curvature signature having a relative value. In an embodiment, the wafer has a working surface and a back surface opposite the working surface. A wafer may have an amount of wafer curvature resulting from one or more micro-fabrication processing steps performed to create at least a portion of a semiconductor structure on the working surface of the wafer, for example, a transistor gate may be complete or only partially complete.

[0025] The system 200 further includes a deposition module or spin-coating module (e.g., stressor film forming device 220) configured to deposit and form a stressor film on the backside and / or working surface of the wafer. The stressor film can be exposed to light and have its internal stress modified by the light exposure. The stressor film forming device 220 can be configured to form two or more stressor films having different (e.g., opposing) stresses.

[0026] The system 200 further includes a light generator 230 configured to generate a pattern of light. In an embodiment, the curvature measurement device 210 can measure the wafer to determine a curvature measurement of the wafer, the curvature measurement including multiple sub-curvature measurements corresponding to the pattern of light. The light generator 230 can generate multiple wavelengths of light.

[0027] System 200 further includes a lithography module 250, which may include a number of components, such as a wafer chuck for placing the wafer thereon, a robotic handler configured to flip the wafer, a wafer clamper configured to clamp the wafer, a bake device configured to bake the photoresist, an imaging device configured to expose the photoresist to an actinic radiation pattern, a development device configured to develop a latent image in the photoresist, and an etching device configured to use plasma or gas phase etching or wet etching.

[0028] The system 200 further includes a controller 240, which is coupled to the curvature measurement device 210, the stressor film forming device 220, the light generator 230, and the lithography module 250. The controller 240 is configured to: control the curvature measurement device 210 to measure the wafer to determine the curvature measurements (and sub-curvature measurements) of the wafer; control the stressor film forming device 220 to form a stressor film on the backside and / or working surface of the wafer; control the light generator 230 to generate patterns of light with different wavelengths and transfer the patterns of light with different wavelengths onto the stressor film, where the patterns of light with different wavelengths correspond to the curvature measurements (and sub-curvature measurements); and control the lithography module 250 to form a stress film, etch away portions of the stress film, and replace the removed portions of the stress film with a neutral, tensile, or compressive stress material.

[0029] Alternatively or in addition, the controller 240 may be coupled to one or more additional controllers / computers (not shown) from which the controller 240 can obtain setting and / or configuration information. The controller 240 may be used to configure any or all of the elements of the system 200, and the controller 240 may collect, provide, process, store and display data from any or all of the tool components. The controller 240 may include multiple applications for controlling any or all of the tool components. For example, the controller 240 may include a graphic user interface (GUI) component that may provide an easy-to-use interface that allows a user to monitor and / or control one or more tool components.

[0030] The controller 240 may include a microprocessor, memory, and digital I / O ports that may generate sufficient control voltages to communicate with, activate inputs to, and exchange information with the semiconductor processing system 200, as well as monitor outputs from the semiconductor processing system 200. For example, the controller 240 may utilize a program stored in the memory to activate inputs to the lithography module 250 and / or the stressor film forming device 220 according to a process recipe to perform integrated substrate processing. The controller 240 may be implemented as a general-purpose computer system in which the processor executes some or all of the microprocessor-based processing steps of the present invention in response to executing one or more sequences of one or more instructions contained in the memory. Such instructions may be read into the controller's memory from another computer-readable medium, such as a hard disk or a removable media drive. One or more processors of a multi-processing configuration may also be used as the controller's microprocessor to execute the sequences of instructions contained in the main memory. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions. Thus, the embodiments are not limited to any particular combination of hardware circuitry and software.

[0031] The controller 240 may be located locally relative to the system 200 or may be located remotely relative to the system 200. For example, the controller 240 may exchange data with the system 200 using at least one of a direct connection, an intranet, the Internet, and a wireless connection. The controller 240 may be coupled to an intranet, for example, at a customer site (i.e., device manufacturer, etc.), or may be coupled to an intranet, for example, at a vendor site (i.e., equipment manufacturer). In addition, for example, the controller 240 may be coupled to the Internet. Furthermore, another computer (i.e., controller, server, etc.) may access and exchange data with, for example, the controller 240 via at least one of a direct connection, an intranet, and the Internet. Also, as will be appreciated by those skilled in the art, the controller 240 may exchange data with the system 200 via a wireless connection.

[0032] 3-9 show an exemplary method used to optimize the wafer shape of a semiconductor structure 300 according to a first embodiment of the present disclosure. In the exemplary method of the first embodiment, a light-responsive stressor film is deposited and formed on the backside of the wafer, and light is exposed such that the internal stress of the stressor film is modified based on the curvature measurements of the wafer. As shown in FIG. 3, the semiconductor structure 300 is placed on a wafer chuck 390. The semiconductor structure 300 may include a substrate 310 and one or more semiconductor devices 320 fabricated on a working surface 340 of the substrate 310 by stacking 3D gate-all-around (GAA) nanosheets. The semiconductor devices 320 may include logic gates, memory, and / or other components. For example, the semiconductor devices 320 may include complementary field effect transistors (CFETs). A protective layer 330 may be formed on the working surface 340 of the wafer (including the substrate 310 and the semiconductor devices 320) to protect the semiconductor devices 320.

[0033] As shown in FIG. 4, scanning laser technology 410 can be used (e.g., by curvature measurement device 210) to measure height deviations in the z direction across the surface of the wafer and store the height deviations by (x,y) coordinates to identify sub-curvature measurements of the wafer curvature measurements. Stress measurements are required for each wafer since each wafer has a unique stress / curvature measurement. Conventional and novel metrology tools can be used to measure or scan the surface of the wafer. Thus, the wafer curvature measurements herein are maps of coordinate locations of height values ​​or wafer curvature in the z direction.

[0034] As shown in FIG. 5, the wafer is flipped upside down and then a stressor film 510 can be formed (e.g., by the stressor film forming device 220) and attached to the backside 540 of the wafer. The stressor film 510 (e.g., an epoxy film) can be light sensitive in that exposure of the stressor film 510 to light modifies the internal stress of the stressor film 510. For example, the stressor film 510 can have a neutral internal stress and can be exposed to a pattern of light generated by the light generator 230 and reacted to be modified to be in compression or tension at various locations corresponding to the pattern of light. In some embodiments, the stressor film 510 can be initially in compression or tension and after the stressor film 510 is formed, a scanning laser technique 410 is used to measure the height deviation in the z direction across the surface of the wafer (including the stressor film 510) and store the height deviation by (x,y) coordinates to identify sub-curvature measurements of the curvature measurements of the wafer (including the stressor film 510).

[0035] 6, a pattern of light 610 is then generated (e.g., by light generator 230) based on the sub-curvature measurements of the curvature measurements of the wafer, and the pattern of light 610 is exposed to the stressor film 510 such that the internal stress of the stressor film 510 is modified by the pattern of light 610 corresponding to the sub-curvature measurements. Thus, the modified internal stress of the stressor film 510 corresponds to the curvature measurements of the wafer, and the wafer is considered to be near flat or flat.

[0036] The wafer is flipped again, as shown in Figure 7, and then the protective layer 330 (shown in Figure 6) is removed. The semiconductor structure 300 can then be ready for processing via a masking step with the stressor film 510, whose internal stress has been modified, to obtain a photopattern (not shown).

[0037] As shown in FIG. 8, a protective layer 810 is formed on the working surface 340 of the wafer to protect the device to be fabricated during the masking step, the wafer is flipped again, and the stressor film 510 (shown in FIG. 7) is removed. Stress memorization may also be used here. In some embodiments, even if the stressor film 510 is removed, the semiconductor lattice still has a memory effect because the stress of the stressor film 510 is transferred to the silicon lattice.

[0038] The wafer can then be flipped over and the next backside stress photo sequence repeated, as shown in FIG.

[0039] 10-13 show an exemplary method used to optimize the wafer shape of a semiconductor structure 1000 according to a second embodiment of the present disclosure. In the exemplary method of the second embodiment, when the stressor film is formed, the wafer is clamped by a wafer clamper. As shown in FIG. 10 following FIG. 3 and FIG. 4, the wafer is turned upside down and clamped by a wafer clamper 1090 with the back surface 540 and the protective layer 330 exposed, and the stressor film 1010 is deposited and formed on the back surface 540 of the wafer. The stressor film 1010 may initially have a compressive stress, a neutral stress, or a tensile stress.

[0040] 11, the stressor film 1010 is exposed to a pattern of light 1110 that corresponds to the curvature measurements (sub-curvature measurements) of the wafer, and its internal stresses are modified accordingly. In an exemplary embodiment, the pattern of light (and light generator 230) is located below the wafer, as the wafer is clamped by wafer clamper 1090 such that the backside 540 of the wafer is open to light (e.g., laser) treatment.

[0041] As shown in Figure 12, the protective layer (shown in Figure 11) is removed and the wafer is placed back on the wafer chuck 390. The semiconductor structure 1000 can then be ready for processing via a masking step with the stressor film 1010, whose internal stress has been modified, to obtain a photopattern (not shown).

[0042] The wafer is clamped by wafer clamper 1090 and flipped upside down again, as shown in Figure 13, and the stressor film 1010 (shown in Figure 12) is removed. The wafer is flipped again, and the next backside stress photo sequence can then be repeated.

[0043] In the exemplary method of the first embodiment shown in Figures 10-13, the stressor film 1010 can be replaced with another stressor film, which can be patterned and etched based on the curvature measurements of the wafer using direct writing (or masking / etching) at a laser wavelength different from that used in the pattern of light 1110.

[0044] 14-19 show an exemplary method used to optimize the wafer shape of a semiconductor structure 1400 according to a third embodiment of the present disclosure. In the exemplary method of the third embodiment, two stressor films are formed on the backside of the wafer and two patterns of light having different wavelengths are exposed. As shown in FIG. 14, which follows FIG. 3 and FIG. 4, the wafer is turned upside down and placed on a wafer chuck 390, and a first stressor film 1410 and a second stressor film 1420 are sequentially deposited and formed on the backside 540 of the wafer. The first and second stressor films 1410 and 1420 may initially have compressive, stress, neutral stress or tensile stress. The first stressor film 1410 is sensitive to a laser of a first wavelength, and the second stressor film 1420 is sensitive to a laser of a second wavelength. Exposing the first and second stressor films 1410 and 1420 to a laser of a first and second wavelength, respectively, modifies their internal stress, which may be neutral, compressive or tensile.

[0045] 15, based on the wafer curvature measurements (sub-curvature measurements), a pattern 1510 of light (or laser) having a first wavelength is generated (e.g., by using direct writing) and the pattern 1510 of light is exposed to the first stressor film 1410 such that the pattern 1510 of light modifies the internal stress of the first stressor film 1410. The semiconductor structure 1400 can then be cleaned with lithography chemicals to remove the first film (stress) modifying film 1410 in undesired areas.

[0046] As shown in FIG. 16, based on the curvature measurements (sub-curvature measurements) of the wafer, another light (or laser) pattern 1610 having a second wavelength is generated (e.g., by using direct writing) and the light pattern 1610 is exposed to the second stressor film 1420 such that the light pattern 1610 modifies the internal stress of the second stressor film 1420. The semiconductor structure 1400 can then be cleaned with lithography chemicals to remove the second film (stress) modifying film 1420 in the undesired areas. Thus, the modified internal stresses of the first and second stressor films 1410 and 1420 correspond to the curvature measurements of the wafer, and the wafer is considered to be near flat or flat.

[0047] As shown in Figure 17, the wafer is flipped and the protective layer 330 (shown in Figure 16) is removed. The semiconductor structure 1400 can then be ready for processing via a masking step with the first and second stressor films 1410 and 1420, whose internal stresses have been modified, to obtain a precise photopattern (not shown).

[0048] As shown in FIG. 18, a protective layer 1810 is formed on the working surface 340 of the wafer to protect the devices being fabricated during the masking steps.

[0049] 19, the wafer is flipped again and the first and second stressor films 1410 and 1420 are removed. The next backside stress photo sequence can then be repeated.

[0050] 20 and 21 show an exemplary method used to optimize the wafer shape of a semiconductor structure 2000 according to a fourth embodiment of the present disclosure. The fourth embodiment differs from the third embodiment in that the wafer chuck 390 is replaced with a wafer clamper 1090 in the fourth embodiment. As shown in FIG. 20 following FIG. 14, the wafer is turned upside down and clamped by the wafer clamper 1090 with the first and second stressor films 1410 and 1420 and the protective layer 330 exposed, and the first stressor film 1410 is exposed to a light pattern 1510 such that the internal stress of the first stressor film 1410 is modified by the light pattern 1510.

[0051] As shown in FIG. 21, the second stressor film 1420 is exposed to a light pattern 1610 such that the internal stress of the second stressor film 1420 is modified by the light pattern 1610 .

[0052] 22-25 show an exemplary method used to optimize the wafer shape of a semiconductor structure 2200 according to a fifth embodiment of the present disclosure. In the exemplary method of the fifth embodiment, a single blanket nitride film (first compressive or tensile film example) or a single blanket oxide film (first compressive or tensile film example) that handles global wafer shape correction is formed on the backside of the wafer, and a light-responsive stressor film is formed on the single blanket nitride film or oxide film for local wafer shape correction. As shown in FIG. 22, which follows FIG. 3, the wafer is turned upside down, and a global stressor film (compressive or tensile) 2210 is formed on the backside 540 of the wafer.

[0053] As shown in FIG. 23, the wafer can be flipped and a scanning laser technique 410 can be used to measure height deviations in the z direction across the surface of the wafer, storing the height deviations by (x,y) coordinates and identifying sub-curvature measurements of the wafer curvature measurements.

[0054] As shown in FIG. 24, the wafer can be flipped upside down and a stressor film (eg, stressor film 510) can be formed on the global stress film 2210.

[0055] Then, as shown in FIG. 25, a pattern of light (e.g., light pattern 610) is generated based on the sub-curvature measurement values ​​of the wafer curvature measurement values, and the light pattern 610 is exposed to the stressor film 510 such that the internal stress of the stressor film 510 is modified by the light pattern 610 corresponding to the sub-curvature measurement values.

[0056] 26-30 show an exemplary method used to optimize the wafer shape of a semiconductor structure 2600 according to a sixth embodiment of the present disclosure. In the exemplary method of the sixth embodiment, a single blanket nitride film (first compressive or tensile film example) or a single blanket oxide film (first compressive or tensile film example) that handles global wafer shape and gross local shape correction is formed on the backside of the wafer, and a light-responsive stressor film is formed on the single blanket nitride film or oxide film for micro local wafer shape correction. As shown in FIG. 26 following FIG. 22, the global stress film 2210 is patterned and etched, and then a stress layer 2610 is deposited, followed by chemical mechanical polishing (CMP) to ensure wafer flatness. The stress layer 2610 may have a different stress type than the global stress film 2210. For example, the stress layer 2610 has a neutral stress.

[0057] As shown in FIG. 27, the wafer can be flipped upside down and a scanning laser technique 410 can be used to measure height deviations in the z direction across the surface of the wafer, storing the height deviations by (x,y) coordinates and identifying sub-curvature measurements of the wafer curvature measurements.

[0058] 28, the wafer is flipped over and a stressor film (e.g., stressor film 510) is formed on the global stress film 2210. Then, a light pattern (e.g., light pattern 610) is generated based on the sub-curvature measurement values ​​of the wafer curvature measurement values, and the light pattern 610 is exposed to the stressor film 510 such that the internal stress of the stressor film 510 is modified by the light pattern 610 corresponding to the sub-curvature measurement values. Thus, the wafer is considered to be near flat or flat.

[0059] As shown in Fig. 29, the wafer is flipped and the protective layer (shown in Fig. 28) is removed. The semiconductor structure 2600 can then be ready for processing via a masking step with the stressor film 510, whose internal stress has been modified, to obtain a photopattern (not shown).

[0060] As shown in FIG. 30, a protective layer 3010 is formed on the working surface 340 of the wafer to protect the devices being fabricated during the masking steps, the wafer is again flipped over, and the stressor film 510 (shown in FIG. 29) is removed.

[0061] 31-33 show an exemplary method used to optimize the wafer shape of a semiconductor structure 3100 according to a seventh embodiment of the present disclosure. In the exemplary method of the seventh embodiment, a single blanket nitride film (first compressive or tensile film example) or a single blanket oxide film (first compressive or tensile film example) that handles the global wafer shape is formed on the backside of the wafer, and two stressor films that respond to different wavelengths of light for micro-local wafer shape correction are sequentially formed on the single blanket nitride film or oxide film. As shown in FIG. 31, which is a continuation of FIGS. 22 and 23, the wafer is flipped upside down, and two stressor films (e.g., first and second stressor films 1410 and 1420) are sequentially formed on the global stressor film 2210.

[0062] As shown in FIG. 32, the wafer is inverted and clamped by a wafer clamper 1090, a light pattern (e.g., light pattern 1510) is generated, and the light pattern 1510 is exposed to the first stressor film 1410 such that the internal stress of the first stressor film 1410 is modified by the light pattern 1510.

[0063] 33, another light pattern (e.g., light pattern 1610) is generated and the light pattern 1610 is exposed to the second stressor film 1420 such that the light pattern 1610 modifies the internal stress of the second stressor film 1420. Thus, the modified internal stresses of the first and second stressor films 1410 and 1420 correspond to the measured curvature of the wafer, and the wafer is considered near flat or flat.

[0064] In the above description, specific details have been described, such as the specific geometry of the processing system and a description of the various components and processes used. However, it should be understood that the technology described herein can be implemented in other embodiments that differ from these specific details, and such details are for the purpose of explanation, not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numerical values, materials, and configurations have been shown to provide a sufficient understanding. However, the embodiments can be implemented without such specific details. Components having substantially the same functional structure are indicated by similar reference numerals, and redundant descriptions may be omitted.

[0065] It should be understood that the order of description of the various steps described herein has been presented for clarity of explanation. In general, these steps may be performed in any suitable order. Moreover, although each of the various features, techniques, configurations, etc. described herein may be described in separate parts of this disclosure, it is understood that each concept may be practiced independently of one another or in combination with one another. Thus, the present invention may be embodied and viewed in many different ways.

[0066] To aid in understanding various embodiments, various techniques have been described as multiple separate operations. The order of description should not be construed to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

[0067] As used herein, "substrate" or "target substrate" generally refers to an object to be processed according to the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, such as a base substrate structure, such as a semiconductor wafer, a reticle, or a layer provided or overlying a base substrate structure, such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer, or overlying layer, whether patterned or not, but is intended to include such layers or base structures, and any combination of layers and / or base structures. References to particular types of substrates may be made herein for illustrative purposes only.

[0068] Those skilled in the art will also appreciate that many variations are possible in the operation of the techniques described above while still achieving the same objectives of the present invention. Such variations are intended to be within the scope of the present disclosure. Thus, the above description of the embodiments of the present invention is not intended to be limiting. Rather, limitations of the embodiments of the present invention are set forth in the following claims.

Claims

1. 1. A method comprising: receiving a wafer having a work surface for fabricating one or more devices thereon and a back surface opposite the work surface; measuring the wafer to determine a curvature measurement of the wafer; forming a first stressor film on the backside, the first stressor film being responsive to light at a first wavelength in that exposure to light at the first wavelength modifies an internal stress of the first stressor film; forming a second stressor film on the first stressor film, the second stressor film being responsive to light at a second wavelength in that exposure to light at a second wavelength modifies an internal stress of the second stressor film; exposing the first stressor film to a pattern of light at the first wavelength to modify the internal stress of the first stressor film, the pattern of light at the first wavelength corresponding to the curvature measurement; exposing the second stressor film to a pattern of light at the second wavelength to modify the internal stress of the second stressor film, the pattern of light at the second wavelength corresponding to the curvature measurement; The method wherein the second stressor film is insensitive to light at the first wavelength and the first stressor film is insensitive to light at the second wavelength.

2. The method of claim 1 , wherein measuring the wafer to determine a curvature measurement of the wafer is performed before forming a first stressor film.

3. The method of claim 1 , wherein measuring the wafer to determine a curvature measurement of the wafer is performed after forming a first stressor film.

4. 10. The method of claim 1, wherein one or more devices are fabricated on the work surface of the wafer, comprising: The method further includes forming a protective layer on the working surface of the wafer to protect the device.

5. The method of claim 4 , wherein measuring the wafer to determine a curvature measurement of the wafer is performed after forming a protective layer.

6. The method of claim 4 , wherein measuring the wafer to determine a curvature measurement of the wafer is performed before forming a protective layer.

7. 5. The method of claim 4, further comprising inverting the wafer so that the protective layer contacts a wafer chuck when forming the first stressor film.

8. performing one or more lithographic patterning processes on the working surface of the wafer; The method of claim 1 further comprising:

9. removing the first stressor film after performing the lithographic patterning process. The method of claim 8 further comprising:

10. The method of claim 1 , wherein the first stressor film is formed while holding a peripheral edge of the wafer.

11. The method of claim 1 , wherein measuring the wafer to determine a curvature measurement of the wafer is performed after forming a second stressor film.

12. forming a stress film on the back surface of the wafer before forming the first stressor film.

10. The method of claim 1, further comprising: The method, wherein forming the first stressor film on the backside includes forming the first stressor film on the stress film.

13. removing a portion of the stress film; Replacing the removed part with a stress layer The method of claim 12 further comprising:

14. The method of claim 13 , wherein the stress layer has a different stress type than the stress film.

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