Method for computing narrow bit-width linear algebraic operations - Patents.com

Abstract

The present invention relates to a method for computing linear algebraic operations of two operands or arrays containing one or more bit-width elements using a digital circuit. The method uses the principle of binary segmentation to reduce the computational overhead of linear algebraic operations such as linear convolution and dot product of operands such as vectors with narrow bit-width components. The invention is also directed to a digital circuit configured to perform the method.

Description

[Technical field]

[0001] The present invention relates to a method for computing linear algebraic operations of two operands or arrays containing one or more elements of a narrow bit-width using digital circuits. The method uses the principle of binary segmentation to reduce the computational overhead of linear algebraic operations such as linear convolution and dot products of vector-like operands with components of a narrow bit-width. The invention is also directed to a digital circuit configured to perform the method. [Background technology]

[0002] Modern Internet of Things (IoT), i.e. edge and mobile computing applications, demand high performance. This demand is driving a massive research effort for low-power, high-performance embedded processors. Such devices, constrained primarily by power and cost, must meet the performance and memory requirements of a vast collection of important application domains, such as deep learning, robotics, graph processing, and cryptography. Most of these application classes represent data as matrices and vectors and express computations through a set of linear algebra kernels. When targeting edge platforms, a common approach to reduce energy and memory requirements is to compress the data layout to use smaller data formats while preserving the accuracy of the application.

[0003] On the one hand, representing and computing data using low-precision floating-point formats is gaining traction in the High Performance Edge Computing (HPEC) community as they offer a good trade-off between data size and precision. On the other hand, narrow fixed-point and integer data representations (i.e., byte and subbyte), which feature smaller number representations, are better alternatives in terms of performance per watt ratio. One of the major applications of edge computing that impacts compressed data formats is Quantized Convolutional Neural Network (QCNN) inference, which utilizes quantization to represent data and weights data sizes, typically ranging from 8 to 1 bits, with an acceptable precision penalty.

[0004] Other important application classes of edge computing, such as graph computing and cryptography, rely extensively on Boolean matrix and vector calculations to traverse graphs or encrypt / decrypt messages. These applications would greatly benefit from hardware and software solutions that can efficiently compute narrow integer linear algebra kernels.

[0005] Moving the computation of these applications from the cloud to edge and mobile devices allows for significant improvements in terms of security, safety, and energy efficiency, but the inherently high computational intensity, despite low memory and energy requirements, makes the workloads difficult to compute on highly resource-constrained devices.

[0006] Therefore, there is a need for lightweight, high-performance methods and architectures aimed at improving the efficiency of linear algebra and narrow integer computations on edge processors. Summary of the Invention

[0007] In a first inventive aspect, the present invention provides a method for the computation of a linear algebraic operation of two operands u, v using digital circuitry operatively connected to an arithmetic logic unit, the method comprising: Each contains elements with narrow bit widths of m and n, and u = [u 0 ,...,u m-1 ],v=[v 0 ,...,v n-1 ], and the bit width of each of the elements is b u , b v receiving two operands u, v, The bit width of each element of the operand is expanded to a clustering bit width c by adding zeros to the left of the most significant bit of the element. w and bit width c w m and c w concatenating said elements of each operand to obtain n respective values ​​U, V; providing said values ​​U, V to said logic unit; The logic unit outputs a result value W=[W 0 ,...,W p-1 ], extracting a calculation result w from the result value W; The method includes the steps of: The clustering width is c w ≧max(b u ,b v ) conditions are met, The result w includes one or more bits of W. A method is provided.

[0008] The proposed invention relies on the principles of a mathematical technique called binary segmentation, which significantly reduces the arithmetic complexity of linear algebra calculations on operands with elements of narrow bit-widths, while reducing the processing overhead and memory usage of the calculations.

[0009] It will be understood that throughout this specification, the method is intended to perform a linear algebra operation, preferably a vector linear convolution, a dot product, a vector reduction, a scalar-vector product, or a vector addition or subtraction, on two operands with elements of narrow bit width. An operand with elements of narrow bit width should be understood as an array of elements, where each element is a narrow bit width binary integer. A narrow bit width should be understood as a bit width that is smaller than the word size of the architecture of the arithmetic logic unit.

[0010] According to the method, the digital circuit performs a series of transformations on source operands u, v, converting u, v into values ​​U, V and providing U, V to an arithmetic logic unit. The arithmetic logic unit performs an operation, preferably multiplication or addition, on the values ​​U, V, resulting in a result value W. The result value W is further transformed to extract a result w of the operation. Preferably, the extraction comprises outputting a set of bits of the result value W, for example by a masking operation. Each operation requires a specific pre-processing of the operands and a specific extraction process, as explained below.

[0011] A digital circuit is to be understood as any hardware element capable of performing the transformations of operands and values ​​required by said method. Preferably, the digital circuit is configured to be connected to known computing systems. In particular, the digital circuit is preferably configured to receive and output operands or values ​​from any data storage means. Also preferably, the digital circuit is connectable, directly or through other elements, to a logic unit of a processing unit of a computer. In other embodiments, the digital circuit is configured to be connected to digital circuits capable of storing data and digital circuits capable of multiplying and / or adding two binary operands.

[0012] In a particular embodiment, the value W from the logic unit is obtained by multiplying or adding the values ​​U and V.

[0013] Most common linear algebra operations can be reduced to two basic calculations: multiplication and addition. Advantageously, binary segmentation can reduce a linear algebra operation on an array of elements (which typically requires several computation cycles for each array element) to a multiplication or addition of only two values, thereby reducing the number of cycles required to complete the result calculation.

[0014] Furthermore, the method allows the computation of three very important operations on vectors: the so-called linear convolution, the dot product and vector reduction. In general, the linear convolution of two vectors is computed as follows:

[0015]

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[0016] On the other hand, the inner product is calculated as follows:

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[0018] Finally, vector reduction returns a scalar value that holds the sum across all elements of u, so in a sense, vector reduction is v=[v 0 ,...,v n-1 This is a variant of the dot product of a vector reduced by a vector of ones in [1,...,1]=[1,...,1].

[0019]

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[0020] However, in conventional computing, array operations are computationally intensive, requiring substantial processing cycles and memory usage for storing intermediate results. This means that for each element of an array, e.g., each component of a vector, a fixed size, i.e., a clustering width c wThis is avoided by the binary segmentation implementation of the method, which requires an extension to c. The extension is done by adding zeros to the left of the most significant bits, so that the value of the integer is unchanged, while c w The subsequent concatenation of the normalized elements with θ produces values ​​U, V which can be processed by a logic unit without loss of information.

[0021] In certain embodiments, the clustering width satisfies the following conditions:

[0022]

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[0023] The clustering width for linear convolution, dot product, and vector reduction computations is the bit width b of the elements of the operands. u , b v , and the number of elements in each operand, m, n. This process gives the clustering width, which is the actual bit width b of the input elements, to include extra guardband bits to avoid overflow in the split data due to carry propagation. u , b v It is defined as larger, which allows adding or multiplying n narrow integers with only one addition or multiplication of two long integers, instead of n additions or multiplications of short integers. It is worth noting that binary segmentation is not an approximate computation technique, since the dimension of the clustering width already describes the number of bits needed to represent the computation output without loss of precision, thus ensuring exact computation.

[0024] In a particular embodiment of a dot product calculation, after receiving two operands u, v, the method further comprises: n-1 ,...,v 0 ], the operand v = [v 0 ,...,v n-1This step is also advantageously applied to the computation of linear convolutions in Convolutional Neural Networks (CNNs).

[0025] Calculating the inner product, or dot product, of two vectors involves reversing the order of the elements of one operand, either u or v, and the reversed operand v' is transformed as in the general case of the method, i.e., zeros are added to the left of the most significant bits, and the inner product is obtained from the multiplication of the resulting values ​​U and V.

[0026] In a particular embodiment of vector reduction, each of the elements of the operand v is equal to one.

[0027]

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[0028] As mentioned above, vector reduction is treated as a special case of a dot product via binary segmentation between u, v, where v is a unit vector that is compounded only by elements that are equal to 1. The result is to reduce a vector u compounded with n elements to a scalar value that holds the sum of all elements of u.

[0029] In a particular embodiment of linear convolution, the result w is calculated by dividing the result by one or more elements w=[w 0 ,w 1 ,...], where each element w i contains one or more bits of W according to the following formula:

[0030]

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[0031] In the method of the present invention, when values ​​U and V are multiplied, the product W must be transformed to obtain a result. For linear convolution, the result is an array of elements, each element containing a set of bits of W. In particular, in linear convolution, each element w i is a set of c in Ww Conversely, if W contains a set of c consecutive bits, w If the bit length is evenly divided into sets of consecutive bits, then i For example, w 0 contains one of these sets as the next value.

[0032]

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[0033] This is the c at the right end of W. w The next element w corresponds to the set of bits. 1 is W cw From W 2·cw-1 These elements may also be known as slices.

[0034] However, for other operations besides linear convolution, the extraction of the result w is slightly different. In a specific embodiment of the dot product and vector reduction computation, the result w contains one or more bits of W according to the following formula:

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[0036] For dot products and vector reductions, the extraction of the results is done by multiplying W by (m-1)·c w The cth bit, the least significant bit, or in other words, the value W starting from the center slice of W w The method includes extracting a set of consecutive bits.

[0037] The method also includes the steps of: n=1 and v=[v 0 We also consider the specific embodiment of computing a product between a vector and a scalar where ]=[k].

[0038] For vector and scalar computations, the operands are interpreted as multi-element and single-element arrays, respectively, whose values ​​are equivalent to scalar operands, or in other words, m≧2, n=1.

[0039] The clustering width needs to be adapted accordingly, and in a particular embodiment, the clustering width satisfies the following conditions:

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[0041] We note that the method is also suitable for computing addition and subtraction of arrays. For addition or subtraction according to binary segmentation, the clustering width satisfies the following condition:

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[0043] While the addition of two binary operands is easy and can be calculated with an adder, subtraction of two operands means calculating the two's complement of the operands being subtracted. In an embodiment corresponding to a subtraction operation, the method includes: 0 ,...,v n-1 The method includes the step of calculating the two's complement of

[0044] Two's complement arithmetic is an operation known in the art as a binary number calculated by inverting bits and adding 1 to the original binary number, thereby computing the negation of the original number. The subtraction of two operands is calculated as the addition of the first value with the negative of the second value.

[0045] For addition and subtraction as well as scalar-vector multiplication, the result w is one or more elements w=[w 0 ,w 1 ,...], where each element w icontains one or more bits of W according to the following formula:

[0046]

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[0047] This extraction process is similar to that for extracting the linear convolution result, differing only in the number of elements of the result w.

[0048] In a second aspect, the present invention provides a digital circuit configured to carry out a method according to the first aspect of the invention, said digital circuit comprising: a pre-processing unit configured to receive and extend operands u, v and provide values ​​U, V to the logic unit; and a post-processing unit configured to receive the result value W from the logic unit and extract the operation result w.

[0049] As mentioned above, the method is intended to be performed by any digital circuit capable of performing the described transformation of the operands. The digital circuit may be implemented by an assembly of interconnected conventional logic gates or by a purposely constructed printed circuit board or integrated circuit. In all cases, the digital circuit may optionally comprise arithmetic logic and / or input and output connections and / or data storage means for supplying, storing, multiplying or adding values ​​to form an integer binary segmentation calculation unit configured to receive the operands and output the operation result.

[0050] The digital circuit comprises two process-oriented units, a pre-processing unit and a post-processing unit, each configured to perform a transformation before and after an addition or multiplication, respectively. Depending on the particular architecture of the digital circuit, some elements of the circuit may be shared between the pre-processing unit and the post-processing unit, or may be used in combination with other elements to perform one or more steps of the method.

[0051] In an embodiment of the digital circuit, the pre-processing unit comprises an expansion unit configured to expand the bit-width of the elements of the operands to a clustering width, and a compression unit configured to compress the input data to the actual data size by converting the elements of the operands to a target output bit-width and forwarding them to a mask unit for integration, said mask unit being an element of the post-processing unit and also configured to extract the associated operation result w from the result value W. The digital circuit may further comprise a control unit having a control register configured to determine the clustering width and other key parameters depending on the input operand bit-width and the operation type.

[0052] In particular embodiments, the circuitry is further configured to be operatively connected to a logic unit of the computer and further configured to provide values ​​U, V, W to or receive values ​​U, V, W from the logic unit via a register file, bypass logic, and / or a memory hierarchy.

[0053] In this embodiment, the digital circuit may be configured as an add-on or pluggable device configured to be connected to an existing processing unit or equivalent computational element, so that the digital circuit may be advantageously retrofitted in any computer. In this embodiment, when connected to a computer, the digital circuit loads the values ​​U, V resulting from the transformation of the input operands u, v into registers of the arithmetic logic unit, possibly together with instructions for the operation, and receives the result W of the calculation. The digital circuit may provide and receive these values ​​via a direct bus to the arithmetic logic unit, or via other elements such as register files with pass logic or any form of data storage means including any level of the memory hierarchy. In processor architectures, for example CPUs and GPUs, the behavior of the digital circuit is controlled by instructions specific to those architectures.

[0054] In a particular embodiment, the pre-processing unit and the post-processing unit are implemented with a configurable logic block CLB, where the CLB includes a register and a look-up table LUT.

[0055] A particularly advantageous application of digital circuits is data flow computer architectures. Examples of data flow architectures to which digital circuits may be applied are those implemented by field programmable gate arrays (FPGAs) with a number of programmable logic units, or configurable logic blocks (CLBs) interconnected via a cross matrix. In these embodiments, the digital circuits may be composed of one or more CLBs and a digital signal processing unit DSP, and the pre-processing and post-processing units are implemented by look-up tables (LUTs). [Brief description of the drawings]

[0056] The foregoing and other advantages and features will be more fully understood from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings, which are to be considered as illustrative and not restrictive.

[0057] [Figure 1a] 1 depicts a flow chart of three embodiments of the method. [Figure 1b] 1 depicts a flow chart of three embodiments of the method. [Figure 1c] 1 depicts a flow chart of three embodiments of the method. [Diagram 2] FIG. 2 is a schematic diagram of a preferred example of a digital circuit. [Diagram 3] FIG. 2 is a schematic diagram of another preferred example of a digital circuit implemented in an FGPA architecture. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0058] It is understood that throughout this specification, various portions of one embodiment of the invention can be freely combined with portions described in other embodiments, and that such combinations are permissible even if the combinations are not explicitly described.

[0059] The object of the method of the present invention is to perform a binary segmentation computation process of two array operands, including narrow bit-width operands, using digital circuits. The method can compute at least vector product linear convolution, dot product, vector reduction, scalar vector product, or vector addition or subtraction, all of which linear algebraic operations are computed by a common step (10, 20, 30, 40, 50) of changing the clustering bit-width of the elements of the operands, a result extraction procedure, and the type of operation in the particular computation by the Arithmetic Logic Unit (ALU), which is either addition or multiplication.

[0060] 1a, 1b, 1c show three flow diagrams corresponding to three embodiments of the method. In general, the method may be divided into three phases: a pre-processing phase comprising the steps of receiving (10) two operands u, v containing m, n narrow bit-width elements, expanding (20) the bit-width of each element of the operands to the clustering bit-width and supplying (30) values ​​U, V to a logic operation unit. - The computation phase performed by the ALU, during which the values ​​U and V are either added or multiplied, and the values ​​U and V are output to the digital circuit. a post-processing phase comprising the steps of receiving (40) the result value W and extracting (50) the result of the operation w.

[0061] Figure 1a shows the general case that is valid for any operation, while Figure 1b shows the specific case of computing an inner product, and Figure 1c shows the specific case of computing a subtraction.

[0062] In a first step, the digital circuit receives two operands u and v, for example two vectors with m and n elements or components, respectively (10).

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[0064] If the selected operation is a dot product, then the digital circuitry must reverse the order of the elements of the second vector (11):

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[0066] Convolutional neural networks (CNNs) apply a form of linear convolution that can also be calculated in the manner of the present invention. This operation is calculated in the same way as the general case of linear convolution, except that the order of one element of the vector is reversed (11), as in the case of the inner product calculation.

[0067] The next step is to have the digital circuit scale the bit width of each element of both vectors to a clustering width c w (20) to the left of the most significant bit. The target clustering width is achieved by adding zeros to the left of the most significant bit, and the clustering width is defined to space elements in the concatenated value (U or V) to avoid computational overflow. The clustering width c w is an integer that satisfies the following conditions:

[0068]

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[0069] Here b u , b v are the bit widths of the elements of u and v, respectively. To better take advantage of binary segmentation, the clustering width should be the smallest possible integer that gives sufficient separation between the vector components, which in turn depends on the operation. In short, for each operation, the clustering width is the smallest integer that satisfies the following condition:

[0070] - Linear convolution, dot product and vector reduction

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[0072] - Vector-scalar product

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[0074] - Addition or multiplication

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[0076] It is clear that certain operations require the same number of elements in both the operands and the vectors, such as the case with m = n, and in the case of a scalar vector product, the scalar operand can be thought of as a single-element array with the value of the scalar k, and the rest of the process remains unchanged.

[0077] Furthermore, if the selected operation is subtraction, the digital circuitry computes (21) the two's complements of the elements of the vector to be subtracted (v in this case) after expanding (20) it to the clustering width.

[0078] After expanding the elements to the normalized clustering width, the digital circuits are each w m and c w Concatenate the elements to obtain two values ​​U, V of n. If the operation is subtraction or dot product, the second vector v is transformed as above and then expanded and concatenated as in the general case.

[0079] The two values ​​U, V are fed to the ALU (30), possibly together with a signal indicating the type of operation, i.e., multiplication or addition, and returned to the digital circuitry, which receives the result value W (40). The type of operation is multiplication, except for subtraction and addition, where the values ​​U, V are added.

[0080] The result value W is a binary integer of p bits, where the size of p depends on whether U and V are added or multiplied, and on the bit-widths of U and V. If W is written as an array of bits as:

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[0082] The extraction (50) step requires the digital circuitry to isolate or somehow output a subset of the bits of W. The particular set of bits depends on the type of operation, and can be summarized as follows:

[0083] For linear convolution, the result of an operation w is an array or vector, and each element w of the array or slice i is defined as follows:

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[0085] Similar principles apply to scalar-vector multiplication, addition and subtraction with differing numbers of components in w.

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[0087] Finally, for dot products and vector reductions, the result of the operation comprises a single slice of the result value W.

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[0089] The following numerical examples show two implementations of the method using specific numerical values.

[0090] (Example 1: Inner product) Operands: u=(7,5); v=(4,2) Clustering width: c w =7

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[0092] (Example 2: Linear convolution) Operands: u=(3,1,2); v=(1,2) Clustering width: c w =5

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[0094] With respect to the digital circuit, in a preferred example shown in FIG. 2, the digital circuit is implemented as a RISC (reduced instruction set computer) instruction set architecture integrated in a system-on-chip (SoC) versus a traditional central processing unit (CPU). For example, RISC-V vector extension v1.0 has eliminated support for narrow single instruction multiple data processing (SIMD) computations, and the initial specification that only described 8-bit, 4-bit, and 1-bit data formats. In contrast to standard SIMD units, the digital circuit can perform SIMD computations on many data sizes while keeping them compressed in memory, without incurring the area overhead associated with data manipulation. The digital circuit also features support for mixed-precision computations by design, since the clustering width already accounts for the different data sizes between the data sources. As a result, the digital circuit can compute on compressed data, performing flexible SIMD-style computations with widths proportional to the data sizes of the operands of all operations without the associated overhead. Furthermore, the implementation of the digital circuit, whose key novelty relies on hardware reuse, does not require any additional data paths or separate register files or functional units, resulting in negligible area and power overhead.

[0095] The digital circuit relies on standard logic units (e.g. integer multipliers) whose data paths and implementations are already implemented in processors supporting integer calculations. As a result, the main objectives of the digital circuit are to efficiently gather the data before the multiplication and to optimize the data extraction at the output of the multiplier. The digital circuit addresses these issues by means of two units called pre-processing unit and post-processing unit. The functionality of the pre-processing unit is twofold. The extension unit converts the elements that are operands into input values ​​U, V and delivers them to the processor multiplier via an output bus, which performs the actual calculation. The number of elements to be gathered as well as the bit width are specified in a control register. The result of the multiplication or addition is processed by a mask unit to form the final result in the form of an operation. In particular, the mask unit extracts a set of bits w of the value W according to their position, as defined by a binary segmentation technique.

[0096] To speed up the data compression phase, the pre-processing unit includes a compression unit that compresses the input data to the actual data size. The compression unit converts the elements of the operands to the target output bit width and delivers them to a mask unit that combines them. The post-processing unit is thus used to compress the data or to filter the meaningful slices of data from the output of the logic unit, and its operation depends on the values ​​set in the control registers and the type of operation.

[0097] In another embodiment, the digital circuit is applied to a dataflow computer architecture, and in the example shown in Fig. 3, the digital circuit is implemented in an FPGA architecture. The FPGA architecture consists of dataflow blocks, known as CLBs, each block with logic circuits such as ALUs, memory units, and / or LUTs, which are hardware components specialized to perform logic units such as shifts, Boolean operations, etc. The CLBs are interconnected via a cross matrix and can receive and send data to nearby blocks.

[0098] In such an example, three CLBs are connected as a chain, and the first CLB in the chain (CLB0) has two memory units that output a new vector of two elements every clock cycle. The middle block in the chain (CLB1) uses an internal ALU as a multiplier and a LUT as a logic circuit that implements the pre-processing and post-processing units of the digital circuit, while in other examples the ALU is external implemented in the DSP. That is, the two source vectors from CLB0 are processed by the expand unit of the pre-processing unit to obtain the output cluster, multiplied by the ALU to obtain W, and processed by the mask unit of the post-processing unit to extract one operation result per cycle. Each result is saved in a store buffer in the third block (CLB2).

Claims

1. 1. A method for computing a linear algebraic operation of two operands u, v using digital circuitry operatively connected to an arithmetic logic unit, comprising: The digital circuit Each contains elements with narrow bit widths of m and n, and u = [u ０ ,...,u ｍ－１ ]、v=[v ０ ,... ,v ｎ－１ ], and the bit width of each of the elements is b ｕ , b ｖ receiving two operands u, v, where u, v are the vectors of the two operands u, v; The bit width of each element of the operand is increased to a clustering bit width c by adding zeros to the left of the most significant bit of the element. ｗ (20) and bit width c ｗ m and c ｗ concatenating said elements of each operand to obtain n respective values ​​U, V; providing said values ​​U, V to said logic unit (30); The logical operation unit outputs a result value W=[W ０ , . . . , W ｐ－１ ] (40), Extracting a calculation result w from the result value W (50); The method includes the steps of: The clustering bit width is c ｗ ≧max(b ｕ , b ｖ ) conditions are met, The result w includes one or more bits of W. method.

2. The value W from the logic unit is obtained by multiplying or adding the value U and the value V. The method of claim 1.

3. The clustering bit width is c ｗ ≧b ｕ +b ｖ +log ２ Satisfy the condition (max(m, n)) The method of claim 1.

4. After receiving two operands u and v (10), the operand v′=[v ｎ－１ ,... ,v ０ ], the operand v=[v ０ ,... ,v ｎ－１ (11) reversing the order of the elements of The method of claim 3.

5. each of said elements of operand v is equal to 1; v ０ =...=v ｎ－１ = 1 The method of claim 3.

6. The calculation result w is one or more elements w=[w ０ , w １ ,... . . ], Each element w ｉ teeth, Contains one or more bits of W according to The method according to any one of claims 1 to 3.

7. The calculation result w is Contains one or more bits of W according to 6. The method according to claim 4 or 5.

8. The clustering bit width is c ｗ ≧b ｕ +log ２ Satisfy condition (m) 3. The method according to claim 1 or 2.

9. n=1 and v=[v ０ ]=[k] The method of claim 8.

10. The clustering bit width is c ｗ ≧max(b ｕ , b ｖ ) +1 condition met 3. The method according to claim 1 or 2.

11. After the step of expanding the bit width of each element (20), the element v of operand v ０ ,... ,v ｎ－１ Calculating the two's complement of (21) The method of claim 10.

12. The operation result w is one or more elements w=[w ０ , w １ ,... . . ], Each element w ｉ teeth, Contains one or more bits of W according to The method of claim 10.

13. a pre-processing unit configured to receive (10) and extend (20) operands u, v and provide (30) values ​​U, V to the logic unit; a post-processing unit configured to receive (40) a result value W from the logic unit and to extract (50) the operation result w. A digital circuit configured to perform the method according to any one of claims 1 to 3.

14. and further configured to be operatively connected to an arithmetic logic unit of the computer, and further configured to provide (30) or receive (40) values ​​U, V, W from said arithmetic logic unit via a register file, bypass logic, and / or memory hierarchy.

14. The digital circuit of claim 13.

15. The pre-processing unit and the post-processing unit are implemented with configurable logic blocks (CLBs), the CLBs including registers and look-up tables (LUTs).

14. The digital circuit of claim 13.

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