Latch-off timer for output impedance and load independent voltage limit mode protection

Abstract

An example includes a power supply system. The system includes a voltage-limited power regulator for generating an output voltage and an instantaneous overvoltage sensor configured to detect an overvoltage condition associated with the output voltage. The system further includes an overvoltage latch-off timer system configured to initiate a latch-off timer in response to detecting the overvoltage condition. The latch-off timer can be uninterrupted by the amplitude of the output voltage. The overvoltage latch-off timer system can be further configured to detect a persistent overvoltage fault in response to detecting the overvoltage condition after expiration of the latch-off timer. The overvoltage latch-off timer system can be configured to generate a fault signal to disable the voltage-limited power regulator in response to detecting the persistent overvoltage fault.

Description

[Technical field]

[0001] The present invention relates generally to electronic circuits, and more particularly to a latch-off timer for output impedance and load independent voltage limit mode protection. (Government Rights) This invention was made under a government contract. Accordingly, the United States Government has rights to the invention as specified in that contract. [Background technology]

[0002] Power supply circuits are implemented in various circuits for converting direct current (DC) or alternating current (AC) voltages to different voltages (e.g., DC voltages). Thus, a given power supply circuit can generate an output voltage that is implemented to power other circuits or other parts of circuits. An overvoltage (OV) condition in a power supply can result in a reduction in the operational life of a circuit or can result in damage to circuit components (e.g., transistors) therein. Thus, OV protection can be beneficial to preserve the operational life of a circuit. Some OV protection systems use a latch-off timer to distinguish between a temporary OV condition that may be the result of a false triggering of an OV detection circuit and a true sustained OV event that may result in damage to the circuit, causing the protection circuit to latch off the system permanently. The determination of the latch-off timer period is based on the reliability tolerances of the load circuit components, and the timer period must be precisely controlled. However, a power supply with instantaneous output overvoltage protection circuitry may operate in a voltage-limiting mode during an overvoltage event, in which the output voltage may fluctuate around the overvoltage threshold amplitude, generating a large, non-periodic, irregular ripple waveform whose time-varying frequency and magnitude are directly dependent on the output impedance and dynamic load conditions of the power supply. The non-periodic nature of the output waveform in voltage-limiting mode makes the OV latch-off timer in a system with instantaneous OV protection very inaccurate with large variations in its duration. Summary of the Invention

[0003] An example includes a power supply system. The system includes a power regulator operating in a voltage-limited mode and generating an output voltage, and an instantaneous overvoltage sensor configured to detect an overvoltage condition associated with the output voltage. The system further includes an overvoltage latch-off timer system configured to initiate a latch-off timer in response to detecting the overvoltage condition. The latch-off timer can be uninterrupted by the amplitude of the output voltage. The overvoltage latch-off timer system can be further configured to detect a persistent overvoltage fault in response to detecting the overvoltage condition after expiration of the latch-off timer. The overvoltage latch-off timer system can be configured to generate a latch-off signal to disable the voltage-limited power regulator in response to detecting the persistent overvoltage fault.

[0004] Another example includes a method for detecting a persistent overvoltage fault in a power supply system. The method includes detecting an overvoltage condition associated with an output voltage provided from a power regulator operating in a voltage-limiting mode. The method also includes generating an overvoltage signal in response to the overvoltage condition and initiating a latch-off timer in response to the overvoltage signal. The latch-off timer can be uninterrupted by the amplitude of the output voltage. The method also includes determining a persistent overvoltage fault in response to the overvoltage signal after expiration of the latch-off timer and generating a latch-off signal to disable the voltage-limiting power regulator in response to detecting the persistent overvoltage fault. The method further includes detecting a nuisance overvoltage condition in response to not detecting an overvoltage condition after expiration of the latch-off timer and before expiration of the nuisance overvoltage timer.

[0005] Another example includes a power supply system. The system includes a power regulator operating in a voltage-limited mode and generating an output voltage, and an instantaneous overvoltage sensor configured to detect an overvoltage condition associated with the output voltage. The system further includes an overvoltage latch-off timer system. The overvoltage latch-off timer system includes a latch-off timer circuit configured to initiate a latch-off timer in response to detecting an overvoltage condition. The latch-off timer can be uninterrupted by the amplitude of the output voltage. The overvoltage latch-off timer system further includes a finite state machine (FSM) controller system configured to detect a persistent overvoltage fault in response to detecting the overvoltage condition after expiration of the latch-off timer, and to generate a fault signal that permanently disables the voltage-limited power regulator in response to detecting the persistent overvoltage fault. The FSM controller system can detect a nuisance or momentary overvoltage condition in response to not detecting an overvoltage condition after expiration of the latch-off timer and before expiration of the nuisance overvoltage timer. The FSM controller system can also reset the latch-off timer in response to not detecting an overvoltage condition after expiration of the latch-off timer and before expiration of the nuisance overvoltage timer. Additionally, the FSM controller includes radiation-hardened circuitry that eliminates inaccurate and / or premature latch-off of the power system and / or resetting of the latch-off timer. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is an example block diagram of a power supply system. [Diagram 2] FIG. 2 is a diagram illustrating an example of an overvoltage latch-off timer system. [Diagram 3] FIG. 3 is a diagram illustrating an example of a latch-off timer circuit. [Figure 4] FIG. 4 illustrates an example of a fault detector. [Diagram 5] FIG. 5 is a diagram showing an example of a timing diagram. [Figure 6]FIG. 6 is a diagram showing another example of a timing diagram. [Figure 7] FIG. 7 illustrates an example method for detecting a persistent overvoltage fault in a power supply system. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The present invention relates generally to electronic circuits, and more particularly to a latch-off timer for output impedance and load independent voltage limit mode protection. The power supply system can be implemented as any of a variety of power supply systems capable of providing an output voltage (e.g., a direct current (DC) output voltage). The power supply system can include a power regulator configured to operate in a voltage limit mode and generate an output voltage based on an input voltage (e.g., a DC or alternating current (AC) voltage), or the like. By way of example, the voltage limiting power regulator can be fabricated as any of a variety of power regulators, such as a switching power supply (e.g., full or half bridge, resonant, rectifying, buck, boost, buck boost), a linear power supply, or any of a variety of other types of power regulators.

[0008] The power supply system includes an instantaneous overvoltage sensor and an overvoltage latch-off timer system. The instantaneous overvoltage sensor can be configured to monitor the output voltage to detect an overvoltage condition. The overvoltage latch-off timer system can detect the occurrence of a persistent overvoltage fault based on the detection of the overvoltage condition. As described herein, the term "overvoltage condition" refers to an output voltage amplitude greater than or approximately equal to a predetermined overvoltage reference signal. Thus, an overvoltage condition may be a momentary occurrence that can be quickly mitigated by an instantaneous overvoltage protection circuit, resulting in a voltage limiting mode. As described herein, the term "persistent overvoltage fault" refers to a more serious condition of the power supply circuit, where the overvoltage condition may be very frequent and / or very persistent in duration, thus indicating a permanent fault of the power supply circuit. Thus, a persistent overvoltage fault may require a permanent latch-off (e.g., shutdown) of the power supply circuit and / or an indication of the fault to other parts of the circuit.

[0009] The overvoltage latch-off timer system includes a latch-off timer circuit and a finite state machine (FSM) controller system. In response to detecting an overvoltage condition, the latch-off timer circuit is configured to initiate a latch-off timer corresponding to a voltage that increases with a constant slope as a function of time, regardless of the amplitude of the output voltage. After expiration of the latch-off timer, the FSM controller system can determine the presence of a persistent overvoltage fault in response to the overvoltage signal. As an example, the latch-off timer is initiated by latching a voltage to activate (e.g., close) a switch to charge a timing capacitor, so that the latched voltage can be maintained regardless of the state of the overvoltage switch and thus the amplitude of the output voltage. Thus, the latch-off timer can operate at a predictable time regardless of the output impedance or load associated with the power supply circuit. Thus, unlike the latch-off timer in a typical overvoltage latch-off timer system that has timing based on the amplitude of the output voltage, the latch-off timer can have a highly predictable time value from the time it is initiated to the time it expires. Additionally, as described herein, the FSM controller system can determine the presence of a temporary or nuisance overvoltage condition in response to the expiration of a nuisance overvoltage timer. As described herein, the term "nuisance overvoltage condition" refers to the failure to detect a sustained overvoltage fault despite the presence of an overvoltage condition, and thus, a determination that the overvoltage condition is not severe enough to justify a sustained overvoltage fault and the resulting deactivation of the voltage limiting power regulator.

[0010] 1 illustrates an example block diagram of a power supply system 100. The power supply system 100 may be implemented as any of a variety of applications requiring conversion of a voltage from one type and / or amplitude to another, such as converting an AC or DC voltage to another DC voltage. The power supply system 100 includes a voltage limiting power regulator 102, an instantaneous overvoltage sensor 104, and an overvoltage latch-off timer system 106. The voltage limiting power regulator 102 regulates an output voltage V based on an input voltage, etc. OUT (e.g., a DC output voltage). By way of example, the voltage-limited power regulator 102 may be fabricated as any of a variety of power supply circuits, such as a switching power supply (e.g., full or half bridge, resonant, rectifying, buck, boost, buck boost), a linear power supply, or any of a variety of other types of power regulators.

[0011] In the example of FIG. 1, a voltage limited power regulator 102 provides an output voltage V OUT In response to the excessive swing of the output voltage V OUT As another example, the voltage limiting component of the voltage limiting power regulator 102 is configured to reduce the amplitude of the output voltage V OUT Therefore, the voltage limiting component of the voltage limiting power regulator 102 can clamp the output voltage V OUT By clamping the output voltage V OUT For example, the voltage limiting component of voltage limited power regulator 102 may provide limited protection against overvoltage conditions associated with the output voltage V OUT , and thus reduces the output voltage V during an overvoltage condition, as described in more detail herein. OUT Bring on the ratchet.

[0012] The instantaneous overvoltage sensor 104 detects the output voltage V OUT, to detect an overvoltage condition. OUT is compared with a predetermined overvoltage reference signal to determine the output voltage V OUT 1, the overvoltage signal is shown as signal OV.

[0013] The overvoltage latch-off timer system 106 includes a latch-off timer circuit 108 and a finite state machine (FSM) controller system 110. In response to detecting an overvoltage condition via an overvoltage signal OV, the latch-off timer circuit 108 may be configured to start a latch-off timer. In the example of FIG. 1, the latch-off timer includes a timing capacitor C TMR and in response to an overvoltage condition, the charge switch is latched closed to charge a timing capacitor C TMR Therefore, the timing capacitor C TMR is the timing capacitor C TMR The timing voltage can be increased with a constant slope determined by the capacitance of the timing capacitor C. TMR , thus, the latch-off timer can define a duration until expiration, after which the FSM controller system 110 can detect a sustained overvoltage fault. TMR may be configured as an external component to the power supply system 100, such that the timing capacitor C TMR is provided by a user after manufacture of the power supply system 100 to allow the user to set the desired duration of the latch-off timer.

[0014] As described above, the latch-off timer of the latch-off timer circuit 108 is initiated in response to detecting an over-voltage condition. After expiration of the latch-off timer, the FSM controller system 110 can determine whether a persistent over-voltage fault has occurred at the voltage-limited power regulator 102. As an example, the latch-off timer can expire in response to the timing voltage described above having an amplitude approximately equal to the threshold voltage. After expiration of the latch-off timer, if an over-voltage condition is detected, the FSM controller system 110 detects a persistent over-voltage fault. As described in more detail herein, the FSM controller system 110 can detect a persistent over-voltage fault after expiration of the latch-off timer and in response to at least one predetermined condition. Thus, as an example, the FSM controller system 110 can provide a fault signal to the voltage-limited power regulator 102 to disable (e.g., shut down) the voltage-limited power regulator 102. As another example, the fault signal can provide an indication of the persistent over-voltage fault to other portions of the circuit and / or to a user interface.

[0015] As an example, the latch-off timer can define a detection window for detecting an overvoltage vault via the FSM controller system 110. For example, the detection window can be defined by a timing voltage having an amplitude between a first threshold voltage corresponding to expiration of the latch-off timer and a second threshold voltage greater than the first threshold voltage and corresponding to expiration of the nuisance overvoltage timer. Thus, if the FSM controller system 110 detects an overvoltage condition after expiration of the latch-off timer but before expiration of the nuisance overvoltage timer, the FSM controller system 110 can provide a fault signal, as described above. However, if the FSM controller system 110 does not detect an overvoltage condition after expiration of the nuisance overvoltage timer, the FSM controller system 110 can provide a reset signal to reset the overvoltage latch-off timer system 106. For example, the reset signal can unlatch the charging switch and latch the timing capacitor C. TMR Thus, the reset signal can indicate a potential persistent overvoltage fault, a false trip for a nuisance overvoltage condition, and thus allow the power supply system 100 to maintain normal operation.

[0016] Figure 2 shows an example of an overvoltage latch-off timer system 200. The overvoltage latch-off timer system 200 may correspond to the overvoltage latch-off timer system 106 in the example of Figure 1. Accordingly, in the following description of the example of Figure 2, reference is made to the example of Figure 1.

[0017] The overvoltage latch-off timer system 200 receives as an input an overvoltage signal OV. As described above in the example of FIG. 1, the overvoltage signal OV is OUTcorresponds to an overvoltage condition where V is greater than a predetermined overvoltage threshold amplitude. The overvoltage signal OV is provided to an OR gate 202 that is configured to generate a shutoff signal SO that is provided to the voltage limited power regulator 102 to deactivate the voltage limited power regulator 102. As a result, in response to an overvoltage condition as indicated by a logic high state of the overvoltage signal OV, the OR gate 202 provides the shutoff signal SO to deactivate the voltage limited power regulator 102, thereby reducing the output voltage V OUT Decrease the amplitude of

[0018] 2, the overvoltage signal OV is also provided to a timer latch 204 ("FSM timer latch") that is part of the FSM controller system 110. The timer latch 204, in response to detecting a logic high state of the overvoltage signal OV and thus an overvoltage condition, latches a latch voltage V LTCH In the example of FIG. 2, the overvoltage latch-off timer system 200 includes a latch-off timer circuit 206. The latch-off timer circuit 206 is configured to provide a latch voltage V LTCH 2, the latch-off timer is activated by a timing capacitor C TMR and the latch voltage V LTCH In response to the charge switch being latched closed, the timing capacitor C TMR Therefore, the timing capacitor C TMR is the timing capacitor C TMR The timing voltage can be increased with a constant slope determined by the capacitance of the timing capacitor C. TMR , so the latch-off timer can define the duration until expiration. As an example, a timing capacitor C TMR may be configured as an external component to the power supply system 100, such that the timing capacitor C TMRis provided by a user after manufacture of the power supply system 100 to allow the user to set the desired duration of the latch-off timer.

[0019] In the example of FIG. 2, the latch-off timer circuit 206 is configured to latch a first threshold voltage V TH1 , the second threshold voltage V TH2 , and a third threshold voltage V TH3 The threshold voltage V TH1 , V TH2 , and V TH3 Each of the third threshold voltages V may define a separate timer corresponding to a separate condition for detecting a sustained overvoltage fault and a nuisance overvoltage condition. TH3 is the first threshold voltage V TH1 and a second threshold voltage V TH2 is the third threshold voltage V TH2 The latch-off timer circuit 206 is configured to latch the timing voltage V TH1 The latch-off timer circuit 206 is configured to provide a first timer signal TMR1 in response to the timing voltage increasing to be approximately equal to a second threshold voltage V TH2 The latch-off timer circuit 206 is configured to provide a second timer signal TMR2 in response to the timing voltage increasing to be approximately equal to a third threshold voltage V TH3 and providing a third timer signal TMR3 in response to the third threshold voltage V falling below 0. As described in more detail herein, the third threshold voltage V TH3 is the second threshold voltage V TH2 (e.g., the amplitude is close to the amplitude of the first threshold voltage V TH1 than the second threshold voltage V TH2As an example, power supply system 100 may be designed for particular environmental considerations (e.g., radiation hardened by design (RHBD), such as for use in space). Accordingly, radiation hardened design considerations are provided for several features of power supply system 100 as described herein.

[0020] The first timer signal TMR1 is provided to a fault detector ("FSM fault detector") 208 that is part of the FSM controller system 110. In response to the first timer signal TMR1 being provided to the fault detector 208 (e.g., a state change to logic high), and thus expiration of the latch-off timer, the fault detector 208 can determine whether a persistent overvoltage fault is detected. The fault detector 208 receives an overvoltage signal OV, and if the overvoltage signal OV is provided to the fault detector 208 (e.g., logic high) after expiration of the latch-off timer, the fault detector 208 can provide a fault signal FLT that is latched to indicate a persistent overvoltage fault. The fault signal FLT is provided to the OR gate 202, and the latched fault signal FLT results in a latched state of the shut-off signal SO. The latched shut-off signal SO can thus deactivate the voltage-limited power regulator 102 as a result of the persistent overvoltage fault.

[0021] As another example, the fault detector 208 may detect a persistent overvoltage fault based on at least one predetermined condition. In the example of FIG. 2, the fault detector 208 receives a clock signal CLK and a programming signal PRG. The clock signal CLK may correspond to a system clock associated with the system in which the power supply system 100 is implemented and may therefore have a constant frequency. The programming signal PRG may correspond to a programmable digital signal that may define the predetermined condition(s) associated with detecting a persistent overvoltage fault. As an example, the programming signal PRG may define the number of cycles of the clock signal CLK that the overvoltage signal OV is provided for before detecting a persistent overvoltage fault. As another example, the programming signal PRG may define the number of rising edges of the overvoltage signal OV within a predetermined number of cycles of the clock signal CLK before detecting a persistent overvoltage fault. Thus, the combination of the clock signal CLK and the programming signal PRG may define various or programmable conditions as prerequisites for detecting a persistent overvoltage fault.

[0022] The overvoltage latch-off timer system 200 further includes an overvoltage nuisance detector ("FSM fault detector") 210 that is part of the FSM controller system 110. By way of example, the overvoltage nuisance detector 210 may be configured as an SR latch and may be configured to prioritize a "set" input, as described in more detail herein, with radiation-hardened design considerations in mind. The overvoltage nuisance detector 210 is shown receiving a second timer signal TMR2 (e.g., at a set input), a third timer signal TMR3 (e.g., at a reset input), and a fault signal FLT (e.g., at a reset input) provided from the fault detector 208. The second timer signal TMR2 is a latched signal that is generated when the timing voltage is greater than or equal to a second threshold voltage V TH2 , which may correspond to a nuisance overvoltage timer.

[0023] As mentioned above, the second threshold voltage V TH2 is the first threshold voltage V TH1 Therefore, the timing voltage is approximately the second threshold voltage V TH2 A nuisance overvoltage timer expires in response to the voltage V increasing to an amplitude of V. If the fault detector 208 does not detect a persistent overvoltage fault after the expiration of the latch-off timer, then upon expiration of the nuisance overvoltage timer, the overvoltage nuisance detector 210 may provide a reset signal RST to indicate an overvoltage nuisance condition. Thus, the reset signal RST may reset the overvoltage latch-off timer system 200. In the example of FIG. 2, the reset signal RST is provided to the timer latch 204 to reset the latched voltage V. LTCH is also provided to a latch-off timer circuit 206, which latches off the timing capacitor C TMR As a result, the overvoltage condition may correspond to a nuisance overvoltage condition and normal operation of voltage limited power regulator 102 may be maintained. However, in response to detecting a persistent overvoltage fault, a fault signal FLT is provided to overvoltage nuisance detector 210, thus disabling overvoltage nuisance detector 210 in response to detecting a persistent overvoltage fault.

[0024] As mentioned above, the overvoltage nuisance detector 210 also receives a third timer signal TMR3 provided to a reset input. The third timer signal TMR3 is generated when the timing voltage falls below a third threshold voltage V TH3 Therefore, the latch voltage V that starts the latch-off timer may be asserted (e.g., logic high) in response to the latch voltage V being less than LTCH When the timing voltage increases in response to V, the third timer signal TMR3 may go to logic high to hold the overvoltage nuisance detector 210 in reset. Also, as described above, the third threshold voltage V TH3 is the first threshold voltage V TH1 than the second threshold voltage V TH2Thus, the overvoltage nuisance detector 210 may be held in a reset state until just before the expiration of the nuisance overvoltage timer to accommodate radiation-hardened design considerations (e.g., which may affect undesired state changes of the second timer signal TMR2).

[0025] Upon expiration of the nuisance overvoltage timer, the third timer signal TMR3 is asserted such that the timing voltage is equal to or greater than the third threshold voltage V TH3 and the second timer signal TMR2 may be a logic low based on the timing voltage being greater than a second threshold voltage V TH2 Therefore, the second timer signal TMR2 may be provided to a set input of the overvoltage nuisance detector 210 to set the SR latch of the overvoltage nuisance detector 210 and latch the reset signal RST. As described in more detail herein, the reset signal RST opens a switch and latches the timing capacitor C TMR However, if the timing voltage exceeds the third threshold voltage V TH3 In response to the timing voltage dropping below 1 V, the third timer signal TMR3 may be re-asserted (e.g., logic high) to set a reset condition for the over-voltage nuisance detector 210. Thus, the reset signal RST may be de-asserted in response to the third timer signal TMR3 to allow the timing voltage to drop more slowly after a nuisance over-voltage condition is detected.

[0026] Figure 3 shows an example of a latch-off timer circuit 300. The latch-off timer circuit 300 may correspond to the latch-off timer circuit 108 in the example of Figure 1. Accordingly, in the following description of the example of Figure 3, reference will be made to the examples of Figures 1 and 2.

[0027] In the example of FIG. 3, the latch-off timer includes a current source 302 and a charging switch N, shown as an N-channel field effect transistor (N-FET). 1 and a timing capacitor C TMRTherefore, the latch voltage V LTCH In response to the 1 is latched closed. Thus, the current source 302 supplies 1 Through the input voltage V IN From the charging current I CHG As a result, the timing capacitor C TMR is the timing capacitor C TMR The timing voltage V TMR The timer latch 204 indicates an increase in the latch voltage V LTCH , so that a change in the logic state of the overvoltage signal OV from logic high to logic low is latched by the latch voltage V LTCH Therefore, the amplitude of the output voltage V OUT The output voltage V OUT A change in the amplitude of, and therefore a change in the logic state of, the overvoltage signal OV generates a latched voltage V LTCH After the first latch of the timing voltage V TMR does not affect the amplitude of

[0028] Therefore, the timing capacitor C TMR is the timing voltage V TMR As an example, the timing capacitor C TMR may be configured as an external component to the overvoltage latch-off timer system 200, such that the timing capacitor C TMR is provided by a user after manufacture of latch-off timer circuit 300 to allow the user to set the desired duration of the latch-off timer. Thus, unlike the latch-off timer in a typical overvoltage latch-off timer system, which has timing based on the amplitude of the output voltage, the timing capacitor C TMRThe latch-off timer formed by can have a highly predictable time value from the time it is started to the time it expires. In other words, because a typical overvoltage latch-off timer system does not latch an overvoltage condition, the charging of the capacitor to define the latch-off timer can be interrupted (e.g., inconsistent), such as during ratcheting of the output voltage. Such inconsistent and interrupted charging can result in a highly unpredictable timer (e.g., orders of magnitude inaccuracy from testing), which can pose difficulties in planning how to manage and detect sustained overvoltage faults. However, by latching the start of the timer as described herein, the output voltage V relative to the overvoltage reference voltage can be easily determined. OUT Despite the change in timing capacitor C TMR The charging of the power supply can be continuous and uninterrupted, resulting in a timer that is highly predictable in detecting persistent overvoltage faults. Thus, the timer can operate for a predictable period of time regardless of the output impedance or load associated with the power supply circuit.

[0029] In the example of Figure 3, the timing voltage V TMR are provided to a first threshold detector ("TD 1") 304, a second threshold detector ("TD 2") 306, and a third threshold detector ("TD 3") 308. By way of example, the threshold detectors 304, 306, and 308 may be configured as or include comparators and / or other related circuitry for detecting relative voltage amplitudes. The first threshold detector 304 detects a timing voltage V TMR to the first threshold voltage V TH1 so that the first threshold detector 304 compares the timing voltage V TMR is the first threshold voltage V TH12, the fault detector 208 provides a first timer signal TMR1 of a logic high state in response to the output voltage V being greater than V. The first timer signal TMR1 is provided to the fault detector 208, as described above in the example of FIG. 2, and thus corresponds to the expiration of the latch-off timer. Thus, upon receiving the first timer signal TMR1 corresponding to the expiration of the latch-off timer, the fault detector 208 can determine whether the power supply system 100 has experienced a sustained overvoltage fault. The latch-off timer thus provides a first timer signal TMR1 of a logic high state in response to the output voltage V being greater than V, such as in response to a nuisance overvoltage condition, as described in more detail herein. OUT This allows sufficient time for the amplitude to settle to an acceptable amplitude.

[0030] The second threshold detector 306 detects the timing voltage V TMR , the first threshold voltage V TH1 A second threshold voltage V TH2 Therefore, the second threshold detector 306 is configured to compare the timing voltage V TMR is the second threshold voltage V TH2, providing the second timer signal TMR2 in a logic high state in response to the first timer signal TMR1 and the second timer signal TMR2 being approximately equal to 1. Thus, the time between the assertion (e.g., logic high state) of the first timer signal TMR1 and the second timer signal TMR2 may define a detection window for detecting an overvoltage vault via the fault detector 208. Thus, if the fault detector 208 detects an overvoltage condition during the detection window (e.g., after the assertion of the first timer signal TMR1 but before the assertion of the second timer signal TMR2), the fault detector 208 may provide a fault signal FLT, as described above. However, the detection window ends upon the assertion of the second timer signal TMR2 corresponding to the expiration of the nuisance overvoltage timer. If the fault detector 208 does not detect an overvoltage condition prior to the assertion of the second timer signal TMR2, and thus prior to the expiration of the nuisance overvoltage timer, the fault detector 208 may provide a reset signal RST to reset the latch-off timer circuit 300. As a result, the overvoltage condition can be accommodated as a nuisance overvoltage condition and normal operation of the power supply system 100 can be maintained.

[0031] As described above, the reset signal RST is provided to the timer latch 204 to reset the timer latch 204. Thus, the latch voltage V LTCH is no longer provided by the timer latch 204 (e.g., provided at zero volts), thereby turning on the charging switch N 1 As a result, the charging current I CHG is the timing capacitor C TMR In addition, the reset signal RST stops charging the timing capacitor C TMR and a reset switch SW RST , so that the reset signal RST is provided to the reset switch SW RST Therefore, the timing capacitor C TMR is the reset switch SW RST to ground via the timing voltage V TMROnce the latch-off timer circuit 300 is reset by the reset signal RST, the overvoltage latch-off timer system 200 is allowed to operate normally, as described above, until another overvoltage condition is detected, at which point the detection process begins again.

[0032] 3, the latch-off timer circuit 300 also receives a fault signal FLT from the fault detector 208. The fault signal FLT is a signal that is proportional to the input voltage V IN and timing voltage V TMR A P-channel FET (P-FET) P 1 Thus, in response to detection of a sustained overvoltage fault, and thus the assertion of the fault signal FLT, the P-FET P 1 is activated and the timing voltage V TMR Approximately the input voltage V IN Therefore, the fault signal FLT is raised to an amplitude of the timing voltage V TMR In addition, in the example of FIG. 3, the fault signal FLT is latched up by an N-FET N 2 Thus, in response to the detection of a sustained overvoltage fault, and thus the assertion of the fault signal FLT, the N-FET N 2 is activated to pull the second timer signal TMR2 to a logic low state to prevent false detection of a nuisance overvoltage condition in response to detecting a persistent overvoltage fault.

[0033] The third threshold detector 308 detects the timing voltage V TMR , the first threshold voltage V TH1 and the second threshold voltage V TH2 A third threshold voltage V TH3 As an example, the third threshold voltage V TH3 is the first threshold voltage V TH1 than the second threshold voltage V TH2In contrast to the first threshold detector 304 and the second threshold detector 306, the timing voltage V TMR is provided to the inverting input of the third threshold detector 308. Thus, the third threshold detector 308 detects the timing voltage V TMR is the third threshold voltage V TH3 provides a third timer signal TMR3 in a logic high state in response to the timing voltage V being less than TMR is the charging switch N 1 , the third timer signal TMR3 may be logic high and hold the overvoltage nuisance detector 210 in a reset state. The third timer signal TMR3 may thus hold the overvoltage nuisance detector 210 in a reset state until just prior to expiration of the nuisance overvoltage timer (e.g., assertion of the second timer signal TMR2), providing for radiation-hardened design considerations (e.g., that may affect an undesired state change of the second timer signal TMR2).

[0034] Upon expiration of the nuisance overvoltage timer, the third timer signal TMR3 is asserted such that the timing voltage is equal to or greater than the third threshold voltage V TH3 and the second timer signal TMR2 may be a logic low based on the timing voltage being greater than a second threshold voltage V TH2 Therefore, the reset signal RST may be asserted based on the timing voltage V TMR is the third threshold voltage V TH3 and the second threshold voltage V TH2 A logic high is provided between the reset switch SW RST via the timing capacitor C TMR Discharge the timing voltage V TMR However, the timing voltage V TMR is the third threshold voltage V TH3 In response to the third timer signal TMR3 dropping below logic high, the third timer signal TMR3 may be re-asserted (e.g., logic high) to deassert the reset signal RST. Thus, the reset switch SW RSTis opened and the timing voltage V TMR is allowed to decrease more slowly.

[0035] Thus, the time between the assertion (e.g., logic high state) of the first timer signal TMR1 and the second timer signal TMR2 may define a detection window for detecting an overvoltage vault via the fault detector 208. Thus, if the fault detector 208 detects an overvoltage condition during the detection window (e.g., after the assertion of the first timer signal TMR1 but before the assertion of the second timer signal TMR2), the fault detector 208 may provide a fault signal FLT, as described above. However, the detection window ends when the second timer signal TMR2, which corresponds to the expiration of the nuisance overvoltage timer, is asserted. If the fault detector 208 does not detect an overvoltage condition before the assertion of the second timer signal TMR2, and thus before the expiration of the nuisance overvoltage timer, the fault detector 208 may provide a reset signal RST to reset the overvoltage latch-off timer system 200. As a result, the overvoltage condition may correspond to a nuisance overvoltage condition, and normal operation of the power supply system 100 may be maintained.

[0036] Figure 4 shows an example of a fault detector 400. The fault detector 400 may correspond to the fault detector 208 in the example of Figure 2. Therefore, in the following description of the example of Figure 4, reference will be made to the examples of Figures 1 to 3.

[0037] The fault detector 400 includes a fault determination component ("FSM fault determination component") 402 and a detection control component ("FSM detection control component") 404, which are parts of the FSM controller system 110. The fault determination component 402 is configured to receive a first timer signal TMR1 indicative of expiration of a latch-off timer. The fault determination component 402 also receives a trigger signal TRG indicative of a predetermined condition indicative of a persistent overvoltage fault after expiration of the latch-off timer. Thus, in response to the first timer signal TMR1 and the trigger signal TRG, the fault determination component 402 is configured to generate a fault signal FLT indicative of detection of a persistent overvoltage fault.

[0038] The fault detector 400 also includes a clock adjustment component 406 and a radiation-hard guardband component 408. The clock adjustment component 406 and the radiation-hard guardband component 408 each similarly receive a first timer signal TMR1 indicative of expiration of a latch-off timer. The clock adjustment component 406 also receives the clock signal CLK, and the radiation-hard guardband component 408 also receives an overvoltage signal OV. The clock adjustment component 406 and the radiation-hard guardband component 408 may each be configured to ignore the clock signal CLK and the overvoltage signal OV, respectively, until expiration of the latch-off timer via the first timer signal TMR1. Thus, the clock adjustment component 406 is configured to provide an adjusted clock signal CC at each pulse of the clock signal CLK after expiration of the latch-off timer. As an example, the adjusted clock signal CC can shorten the pulse width of the clock signal CLK to mitigate potential logic errors. Similarly, the radiation-hard guardband component 408 is configured to provide a guardband signal GB that can accommodate the overvoltage signal OV after expiration of the latch-off timer. For example, the guard band signal GB may follow the logic state of the overvoltage signal OV while the first timer signal TMR1 is logic high.

[0039] The detection control component 404 is configured to receive the programming signal PRG and generate the trigger signal TRG based on a predefined condition defined by the programming signal PRG. The programming signal PRG can correspond to a programmable digital signal that can define a predefined condition(s) associated with detecting a persistent overvoltage fault. As an example, the programming signal PRG can define the number of cycles of the clock signal CLK provided by the regulated clock signal CC for which the overvoltage signal OV provided by the guardband signal GB is provided before detecting a persistent overvoltage fault. As another example, the programming signal PRG can define the number of rising edges of the overvoltage signal OV provided by the guardband signal GB within a predefined number of cycles of the clock signal CLK provided by the regulated clock signal CC before detecting a persistent overvoltage fault. Thus, the combination of the clock signal CLK and the programming signal PRG can define various or programmable conditions as preconditions for detecting a persistent overvoltage fault. In response to a predetermined condition(s) being met, the detection control component 404 can provide a trigger signal TRG, which can cause the fault determination component 402 to indicate a persistent overvoltage fault after expiration of the latch-off timer by providing a fault signal FLT.

[0040] Figure 5 illustrates an example of a timing diagram 500. Timing diagram 500 may correspond to the operation of overvoltage latch-off timer system 200 in the example of Figures 1-4. Accordingly, in the following description of the example of Figure 5, reference will be made to the example of Figures 1-4.

[0041] Timing diagram 500 illustrates the output voltage V OUT , overvoltage signal OV, latch voltage V LTCH , timing voltage V TMR, the amplitudes of the first timer signal TMR1, the second timer signal TMR2, the third timer signal TMR3, the guard band signal GB, the adjusted clock signal CC, the trigger signal TRG, the fault signal FLT, the interrupt signal SO, and the reset signal RST are shown. 0 At time T 0 From the output voltage V OUT rises. At time T 1 At this point, the output voltage V OUT is the overvoltage reference voltage V OVREF Therefore, at time T 1 At , the instantaneous overvoltage sensor 104 asserts the overvoltage signal OV from a logic low state to a logic high state. In response to the logic high state of the overvoltage signal OV, the shut-off signal SO is asserted to shut off the voltage limited power regulator 102 and the timer latch 204 asserts the latched voltage V LTCH to a logic high state to turn on the charging switch N 1 can be activated (e.g., closed) so that the timing voltage V TMR At time T 1 It can then start to rise at a constant rate.

[0042] In the example of Figure 5, time T 1 in response to deactivating the voltage limited power regulator 102 via a shutoff signal SO, the output voltage V OUT begins to plateau and eventually decreases in amplitude. At time T 2 At this point, the output voltage V OUT is the overvoltage reference voltage V OVREF When the overvoltage signal OV is deasserted to a logic low state, the shutdown signal SO is deasserted to a logic low state as well. However, the timer latch 204 does not latch the latch voltage V LTCH To provide a latch voltage V LTCH is maintained at a logic high swing, and charging switch N 1 closed, thus keeping the timing capacitor C TMR Therefore, the timing voltage V TMR The increase in the amplitude of the output voltage VOUT Regardless of the amplitude of T, the time T can be maintained at a constant slope to provide a predictable duration for the timer. 3 At this point, the output voltage V OUT is the overvoltage reference voltage V OVREF When the output voltage V OUT is the overvoltage reference voltage V OVREF Time T 4 and the output voltage V OUT is the overvoltage reference voltage V OVREF Time T 5 As further evidenced in, the output voltage V OUT is the overvoltage reference voltage V OVREF may oscillate (e.g., ratchet) non-periodically up and down.

[0043] Time T 6 At this time, the timing voltage V TMR is the first threshold voltage V TH1 5, the predetermined condition(s) set by the programming signal PRG may correspond to a single clock adjustment signal CC at expiration of the latch-off timer to detect a persistent overvoltage fault. At time T 6 At time T, the overvoltage signal OV is logic high, indicating that the voltage limited power regulator 102 is still experiencing an overvoltage condition. Thus, in response to the assertion of the first timer signal TMR1, the radiation-tolerant guard band component 408 provides the guard band signal GB. Thus, at time T 6In response to the first clock adjustment signal CC after (shown as immediate in the example of FIG. 5), the detection control component 404 can assert the trigger signal TRG. As a result, the fault determination component 402 detects a persistent overvoltage fault based on the logic high state of both the first timer signal TMR1 and the trigger signal TRG. Thus, the fault determination component 402 asserts the fault signal FLT.

[0044] In response to the fault signal FLT being asserted, the timing voltage V TMR is a P-FET P 1 Through the input voltage V IN The second timer signal TMR2 is pulled to an amplitude of 2 is pulled to ground via the time T 7 At this time, the timing voltage V TMR is the third threshold voltage V TH3 When the shutoff signal SO rises higher than the time T 5 Since the voltage limited power regulator 102 is asserted at time T 5 , resulting in an output voltage V OUT eventually levels off and decreases. At time T 8 At this point, the output voltage V OUT is the overvoltage reference voltage V OVREF 1. As a result, overvoltage signal OV is deasserted to a logic low state, as is guardband signal GB. However, because fault signal FLT remains latched, shutoff signal SO remains in a logic high state, thus indefinitely disabling voltage limited power regulator 102 in response to detecting the persistent overvoltage fault. Thus, appropriate action can then be taken to repair the persistent overvoltage fault.

[0045] Figure 6 illustrates an example of a timing diagram 600. The timing diagram 600 may correspond to the operation of the overvoltage latch-off timer system 200 in the example of Figures 1-4. Accordingly, in the following description of the example of Figure 6, reference will be made to the examples of Figures 1-4.

[0046] Timing diagram 600 illustrates the output voltage V OUT , overvoltage signal OV, latch voltage V LTCH , timing voltage V TMR , the amplitudes of the first timer signal TMR1, the second timer signal TMR2, the third timer signal TMR3, the guard band signal GB, the adjusted clock signal CC, the trigger signal TRG, the fault signal FLT, the interrupt signal SO, and the reset signal RST are shown. 0 At time T 0 From the output voltage V OUT rises. At time T 1 At this point, the output voltage V OUT is the overvoltage reference voltage V OVREF Therefore, at time T 1 At , the instantaneous overvoltage sensor 104 asserts the overvoltage signal OV from a logic low state to a logic high state. In response to the logic high state of the overvoltage signal OV, the shut-off signal SO is asserted to shut off the voltage limited power regulator 102 and the timer latch 204 asserts the latched voltage V LTCH to a logic high state to turn on the charging switch N 1 can be activated (e.g., closed) so that the timing voltage V TMR At time T 1 It can then start to rise at a constant rate.

[0047] In the example of Figure 5, time T 1 in response to deactivating the voltage limited power regulator 102 via a shutoff signal SO, the output voltage V OUT begins to plateau and eventually decreases in amplitude. At time T 2 At this point, the output voltage V OUT is the overvoltage reference voltage V OVREFWhen the overvoltage signal OV is deasserted to a logic low state, the shutdown signal SO is deasserted to a logic low state as well. However, the timer latch 204 does not latch the latch voltage V LTCH To provide a latch voltage V LTCH is maintained at a logic high swing, and charging switch N 1 closed, thus keeping the timing capacitor C TMR Therefore, the timing voltage V TMR The increase in the amplitude of the output voltage V OUT Regardless of the amplitude of T, the time T can be maintained at a constant slope to provide a predictable duration for the timer. 3 At this point, the output voltage V OUT is the overvoltage reference voltage V OVREF When the output voltage V OUT is the overvoltage reference voltage V OVREF Time T 4 and the output voltage V OUT is the overvoltage reference voltage V OVREF Time T 5 As further evidenced in, the output voltage V OUT is the overvoltage reference voltage V OVREF may oscillate (e.g., ratchet) non-periodically up and down.

[0048] Time T 6 At this point, the output voltage V OUT is the overvoltage reference voltage V OVREF When the overvoltage signal OV is deasserted to a logic low state, the shutdown signal SO is also deasserted to a logic low state. 7 At this time, the timing voltage V TMR is the first threshold voltage V TH1. Thus, the threshold detector 304 provides the first timing signal TMR1 in a logic high state to the fault detector 208, which corresponds to the expiration of the latch-off timer. Thus, the fault detector 208 determines whether the voltage-limited power regulator 102 indicates a persistent overvoltage fault.

[0049] Time T 7 At , the overvoltage signal OV is logic low. Thus, the predetermined condition for indicating a persistent overvoltage fault has not yet been met. Thus, the fault signal FLT, and therefore the shutoff signal SO, remain logic low. TMR continues to increase linearly. Time T 8 At this time, the timing voltage V TMR is the third threshold voltage V TH3 When the third timer signal TMR3 rises above the time T 9 At this time, the timing voltage V TMR is the second threshold voltage V TH2 Therefore, the nuisance overvoltage timer is 9 It will expire at.

[0050] Time T 9 In response to the expiration of the nuisance overvoltage timer at timing voltage V, the fault determination detector 402 has not detected a persistent overvoltage fault. Instead, a nuisance overvoltage condition has been detected. TMR is the second threshold voltage V TH2 In response to the overvoltage nuisance detector 210 rising approximately equal to the first timer signal TMR2, the second timer signal TMR2 is asserted to a logic high state. In response, the overvoltage nuisance detector 210 asserts the reset signal RST. The reset signal RST is thus asserted by the reset switch SW RST via the timing capacitor C TMR Discharge at time T 9 to timing voltage V TMR Lower the timing voltage V TMR is time T 10 At the third threshold voltage V TH3When the timer signal TMR3 drops below 1 V, the third timer signal TMR3 is re-asserted (e.g., logic high), thus deasserting the reset signal RST. Thus, the reset switch SW RST is opened and the timing voltage V TMR This allows the timing voltage V TMR is time T 10 , then may be slowly ramped down (e.g., based on leakage) after 100 V. Thus, the voltage limited power regulator 102 may maintain normal operation after detection of a nuisance overvoltage condition, as described above, at which point the detection process may be started over.

[0051] In view of the above structural and functional features, methods according to various embodiments of the present disclosure will be better understood with reference to Figure 7. It should be understood and appreciated that some aspects may occur in different orders and / or simultaneously with other aspects in accordance with the present disclosure than those shown and described herein, and therefore the method of Figure 7 is not limited by the order shown. Furthermore, not all illustrated features are required to practice a method according to an embodiment of the present example.

[0052] 7 illustrates an example of a method 700 for detecting a sustained overvoltage fault in a power supply system (e.g., power supply system 100). At 702, an output voltage (e.g., an output voltage V OUT) is detected. At 704, an overvoltage signal (e.g., overvoltage signal OV) is generated in response to the overvoltage condition. At 706, a latch-off timer is started in response to the overvoltage signal. The latch-off timer may be uninterrupted by the amplitude of the output voltage. At 708, a persistent overvoltage fault is determined in response to the overvoltage signal after expiration of the latch-off timer. At 710, a fault signal (e.g., fault signal FLT) is generated to disable the voltage limited power regulator in response to detecting the persistent overvoltage fault. At 712, a nuisance overvoltage condition is detected in response to not detecting an overvoltage condition after expiration of the latch-off timer and before expiration of the nuisance overvoltage timer.

[0053] The foregoing are examples of the present invention. Of course, it is not possible to describe every conceivable combination of components or methods for purposes of describing the present invention, but one skilled in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such changes, modifications, and variations that fall within the spirit and scope of the appended claims. Moreover, when a disclosure or claim recites "a, an," "a first," "another" element, or the equivalent thereof, it should be construed as including one or more such elements, and does not require or exclude two or more such elements. As used herein, the term "includes" means including without limitation. The term "based on" means based at least in part on.

Claims

1. 1. A power supply system comprising: a power regulator operating in a voltage limit mode to generate an output voltage; an instantaneous overvoltage sensor configured to detect an overvoltage condition associated with the output voltage; an overvoltage latch-off timer system configured to initiate a latch-off timer in response to detecting the overvoltage condition; wherein the latch-off timer is not interrupted by an amplitude of the output voltage, and the overvoltage latch-off timer system is further configured to detect a persistent overvoltage fault in response to detecting the overvoltage condition after expiration of the latch-off timer, and the overvoltage latch-off timer system is configured to generate a fault signal to disable a voltage limiting power regulator in response to detecting the persistent overvoltage fault.

2. The overvoltage latch-off timer system comprises: a latch-off timer circuit configured to initiate the latch-off timer; a finite state machine (FSM) controller system configured to detect the persistent overvoltage fault in response to detecting the overvoltage condition after expiration of the latch-off timer or to detect a nuisance overvoltage condition in response to not detecting the overvoltage condition after expiration of the latch-off timer and before expiration of a nuisance overvoltage timer; The power supply system of claim 1 .

3. The FSM controller system includes a timer latch configured to generate a latched voltage in response to a logic transition from a first state to a second state of an overvoltage signal and to maintain the latched voltage in response to a logic transition from the second state to the first state of the overvoltage signal, the latch-off timer circuit comprising: a charge switch configured to close in response to the latch voltage; a timing capacitor coupled to the charging switch and configured to charge via a charging current through the closed charging switch to generate a timing voltage; The power supply system of claim 2 .

4. 4. The power supply system of claim 3, wherein the latch-off timer circuit includes a threshold detector configured to compare the timing voltage to a threshold voltage, the threshold detector providing a timer signal to the FSM controller system in response to the timing voltage being approximately equal to the threshold voltage corresponding to expiration of the latch-off timer.

5. 5. The power supply system of claim 4, wherein the FSM controller system further includes a fault detector configured to generate the fault signal in response to the timer signal and in response to at least one programmable condition.

6. 6. The power supply system of claim 5, wherein the at least one programmable condition corresponds to receiving the timer signal for at least one of a predetermined duration and a predetermined number of clock cycles.

7. 7. The power supply system of claim 6, wherein the fault detector includes a radiation-hardened guard band component configured to enable the at least one programmable state in response to the timer signal and the overvoltage signal.

8. 5. The power supply system of claim 4, wherein the threshold detector is a first threshold detector configured to compare the timing voltage with a first threshold voltage to provide a first timer signal, and the latch-off timer circuit further includes a second threshold detector configured to compare the timing voltage with a second threshold voltage greater than the first threshold voltage, and the second threshold detector provides a second timer signal to the FSM controller system in response to the timing voltage being approximately equal to the second threshold voltage corresponding to the nuisance overvoltage timer.

9. 9. The power supply system of claim 8, wherein the FSM controller system includes an overvoltage nuisance detector configured to generate a reset signal after expiration of the nuisance overvoltage timer, the reset signal being provided to the timer latch to unlatch the latched voltage and open the charge switch and provided to a discharge switch to discharge the timing capacitor and decrease the timing voltage.

10. 10. The power supply system of claim 9, wherein the latch-off timer circuit includes a third threshold detector configured to compare the timing voltage to a third threshold voltage between the first threshold voltage and the second threshold voltage, the third threshold detector configured to provide a third timer signal to the overvoltage nuisance detector in response to the timing voltage dropping below the third threshold voltage, and the overvoltage nuisance detector configured to disable the reset signal in response to the third timer signal.

11. 11. The power supply system of claim 10, wherein the third threshold voltage has an amplitude closer to that of the second threshold voltage than that of the first threshold voltage to provide a radiation hardened design feature, and the overvoltage nuisance detector is configured as an SR latch including a set input receiving the second timer signal and a reset input receiving the third timer signal, the SR latch designed to override the set input to provide another radiation hardened design feature.

12. 1. A method for detecting a persistent overvoltage fault in an electrical power supply system, comprising: detecting an overvoltage condition associated with an output voltage provided by a power regulator operating in a voltage limit mode; generating an overvoltage signal in response to the overvoltage condition; initiating a latch-off timer in response to the overvoltage signal, the latch-off timer not being interrupted by the amplitude of the output voltage; determining the persistent overvoltage fault in response to the overvoltage signal after expiration of the latch-off timer; generating a fault signal to disable a voltage limiting power regulator in response to detecting the persistent overvoltage fault; detecting a nuisance overvoltage condition in response to not detecting the overvoltage condition after expiration of the latch-off timer and before expiration of a nuisance overvoltage timer. A method comprising:

13. Initiating the latch-off timer generating a latch voltage in response to a logic transition of the overvoltage signal from a first state to a second state; maintaining the latch voltage in response to a logic transition from the second state to the first state of the overvoltage signal to charge a timing capacitor to generate a timing voltage corresponding to the latch-off timer; Including, Determining the persistent overvoltage fault comprises: comparing said timing voltage to a threshold voltage; providing a timer signal in response to the timing voltage being approximately equal to the threshold voltage corresponding to expiration of the latch-off timer; generating said fault signal in response to said timer signal and in response to at least one programmable condition; The method of claim 12, comprising:

14. Comparing the timing voltage includes comparing the timing voltage to a first threshold voltage to provide a first timer signal, the method comprising: comparing the timing voltage to a second threshold voltage greater than the first threshold voltage; providing a second timer signal in response to the timing voltage being approximately equal to the second threshold voltage corresponding to expiration of the nuisance overvoltage timer; generating a reset signal in response to expiration of the nuisance overvoltage timer in the absence of the at least one programmable condition, the reset signal being provided to unlatch the latched voltage; discharging the timing capacitor in response to the reset signal to decrease the timing voltage; The method of claim 13 further comprising:

15. comparing the timing voltage to a third threshold voltage between the first threshold voltage and the second threshold voltage; providing a third timer signal in response to the timing voltage dropping below the third threshold voltage; disabling the reset signal in response to the third timer signal. The method of claim 14 further comprising:

16. 1. A power supply system comprising: a power regulator operating in a voltage limit mode to generate an output voltage; an instantaneous overvoltage sensor configured to detect an overvoltage condition associated with the output voltage; Overvoltage Latch-Off Timer System and The overvoltage latch-off timer system comprises: a latch-off timer circuit configured to initiate a latch-off timer in response to detecting the overvoltage condition, the latch-off timer not being interrupted by an amplitude of the output voltage; a finite state machine (FSM) controller system configured to detect a persistent overvoltage fault in response to detecting the overvoltage condition after expiration of the latch-off timer, and to generate a fault signal that disables a voltage limiting power regulator in response to detecting the persistent overvoltage fault, or to detect a nuisance overvoltage condition in response to not detecting the overvoltage condition after expiration of the latch-off timer and before expiration of a nuisance overvoltage timer; A power supply system comprising:

17. The FSM controller system includes a timer latch configured to generate a latched voltage in response to a logic transition from a first state to a second state of an overvoltage signal and to maintain the latched voltage in response to a logic transition from the second state to the first state of the overvoltage signal, the latch-off timer circuit comprising: a charge switch configured to close in response to the latch voltage; a timing capacitor coupled to the charging switch and configured to charge via a charging current through the closed charging switch to generate a timing voltage; The power supply system of claim 16 , comprising:

18. 18. The power supply system of claim 17, wherein the latch-off timer circuit includes a threshold detector configured to compare the timing voltage to a threshold voltage, the threshold detector providing a timer signal to the FSM controller system in response to the timing voltage being approximately equal to the threshold voltage corresponding to expiration of the latch-off timer, the FSM controller system further including a fault detector configured to generate the fault signal in response to the timer signal and in response to at least one programmable condition.

19. 20. The power supply system of claim 18, wherein the threshold detector is a first threshold detector configured to compare the timing voltage with a first threshold voltage to provide a first timer signal, the latch-off timer circuit further includes a second threshold detector configured to compare the timing voltage with a second threshold voltage greater than the first threshold voltage, the second threshold detector providing a second timer signal to the FSM controller system in response to the timing voltage being approximately equal to the second threshold voltage corresponding to the nuisance overvoltage timer, and the fault detection circuit includes an overvoltage nuisance detector configured to generate a reset signal after expiration of the nuisance overvoltage timer, the reset signal being provided to the timer latch to unlatch the latched voltage and open the charge switch and provided to a discharge switch to discharge the timing capacitor and decrease the timing voltage.

20. 20. The power supply system of claim 19, wherein the latch-off timer circuit includes a third threshold detector configured to compare the timing voltage to a third threshold voltage between the first threshold voltage and the second threshold voltage, the third threshold detector configured to provide a third timer signal to the overvoltage nuisance detector in response to the timing voltage dropping below the third threshold voltage, and the overvoltage nuisance detector configured to disable the reset signal in response to the third timer signal.

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