Apparatus and method for reducing wafer backside damage - Patents.com

Abstract

A wafer chuck assembly is disclosed according to at least one embodiment. In at least one embodiment, the wafer chuck assembly comprises a wafer chuck including a substantially circular surface having a first area. In at least one embodiment, a plurality of mesas are distributed on the surface of the wafer chuck. In at least one embodiment, each mesa of the plurality of mesas extends to a height above the wafer chuck surface. In at least one embodiment, the plurality of mesas has a contact surface having a second area that is at least 3% of the first area.

Description

[Technical field]

[0001] CROSS REFERENCE TO RELATED APPLICATIONS: This application is a continuation of and claims the benefit of priority to U.S. patent application Ser. No. 63 / 269,607, entitled "Apparatus and Method for Reducing Wafer Backside Damage," filed on March 18, 2022, which is incorporated by reference in its entirety. [Background technology]

[0002] Substrate processing tools are used to perform processes such as deposition and etching of thin films on substrates such as semiconductor wafers. Deposition may be performed, for example, using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), and / or other deposition processes to deposit conductive, dielectric, or other types of films. During deposition, the wafer substrate is secured on a substrate support (e.g., a pedestal). The pedestal may hold the substrate by electrostatic or vacuum clamping facilitated by a chuck on the pedestal. In either case, the wafer substrate is pressed against the chuck. In many processes, the wafer is thermally cycled to control the deposition or etching chemistry on the exposed surface of the wafer substrate. Microscopic irregularities on the chuck surface can scrape or chip small particles off the backside of the wafer substrate during thermal equilibrium as the wafer expands or contracts. The particles can accumulate on the chuck and transfer to subsequent wafer substrates during sequential processing of multiple wafers on the same tool. Contamination of the backside of a wafer due to accidental particle deposition can affect downstream processing, for example, backside particle contamination can affect the quality of subsequent photolithography operations.

[0003] A common solution is to incorporate multiple contact minimization structures on the chuck surface, which provide a minimum contact area for the wafer secured to the chuck. The contact minimization structures may be, for example, in the form of small hemispherical domes or pillars distributed on the chuck surface. The structures minimize the contact area between the backside of the wafer substrate and the chuck. The wafer mounted on the chuck may rest on the contact minimization structures, which offset the wafer from the chuck surface. The advantage realized by the vertical offset between the wafer and the chuck surface may be a reduction in the formation of debris, such as large dust particles and fine photoresist particles, caused by contact with a flat surface. The number of point contact structures may be small. The total contact area of ​​the structures may be limited to a small fraction of the wafer area, for example less than 1%. Minimizing the contact area is beneficial in reducing particle generation, but the clamping force may be large on the contact minimization structures, which may press the structures against the backside of the substrate. Often the structures are dome-shaped, with a single point of contact to the wafer backside. At these contact points, the clamping pressures can be very high. For example, resist coatings and deposited metal, oxide, and nitride films on the backside of the wafer can be damaged by excessive pressure, either indenting or cracking the metal or dielectric films, because the contact area of ​​the structures is very small. A solution is needed to reduce the damage caused by the mesa while maintaining its benefits. [Brief description of the drawings]

[0004] The subject matter described herein is presented by way of example and not limitation in the accompanying figures. For simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified "ideal" forms and geometries for clarity of illustration, but it will nevertheless be understood that actual embodiments may only approximate the illustrated ideals. For example, smooth surfaces and right angle intersections may be depicted while ignoring the finite roughness, corner rounding, and imperfect corner intersections characteristic of structures formed by nanofabrication techniques. Additionally, where considered appropriate, reference labels are repeated among the figures to indicate corresponding or similar elements.

[0005] [Figure 1] FIG. 1 illustrates a cross-sectional view of a wafer chuck assembly with a mesa on a wafer chuck surface in accordance with at least one embodiment.

[0006] [Diagram 2] FIG. 2 illustrates a top view of a first embodiment of a wafer chuck assembly with hexagonal mesas, according to at least one embodiment.

[0007] [Diagram 3] FIG. 3 illustrates a top view of a wafer chuck assembly comprising multiple circular mesas, according to at least one embodiment.

[0008] [Figure 4] FIG. 4 illustrates a top view of a wafer chuck assembly comprising a plurality of linear mesas, according to at least one embodiment.

[0009] [Diagram 5] FIG. 5 illustrates a top view of a wafer chuck assembly with multiple wedge-shaped mesas with a symmetrical angular distribution in accordance with at least one embodiment.

[0010] [Figure 6] FIG. 6 illustrates a top view of a wafer chuck assembly with a logarithmically increasing radial distribution of mesas in accordance with at least one embodiment.

[0011] [Figure 7] FIG. 7 illustrates a top view of a wafer chuck assembly with a plurality of mesas with a logarithmically decreasing radial distribution in accordance with at least one embodiment.

[0012] [Figure 8] FIG. 8 illustrates a top view of a wafer chuck assembly with multiple mesas having a logarithmic radial distribution and a logarithmic diameter progression, in accordance with at least one embodiment.

[0013] [Figure 9] FIG. 9 illustrates a top view of a wafer chuck assembly with multiple mesas, including tiled mesas, in accordance with at least one embodiment.

[0014] [Figure 10] FIG. 10 illustrates a cross-sectional view of a wafer processing apparatus including a wafer chuck assembly including multiple mesas, according to at least one embodiment.

[0015] [Figure 11] FIG. 11 illustrates a flow chart summarizing an exemplary method of use of a wafer processing apparatus, according to at least one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] At least one embodiment describes a minimum contact area separation pattern to reduce damage to the backside of the wafer. Numerous specific details, such as construction schemes, are described herein to provide a thorough understanding of at least one embodiment. It will be apparent to one of ordinary skill in the art that at least one embodiment can be practiced without these specific details. In other instances, well-known features, such as gas line tube fittings, heating elements, snap switches, and the like, are not described in great detail so as not to unnecessarily obscure the embodiments. Additionally, it should be understood that at least one embodiment as depicted is an illustrative representation and may not necessarily be drawn to scale.

[0017] In some instances, well-known methods and devices are shown in block diagram form rather than in detail so as not to obscure the disclosure. Throughout this specification, reference to "an embodiment," "at least one embodiment," or "one embodiment," or "some embodiments" means that a particular feature, structure, function, or characteristic described in connection with at least one embodiment may be included in at least one embodiment of the disclosure. Thus, the appearance of the phrases "in an embodiment," or "at least one embodiment," or "in one embodiment," or "some embodiments" in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment if particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0018] Here, "coupled" and "connected," along with their derivatives, may be used herein to describe a functional or structural relationship between components. These terms are not intended as synonyms for each other. Rather, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct, physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect (with other elements between them) physical, electrical, or magnetic contact with each other and / or that two or more elements cooperate or interact with each other (e.g., in a cause and effect relationship).

[0019] Here, as used herein, "over," "under," "between," and "on" may generally refer to the relative location of one component or material with respect to other components or materials to which such physical relationship is noted. Unless these terms are modified with "direct" or "directly," one or more intervening components or materials may be present. A similar distinction is made in the context of component assemblies. As used throughout this specification and in the claims, a list of items joined by "at least one of" or "one or more of" may mean any combination of the listed terms.

[0020] As used herein, "adjacent" may generally refer to the location of one thing next to (e.g., immediately adjacent or nearby with one or more things between) or bordering (e.g., touching) another.

[0021] Unless the clear context of usage dictates otherwise, the terms "substantially equal," "about equal," and "approximately equal" generally may mean that there is no more than an incidental variation between the two items so described. Such variation is usually no more than ±10% of the reference value.

[0022] To address at least the limitations described herein, embodiments of a wafer chuck assembly are disclosed that include a dense mesa pattern. Here, "mesa" may generally refer to a plurality of contact-minimizing structures, such as small mesas, on a wafer chuck surface to which a substrate, such as a semiconductor wafer, may be attached. In this disclosure, "mesa" may be used throughout as an embodiment of a mesa. In at least one embodiment, the mesa may have a substantially flat contact surface, providing a larger contact area than the point contact of a conventional hemispherical structure. In at least one embodiment, while an individual mesa provides a very small contact area between the wafer and the platen, when integrated into a dense pattern, the collective contact area may be sufficient to reduce the contact pressure due to the clamping force on the individual mesas below a critical level above which backside layer damage may occur.

[0023] In at least one embodiment, the threshold contact area may be at least 3% (e.g., 3%-90%) of the total surface area of ​​the wafer chuck assembly to reduce the clamping force load per individual mesa. Reducing the clamping force load per individual mesa may reduce damage to the wafer backside due to excessive loads caused by the individual mesas. In at least one embodiment, the mesas include rounded or sloped leading edges between the sidewalls and the top surface. In at least one embodiment, the top and / or side edges located at the rounded tips may reduce scratching and damage to the backside wafer film or layers caused by the mesa when the wafer expands or contracts during thermal cycling. Here, "rounded" generally refers to the top edge of the mesa where the top contact surface and the sidewall intersect. In at least one embodiment, the rounded edges may be characterized by a radius of curvature rather than a sharp angle. Here, "sloped" in the context of the top edge of a mesa generally refers to an edge that may have a transition between a substantially vertical sidewall and a substantially horizontal top surface that runs at an oblique angle.

[0024] Here, a "wafer chuck" may generally refer to a structure including a plate or platen on which a wafer may be mounted and clamped. In at least one embodiment, the clamping of the wafer may be by vacuum clamping or electrostatic clamping. Here, a "vacuum clamp" may generally refer to a means for clamping a wafer substrate to a wafer chuck by vacuum. Here, an "electrostatic clamp" may generally refer to a means for clamping a wafer substrate to a wafer chuck by electrostatic forces. In at least one embodiment, the platen may comprise a surface having a substantially circular shape. Here, a "wafer chuck assembly" may generally refer to an assembly including a wafer chuck and may further include a tube attached to the wafer chuck, which may house cables, wires, vacuum tubes, and gas lines that feed the wafer chuck. Here, a "wafer chuck surface" may generally refer to a surface of a platen that is part of a wafer chuck on which a wafer substrate may be placed. In at least one embodiment, the wafer chuck surface may be substantially circular. Other suitable shapes of the wafer chuck surface may be within the scope of the present disclosure. Here, a "wafer" or "wafer substrate" may generally refer to a semiconductor wafer. In at least one embodiment, the semiconductor wafer, such as a silicon wafer, has a generally disk-shaped shape, and in at least one embodiment, the diameter of the wafer can range from 3 cm to 50 cm.

[0025] In at least one embodiment, the plurality of mesas may be distributed in a substantially uniform pattern on the surface of the wafer chuck assembly. In at least one embodiment, the number of mesas per unit area may be substantially constant across substantially the entire wafer chuck surface. In at least one embodiment, the plurality of mesas has a non-uniform distribution pattern across the wafer chuck surface. In at least one embodiment, the number of mesas per unit area may have a radially varying distribution across substantially the entire wafer chuck surface. In at least one embodiment, the plurality of mesas may have a uniform contact surface area and / or shape. In at least one embodiment, the mesas may have a contact surface shape (e.g., variation in contact area dimensions) that varies across a portion of the wafer chuck surface. In at least one embodiment, for all mesa distribution patterns, the combined area percentage of the plurality of mesas may be at least 3% of the wafer chuck surface area, and thus the wafer surface area.

[0026] FIG. 1 illustrates a cross-sectional view of a wafer chuck assembly 100, according to at least one embodiment. In at least one embodiment, the wafer chuck assembly 100 comprises a plurality of mesas 102 distributed on a wafer chuck surface 104 of a wafer chuck 106. In at least one embodiment, the wafer chuck surface 104 may be substantially circular. The wafer chuck 106 may be mounted on a pedestal 108. In at least one embodiment, the wafer chuck assembly 100 may generally comprise a wafer chuck 106 and a pedestal 108. In at least one embodiment, the mesas 102 may have a width w1. In at least one embodiment, the width w1 may be in a range of 100 mils to 250 mils (e.g., about 2.50 mm to 6 mm). In at least one embodiment, the mesas 102 may have a separation distance s1 between adjacent mesas 102. In some embodiments, s1 may be in a range of 100 mils to 1000 mils. In at least one embodiment, the mesa 102 can have a z-height h1 that can range from 10 mils (eg, about 250 microns) to 100 mils (eg, about 2.5 mm).

[0027] In at least one embodiment, the mesa 102 may include upper edges 110 and 112 between the sidewalls 114 and 116 and the contact surface 118. Here, the "contact surface" may generally refer to the top or upper surface of the mesa 102 (and other embodiments of the mesas disclosed herein) that contacts (e.g., contacts) an overlying substrate, such as a semiconductor wafer. In at least one embodiment, the contact surface may be the interface between the overlying substrate and the mesa. In at least one embodiment, the semiconductor wafer may have a disk shape that includes a substantially flat surface. In at least one embodiment, the contact surface may be flat or slightly curved, but is generally not sharp. As used herein, the contact surface of the disclosed mesa embodiments is flat. As used herein, the contact surface may be substantially smooth or textured. In at least one embodiment, the contact surface 118 of the mesa 102 may have an area that contacts an overlying substrate, such as a semiconductor wafer. In at least one embodiment, the total contact area of ​​the mesas with the overlying wafer substrate may be calculated, for example, as the contact area of ​​an individual mesa multiplied by the total number of mesas on the wafer chuck surface, hi at least one embodiment, the contact surface area of ​​the mesas may be given as a percentage of the surface area of ​​the wafer chuck surface.

[0028] In at least one embodiment, the contact surface of the disclosed mesa may be bordered with an upper edge, where "upper edge" may generally refer to the intersection of the contact surface and the sidewall of the mesa. In at least one embodiment, the upper edge is the edge of the top of the mesa. In at least one embodiment, the upper edge may be rounded or beveled to eliminate sharp edges that may contribute to damage to the backside of the wafer.

[0029] In at least one embodiment, the top edges 110 and 112 may present an oblique or perpendicular angle to the radial direction of the wafer chuck surface 104. In at least one embodiment of the wafer chuck assembly 100, the backside 120 of the wafer substrate 122 may contact the mesa 102. In at least one embodiment, the wafer chuck 106 may be heated to high temperatures due to thermal cycling of the wafer substrate 122 during processing. In at least one embodiment, during thermal cycling, the wafer substrate 122 may expand and contract. In some embodiments, the top edges 110 and 112 may be leading edges of the mesa 102 relative to the wafer backside 120. Here, a "leading edge" may generally refer to one or more top edges near the contact surface of the mesa. In at least one embodiment, the leading edge may be perpendicular or parallel to the direction of thermal expansion or contraction of the wafer that may occur during thermal cycling. Due to the radial symmetry of the wafer, the thermal expansion and contraction may generally occur along the radial direction. In at least one embodiment, the leading edge may be rounded, beveled, or formed with other geometric designs to avoid sharp edges, thereby reducing damage and scratching during thermal expansion and contraction of the wafer.

[0030] In at least one embodiment, the upper edges 110 and 112 may be rounded or beveled to reduce scratching of layers or thin films on the wafer backside 120. In at least one embodiment, the upper edges 110 and 112 may have at least one rounded edge with an appropriate radius of curvature r1 that allows the mesa 102 to slide on the wafer backside 120. In at least one embodiment, the upper edges 110 and 112 may extend around the contact surface 118 of the mesa 102.

[0031] In at least one embodiment, the contact surface 118 may be substantially planar. In at least one embodiment, a substantially planar contact surface 118 may be advantageous over a single point contact or a small surface area contact, such as a hemispherical contact surface. In at least one embodiment, a planar contact surface 118 may provide a lower contact pressure against the wafer backside 120 than a hemispherical or pointed surface.

[0032] 2 illustrates a top view of a wafer chuck assembly 200 including a plurality of hexagonal mesas 202 distributed over a surface 204 of a wafer chuck 205, according to at least one embodiment. In at least one embodiment, the wafer chuck 205 may have a diameter D1 in the range of, for example, 100 mm to 300 mm. In at least one embodiment, the wafer chuck 205 may be mounted on a pedestal 108 as shown. In at least one embodiment, the mesas 202 may be arranged in a uniform pattern on the wafer surface 204, as shown. In at least one embodiment, the mesas 202 are arranged in a hexagonal close-packed pattern that substantially fills the circular wafer chuck surface 204.

[0033] Here, "dense" or "dense distribution" may generally refer to a geometric arrangement that minimizes spacing between substantially identical individual objects in an array of objects. In at least one embodiment, the minimum spacing results in maximum packing density of the array of identical objects within the boundaries of a defined surface or volume. In at least one embodiment, "hexagonal dense" may generally refer to a two-dimensional packing geometry in which one object of a plurality of objects may be surrounded by six other identical objects such that the six adjacent objects are centered on the vertices of a symmetrical hexagon and the surrounded object is located at the center of the hexagon. In at least one embodiment, in a hexagonal dense array, a defined area may be maximally packed with identical objects. In at least one embodiment, the objects may have a circular or polygonal horizontal cross section. In at least one embodiment, for maximum packing within a defined surface area or volume, circular objects (e.g., cylinders) may have a closest spacing that may be touching at least at one point or that may be 10% or less of the diameter of the circular objects. In at least one embodiment, the sidewalls of a polygonal object may also touch or have a closest spacing that may be no more than 10% of the object's width.

[0034] Here, the dark lines between mesas 202 (e.g., shown as open hexagons) are spaces between adjacent mesas 202. In at least one embodiment, the mesas 202 may fill 70%-90% of the wafer chuck surface 204. In at least one embodiment, the degree of filling of the surface may depend on the width w2 of the mesas 202 and the spacing s2 between the sidewalls 206 of adjacent mesas 202, as shown in the inset. In at least one embodiment, the mesas 202 have a symmetrical hexagonal cross-section (e.g., the mesas 202 have substantially equal polygonal cross-sections and perimeter dimensions). In at least one embodiment, the mesas 202 may have any suitable polygonal cross-section.

[0035] In at least one embodiment, other suitable polygonal symmetric or asymmetric cross-sectional shapes (e.g., square, rectangular, parallelepiped, or trapezoidal, alone or in combination with other suitable polygonal shapes such as triangles, pentagons, and hexagons) may be employed. In at least one embodiment, the hexagonal mesas 202 are equally spaced apart on all six sides from adjacent mesas 202 at a spacing s2. In at least one embodiment, the mesas 202 are substantially symmetric. For example, all six sidewalls 206 have a length L1. In at least one embodiment, the mesas 202 may be asymmetric. For example, one or more sidewalls 206 may have a different length than adjacent sidewalls (not shown) on the same mesa 202. In at least one embodiment, the sidewalls 206 may be substantially non-vertical and may have a slope.

[0036] In at least one embodiment, mesa 202 includes contact surface 208. In some embodiments, contact surface 208 may be substantially planar, as described above for contact surface 118. In at least one embodiment, upper edge 210 is rounded. In at least one embodiment, upper edge 210 may have a radius of curvature r2. In at least one embodiment, r2 may be adjusted to optimize the contact area of ​​contact surface 208. In at least one embodiment, apex 212 is also rounded, e.g., having a radius of curvature r3. In at least one embodiment, upper edge 210 and apex 212 may be rounded to reduce damage to layers and / or thin films that may be on the wafer backside (e.g., backside 120).

[0037] In at least one embodiment, the number of mesas 202 per unit area of ​​the wafer chuck surface 204 may be constant. In at least one embodiment, the coverage of the wafer chuck surface 204 by the hexagonal dense mesas 202 may be about 70%. In at least one embodiment, the area percentage of the wafer chuck surface 204 that may be occupied by the contact surface 208 may be controlled by adjusting the space distance s2 and the radius of curvature r2 of the rounded top edge 210. In at least one embodiment, increasing r2 may reduce the contact area of ​​the mesas 202. In at least one embodiment, while a dense pattern as shown in FIG. 2 may provide approximately the maximum contact area, other distribution patterns with less dense mesas 202 may be employed to adjust the contact area to an appropriate value.

[0038] In at least one embodiment, the clamping load may be generated by electrostatic or vacuum clamping of the wafer substrate (e.g., wafer substrate 122) to the wafer chuck 205. In at least one embodiment, a particular area percentage of the wafer substrate (e.g., occupied by the contact surfaces 208 of the mesas 202) may be optimized to reduce the clamping load per mesa to a desired level. In at least one embodiment, the greater the surface percentage occupied by the contact surfaces 208, the smaller the clamping load carried by each individual mesa 202. In at least one embodiment, a typical advantage of reducing the clamping load per mesa 202 is that by providing a high contact area, it may reduce or eliminate imprinting or penetration into the soft photoresist layer on the wafer backside. In at least one embodiment, the contact area may be optimized to reduce particle generation while increasing the contact area may reduce damage to the backside thin films and layers. In at least one embodiment, particles that may be generated due to friction between the contact surfaces and the wafer backside may be isolated between adjacent mesas 202. In at least one embodiment, the mesa may have a height h2 that may be optimized to separate the contact surface 208 from the wafer chuck surface 204. In at least one embodiment, h2 may range from 0.01 mm (10 microns) to 0.25 mm (250 microns). In at least one embodiment, particles may fall below the contact surface 208, thereby mitigating particle contamination of the backside surface.

[0039] In at least one embodiment, the wafer chuck assembly 200 may be a vacuum wafer chuck assembly that includes a vacuum port 214 on the wafer chuck surface 204. Here, a "vacuum port" may generally refer to a connection point to a vacuum line. In at least one embodiment, the wafer chuck assembly 200 may include a lift pin port 216 from which a lift pin (not shown) may rise to lift a wafer substrate (e.g., wafer substrate 122, FIG. 1) off of the contact surface 208. In at least one embodiment, the vacuum ports 214 may be arranged in a symmetrical pattern, such as the hexagonal pattern shown. In at least one embodiment, during operation of the wafer chuck assembly 200, a wafer substrate (e.g., wafer substrate 122) may be placed on the wafer chuck 205. In at least one embodiment, the wafer substrate may contact a plurality of mesas 202. In at least one embodiment, a backside of the substrate (e.g., wafer backside 120) may be offset from the wafer chuck surface 204 by a height h2 of the mesas 202. The vacuum clamp may be created by drawing in ambient gas through vacuum ports 214 to generate a low pressure in the space between the mesas 202. In at least one embodiment, the height h2 of the mesas 202 may be adjusted to optimize the vertical offset of the wafer substrate to optimize vacuum clamping, which requires adjusting the open volume below the substrate for a particular pressure differential between the top and bottom sides of the wafer substrate.

[0040] FIG. 3 illustrates a top view of a wafer chuck assembly 300 including a plurality of mesas 302 distributed on a surface 304 of a wafer chuck 305, according to at least one embodiment. In at least one embodiment, the wafer chuck 305 may have a diameter D1 in the range of, for example, 100 mm to 300 mm. In at least one embodiment, the wafer chuck 305 may be mounted on a pedestal 108 as shown. In at least one embodiment, the mesas 302 may be uniformly distributed on the wafer chuck surface 304 in a hexagonal dense pattern to maximize the contact surface area with the wafer substrate (e.g., wafer substrate 122). In at least one embodiment, the area percentage of the wafer contacted by the mesas 302 in the dense pattern may be between 3% and 90%. In the illustrated embodiment, the mesas 302 are substantially identical (e.g., the mesas 302 have a substantially equal circular cross section) cylindrical mesas or cylindrical posts having a circular horizontal cross section with a diameter D2. In at least one embodiment, D2 may range from 100 to 300 mils (e.g., about 2.5 mm to 7.5 mm). In at least one embodiment, other suitable circular shapes (e.g., elliptical and / or oval) may be employed. In at least one embodiment, circular or round mesas may be combined with other suitable circular and / or polygonal shapes.

[0041] In at least one embodiment, as shown in the inset, the mesas 302 can have a spacing s4 between adjacent mesas 302. The spacing s4 may be adjusted to optimize the contact surface area. In at least one embodiment, the spacing s4 can be in the range of 80 to 160 mils (e.g., about 2 mm to 4 mm). In at least one embodiment, the mesas 302 can have a z-height h3 of 0.01 mm to 0.25 mm.

[0042] In at least one embodiment, the mesa 302 can include a rounded upper edge 310 between the contact surface 308 and the sidewall 306. In at least one embodiment, the rounded upper edge 310 can have a radius of curvature r4, as shown in the inset. As discussed above, the radius of curvature r4 can be tailored to minimize effects on backside thin films or layers during thermal cycling of the wafer substrate during processing. At the same time, in at least one embodiment, the radius of curvature r4 can be tailored for optimal area of ​​the contact surface 308.

[0043] In at least one embodiment, the total contact area can be the sum of the contact surfaces 308 of all mesas 302. In at least one embodiment, a wafer chuck surface 304 having a diameter D1 of about 300 mm (e.g., 11.2 inch diameter, 98.5 square inch area) can include, for example, 2259 substantially identical mesas 302 with a center-to-center spacing s4 of about 230 mils (e.g., about 5.7 mm). In at least one embodiment, the contact surface 308 of an individual mesa 302 (e.g., having a diameter D2 of 120 mils) can be 0.011 square inches (e.g., about 7.1 mm). 2 In at least one embodiment, the total area in contact with the wafer substrate can be about 25.5 square inches (e.g., about 164.5 cm 2 In at least one embodiment, the contact area ratio at mesa 302 may be approximately 26%, which exceeds the threshold of 3%.

[0044] In at least one embodiment, a wafer vacuum clamped to the wafer chuck assembly 300 can have a pressure differential of 10 torr (e.g., 0.193 psi) between the top and backside of a wafer substrate clamped to the wafer chuck assembly 300. In at least one embodiment, the total atmospheric (e.g., clamp) load on the wafer can be about 19 pounds (e.g., about 8.6 kg). In at least one embodiment, the load can be substantially evenly distributed across the multiple mesas 302. In at least one embodiment, the load per mesa 302 can be about 0.0084 pounds (e.g., about 3.8 grams, 0.76 psi). In at least one embodiment, the threshold pressure per mesa can be less than 0.76 psi, for example.

[0045] FIG. 4 is a plan view of a wafer chuck assembly 400, according to at least one embodiment. In at least one embodiment, the wafer chuck assembly 400 comprises a plurality of linear mesas, including a first subset comprising linear mesas 402, a second subset comprising linear mesas 404, and a third subset comprising linear mesas 406. In at least one embodiment, the collection of linear mesas 402, 404, and 406 constitutes a subset of the plurality of mesas. In at least one embodiment, the linear mesas 402, 404, and 406 may be distributed in a polar geometry, where "polar geometry" may generally refer to an angular distribution (e.g., in a polar coordinate system), where the linear mesas may be repeated at regular or irregular angles around a circular surface. In at least one embodiment, the linear mesas 402-406 are substantially formed as lines having three different lengths. In at least one embodiment, mesa 402 has the longest length and mesa 406 has the shortest length. In at least one embodiment, mesas 402, 404, and 406 are symmetrically distributed on surface 408 of wafer chuck 409. In at least one embodiment, mesas 402, 404, and 406 are repeated in sequence at multiple angular intervals, although they may be distributed in any suitable manner. In at least one embodiment, wafer chuck 409 may be mounted on pedestal 108 as shown. In at least one embodiment, wafer chuck 409 may have a diameter D1 in the range of 100 mm to 300 mm. In at least one embodiment, mesas 402, 404, and 406 are angularly symmetric (e.g., have substantially the same angular spacing in degrees) but distributed in a radially non-uniform pattern as shown. In at least one embodiment, the density of mesas 402, 404, and 406 may increase toward the periphery of wafer chuck surface 408, for example, to support radially increasing clamping loads.

[0046] In at least one embodiment, mesas 402, 404, and 406 may each be a linear structure and may extend between radii R1, R2, and R3. In at least one embodiment, mesa 402 is the longest of the three mesa subsets and extends between radii R1 and R4. In at least one embodiment, some mesas 402 are interrupted by vacuum ports 410. In at least one embodiment, mesa 404 has a medium length and extends between radii R1 and R3. In at least one embodiment, mesa 406 is the shortest of the tree mesas and extends between radii R1 and R2 near the periphery of the wafer chuck surface 408.

[0047] In at least one embodiment, mesas 402, 404, and 406 may have substantially the same width w4. In at least one embodiment, the mesas may have different widths. In at least one embodiment, mesas 402, 404, and 406 may be interleaved as shown. In at least one embodiment, mesas 402 are repeated every 30 degrees around wafer chuck surface 408. In at least one embodiment, mesas 404 are repeated every 30 degrees and are interspersed between mesas 402. In at least one embodiment, mesas 406 are repeated every 15 degrees between adjacent mesas 402 and 404. In at least one embodiment, depending on width w4 and the number of mesas desired, the mesas (e.g., mesas 402, 404, 406) may be positioned at any suitable angular position.

[0048] FIG. 5 illustrates a plan view of a wafer chuck assembly 500 comprising a plurality of wedge-shaped mesas 502 arranged in a symmetric angular distribution around a surface 504 of the wafer chuck 505, according to at least one embodiment. The plan view of FIG. 5 illustrates the wafer chuck 505 mounted on a pedestal 108, according to at least one embodiment. In at least one embodiment, the wafer chuck 505 may have a diameter D1 in the range of 100 mm to 300 mm. In at least one embodiment, the mesas 502 are substantially wedge-shaped and comprise diverging sidewalls 506 that fan out from a central region of the surface 504 toward the periphery. In at least one embodiment, the mesas 502 may have a width w5 that increases with increasing radial distance from the center of the surface 504. Herein, "wedge-shaped" may generally refer to the shape of a substantially triangular object. In at least one embodiment, a general definition of a wedge can be a triangular or trapezoidal shape having non-parallel sidewalls that subtend an angle between them and a width that increases with the distance from one end to the other.

[0049] In at least one embodiment, the mesas 502 are substantially identical. In some embodiments, the sidewalls 506 and 507 of the mesas 502 extend between radii R4 and R5, spanning a radial distance R5-R4. In at least one embodiment, the mesas 502 may be arranged in a symmetrical dense pattern, as shown. In at least one embodiment, the sidewalls 506 and 507 of adjacent mesas 502a and 502b are also adjacent and spaced apart by a distance g1, as shown in the inset. In at least one embodiment, the mesas 502 may include a contact surface 508 that may provide a large contact area. In at least one embodiment, the contact surface 508 may be joined to the sidewalls 506 and 507 by a blunt upper edge 509, which is shown as a sloped transition between the sidewalls 506 and 507 and the contact surface 508. In at least one embodiment, the upper edge 509 may be a rounded edge, such as the leading edge 210 shown in FIG. 2.

[0050] In at least one embodiment, the sidewalls 506 and 507 extend along a radial vector of the wafer chuck surface 504. In at least one embodiment, the extension of the sidewalls 506 and 507 along a radial vector may substantially eliminate or completely avoid scratching of the wafer backside during thermal cycling of the attached wafer. Like the edges of the mesa 502. In at least one embodiment, the bevel or rounding of the upper edge 509 may also reduce scratching of the wafer backside during thermal cycling. In at least one embodiment, during thermal cycling of a wafer substrate clamped to the wafer chuck assembly 500, the radially extending upper edge 509 of the mesa 502 may be substantially parallel to the direction of thermal expansion and contraction. As a result, in at least one embodiment, the upper edge 509 may be less likely to scratch the wafer backside during thermal expansion and contraction. In at least one embodiment, because mesa 502 may also undergo thermal expansion and contraction during thermal cycling, the coefficient of thermal expansion (CTE) of mesa 502 may be designed to substantially match the CTE of the wafer so that relative motion between mesa 502 and the wafer may be minimized.

[0051] In at least one embodiment, the wedge shape of the mesas 502 may enable uniform radial and angular distribution of contact surface on the wafer chuck surface 504. In at least one embodiment, as the clamping force on a wafer substrate (e.g., wafer substrate 122) increases parabolically (e.g., as the radius or diameter squared), the contact area also increases parabolically in the radial direction, so the fan-like structure of the mesas 502 may distribute the clamping force evenly across the wafer surface.

[0052] FIG. 6 illustrates a top view of a wafer chuck assembly 600 comprising a plurality of mesas 602 distributed on a surface 604 of a wafer chuck 605 mounted on a pedestal 108 as shown, according to at least one embodiment. In at least one embodiment, the wafer chuck 605 may have a diameter D1 in the range of 100 mm to 300 mm. In at least one embodiment, the mesas 602 are substantially identical. In at least one embodiment, the mesas 602 may have a circular horizontal cross section, such as the mesas 302 described herein. In at least one embodiment, the mesas 602 have a logarithmic radial distribution. In at least one embodiment, the mesas 602 may be distributed along a plurality of concentric circles having a logarithmic radial spacing s4. In at least one embodiment, the concentric circles may be grouped into several annuli. Here, "annuli" may generally refer to a plurality of circular portions of the surface 604 extending between radii. The plural form of annulus is "annulus." In at least one embodiment, the logarithmic radial separation s4 may decrease substantially toward the periphery of the wafer chuck surface 604. In at least one embodiment, the distribution of the mesas 602 may be concentrated toward the periphery of the wafer chuck surface 604. In at least one embodiment, the periphery of a wafer clamped to the wafer chuck assembly 600 may have the largest contact area due to the concentrated distribution of the outermost mesas 602. In at least one embodiment, an inner region near the center of the wafer also has the lowest clamping force and a relatively smaller contact area due to a sparser distribution of the mesas 602. In at least one embodiment, the radial distribution of the contact surface may follow a parabolically increasing distribution of the clamping force on a wafer clamped to the wafer chuck 605.

[0053] In at least one embodiment, the angular distribution of the mesas 602 may be substantially symmetrical, as shown. In at least one embodiment, the mesas 602 may be repeated at 15 degree angular increments around the wafer chuck surface 604, forming a concentric distribution of mesas 602 along a logarithmic progression of radial distance. In at least one embodiment, at each radius, the mesas may have uniform angular spacing s5. In at least one embodiment, the spacing s5 may increase as the radial distance increases toward the periphery. In at least one embodiment, the mesas 602 near the periphery may be repeated at smaller angular increments. In at least one embodiment, the mesas 602 at the periphery may be repeated at 7.5 degree angular increments, as shown.

[0054] FIG. 7 illustrates a top view of a wafer chuck assembly 700 comprising a plurality of mesas 702 distributed on a surface 704 of a wafer chuck 705, according to at least one embodiment. In at least one embodiment, the wafer chuck 705 may be mounted on a pedestal 108, as shown. In at least one embodiment, the wafer chuck 705 may have a diameter D1 in the range of 100 mm to 300 mm. In at least one embodiment, the mesas 702 are substantially identical and have a circular horizontal cross-section of uniform diameter, as illustrated in FIG. 2. In at least one embodiment, the mesas 702 may have a polygonal horizontal cross-section.

[0055] In at least one embodiment, the mesas 702 are radially distributed with a logarithmic increasing progression. In at least one embodiment, the radial separation distance s6 may increase substantially logarithmically toward the periphery of the wafer chuck surface 704. In at least one embodiment, the number of mesas 702 per unit area may be concentrated toward the center of the wafer chuck surface 704 and decrease toward the periphery. In at least one embodiment, the clamping force may be stronger near the center of the clamped wafer. In at least one embodiment, if the height clearance (e.g., z-height h2 or h3) of the mesas 702 is small (e.g., less than 10 mils), a radial pressure difference may exist during operation of the vacuum pump. In at least one embodiment, the pressure near the center of the wafer chuck surface 704 is lower than the periphery, which may result in an increased clamping force near the center of the wafer substrate compared to the periphery.

[0056] In at least one embodiment, the mesas 702 may have a uniform angular distribution. For example, the mesas 702 may be uniformly repeated at 15 degree angular increments around the wafer chuck surface 704, as shown. In at least one embodiment, the spacing s7 between angularly adjacent mesas 702 may increase logarithmically toward the periphery.

[0057] FIG. 8 illustrates a top view of a wafer chuck assembly 800 including a plurality of mesas 802 distributed on a surface 804 of a wafer chuck 805, according to at least one embodiment. In at least one embodiment, the wafer chuck 805 may be mounted on a pedestal 108 as shown. In at least one embodiment, the wafer chuck 805 may have a diameter D1 in the range of 100 mm to 300 mm. In at least one embodiment, the mesas 802 are substantially cylindrical and have a circular horizontal cross section with a diameter D3. In at least one embodiment, D3 increases in a logarithmic progression toward the periphery. Here, "logarithmic progression" may generally refer to an increase in the diameter of the mesa that follows a logarithmic relationship with the radial position of the mesa. In at least one embodiment, doubling the distance of the mesa location from the center of the chuck surface corresponds to a 30% increase in the mesa diameter. In at least one embodiment, the mesas 802 are concentrically arranged with a uniform angular distribution with an angular increment between concentric mesas 802 of 15 degrees.

[0058] In at least one embodiment, the mesas 802 may be arranged along logarithmically spaced concentric circles with a logarithmic progression of center-to-center spacing s8. In at least one embodiment, s8 increases logarithmically toward the periphery. In at least one embodiment, the diameter D3 of the concentric mesas 802 increases in a logarithmic progression toward the periphery of the wafer chuck surface 804, as shown. In at least one embodiment, all mesas 802 having the same diameter D3 may be arranged on one concentric circle. Mesas having the same diameter D3 may be arranged along the concentric circles at gradually increasing radial distances. In at least one embodiment, a logarithmic progression in both the diameter D3 and the radial spacing s8 is performed, although other suitable nonlinear and / or linear relationships may be employed as well.

[0059] In at least one embodiment, the mesas 802 may have a uniform angular distribution around the wafer chuck surface 804. In at least one embodiment, the mesas may be repeated at 15 degree angular increments, resulting in a linear spacing s9 between adjacent mesas 802.

[0060] In at least one embodiment, the clamping load on the mesas 802 from the wafer substrate may increase parabolically (e.g., as the square of the wafer radius) toward the periphery. In at least one embodiment, the diameter D3 of the mesas 802 may be related to the area of ​​the contact surface 806, so that a logarithmic increase in contact area (e.g., a logarithmic progressive increase in diameter D3) may approximately track the parabolic increase in load. In at least one embodiment, the clamping load may be evenly distributed among the mesas 802. In at least one embodiment, the diameter D3 may be optimized to tune for a particular clamping load profile.

[0061] 9 is a top view of a wafer chuck assembly 900 according to at least one embodiment. In at least one embodiment, wafer chuck assembly 900 includes a plurality of mesas 902, 904, 906, 908, 910, and 911 distributed on a surface 912 of wafer chuck 901, which may be defined by a dashed circle. In at least one embodiment, wafer chuck 901 may be mounted on pedestal 108, as shown. In at least one embodiment, wafer chuck 901 may have a diameter D1 in the range of 100 mm to 300 mm.

[0062] In at least one embodiment, mesas 902-911 may be arranged in a tiled fashion on wafer chuck surface 912. The contact surfaces of mesas 902-911 are shown, according to at least one embodiment. In at least one embodiment, each mesa is separated from an adjacent mesa by a relatively narrow gap, as defined below. In at least one embodiment, the plurality of mesas may be divided into a first plurality of mesas, a second plurality of mesas, a third plurality of mesas, and a fourth plurality of mesas. In at least one embodiment, the first plurality of mesas constitutes a first subset that includes a collection of mesas 902. In at least one embodiment, the second plurality of mesas constitutes a second subset that includes a collection of mesas 904. In at least one embodiment, the third plurality of mesas constitutes a third subset that includes a collection of mesas 906. In at least one embodiment, the fourth plurality of mesas constitutes a fourth plurality that includes a collection of mesas 908, 910, and 911. In at least one embodiment, the first, second, third, and fourth subsets including mesas 902 , 904 , 906 , 908 , 910 , and 911 , respectively, may be distributed within concentric annular rings on the wafer chuck surface 912 .

[0063] In at least one embodiment, each mesa 902 may include sidewalls 914 and 915 extending along a first radial direction and a second radial direction, respectively. In at least one embodiment, the radial directions may be defined by polar coordinates r and q, where r is the radius and q is the angle, and may be repeated at substantially equal angular intervals q0, where q0 may range from 15 to 60 degrees. In at least one embodiment, the radial directions may generally be located at any angular location on the wafer chuck surface 912. Here, "radial directions" may generally refer to lines or directions extending along an imaginary radial line passing through the center of the wafer chuck surface 912. In at least one embodiment, the radial directions may be radial vectors having coordinates r and q, for example, extending from the center to the circumference of the wafer chuck surface.

[0064] In at least one embodiment, the sidewalls 914 and 915 extend a first radial distance between a center of the wafer chuck surface and a first radius R6. In at least one embodiment, the first and second radial directions may have a first angular separation on the wafer chuck surface, such as every 60 degrees around the wafer chuck surface 912, thereby including six mesas 902.

[0065] In at least one embodiment, each mesa 904 may include sidewalls 916 and 917 extending along a third radial direction and a fourth radial direction, respectively. In at least one embodiment, the third and fourth radial directions may have a second angular separation, e.g., repeated every 20 degrees around the wafer chuck surface 912. In at least one embodiment, the sidewalls 916 or 917 of every third mesa 904 may be aligned with the sidewalls 914 and 915 of each mesa 902. In at least one embodiment, the sidewalls 916 and 917 may extend over a second radial distance between radii R6 and R7, where the second radial distance is R7-R6.

[0066] In at least one embodiment, each mesa 906 can include sidewalls 918 and 919 extending along a fifth radial direction and a sixth radial direction, respectively. In at least one embodiment, the fifth and sixth radial directions can have a third angular separation, e.g., repeated every 20 degrees around the wafer chuck surface 912. In at least one embodiment, the sidewalls 918 and 919 can be aligned with the sidewalls 916 and 917 of the mesa 904. In at least one embodiment, the sidewalls 918 and 919 can extend over a third radial distance extending between radii R7 and R8, where the third radial distance is R8-R7.

[0067] In at least one embodiment, each mesa 908 may include a sidewall 920 extending along a seventh radial direction and a sidewall 921 extending along a first non-diametric chord 927, shown by a dashed line labeled 927. In at least one embodiment, the non-diametric chord 927 may extend at a first oblique angle relative to the seventh radial direction. Here, a "non-diametric chord" may generally refer to a chord of the circular wafer chuck surface 912 that extends at an oblique angle relative to any radial direction that passes through the center of the wafer chuck surface 912. In at least one embodiment, the non-diametric chord does not pass through the center of the wafer chuck surface 912. In at least one embodiment, the sidewalls 920 and 921 may extend over a fourth radial distance that extends between radii R8 and R9, where the fourth radial distance is R9-R8. R9 may extend substantially from the center of the wafer chuck surface 912 to the circumference of the wafer chuck surface 912.

[0068] In at least one embodiment, each mesa 910 may include a sidewall 922 extending along an eighth radial direction and a sidewall 923 extending along a second non-diametric chord 929, shown by the dashed line labeled 929. In at least one embodiment, the non-diametric chord 929 may extend at a second oblique angle relative to the eighth radial direction. In at least one embodiment, the second non-diametric chord 929 may be reflected across a mirrored surface to a first non-diametric chord 927, where the first oblique angle may be equal to the second oblique angle relative to the mirrored surface that cuts a diameter of the wafer chuck surface 912. In at least one embodiment, like sidewalls 920 and 921, sidewalls 922 and 923 may also extend over a fourth radial distance extending between radii R8 and R9, where the fourth radial distance is R9-R8. In at least one embodiment, due to the symmetry of first and second non-diameter chords 927 and 929, mesas 908 and 910 can be mirror images of one another.

[0069] In at least one embodiment, each mesa 911 is a triangular tile sandwiched between mesas 908 and 910. In at least one embodiment, each mesa 911 may include a sidewall 924 that extends along a first non-diametric chord 927 and may be adjacent to and parallel to sidewall 921 of mesa 908. In at least one embodiment, mesa 911 may also include a sidewall 925 that extends along a second non-diametric chord 929 and may be adjacent to and parallel to sidewall 922 of mesa 910. In at least one embodiment, sidewalls 924 and 925 may be seen to intersect at a radius R8 and diverge along non-diametric chords 927 and 929. In at least one embodiment, sidewalls 924 and 925 also extend between radii R8 and R9.

[0070] In at least one embodiment, mesas 902-911 may include leading edges 926, 928, 930, 932, 934, and 936 corresponding to mesas 902, 904, 906, 908, 910, and 911, respectively. In at least one embodiment, leading edges 926, 928, 930, 932, 934, and 936 may trace concentric circular arcs at increasing radial distances R6, R7, R8, and R9, as shown.

[0071] 9 is a cross-sectional view through adjacent mesas 906a and 906b, showing sidewalls 918 and 919 spaced apart by spacing distance g2, according to at least one embodiment. In at least one embodiment, mesas 906a and 906b include sloped, blunt upper edges 936 and 938. In other embodiments, upper edges 936 and 938 may be rounded. In at least one embodiment, all of mesas 902-911 may include blunt upper edges similar or identical to upper edges 936 and 938.

[0072] FIG. 10 is a cross-sectional view of a wafer processing apparatus 1000 according to at least one embodiment. In at least one embodiment, the wafer processing apparatus 1000 includes a wafer chuck assembly 100 in a wafer processing chamber 1002. Here, the term "wafer processing chamber" may generally refer to a high vacuum chamber into which a wafer substrate may be loaded for processing operations. In at least one embodiment, the wafer processing chamber may include components such as a wafer chuck for holding the wafer substrate. In at least one embodiment, the wafer processing chamber 1002 may include an antechamber (not shown) into which the wafer substrate 122 may be loaded. In at least one embodiment, the wafer processing chamber 1002 may include a lid that may be opened and closed to load and unload the wafer substrate 122. Here, the term "wafer processing apparatus" generally refers to a semiconductor processing tool that includes a vacuum chamber into which a wafer substrate may be placed for processing.

[0073] In at least one embodiment, the wafer chuck 106 may be mounted on a pedestal 108. In at least one embodiment, the wafer chuck surface 104 may comprise, for example, a mesa 102. In at least one embodiment, any of the mesas 202, 302, 402, 502, 602, 702, and 802 disclosed above may be similarly employed. In at least one embodiment, the mesas 102 are distributed on the wafer chuck surface 104. In at least one embodiment, the wafer substrate 122 may be mounted on the wafer chuck assembly 100 as shown. In at least one embodiment, the wafer backside 120 may contact the mesa 102. In at least one embodiment, the mesa includes a contact surface 118 that may contact at least 20% of the area of ​​the wafer backside 120. In at least one embodiment, the wafer chuck assembly 100 may comprise an electrode 1004 embedded within the wafer chuck surface for electrostatic clamping (ESC) of the wafer substrate 122 to the mesa 102. Here, an "electrode" may generally refer to a metal structure electrically coupled to a voltage source or power source. In at least one embodiment, an "electrode" may be a contact electrode for sparking and maintaining a plasma or a clamping electrode for electrostatically clamping a wafer on the wafer chuck. In at least one embodiment, the wafer chuck assembly 100 may alternatively include one or more vacuum ports 1006 for vacuum clamping the wafer substrate 122 to the mesa 102. In at least one embodiment, the mesa 102 may contact at least a threshold percentage (e.g., at least 3%) of the wafer backside 120.

[0074] FIG. 11 illustrates a flow chart 1100 summarizing an exemplary method for using the wafer processing apparatus 1000, according to at least one embodiment. In at least one embodiment, in operation 1102, a wafer substrate (e.g., wafer substrate 122) is mounted in a processing chamber comprising a wafer chuck assembly (e.g., wafer chuck assembly 100 in wafer processing chamber 1002). In at least one embodiment, the wafer may be mounted on a wafer chuck surface comprising a plurality of mesas (e.g., mesas 102 distributed on the wafer chuck surface 104). In at least one embodiment, the wafer has a structured layer, or a thin film of dielectric or photoresist, on the wafer backside or wafer side that may be contacted by the plurality of mesas. In at least one embodiment, the plurality of mesas may contact at least 3% (e.g., 3%-90%) of the wafer substrate. In at least one embodiment, the plurality of mesas may be distributed on the wafer chuck surface to evenly distribute the clamping force. In at least one embodiment, such distribution may reduce pressure on the individual mesas due to the clamped wafer below a threshold level.

[0075] In at least one embodiment, in operation 1104, the wafer substrate may be electrostatically clamped by an ESC chuck as described above or by a vacuum applied to ports in the wafer chuck surface. In at least one embodiment, the clamping force may be controlled by adjusting the voltage on the ESC electrodes or by adjusting the pressure differential between the wafer chuck surface below the wafer substrate and the top surface of the wafer substrate.

[0076] The following examples are provided to illustrate at least one embodiment, which may be combined with at least one other embodiment without changing the scope of the at least one embodiment.

[0077] Example 1: A wafer chuck assembly comprising: a wafer chuck including a surface having a substantially circular shape, the surface having a center and a first area; and a plurality of mesas distributed on the surface of the wafer chuck, each mesa of the plurality of mesas extending to a height above the surface of the wafer chuck, each mesa of the plurality of mesas comprising a contact surface, and a second area substantially equal to a sum of the areas of the contact surfaces of each mesa of the plurality of mesas being at least 3% of the first area.

[0078] Example 2: The wafer chuck assembly of example 1, wherein each mesa of the plurality of mesas comprises at least one leading edge that is rounded or beveled.

[0079] Example 3: The wafer chuck assembly of Example 1, wherein the second area is between 3% and 90% of the first area.

[0080] Example 4: The wafer chuck assembly of Example 1, wherein the height is 0.01 mm to 0.25 mm.

[0081] Example 5: The wafer chuck assembly of Example 1, wherein each mesa of the plurality of mesas comprises a substantially circular or polygonal cross-section.

[0082] Example 6: The wafer chuck assembly of example 5, wherein each mesa of the plurality of mesas has a substantially equal diameter.

[0083] Example 7: The wafer chuck assembly of Example 5, wherein a diameter of each individual mesa of the plurality of mesas increases with increasing radial distance along the surface.

[0084] Example 8: The wafer chuck assembly of Example 8, wherein each mesa of the plurality of mesas includes a substantially polygonal cross-section in plan view, and each mesa of the plurality of mesas has substantially equal peripheral dimensions.

[0085] Example 9: The wafer chuck assembly of Example 9, wherein the substantially polygonal planar cross section is substantially hexagonal.

[0086] Example 10: The wafer chuck assembly of Example 10, wherein the individual mesas of the plurality of mesas are arranged in a dense distribution on the surface, and adjacent individual mesas of the plurality of mesas have substantially equal distances between adjacent individual mesas of the plurality of mesas.

[0087] Example 11: The wafer chuck assembly of example 10, wherein the distance between adjacent individual mesas of the plurality of mesas increases with increasing radial distance along the surface.

[0088] Example 12: The wafer chuck assembly of Example 12, wherein the radial distribution of the number per unit area of ​​individual mesas of the plurality of mesas decreases from the center toward the periphery of the surface.

[0089] Example 13: The wafer chuck assembly of example 10, wherein the distance between adjacent individual mesas of the plurality of mesas decreases with increasing radial distance along the surface.

[0090] Example 14: The wafer chuck assembly of Example 14, wherein the radial distribution of the number per unit area of ​​the individual mesas on the surface increases from the center to the periphery of the surface.

[0091] Example 15: The wafer chuck assembly of Example 1, wherein each mesa of the plurality of mesas comprises a wedge having a first sidewall extending from a central region of the surface to a peripheral edge of the surface and a second sidewall extending from the central region to the peripheral edge of the surface, and wherein the first sidewall of the first individual mesa of the plurality of mesas is adjacent to the second sidewall of the second individual mesa of the plurality of mesas.

[0092] Example 16: The wafer chuck assembly of Example 1, wherein a first individual mesa of the plurality of mesas is a first linear mesa distributed in a first polar geometric arrangement on the surface, and each mesa of the first linear mesa extends a first radial distance along a first radial direction on the surface, and the first radial distance extends from substantially a center of the surface to substantially a periphery of the surface.

[0093] Example 17: The wafer chuck assembly of Example 1, wherein a first individual mesa of the plurality of mesas is a first linear mesa distributed in a first polar geometric arrangement on the surface, and each mesa of the first linear mesa extends a first radial distance along a first radial direction on the surface, and the first radial distance extends from substantially a center of the surface to substantially a periphery of the surface.

[0094] Example 18: The wafer chuck assembly of Example 16, wherein a second individual mesa of the plurality of mesas is a second linear mesa distributed in a second polar geometric arrangement on the surface, and the individual mesas of the second linear mesa extend a second radial distance along a second radial direction on the surface, and the second radial distance extends substantially between the first radial distance and substantially between a periphery of the surface, and the second radial distance is shorter than the first radial distance.

[0095] Example 19: The wafer chuck assembly of Example 18, wherein the third linear mesa is between the first linear mesa and the second linear mesa.

[0096] Example 20: The wafer chuck assembly of Example 19, wherein the individual mesas of the first linear mesa are spaced apart from one another at a first angle, the individual mesas of the second linear mesa are spaced apart from one another at a second angle, and the individual mesas of the third linear mesa are spaced apart from one another at a third angle.

[0097] Example 21: The wafer chuck assembly of Example 20, wherein the first angle is substantially equal to the second angle, and the second angle is substantially equal to the third angle.

[0098] Example 22: The wafer chuck assembly of Example 1, wherein the first plurality of mesas includes a first subset of the plurality of mesas, each mesa of the first plurality of mesas includes a first sidewall and a second sidewall, the first sidewall extends along a first radial direction on the surface, the second sidewall extends along a second radial direction on the surface, and the first sidewall and the second sidewall extend between a first radial distance from a center of the surface.

[0099] Example 23: The wafer chuck assembly of Example 22, wherein the second plurality of mesas includes a second subset of the plurality of mesas, each mesa of the second plurality of mesas includes a third sidewall and a fourth sidewall, the third sidewall extends along a third radial direction on the surface, the fourth sidewall extends along a fourth radial direction on the surface, and the third sidewall and the fourth sidewall extend between the first radial distance and the second radial distance.

[0100] Example 24: The wafer chuck assembly of Example 23, wherein the third plurality of mesas includes a third subset of the plurality of mesas, each mesa of the third plurality of mesas includes a fifth sidewall and a sixth sidewall, the fifth sidewall extends along a fifth radial direction on the surface, the sixth sidewall extends along a sixth radial direction on the surface, and the fifth sidewall and the sixth sidewall extend between the second radial distance and the third radial distance.

[0101] Example 25: The wafer chuck assembly of example 24, wherein the fourth plurality of mesas includes a fourth subset of the plurality of mesas, a first individual mesa of the fourth subset of mesas includes a seventh sidewall extending along a seventh radial direction and an eighth sidewall extending along a first non-diametric chord of the surface, the first non-diametric chord extending at a first oblique angle relative to the seventh radial direction, and the seventh and eighth sidewalls extend between a third radial distance and a fourth radial distance, and a second individual mesa of the fourth subset of mesas includes a ninth sidewall extending along the eighth radial direction and a tenth sidewall extending along a second non-diametric chord of the surface, the second non-diametric chord extending at a first oblique angle relative to the seventh radial direction, and the seventh and eighth sidewalls extend between a third radial distance and a fourth radial distance. a tenth sidewall extending at a second oblique angle relative to the radial direction, and the ninth and tenth sidewalls extending between a third radial distance and a fourth radial distance, and a third individual mesa of the fourth subset of mesas between the first individual mesa and the second individual mesa of the mesas, the third individual mesa of the fourth subset of mesas including an eleventh sidewall adjacent to and parallel to the eighth sidewall, and a twelfth sidewall adjacent to and parallel to the tenth sidewall, the eleventh sidewall and the twelfth sidewall intersecting at a third radius and extending to a fourth radius.

[0102] Example 26: A wafer processing apparatus comprising: a wafer processing chamber with a wafer chuck assembly, the wafer chuck assembly comprising: a wafer chuck including a wafer chuck surface having a substantially circular shape, the wafer chuck surface having a first area; and a plurality of mesas distributed on the wafer chuck surface, each mesa of the plurality of mesas extending to a height above the wafer chuck surface, and each mesa of the plurality of mesas including a second area that is at least about a threshold percentage of the first area.

[0103] Example 27: The wafer processing apparatus of Example 26, wherein the wafer chuck comprises one or more electrodes operable to electrostatically clamp the wafer substrate to the wafer chuck.

[0104] Example 28: The wafer processing apparatus of Example 26, wherein the wafer chuck comprises one or more vacuum ports operable to vacuum clamp the wafer substrate to the wafer chuck.

[0105] Example 29: A method of using a wafer processing apparatus, the method including: mounting a wafer substrate on a wafer chuck including a wafer chuck surface having a substantially circular shape, the wafer chuck surface having a first area and a plurality of mesas distributed on the wafer chuck surface, the plurality of mesas having a second area that is at least about a threshold percentage of the first area; and clamping the wafer substrate to the wafer chuck surface, wherein each mesa of the plurality of mesas contacts at least a threshold percentage of the mesas of a surface of the wafer such that pressure exerted by the clamped wafer substrate on each mesa of the mesas is less than a threshold pressure.

[0106] Example 30: The method of example 29, wherein the threshold percentage of the first area of ​​the wafer chuck surface is between 3% and 90%.

[0107] Example 31: The method of example 29, wherein clamping the wafer substrate to the wafer chuck surface includes electrostatically clamping the wafer substrate to the wafer chuck surface.

[0108] Example 32: The method of example 29, wherein clamping the wafer substrate to the wafer chuck surface includes vacuum clamping the wafer substrate to the wafer chuck surface.

Claims

1. 1. A wafer chuck assembly comprising: a wafer chuck including a surface having a substantially circular shape, the surface having a center and a first area; a plurality of mesas distributed on the surface of the wafer chuck; each mesa of the plurality of mesas extends to a height above the surface of the wafer chuck; each of the plurality of mesas includes a contact surface; and a plurality of mesas, a second area substantially equal to a sum of the areas of the contact surfaces of the individual mesas of the plurality of mesas being at least 3% of the first area; A wafer chuck assembly comprising:

2. 2. The wafer chuck assembly of claim 1, a wafer chuck assembly, wherein each mesa of the plurality of mesas includes at least one leading edge that is rounded or sloped.

3. 2. The wafer chuck assembly of claim 1, The second area is between 3% and 90% of the first area.

4. 2. The wafer chuck assembly of claim 1, The wafer chuck assembly, wherein the height is between 0.01 mm and 0.25 mm.

5. 2. The wafer chuck assembly of claim 1, A wafer chuck assembly, wherein each mesa of the plurality of mesas comprises a substantially circular or polygonal cross-section.

6. 6. The wafer chuck assembly of claim 5, the individual mesas of the plurality of mesas having substantially equal diameters.

7. 6. The wafer chuck assembly of claim 5, A wafer chuck assembly, wherein a diameter of each of the plurality of mesas increases with increasing radial distance along the surface.

8. 8. The wafer chuck assembly of claim 7, each of the plurality of mesas includes a substantially polygonal plan cross-section; and a wafer chuck assembly, wherein the individual mesas of the plurality of mesas have substantially equal peripheral dimensions.

9. 9. The wafer chuck assembly of claim 8, A wafer chuck assembly, wherein the substantially polygonal plan cross-section is substantially hexagonal.

10. 10. The wafer chuck assembly of claim 9, the individual mesas of the plurality of mesas are disposed in a dense distribution on the surface; and a wafer chuck assembly, wherein adjacent ones of the plurality of mesas have substantially equal distances between adjacent ones of the plurality of mesas.

11. 11. The wafer chuck assembly of claim 10, A wafer chuck assembly, wherein the distance between adjacent mesas of the plurality of mesas increases with increasing radial distance along the surface.

12. 12. The wafer chuck assembly of claim 11, a radial distribution of the number per unit area of ​​individual mesas of the plurality of mesas decreases from the center toward the periphery of the surface.

13. 11. The wafer chuck assembly of claim 10, A wafer chuck assembly, wherein the distance between adjacent mesas of the plurality of mesas decreases with increasing radial distance along the surface.

14. 14. The wafer chuck assembly of claim 13, A wafer chuck assembly, wherein a radial distribution of the number per unit area of ​​individual mesas on a surface increases from the center toward the periphery of said surface.

15. 2. The wafer chuck assembly of claim 1, the individual mesas of the plurality of mesas include a wedge shape; the wedge comprises a first sidewall extending from a central region of the surface to a periphery of the surface, and a second sidewall extending from the central region to the periphery of the surface; and a first sidewall of a first individual mesa of the plurality of mesas adjacent a second sidewall of a second individual mesa of the plurality of mesas.

16. 2. The wafer chuck assembly of claim 1, a first individual mesa of the plurality of mesas being first linear mesas distributed in a first polar geometry on the surface; each mesa of the first linear mesa extends a first radial distance along a first radial direction on the surface; and the first radial distance extends from substantially a center of the surface to substantially a periphery of the surface.

17. 17. The wafer chuck assembly of claim 16, second individual mesas of the plurality of mesas are second linear mesas distributed in a second polar geometry on the surface; each mesa of the second linear mesa extends a second radial distance along a second radial direction on the surface; and the second radial distance extends substantially between the first radial distance and substantially the periphery of the surface; and The second radial distance is less than the first radial distance.

18. 20. The wafer chuck assembly of claim 17, comprising: a third individual mesa of the plurality of mesas is a third linear mesa distributed in a third polar geometry on the surface; each mesa of the third linear mesa extends a third radial distance along a third radial direction on the surface; and the third radial distance extends substantially between the second radial distance and substantially the periphery of the surface; and the third radial distance is less than the first radial distance and the second radial distance.

19. 20. The wafer chuck assembly of claim 18, wherein the third linear mesa is between the first linear mesa and the second linear mesa.

20. 20. The wafer chuck assembly of claim 19, the individual mesas of the first linear mesa are spaced apart from one another at a first angle; the individual mesas of the second linear mesa are spaced apart from one another at a second angle; and the individual mesas of the third linear mesa being spaced apart from one another at a third angle.

21. 21. The wafer chuck assembly of claim 20, the first angle being substantially equal to the second angle, and the second angle being substantially equal to the third angle.

22. 2. The wafer chuck assembly of claim 1, wherein a first plurality of mesas comprises a first subset of the plurality of mesas; each mesa of the first plurality of mesas includes a first sidewall and a second sidewall; the first sidewall extends along a first radial direction on the surface; the second sidewall extends along a second radial direction on the surface; and the first sidewall and the second sidewall extend a first radial distance from a center of the surface.

23. 23. The wafer chuck assembly of claim 22, wherein a second plurality of mesas comprises a second subset of the plurality of mesas; each mesa of the second plurality of mesas includes a third sidewall and a fourth sidewall; the third sidewall extends along a third radial direction on the surface; the fourth sidewall extends along a fourth radial direction on the surface; and the third sidewall and the fourth sidewall extend between the first radial distance and the second radial distance.

24. 24. The wafer chuck assembly of claim 23, wherein a third plurality of mesas comprises a third subset of the plurality of mesas; each mesa of the third plurality of mesas includes a fifth sidewall and a sixth sidewall; the fifth sidewall extends along a fifth radial direction on the surface; the sixth sidewall extends along a sixth radial direction on the surface; and the fifth sidewall and the sixth sidewall extend between the second radial distance and a third radial distance.

25. 25. The wafer chuck assembly of claim 24, wherein a fourth plurality of mesas comprises a fourth subset of the plurality of mesas; A first individual mesa of the fourth subset of mesas comprises: a seventh sidewall extending along a seventh radial direction; an eighth sidewall extending along a first non-diametric chord of the surface, the first non-diametric chord extending at a first oblique angle relative to the seventh radial direction, and the seventh sidewall and the eighth sidewall extending between the third radial distance and a fourth radial distance; and A second individual mesa of the fourth subset of mesas comprises: a ninth sidewall extending along an eighth radial direction; and a tenth sidewall extending along a second non-diametric chord of the surface, the second non-diametric chord extending at a second oblique angle relative to the ninth radial direction, and the ninth sidewall and the tenth sidewall extending between the third radial distance and the fourth radial distance; and a third individual mesa of a fourth subset of mesas between the first individual mesa and the second individual mesa of mesas, the third individual mesa of the fourth subset of mesas comprising: an eleventh sidewall, the eleventh sidewall being adjacent to and parallel to the eighth sidewall; a twelfth sidewall, the twelfth sidewall being adjacent to and parallel to the tenth sidewall, the eleventh sidewall and the twelfth sidewall intersecting at the third radius and extending to the fourth radius; Including, Wafer chuck assembly.

26. 1. A wafer processing apparatus comprising: a wafer processing chamber having a wafer chuck assembly; The wafer chuck assembly includes: a wafer chuck including a wafer chuck surface having a substantially circular shape, the wafer chuck surface having a first area; a plurality of mesas distributed on a surface of the wafer chuck, each mesa of the plurality of mesas extends to a height above the wafer chuck surface; and a plurality of mesas, the plurality of mesas including a second area that is at least about a threshold percentage of the first area; Equipped with Wafer processing equipment.

27. 27. The wafer processing apparatus of claim 26, The wafer processing apparatus, wherein the wafer chuck comprises one or more electrodes operable to electrostatically clamp a wafer substrate to the wafer chuck.

28. 27. The wafer processing apparatus of claim 26, The wafer processing apparatus, wherein the wafer chuck comprises one or more vacuum ports operable to vacuum clamp a wafer substrate to the wafer chuck.

29. 1. A method for using a wafer processing apparatus, comprising: mounting a wafer substrate on a wafer chuck including a wafer chuck surface having a substantially circular shape, the wafer chuck surface having a first area and a plurality of mesas distributed on the wafer chuck surface, the plurality of mesas having a second area that is at least about a threshold percentage of the first area; clamping the wafer substrate to the wafer chuck surface such that each mesa of the plurality of mesas contacts at least the threshold percentage of mesas on a surface of the wafer such that pressure exerted by the clamped wafer substrate on each mesa of the plurality of mesas is less than a threshold pressure; A method comprising:

30. 30. The method of claim 29, wherein the threshold percentage of the first area of ​​the wafer chuck surface is between 3% and 90%.

31. 30. The method of claim 29, wherein clamping the wafer substrate to the wafer chuck surface comprises electrostatically clamping the wafer substrate to the wafer chuck surface.

32. 30. The method of claim 29, wherein clamping the wafer substrate to the wafer chuck surface comprises vacuum clamping the wafer substrate to the wafer chuck surface.

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