MEMORY DEVICE AND METHODS FOR FORMING SAME - Patent application

Abstract

The memory device includes a memory array structure and a peripheral structure. The memory array structure includes at least one memory bank, each memory bank including a plurality of memory blocks. The peripheral structure includes word line driver circuitry and sense amplifier circuitry. A first area including the word line driver circuitry and sense amplifier circuitry at least partially overlaps a second area including the memory blocks in a plan view of the memory device.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application Publication No. PCT / CN2023 / 109534, filed July 27, 2023, which claims the benefit of priority to U.S. Provisional Application No. 63 / 436,430, filed December 30, 2022, both of which are incorporated by reference in their entireties herein.

[0002] The present disclosure relates to memory devices and methods for fabricating the same. [Background technology]

[0003] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as memory cell feature sizes approach lower limits, planar processes and fabrication techniques become difficult and expensive. As a result, the memory density of planar memory cells approaches upper limits.

[0004] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. 3D memory architectures include a memory array and peripheral circuitry to support the operation of the memory array. Summary of the Invention [Means for solving the problem]

[0005] In one aspect, a memory device is disclosed. The memory device includes a memory array structure and a peripheral structure. The memory array structure includes at least one memory bank, each memory bank including a plurality of memory blocks. The peripheral structure includes word line driver circuits and sense amplifier circuits. A first area including the word line driver circuits and sense amplifier circuits at least partially overlaps a second area including the memory blocks in a plan view of the memory device.

[0006] In some implementations, the first area includes a first sub-area that includes word line driver circuitry and a second sub-area that includes sense amplifier circuitry, the first sub-area and the second sub-area being interleaved in the first area.

[0007] In some implementations, the first area includes two first sub-areas and two second sub-areas, where the two first sub-areas are disposed at diagonal corners of the first area, and the two second sub-areas are disposed at diagonal corners of the first area.

[0008] In some implementations, the first area completely overlaps the second area in a floor plan of the memory device.

[0009] In some implementations, the word line driver circuitry in one of the two first sub-areas is coupled to odd-numbered word lines in the memory block, and the word line driver circuitry in the other of the two first sub-areas is coupled to even-numbered word lines in the memory block.

[0010] In some implementations, the first area includes a first sub-area including a word line driver circuit and two second sub-areas each including a sense amplifier circuit, the two second sub-areas being disposed on two sides of the first sub-area.

[0011] In some implementations, the sense amplifier circuitry in one of the two second sub-areas is shared by two adjacent memory blocks.

[0012] In some implementations, the sense amplifier circuits in the two second sub-areas are coupled to word lines in the memory block.

[0013] In some implementations, the sense amplifier circuitry in one of the two second sub-areas is coupled to odd-numbered word lines in the memory block and odd-numbered word lines in the first adjacent memory block, and the sense amplifier circuitry in the other of the two second sub-areas is coupled to even-numbered word lines in the memory block and even-numbered word lines in the second adjacent memory block.

[0014] In some implementations, the word line driver circuits in the first sub-area are coupled to odd-numbered word lines or even-numbered word lines in the memory block.

[0015] In some implementations, the word line driver circuits in the first sub-area are coupled to odd-numbered word lines or even-numbered word lines in adjacent memory blocks.

[0016] In some implementations, the first area includes a first sub-area including word line driver circuitry, a second sub-area including sense amplifier circuitry, and a third sub-area including decoder circuitry, the first sub-area being disposed between adjacent memory blocks in a plan view of the memory device, and the second sub-area and the third sub-area overlapping with a second area of ​​the memory block in the plan view of the memory device.

[0017] In some implementations, the first area further includes a fourth sub-area including control circuitry for the sense amplifier circuitry, the fourth sub-area being disposed between the second sub-area and the third sub-area.

[0018] In some implementations, the second sub-area, the third sub-area, and the fourth sub-area overlap with the second area of ​​the memory block in a floor plan of the memory device.

[0019] In some implementations, the first area includes a first sub-area including word line driver circuitry and two second sub-areas each including sense amplifier circuitry, the first sub-area being disposed between adjacent memory blocks in a plan view of the memory device, and the two second sub-areas overlapping with second areas of the memory blocks in the plan view of the memory device.

[0020] In some implementations, the first area further includes a third sub-area including control circuitry for the sense amplifier circuitry, the third sub-area being disposed between the two second sub-areas.

[0021] In some implementations, the memory array structure is disposed on a first substrate and the peripheral structure is disposed on a second substrate that is different from the first substrate.

[0022] In some implementations, a memory array structure disposed on a first substrate is bonded to a peripheral structure disposed on a second substrate.

[0023] In some implementations, the memory array structure includes dynamic random access memory (DRAM).

[0024] In another aspect, a memory device is disclosed. The memory device includes a memory array structure and a peripheral structure. The memory array structure is disposed on a first substrate including at least one memory bank, each memory bank including a plurality of memory blocks. The peripheral structure is disposed on a second substrate different from the first substrate including a sense amplifier circuit and a word line driver circuit. The sense amplifier circuit overlaps with the memory blocks in a plan view of the memory device.

[0025] In some implementations, the word line driver circuitry is disposed between adjacent memory blocks in a floor plan of the memory device.

[0026] In some implementations, the peripheral structure further includes decoder circuitry that overlaps with the memory blocks in a floor plan of the memory device.

[0027] In some implementations, the peripheral structure further includes control circuitry for the sense amplifier circuitry that overlaps with the memory blocks in a floor plan of the memory device.

[0028] In some implementations, the word line driver circuitry overlaps with the memory blocks in the floor plan of the memory device.

[0029] In some implementations, the sense amplifier circuitry includes a first sub-area and a second sub-area disposed on two sides of the word line driver circuitry in a plan view of the memory device.

[0030] In some implementations, the sense amplifier circuitry includes a first sub-area and a second sub-area, and the word line driver circuitry includes a third sub-area and a fourth sub-area, the first sub-area and the third sub-area being disposed at diagonal corners that overlap with the memory blocks in a plan view of the memory device, and the second sub-area and the fourth sub-area being disposed at diagonal corners that overlap with the memory blocks in a plan view of the memory device.

[0031] In some implementations, the memory array structure includes dynamic random access memory (DRAM).

[0032] In yet another aspect, a method for forming a memory device is disclosed. A memory array structure is formed in a first substrate. The memory array structure includes at least one memory bank, each memory bank including a plurality of memory blocks. A peripheral structure is formed in a second substrate different from the first substrate. The peripheral structure includes word line driver circuitry and sense amplifier circuitry. The memory array structure and the peripheral structure are joined to at least partially overlap the word line driver circuitry and sense amplifier circuitry with the memory blocks in a plan view of the memory device.

[0033] In some implementations, the word line driver circuitry is formed in a first sub-area and the sense amplifier circuitry is formed in a second sub-area.

[0034] In some implementations, the first sub-area and the second sub-area are disposed at diagonal corners of the memory block in a plan view of the memory device.

[0035] In some implementations, the word line driver circuitry is formed in the first sub-area and the sense amplifier circuitry is formed in the second and third sub-areas.

[0036] In some implementations, the second sub-area and the third sub-area are disposed on two sides of the first sub-area in a plan view of the memory device.

[0037] In some implementations, the first sub-area is disposed between adjacent memory blocks in a floor plan of the memory device, and the second sub-area and the third sub-area overlap the memory blocks in a floor plan of the memory device.

[0038] In some implementations, the word line driver circuitry is formed in a first sub-area, the sense amplifier circuitry is formed in a second sub-area, and the decoder circuitry is formed in a third sub-area.

[0039] In some implementations, the first sub-area is disposed between adjacent memory blocks in a floor plan of the memory device, and the second sub-area and the third sub-area overlap the memory blocks in a floor plan of the memory device.

[0040] In yet another aspect, a system is disclosed. The system includes a memory device and a memory controller coupled to the memory device. The memory device includes a memory array structure and a peripheral structure. The memory array structure includes at least one memory bank, each memory bank including a plurality of memory blocks. The peripheral structure includes word line driver circuits and sense amplifier circuits. A first area including the word line driver circuits and sense amplifier circuits at least partially overlaps a second area including the memory blocks in a plan view of the memory device. The memory controller is configured to control operation of the memory array structure through the peripheral structure.

[0041] In yet another aspect, a system is disclosed. The system includes a memory device and a memory controller coupled to the memory device. The memory device includes a memory array structure and a peripheral structure. The memory array structure is disposed on a first substrate including at least one memory bank, each memory bank including a plurality of memory blocks. The peripheral structure is disposed on a second substrate different from the first substrate including a sense amplifier circuit and a word line driver circuit. The sense amplifier circuit overlaps with the memory blocks in a plan view of the memory device. The memory controller is configured to control operation of the memory array structure through the peripheral structure.

[0042] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable those skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0043] [Figure 1A] 1 is a schematic diagram of a cross section of a memory device according to some aspects of the present disclosure. [Figure 1B] 1 is a schematic diagram of a cross section of another memory device in accordance with some aspects of the present disclosure. [Diagram 2]FIG. 2 is a schematic diagram of a memory device including peripheral circuitry and an array of memory cells each having a vertical transistor, in accordance with some aspects of the present disclosure. [Diagram 3] FIG. 1 is a schematic circuit diagram of a memory device including peripheral circuitry and an array of dynamic random access memory (DRAM) cells in accordance with some aspects of the disclosure. [Figure 4] 1 is a schematic circuit diagram of a memory device including peripheral circuitry and an array of phase change memory (PCM) cells in accordance with some aspects of the present disclosure. [Diagram 5] FIG. 1 is a schematic perspective view of a memory device according to some aspects of the present disclosure. [Figure 6] 1 is a schematic plan view of a memory device according to some aspects of the present disclosure. [Figure 7] FIG. 2 is a schematic diagram of an arrangement of memory devices in accordance with some aspects of the present disclosure. [Figure 8] 2 is a schematic diagram of a word line driver circuit of a memory device in accordance with some aspects of the present disclosure. [Figure 9] 2 is a schematic diagram of a sense amplifier circuit of a memory device in accordance with some aspects of the present disclosure. [Figure 10] 1 is a schematic plan view of a memory device according to some aspects of the present disclosure. [Figure 11] FIG. 2 is a schematic diagram of an arrangement of memory devices in accordance with some aspects of the present disclosure. [Figure 12] 1 is a schematic diagram of a sense amplifier circuit of a memory device in accordance with some aspects of the present disclosure. [Figure 13] 1 is a schematic plan view of a memory device according to some aspects of the present disclosure. [Figure 14] 1 is a schematic diagram of a connection circuit for a memory device according to some aspects of the present disclosure. [Figure 15] 1 is a schematic plan view of a memory device according to some aspects of the present disclosure. [Figure 16] FIG. 2 is a schematic plan view of peripheral circuitry in accordance with some aspects of the present disclosure. [Figure 17]2 is a schematic diagram of a decoder and control logic of a memory device in accordance with some aspects of the present disclosure. [Figure 18] 1 is a flowchart of a method for forming a memory device according to some aspects of the present disclosure. [Figure 19] FIG. 1 is a block diagram of an example system having a memory device in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] The present disclosure will be described with reference to the accompanying drawings.

[0045] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of the present disclosure. The present disclosure may also be utilized in various other applications. The functional and structural features as described in the present disclosure may be combined, coordinated, and modified with one another in ways not specifically shown in the drawings, such that such combinations, coordination, and modifications are within the scope of the present disclosure.

[0046] Generally, terms may be understood at least in part from their usage in context. For example, the term "one or more" may be used herein to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey a singular use or to convey a plural use, depending at least in part on the context. In addition, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may instead allow for the presence of additional factors, also not necessarily expressly described, depending at least in part on the context.

[0047] It should be readily understood that the meanings of "on," "above," and "over" in this disclosure should be interpreted most broadly, such that "on" does not only mean "directly on" something, but also includes the meaning of "on" something with an intermediate thing or layer in between, and such that "on" or "covering" does not only mean "on" something or "covering" it, but can also include the meaning of "on" something or "covering" it without an intermediate thing or layer in between (directly on something).

[0048] Additionally, spatial relationship terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or thing to another element or thing as depicted in the figures. The spatial relationship terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein may be interpreted accordingly.

[0049] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself may be patterned. Materials added onto the substrate may be patterned or left unpatterned. Additionally, substrates may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, substrates may be made from non-conductive materials, such as glass, plastic, or sapphire wafers.

[0050] As used herein, the term "layer" refers to a portion of material that includes a region of thickness. A layer may extend over the entirety of an underlying or overlapping structure, or may have an extent that is less than the extent of the underlying or overlapping structure. Additionally, a layer may be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal surfaces between the top and bottom surfaces of a continuous structure, or on the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers within, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0051] In memory cells of some memory devices, such as DRAM, PCM, and ferroelectric DRAM (FRAM®), transistors are used as switches or selection devices. However, planar transistors commonly used in existing memory cells usually have a horizontal structure, with word lines embedded in a substrate and bit lines above the substrate. The source and drain of the planar transistor are laterally disposed at different positions, which increases the area occupied by the transistor. This design of the planar transistor also complicates the placement of interconnected structures, such as word lines and bit lines, coupled to the memory cell, for example, restricting the pitch of the word lines and / or bit lines, thereby increasing the fabrication complexity and reducing the manufacturing yield. Moreover, since the bit lines and the storage units (e.g., capacitors or PCM elements) are located on the same side of the planar transistor (above the transistor and substrate), the process margin of the bit lines is limited by the storage units, and the coupling capacitance between the bit lines and storage units, such as capacitors, increases. Planar transistors may also have high leakage currents as the saturated drain current continues to increase, which is undesirable for the performance of the memory device.

[0052] On the other hand, the memory cell array and the peripheral circuits for controlling the memory cell array are usually arranged side by side in the same plane. As the number of memory cells continues to increase, in order to maintain the same chip size, the dimensions of the components in the memory cell array, such as transistors, word lines, and / or bit lines, must continue to shrink so as not to significantly reduce the efficiency of the memory cell array.

[0053] To address one or more of the aforementioned problems, the present disclosure introduces an approach in which vertical transistors replace planar transistors as switch and selection devices in memory cell arrays of memory devices (e.g., DRAM, PCM, and FRAM®). Compared with planar transistors, vertically arranged transistors (e.g., drain and source overlap in plan view) can reduce the area of ​​the transistors and simplify the layout of interconnect structures, such as metal wiring word lines and bit lines, which can lower the fabrication complexity and improve yield. For example, the pitch of the word lines and / or bit lines can be reduced to simplify fabrication. The vertical structure of the transistors also allows the bit lines and storage units, capacitors, etc. to be arranged on opposite sides of the transistors in the vertical direction (e.g., one above the transistor and the other below the transistor), which can increase the process margin of the bit lines and reduce the coupling capacitance between the bit lines and the storage units.

[0054] Without being inconsistent with the scope of the present disclosure, according to some aspects of the present disclosure, the memory cell array with vertical transistors and the peripheral circuits of the memory cell array can be formed on different wafers and bonded together face-to-face. Thus, the thermal budget for fabricating the memory cell array does not affect the fabrication of the peripheral circuits. The stacked memory cell array and the peripheral circuits can also reduce the chip size compared to a side-by-side arrangement, thereby improving the array efficiency. In some implementations, more than one memory cell array is stacked on top of each other using bonding techniques to further increase the array efficiency. In some implementations, the word lines and bit lines are disposed near the bonding boundary due to the vertical arrangement of the transistors, and they may be coupled to the peripheral circuits through a large number (e.g., millions) of parallel bonding contacts that span the bonding boundary, which can establish a direct, short-distance (e.g., micron-level) electrical connection between the memory cell array and the peripheral circuits, and increase the throughput and input / output (I / O) speed of the memory device.

[0055] In some implementations, the vertical transistors disclosed herein include multi-gate transistors (e.g., gate-all-around (GAA) transistors, tri-gate transistors, or double-rate transistors), which may have a wider gate control area to achieve better channel control with smaller subthreshold swing. The leakage current of multi-gate transistors can also be greatly reduced because the channel is fully depleted. Thus, much higher speed (saturated drain current) / leakage current performance can be achieved by using multi-gate transistors instead of planar transistors.

[0056] In some implementations, the vertical transistors disclosed herein include single-gate transistors (also known as single-side gate transistors) that are arranged axisymmetrically with respect to adjacent transistors in the bitline direction as a result of splitting a multi-gate transistor (e.g., double-gate transistor) using trench isolation extending in the wordline direction. Thus, the memory cell density in the bitline direction can be significantly increased (e.g., doubled) without excessively complicating the fabrication process compared to using processes such as self-aligned double patterning (SADP). Also, the axisymmetric single-gate transistors have a larger process window for wordline, bitline, and transistor pitch reduction compared to either planar transistors or multi-gate vertical transistors with, for example, dual-side gates or all-around gates.

[0057] FIG. 1A illustrates a schematic diagram of a cross section of a memory device 100 according to some embodiments of the disclosure. The memory device 100 represents an example of a bonded chip. Components of the memory device 100 (e.g., a memory cell array and peripheral circuits) may be formed separately on different substrates and then joined to form a bonded chip. The memory device 100 may include a first semiconductor structure 102 that includes peripheral circuits of the memory cell array. The memory device 100 may also include a second semiconductor structure 104 that includes the memory cell array. The peripheral circuits (also known as control and sensing circuits) may include any suitable digital, analog, and / or mixed-signal circuits used to facilitate operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver (e.g., word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., subcircuit) of the functional circuit mentioned above, or any active or passive component (e.g., transistor, diode, resistor, or capacitor) of the circuit. According to some implementations, the peripheral circuits in the first semiconductor structure 102 use complementary metal oxide semiconductor (CMOS) technology, which may be implemented, for example, in a logic process (e.g., technology nodes of 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.).

[0058] As shown in FIG. 1A, the memory device 100 may also include a second semiconductor structure 104 including an array of memory cells (memory cell array) that can use transistors as switches and selection devices. In some implementations, the memory cell array includes an array of DRAM cells. For ease of explanation, in this disclosure, a DRAM cell array may be used as an example to describe the memory cell array. However, it is understood that the memory cell array is not limited to a DRAM cell array, but may include any other suitable type of memory cell that can use transistors as switches and selection devices, such as a PCM cell array, a static random access memory (SRAM) cell array, a FRAM® cell memory, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, or any combination thereof, to name a few.

[0059] The second semiconductor structure 104 may be a DRAM device in which memory cells are provided in the form of an array of DRAM cells. In some implementations, each DRAM cell includes a capacitor for storing a bit of data as a positive or negative charge, as well as one or more transistors (also known as pass transistors) that control (e.g., switch and select) access to it. In some implementations, each DRAM cell is a one-transistor-one-capacitor (1T1C) cell. Because the transistor always leaks a small amount of charge, the capacitor slowly discharges and loses the stored information. Thus, according to some implementations, the DRAM cell must be refreshed to retain data, for example by peripheral circuitry in the first semiconductor structure 102.

[0060] 1A, the memory device 100 further includes a bonding boundary 106 vertically (vertically, e.g., in the Z direction in FIG. 1A) between the first semiconductor structure 102 and the second semiconductor structure 104. As described in more detail below, the first semiconductor structure 202 and the second semiconductor structure 204 may be fabricated separately (and in some implementations in parallel) such that the thermal budget for fabricating one of the first semiconductor structure 202 and the second semiconductor structure 204 does not limit the process for fabricating the other of the first semiconductor structure 202 and the second semiconductor structure 204. Moreover, numerous interconnects (e.g., bonding contacts) can be formed through the bonding boundary 106 to establish direct, short-distance (e.g., micron-level) electrical connections between the first semiconductor structure 102 and the second semiconductor structure 104, rather than a long-distance (e.g., millimeter or centimeter-level) chip-to-chip data bus on a circuit board such as a printed circuit board (PCB), thus eliminating chip interface delays and achieving faster I / O throughput with less power consumption. Data movement between a memory cell array in the second semiconductor structure 104 and peripheral circuits in the first semiconductor structure 102 can be performed through interconnects (e.g., bonding contacts) across the bonding boundary 106. By vertically integrating the first semiconductor structure 102 and the second semiconductor structure 104, the chip size can be reduced and memory cell density can be increased.

[0061] It is understood that the relative positions of the stacked first semiconductor structure 102 and second semiconductor structure 104 are not limited. Figure 1B shows a schematic cross-sectional view of another exemplary memory device 101 according to some implementations. Unlike the memory device 100 of Figure 1A, in which the second semiconductor structure 104 including the memory cell array is on the first semiconductor structure 102 including the peripheral circuit, in the memory device 101 of Figure 1B, the first semiconductor structure 102 including the peripheral circuit is on the second semiconductor structure 104 including the memory cell array. Nevertheless, according to some implementations, the bonding boundary 106 is formed vertically between the first semiconductor structure 102 and the second semiconductor structure 104 in the memory device 101, and the first semiconductor structure 102 and the second semiconductor structure 104 are joined vertically through bonding (e.g., hybrid bonding). Hybrid bonding, also known as "metal / dielectric hybrid bonding," is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as a solder or adhesive) that can simultaneously obtain metal-metal (e.g., copper-to-copper) and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding. Data transfer between the memory cell array in the second semiconductor structure 104 and the peripheral circuitry in the first semiconductor structure 102 can be performed through interconnects (e.g., bonding contacts) that span the bonding boundary 106.

[0062] It should be noted that X, Y, and Z axes are included in FIG. 1A and FIG. 1B to further illustrate the spatial relationships of the components of memory devices 100 and 101. The substrate of the memory device includes two elongated surfaces extending laterally in the XY plane: a top surface on the front side of the wafer on which the semiconductor devices can be formed, and a bottom surface on the back side opposite the front side of the wafer. The Z axis is orthogonal to each of the X and Y axes. As used herein, whether a component (e.g., a layer or device) is "on," "on top of," or "under" another component (e.g., a layer or device) of the memory device is determined relative to the substrate of the memory device in the Z direction (a vertical direction orthogonal to the XY plane, e.g., the thickness direction of the substrate) when the substrate is disposed on the bottommost surface of the memory device in the Z direction. The same concepts for describing spatial relationships are applied throughout this disclosure.

[0063] 2 shows a schematic diagram of a memory device 200 including a peripheral circuit and an array of memory cells each having a vertical transistor according to some embodiments of the disclosure. The memory device 200 may include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The memory devices 100 and 101 may be examples of the memory device 200, such that the memory cell array 201 and the peripheral circuit 202 may be included in the second semiconductor structure 104 and the first semiconductor structure 102, respectively. The memory cell array 201 may be any suitable memory cell array, such that each memory cell 208 includes a vertical transistor 210 and a storage unit 212 coupled to the vertical transistor 210. In some implementations, the memory cell array 201 is a DRAM cell array, and the storage unit 212 is a capacitor for storing an electric charge as binary information stored by each DRAM cell. In some implementations, the memory cell array 201 is a PCM cell array, and the storage unit 212 is a PCM element for storing binary information of each PCM cell based on different resistivities of the PCM element (e.g., including a chalcogenide alloy) in an amorphous phase and a crystalline phase. In some implementations, the memory cell array 201 is a FRAM cell array, and the storage unit 212 is a ferroelectric capacitor for storing binary information of each FRAM cell based on switching between two polarization states of a ferroelectric material under an external electric field.

[0064] 2, the memory cells 208 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 200 may include word lines 204 coupling the peripheral circuitry 202 and the memory cell array 201 for controlling switches of vertical transistors 210 in the memory cells 208 located in the rows, and bit lines 206 coupling the peripheral circuitry 202 and the memory cell array 201 for transmitting data to and / or receiving data from the memory cells 208 located in the columns. That is, each word line 204 is coupled to a respective row of the memory cells 208, and each bit line is coupled to a respective column of the memory cells 208.

[0065] Without being inconsistent with the scope of the present disclosure, as described in detail below, a vertical transistor 210, such as a vertical metal oxide semiconductor field effect transistor (MOSFET), can replace a planar transistor as a pass transistor of a memory cell 208 to reduce the area occupied by the pass transistor, the coupling capacitance, as well as the complexity of routing the interconnect. As shown in FIG. 2, in some implementations, unlike a planar transistor in which the active area is formed in a substrate, the vertical transistor 210 includes a semiconductor body 214 that extends vertically (in the Z direction) above a substrate (not shown). That is, the semiconductor body 214 can extend above the top surface of the substrate to allow a channel to be formed not only on the top surface of the semiconductor body 214 but also on one or more side surfaces thereof. As shown in FIG. 2, for example, the semiconductor body 214 can have a cubic shape to expose its four faces. It is understood that the semiconductor body 214 can have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 214 in a plan view (e.g., in the XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circle (or an elliptical shape), or any other suitable shape. It is understood that, without being inconsistent with the scope of the present disclosure, even for a semiconductor body that has a circular or elliptical cross-section in a plan view, the semiconductor body may be considered to have multiple sides, such that the gate structure is in contact with more than one side of the semiconductor body. As described below with respect to the fabrication process, the semiconductor body 214 may be formed (e.g., by etching or epitaxy) from a substrate, and thus has the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0066] As shown in FIG. 2, the vertical transistor 210 may also include a gate structure 216 in contact with one or more sides of the semiconductor body 214, e.g., in one or more planes on the side of the active area. In other words, the active area of ​​the vertical transistor 210, e.g., the semiconductor body 214, may be at least partially surrounded by the gate structure 216. As shown in FIG. 2, the gate structure 216 may include a gate dielectric 218 covering one or more sides of the semiconductor body 214, e.g., in contact with four sides of the semiconductor body 214. The gate structure 216 may also include a gate electrode 220 covering and in contact with the gate dielectric 218. The gate dielectric 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 218 may include silicon oxide in the form of a gate oxide. The gate electrode 220 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 220 may include doped polysilicon in the form of a gate poly. In some implementations, the gate electrode 220 includes multiple conductive layers, such as a W layer overlying a TiN layer. It is understood that in some examples, the gate electrode 220 and the word line 204 may be a continuous conductive structure. In other words, the gate electrode 220 may be considered as a part of the word line 204 that forms the gate structure 216, or the word line 204 may be considered as an extension of the gate electrode 220 to be coupled to the peripheral circuitry 202.

[0067] As shown in FIG. 2, the vertical transistor 210 may further include a pair of source and drain (also known as S / D, doped regions, source and drain electrodes) formed at two ends of the semiconductor body 214 in the vertical direction (z direction), respectively. The source and drain may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). The source and drain may be separated by a gate structure 216 in the vertical direction (z direction). In other words, the gate structure 216 is formed vertically between the source and drain. As a result, when a gate voltage applied to the gate electrode 220 of the gate structure 216 exceeds a threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 may be formed in the semiconductor body 214 vertically between the source and drain. That is, according to some implementations, each channel of the vertical transistor 210 may also be formed in the vertical direction along which the semiconductor body 214 extends.

[0068] In some implementations, as shown in FIG. 2, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 may contact more than one side (e.g., four sides in FIG. 2) of the semiconductor body 214 to form more than one gate, so that more than one channel may be formed between the source and drain during operation. That is, unlike a planar transistor that includes only a single planar gate (and results in a single planar channel), the vertical transistor 210 shown in FIG. 2 may include multiple vertical gates on multiple sides of the semiconductor body 214 due to the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding multiple sides of the semiconductor body 214. As a result, compared to a planar transistor, the vertical transistor 210 shown in FIG. 2 may have a wider gate control area to achieve better channel control with a smaller subthreshold swing. Since the channel is completely depleted, the leakage current ( Ioff) can also be significantly reduced. As described in more detail below, the multi-gate vertical transistor can include a double-gate vertical transistor (e.g., a dual-side gate vertical transistor), a tri-gate vertical transistor (e.g., a tri-side gate vertical transistor), and a GAA vertical transistor.

[0069] Although vertical transistor 210 is shown as a multi-gate transistor in FIG. 2, it is understood that vertical transistors disclosed herein may also include single-gate transistors as described in more detail below. That is, gate structure 216 may contact a single side of semiconductor body 214, e.g., for purposes of increasing transistor and memory cell density. Although gate dielectric 218 is shown as being separate (a separate structure) from other gate dielectrics of adjacent vertical transistors (not shown), it is also understood that gate dielectric 218 may be part of a continuous dielectric layer with multiple gate dielectrics of the vertical transistor.

[0070] In planar transistors and some lateral multi-gate transistors (e.g., FinFETs), active regions such as semiconductor bodies (e.g., Fins) extend laterally (in the XY plane), and the source and drain are disposed at different locations in the same lateral plane (XY plane). In contrast, in vertical transistors 210, according to some implementations, semiconductor bodies 214 extend vertically (in the Z direction), and the source and drain are disposed in different lateral planes. In some implementations, the source and drain are formed at two ends of the semiconductor body 214 in the vertical direction (Z direction), respectively, and thus overlap in a plan view. As a result, the area (in the XY plane) occupied by the vertical transistor 210 can be reduced compared to planar transistors and lateral multi-gate transistors. Also, metal wiring coupled to the vertical transistor 210 can be simplified because interconnects can be routed in different planes. For example, the bit lines 206 and the storage units 212 can be formed on opposite sides of the vertical transistor 210. In one example, the bit line 206 may be coupled to a source or drain at a top end of the semiconductor body 214 , while the storage unit 212 may be coupled to the other source or drain at a bottom end of the semiconductor body 214 .

[0071] 2, the storage units 212 may be coupled to the source or drain of the vertical transistors 210. The storage units 212 may include any device capable of storing binary data (e.g., 0 and 1), including but not limited to capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In some implementations, the vertical transistors 210 control the selection and / or state switching of each storage unit 212 coupled to the vertical transistors 210.

[0072] 3 shows a schematic diagram of a memory device 200 including peripheral circuitry and an array of memory cells each having a vertical transistor according to some aspects of the disclosure. In some implementations as shown in FIG. 3, each memory cell 208 is a DRAM cell 302 including a transistor 304 (e.g., implemented using a vertical transistor 210 as shown in FIG. 2) and a capacitor 306 (e.g., an example of a storage unit 212 in FIG. 2). A gate (e.g., corresponding to the gate electrode 220) of the transistor 304 may be coupled to a word line 204, one of a source and a drain of the transistor 304 may be coupled to a bit line 206, the other of the source and the drain of the transistor 304 may be coupled to one electrode of a capacitor 306, and the other electrode of the capacitor 306 may be coupled to ground.

[0073] 4 illustrates a schematic diagram of a memory device 200 including peripheral circuitry and an array of memory cells each having a vertical transistor, according to some aspects of the disclosure. In some implementations illustrated in FIG. 4, each memory cell 208 is a PCM cell 402 including a transistor 404 (e.g., implemented using the vertical transistor 210 of FIG. 2) and a PCM element 406 (e.g., an example of the storage unit 212 of FIG. 2). A gate of the transistor 404 (e.g., corresponding to the gate electrode 220) may be coupled to the word line 204, one of the source and drain of the transistor 404 may be coupled to ground, the other of the source and drain of the transistor 404 may be coupled to one electrode of the PCM element 406, and the other electrode of the PCM element 406 may be coupled to the bit line 206.

[0074] FIG. 5 shows a schematic perspective view of a memory device 200 according to some aspects of the disclosure. As shown in FIG. 5, the memory device 200 includes a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. A large number of interconnects (e.g., bonding contacts) can be formed through the bonding boundary 106 to establish a direct, short-distance (e.g., micron-level) electrical connection between the memory cell array 201 and the peripheral circuit 202. During back-end (BEOL) processes of the first semiconductor structure 102 including the peripheral circuit 202 and the second semiconductor structure 104 including the memory cell array 201, interconnects can be formed at the bonding boundary 106 to bond the two wafers together. In some implementations, the conductive layers, e.g., metal layers, of the conductive layers of the word lines 204 and bit lines 206 of the memory cell array 201 can be connected to word line drivers (WLDs), sense amplifiers (SAs), and other related circuits of the peripheral circuit 202 through interconnects formed at the bonding boundary 106.

[0075] FIG. 6 illustrates a schematic plan view of a memory device 600 according to some aspects of the disclosure. As illustrated in FIG. 6, the memory device 600 may include one or more memory array structures 602, e.g., memory dies. Each memory array structure 602 may include multiple memory banks 604. For example, as illustrated in FIG. 6, the memory array structure 602 may include eight memory banks 604. Each memory bank 604 may include multiple memory blocks 606. For example, as illustrated in FIG. 6, the memory bank 604 may include (n×m) memory blocks 606.

[0076] In some implementations, the memory device 600 may further include multiple peripheral structures 612. In some implementations, each peripheral structure 612 may include at least one word line driver circuit (WLD circuit) 614 and at least one sense amplifier circuit (SA circuit) 616. In some implementations, as shown in FIG. 6, the peripheral structure 612 may include one WLD circuit 614 and two SA circuits 616. Note that in FIG. 6, the memory blocks 606 and the peripheral structures 612 are shown side by side to illustrate the size of the area covered by the memory blocks 606 and the peripheral structures 612. However, in an actual structure, in a plan view of the memory device 600, the memory blocks 606 and the peripheral structures 612 may at least partially overlap each other. In some implementations, the memory blocks 606 and the peripheral structures 612 are formed separately on two different wafers or substrates and bonded together with at least a partially overlapping relationship. In some implementations, the memory blocks 606 and the peripheral structures 612 may completely overlap each other.

[0077] In some implementations, the peripheral structures 612 are formed in a first wafer, and one peripheral structure 612 occupies a first area on the first wafer in a plan view of the first wafer. In some implementations, the memory blocks 606 are formed in a second wafer, and one memory block 606 occupies a second area on the second wafer in a plan view of the second wafer. After bonding the first wafer with the second wafer, the first area including the WLD circuit 614 and the SA circuit 616 at least partially overlaps with the second area including the memory block 606 in a plan view of the memory device 600. In some implementations, the first area may include a first sub-area having one WLD circuit 614 and two second sub-areas each having one SA circuit 616. In some implementations, the two second sub-areas may be disposed on two sides of the first sub-area. In other words, as shown in FIG. 6, two SA circuits 616 may be disposed on two sides of one WLD circuit 614.

[0078] In some implementations, when one memory block 606 includes M word lines and N bit lines, a WLD circuit 614 may be used to control M word lines in the corresponding memory block 606, and each SA circuit 616 disposed on one side of the WLD circuit 614 may be used to control N / 2 bit lines in the corresponding memory block 606. In some implementations, an SA circuit 616 may be shared by two adjacent memory blocks 606, and one SA circuit 616 may be used to control odd-numbered or even-numbered bit lines in the two adjacent memory blocks 606.

[0079] FIG. 7 shows a schematic diagram of the arrangement of a memory device 600 according to some aspects of the disclosure. As shown in FIG. 7, the SA circuit 616 includes an SA circuit 616a and an SA circuit 616b. The SA circuit 616a can be used to control even-numbered bit lines in the memory block 606a and the memory block 606b. As shown in FIG. 7, the SA circuit 616a includes two outputs, one output connected to the even-numbered bit lines of the memory block 606a and the other output connected to the even-numbered bit lines of the memory block 606b above the memory block 606a and adjacent to the memory block 606a in the X direction. Similarly, in some implementations, the SA circuit 616b includes two outputs, one output connected to the odd-numbered bit lines of the memory block 606a and the other output connected to the odd-numbered bit lines of the memory block 606c below the memory block 606a and adjacent to the memory block 606a in the X direction.

[0080] In some implementations, the WLD circuit 614 may further include a WLD circuit 614a and a WLD circuit 614b. In some implementations, the WLD circuit 614a may be used to control even-numbered word lines in the memory block 606a, and the WLD circuit 614b may be used to control odd-numbered word lines in the memory block 606a. In some implementations, the WLD circuit 614a may be shared by the memory block 606a and an adjacent memory block (not shown) disposed to the left of the memory block 606a, and the WLD circuit 614b may be shared by the memory block 606a and another adjacent memory block (not shown) disposed to the right of the memory block 606a. In some implementations, WLD circuit 614a may be used to control even word lines in memory block 606a and even word lines in an adjacent memory block, and WLD circuit 614b may be used to control odd word lines in memory block 606a and odd word lines in another adjacent memory block.

[0081] In other words, the SA circuit 616 including the SA circuits 616a and 616b and the WLD circuit 614 including the WLD circuits 614a and 614b may be disposed in at least a partially overlapping memory block 606a or in a completely overlapping memory block 606a. Furthermore, the SA circuit 616 and the WLD circuit 614 may control only the memory block 606a or may control the memory block 606a together with adjacent memory blocks in the X-direction and / or Y-direction.

[0082] Figure 7 further illustrates a schematic diagram of word line routing and bit line routing. As shown in Figure 7, word line routing may include both horizontal (Y direction) and vertical (X direction) directions, while bit line routing may include only vertical directions.

[0083] 8 shows a schematic diagram of a WLD circuit 614 of a memory device 600 according to some embodiments of the present disclosure, and FIG. 9 shows a schematic diagram of a SA circuit 616 of a memory device 600 according to some embodiments of the present disclosure. It is understood that the WLD circuit 614 and the SA circuit 616 shown in FIG. 8 and FIG. 9 are for illustration purposes only, and other designs or structures of the WLD circuit 614 and the SA circuit 616 may also be applied to the present application.

[0084] FIG. 10 illustrates a schematic plan view of a memory device 1000 according to some aspects of the disclosure. As illustrated in FIG. 10, the memory device 1000 may include one or more memory array structures 1002, e.g., memory dies. Each memory array structure 1002 may include multiple memory banks 1004. For example, as illustrated in FIG. 10, the memory array structure 1002 may include eight memory banks 1004. Each memory bank 1004 may include multiple memory blocks 1006. For example, as illustrated in FIG. 10, the memory bank 1004 may include (n×m) memory blocks 1006.

[0085] In some implementations, the memory device 1000 may further include multiple peripheral structures 1012. In some implementations, each peripheral structure 1012 may include at least one word line driver circuit (WLD circuit) 1014 and at least one sense amplifier circuit (SA circuit) 1016. In some implementations, as shown in FIG. 10, the peripheral structure 1012 may include two WLD circuits 1014 and two SA circuits 1016. Note that in FIG. 10, the memory blocks 1006 and the peripheral structures 1012 are shown side by side to illustrate the size of the area covered by the memory blocks 1006 and the peripheral structures 1012. However, in actual applications and actual structures, the memory blocks 1006 and the peripheral structures 1012 may at least partially overlap each other in the plan view of the memory device 1000. In some implementations, the memory blocks 1006 and the peripheral structures 1012 are formed separately on two different wafers or substrates and bonded together with at least a partial overlapping relationship. In some implementations, the memory blocks 1006 and the peripheral structures 1012 may completely overlap one another.

[0086] In some implementations, the peripheral structure 1012 is formed on a first wafer, and one peripheral structure 1012 occupies a first area on the first wafer in the plan view of the first wafer. In some implementations, the memory block 1006 is formed on a second wafer, and one memory block 1006 occupies a second area on the second wafer in the plan view of the second wafer. After bonding the first wafer with the second wafer, the first area including the WLD circuit 1014 and the SA circuit 1016 at least partially overlaps with the second area including the memory block 1006 in the plan view of the memory device 1000. In some implementations, the first area may include two first sub-areas, each having one WLD circuit 1014, and two second sub-areas, each having one SA circuit 1016. In some implementations, the first sub-area and the second sub-area are alternately arranged in the first area, as shown in Fig. 10. In other words, as shown in Fig. 10, the first area (peripheral structure 1012) includes two first sub-areas (WLD circuits 1014) and two second sub-areas (SA circuits 1016), where the two first sub-areas are arranged at diagonal corners in the first area, and the two second sub-areas are arranged at diagonal corners in the first area.

[0087] In some implementations, when one memory block 1006 includes M word lines and N bit lines, one WLD circuit 1014 may be used to control M / 4 word lines in the corresponding memory block 1006, and one SA circuit 1016 may be used to control N / 2 bit lines in the corresponding memory block 1006. In some implementations, the SA circuit 1016 may be shared by two adjacent memory blocks 1006, and one SA circuit 1016 may be used to control odd or even bit lines in the two adjacent memory blocks 1006. In some implementations, the WLD circuit 1014 may be shared by two adjacent memory blocks 1006, and one WLD circuit 1014 may be used to control odd or even word lines in the two adjacent memory blocks 1006, as shown in FIG. 11 . In some implementations, the WLD circuit 614 and the SA circuit 616 shown in FIGS. 8 and 9 may also be applied to the memory device 1000.

[0088] FIG. 11 shows a schematic diagram of an arrangement of a memory device 1000 according to some embodiments of the present disclosure. As shown in FIG. 11, memory blocks 1006a and 1006b are two adjacent memory blocks. A WLD circuit 1014a is located on a peripheral wafer, e.g., a CMOS wafer, corresponding to the position of the memory block 1006a on the memory array wafer. The WLD circuit 1014a provides corresponding signals to odd-numbered word lines (WL1, WL3, WL5, and WL7) of the two memory blocks 1006a and 1006b. A WLD circuit 1014b is located on a peripheral wafer, e.g., a CMOS wafer, corresponding to the position of the memory block 1006b on the memory array wafer. The WLD circuit 1014b provides corresponding signals to even-numbered word lines (WL2, WL4, WL6, and WL8) of the two memory blocks 1006a and 1006b. It is understood that the number of word lines or word line drivers in each WLD circuit 1014 is for illustration only and the actual routing pattern may vary.

[0089] 12 shows a schematic diagram of an SA circuit 1016 of a memory device 1000 according to some aspects of the disclosure. As shown in FIG. 12, one SA circuit 1016 may include multiple sense amplifiers 1022, at least one sense amplifier driver 1024, and at least one decoder and control logic 1026. In some implementations, the SA circuit 1016 may control only one memory block, e.g., memory block 1006a. In some implementations, two SA circuits 1016 in the peripheral structure 1012 may each control N / 2 bit lines of the memory block 1006.

[0090] FIG. 13 illustrates a schematic plan view of a memory device 1300 according to some aspects of the disclosure. As shown in FIG. 13, the memory device 1300 may include one or more memory array structures 1302, e.g., memory dies. Each memory array structure 1302 may include multiple memory banks 1304. For example, as shown in FIG. 13, the memory array structure 1302 may include eight memory banks 1304. Each memory bank 1304 may include multiple memory blocks 1306. For example, as shown in FIG. 13, the memory bank 1304 may include (n×m) memory blocks 1306.

[0091] In some implementations, the memory device 1300 may further include multiple peripheral structures 1312. In some implementations, each peripheral structure 1312 may include at least one word line driver circuit (WLD circuit) 1314 and at least one sense amplifier circuit (SA circuit) 1316. In some implementations, as shown in FIG. 13, the peripheral structure 1312 may include one WLD circuit 1314 and two SA circuits 1316. Note that in FIG. 13, the memory blocks 1306 and the peripheral structures 1312 are shown side by side to illustrate the size of the area covered by the memory blocks 1306 and the peripheral structures 1312. However, in actual applications and actual structures, in the plan view of the memory device 1300, the memory blocks 1306 and the peripheral structures 1312 may at least partially overlap each other. In some implementations, the memory blocks 1306 and the peripheral structures 1312 are formed separately on two different wafers or substrates and bonded together with at least a partial overlapping relationship.

[0092] In some implementations, the peripheral structure 1312 is formed in a first wafer, and one peripheral structure 1312 occupies a first area on the first wafer in a plan view of the first wafer. In some implementations, the memory block 1306 is formed in a second wafer, and one memory block 1306 occupies a second area on the second wafer in a plan view of the second wafer. After bonding the first wafer with the second wafer, the first area including the WLD circuit 1314 and the SA circuit 1316 at least partially overlaps with the second area including the memory block 1306 in a plan view of the memory device 1300. In some implementations, the first area may include one first sub-area having one WLD circuit 1314 and two second sub-areas each having one SA circuit 1316. In some implementations, a first sub-area having one WLD circuit 1314 may be located between two adjacent memory blocks 1306. In some implementations, the first sub-area may not overlap with a second area having memory blocks 1306. In some implementations, the second sub-areas each having one SA circuit 1316 may at least partially overlap with a second area having memory blocks 1306. In some implementations, the second sub-areas may completely overlap with a second area having memory blocks 1306. In some implementations, the SA circuit 1316 may be shared by two adjacent memory blocks 1306, and one SA circuit 1316 may be used to control odd or even bit lines in two adjacent memory blocks 1306. For example, the SA circuit 1316 may include two outputs, one output connected to the even-numbered bit lines of the memory block 1306 and the other output connected to the even-numbered bit lines of a memory block adjacent to the memory block 1306 in the X-direction. In some implementations, the WLD circuit 614 and the SA circuit 616 shown in FIGS. 8 and 9 may also be applied to the memory device 1300.

[0093] In some implementations, the WLD circuit 1314 is located on a peripheral wafer, e.g., a CMOS wafer, that corresponds to a location between two memory blocks 1306 on a memory array wafer. In some implementations, the WLD circuit 1314 provides a corresponding signal to odd-numbered word lines or even-numbered word lines of two adjacent memory blocks 1306. For example, the WLD circuit 1314 may provide a corresponding signal to odd-numbered word lines of two adjacent memory blocks 1306.

[0094] In some implementations, the peripheral structure 1312 may further include a connection circuit 1318 including a control circuit for the SA circuit 1316. FIG. 14 shows a schematic diagram of the connection circuit 1318 of the memory device 1300 according to some aspects of the disclosure. In some implementations, the connection circuit 1318 occupies a third sub-area in the first area. In some implementations, the third sub-area is disposed between the second sub-areas. In some implementations, the connection circuit 1318 may include at least three parts, including a data line circuit (DL / LDL circuit) 1322 for transmitting data out from the bit line to the data line, a switch circuit 1324 for generating a switching voltage and a control timing sequence of the switching operation, and a sense amplifier driver (SA driver) 1326 for generating SA-related control signals. It is understood that the DL / LDL circuit 1322, the switch circuit 1324, and the SA driver 1326 shown in FIG. 14 are for illustrative purposes, and other circuit structures may also be applied to the present application.

[0095] FIG. 15 illustrates a schematic plan view of a memory device 1500 according to some aspects of the disclosure. As shown in FIG. 15, the memory device 1500 may include one or more memory array structures 1502, e.g., memory dies. Each memory array structure 1502 may include multiple memory banks 1504. For example, as shown in FIG. 15, the memory array structure 1502 may include eight memory banks 1504. Each memory bank 1504 may include multiple memory blocks 1506. For example, as shown in FIG. 15, the memory bank 1504 may include (n×m) memory blocks 1506.

[0096] In some implementations, the memory device 1500 may further include multiple peripheral structures 1512. In some implementations, each peripheral structure 1512 may include at least one word line driver circuit (WLD circuit) 1514 and at least one sense amplifier circuit (SA circuit) 1516. In some implementations, as shown in FIG. 15, the peripheral structure 1512 may include one WLD circuit 1514 and one SA circuit 1516. Note that in FIG. 15, the memory block 1506 and the peripheral structure 1512 are shown side by side to illustrate the size of the area covered by the memory block 1506 and the peripheral structure 1512. However, in an actual application and actual structure, in the plan view of the memory device 1500, the memory block 1506 and the peripheral structure 1512 may at least partially overlap each other. In some implementations, the memory blocks 1506 and the peripheral structures 1512 are formed separately on two different wafers or substrates and bonded to one another with at least a partial overlapping relationship.

[0097] In some implementations, the peripheral structure 1512 is formed in a first wafer, and one peripheral structure 1512 occupies a first area on the first wafer in a plan view of the first wafer. In some implementations, the memory block 1506 is formed in a second wafer, and one memory block 1506 occupies a second area on the second wafer in a plan view of the second wafer. After bonding the first wafer with the second wafer, the first area including the WLD circuit 1514 and the SA circuit 1516 at least partially overlaps with the second area including the memory block 1506 in a plan view of the memory device 1500. In some implementations, the first area may include one first sub-area having one WLD circuit 1514 and one second sub-area each having one SA circuit 1516. In some implementations, the first sub-area having one WLD circuit 1514 may be located between two adjacent memory blocks 1506. In some implementations, the first sub-area may not overlap with the second area having memory blocks 1506. In some implementations, the second sub-area having one SA circuit 1516 may at least partially overlap with the second area having memory blocks 1506. In some implementations, the second sub-area may completely overlap with the second area having memory blocks 1506. In some implementations, the WLD circuit 614 and the SA circuit 616 shown in FIG. 8 and FIG. 9 may also be applied to the memory device 1500.

[0098] FIG. 16 shows a schematic plan view of a peripheral structure 1512 according to some aspects of the disclosure. In some implementations, the WLD circuit 1514 is located on a peripheral wafer, e.g., a CMOS wafer, corresponding to a position between two memory blocks 1506 on a memory array wafer. In some implementations, the WLD circuit 1514 provides a corresponding signal to an odd-numbered word line or an even-numbered word line of two adjacent memory blocks 1506. For example, as shown in FIG. 15 and FIG. 16, the odd-numbered WLD circuit 1514 may provide a corresponding signal to an odd-numbered word line of two adjacent memory blocks 1506, and the even-numbered WLD circuit 1514 may provide a corresponding signal to an even-numbered word line of two adjacent memory blocks 1506.

[0099] In some implementations, the peripheral structure 1512 may further include a connection circuit 1518. In some implementations, the connection circuit 1518 occupies a third sub-area in the first area. In some implementations, the third sub-area is disposed next to the first sub-area. In some implementations, the connection circuit 1318 shown in FIG. 14 may also be applied to the memory device 1500.

[0100] In some implementations, the peripheral structure 1512 may further include a decoder and control logic 1520. FIG. 16 shows a schematic diagram of the decoder and control logic 1520 of the memory device 1500 according to some aspects of the disclosure. In some implementations, the decoder and control logic 1520 may decode the address of the word line in the Y direction. It is understood that the decoder and control logic 1520 shown in FIG. 16 is for illustrative purposes and other circuit structures may be applied to the present application.

[0101] By using the memory device 600, 1000, 1300, or 1500, the memory array and peripheral circuits of the memory device can be formed on two different wafers, respectively, and then bonded together. In this way, the peripheral circuits, including the WLD circuit, the SA circuit, the connection circuit, and / or the decoder and control logic, can be hidden under the memory array. Therefore, the size of the memory device 600, 1000, 1300, or 1500 can be reduced, and the array efficiency can also be improved.

[0102] FIG. 18 illustrates a flowchart of a method 1800 for forming a memory device according to some aspects of the disclosure. As illustrated in operation 1802 of FIG. 18, a memory array structure is formed in a first substrate, e.g., a first wafer. The memory array structure may include at least one memory bank, and each memory bank may include a plurality of memory blocks. In some implementations, the memory array structure may use transistors as switches and selection devices. In some implementations, the memory array structure includes an array of DRAM cells. For ease of explanation, a DRAM cell array may be used as an example to explain a memory cell array in the present disclosure. However, it is understood that the memory cell array is not limited to a DRAM cell array, but may include any other suitable type of memory cell array that may use transistors as switches and selection devices, such as a PCM cell array, an SRAM cell array, an FRAM cell array, a resistive memory cell array, a magnetic memory cell array, an STT memory cell array, or any combination thereof, to name a few.

[0103] In some implementations, each DRAM cell includes a capacitor for storing a bit of data as a positive or negative charge, and one or more transistors (also known as pass transistors) that control (e.g., switch and select) access to it. In some implementations, each DRAM cell is a one-transistor, one-capacitor (1T1C) cell. Because the transistor always leaks a small amount of charge, the capacitor slowly discharges and the stored information is lost. Therefore, to retain data, the DRAM cell must be refreshed, for example by peripheral circuitry.

[0104] As shown in operation 1804 of FIG. 18, a peripheral structure having peripheral circuits is formed in a second substrate, e.g., a second wafer, different from the first substrate. The peripheral structure may include word line driver circuits and sense amplifier circuits. In some implementations, the peripheral circuits (also known as control and sensing circuits) may include any suitable digital, analog, and / or mixed-signal circuits used to support the operation of the memory cell array. For example, the peripheral circuits may include one or more of a page buffer, a decoder (e.g., row decoder and column decoder), a sense amplifier, a driver (e.g., word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., subcircuit) of the functional circuits mentioned above, or any active or passive component (e.g., transistor, diode, resistor, or capacitor) of the circuit. According to some implementations, the peripheral circuitry on the second substrate uses CMOS technology, which may be implemented using, for example, a logic process (e.g., technology nodes such as 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.).

[0105] As shown in operation 1806 of FIG. 18, the memory array structure and peripheral structure are bonded with word line driver circuitry and sense amplifier circuitry that at least partially overlap the memory blocks in the floor plan of the memory device.

[0106] In some implementations, the word line driver circuitry is formed in the second substrate in the first sub-area and the sense amplifier circuitry is formed in the second substrate in the second sub-area. In some implementations, the first sub-area and the second sub-area are disposed at diagonal corners of the memory block in a plan view of the memory device, as shown in FIG.

[0107] In some implementations, the word line driver circuitry is formed in the second substrate in the first sub-area, and the sense amplifier circuitry is formed in the second substrate in the second sub-area and the third sub-area. In some implementations, the second sub-area and the third sub-area are disposed on two sides of the first sub-area in a plan view of the memory device, as shown in FIG.

[0108] In some implementations, as shown in FIG. 13, the first sub-area is disposed between adjacent memory blocks in a plan view of the memory device, and the second sub-area and the third sub-area are disposed overlapping the memory blocks in the plan view of the memory device.

[0109] In some implementations, the word line driver circuitry is formed in the second substrate in the first sub-area, the sense amplifier circuitry is formed in the second substrate in the second sub-area, and the decoder circuitry is formed in the second substrate in the third sub-area. In some implementations, the first sub-area is disposed between adjacent memory blocks in a plan view of the memory device, and the second and third sub-areas are disposed overlapping the memory blocks in a plan view of the memory device, as shown in FIG.

[0110] FIG. 19 illustrates a block diagram of a system 1900 having a memory device according to some aspects of the disclosure. The system 1900 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage. As shown in FIG. 19, the system 1900 may include a host 1908 and a memory system 1902 having one or more memory devices 1904 and a memory controller 1906. The host 1908 may be a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). The host 1908 may be configured to transmit data to the memory device 1904 or receive data from the memory device 1904.

[0111] Memory device 1904 may be any memory device disclosed herein, such as memory device 600, 1000, 1300, or 1500. In some implementations, memory device 1904 includes an array of memory cells each including a vertical transistor, as described in detail above.

[0112] According to some implementations, the memory controller 1906 is coupled to the memory device 1904 and the host 1908 and configured to control the memory device 1904. The memory controller 1906 can manage data stored in the memory device 1904 and communicate with the host 1908. The memory controller 1906 can be configured to control operations of the memory device 1904, such as read, write, and refresh operations. The memory controller 1906 can also be configured to manage various functions with respect to data stored or to be stored in the memory device 1904, including, but not limited to, refresh and timing control, command / request translation, buffers and schedules, and power management. In some implementations, the memory controller 1906 is further configured to determine the maximum memory capacity that the computer system can use, the number of memory banks, the type and speed of the memory, the data depth and data width of the memory particles, and other important parameters. Any other suitable functions can also be performed by the memory controller 1906. The memory controller 1906 can communicate with an external device (e.g., the host 1908) according to a particular communication protocol. For example, the memory controller 1906 can communicate with the external device through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, or the like.

[0113] The above description of specific implementations may be easily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to be within the meaning and equivalents of the disclosed implementations based on the teaching and guidance presented herein. The breadth and scope of the present disclosure should not be limited by any of the exemplary implementations described above, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0114] 100 Memory Devices 101 Memory Devices 102 First semiconductor structure 104 Second Semiconductor Structure 106 Bonding Boundary 200 Memory Devices 201 Memory cell array 202 Peripheral Circuit 204 Word Line 206 bit lines 208 memory cells 210 Vertical Transistor 212 Memory Unit 214 Semiconductor body 216 Gate Structure 218 Gate Dielectric 220 Gate electrode 302 DRAM cells 304 Transistor 306 Capacitor 402 PCM cells 404 Transistor 406 PCM element 600 Memory Devices 602 Memory Array Structure 604 Memory Bank 606 Memory Blocks 612 Peripheral Structure 614 WLD circuit 616 SA Circuit 1000 Memory Devices 1002 Memory Array Structure 1004 Memory Bank 1006 Memory Blocks 1012 Peripheral structure 1014 WLD circuit 1016 SA circuit 1022 Sense Amplifier 1024 Sense Amplifier Driver 1026 Decoder and Control Logic 1300 Memory Device 1302 Memory Array Structure 1304 Memory Bank 1306 Memory Blocks 1312 Surrounding Structure 1314 WLD circuit 1316 Sense amplifier circuit 1318 Connection circuit 1322 Data line circuit 1324 Switch Circuit 1326 Sense Amplifier Driver 1500 Memory Device 1502 Memory Array Structure 1504 Memory Bank 1506 Memory Blocks 1512 Surrounding Structure 1514 WLD circuit 1516 SA Circuit 1518 Connection circuit 1520 Decoder and Control Logic 1900 System 1902 Memory System 1904 Memory Device 1906 Memory Controller 1908 Host

Claims

1. 1. A memory device comprising: a memory array structure comprising at least one memory bank, each memory bank comprising a plurality of memory blocks; a peripheral structure including word line driver circuits and sense amplifier circuits; A memory device, wherein a first area comprising the word line driver circuitry and the sense amplifier circuitry at least partially overlaps a second area comprising memory blocks in a plan view of the memory device.

2. 2. The memory device of claim 1, wherein the first area comprises a first sub-area comprising the word line driver circuitry and a second sub-area comprising the sense amplifier circuitry, the first sub-area and the second sub-area being alternately arranged in the first area.

3. 3. The memory device of claim 2, wherein the first area comprises two first sub-areas and two second sub-areas, the two first sub-areas being disposed at diagonal corners in the first area and the two second sub-areas being disposed at diagonal corners in the first area.

4. The memory device of claim 1 , wherein the first area completely overlaps the second area in the plan view of the memory device.

5. 4. The memory device of claim 3, wherein the word line driver circuitry in one of the two first sub-areas is coupled to odd-numbered word lines in the memory block, and the word line driver circuitry in the other of the two first sub-areas is coupled to even-numbered word lines in the memory block.

6. 2. The memory device of claim 1, wherein the first area comprises a first sub-area comprising the word line driver circuitry and two second sub-areas each comprising the sense amplifier circuitry, the two second sub-areas being disposed on two sides of the first sub-area.

7. The memory device of claim 6 , wherein the sense amplifier circuitry in one of the two second sub-areas is shared by two adjacent memory blocks.

8. The memory device of claim 6 , wherein the sense amplifier circuits in the two second sub-areas are coupled to bit lines in the memory block.

9. 7. The memory device of claim 6, wherein the sense amplifier circuitry in one of the two second sub-areas is coupled to odd-numbered bit lines in the memory block and odd-numbered bit lines in a first adjacent memory block, and the sense amplifier circuitry in the other of the two second sub-areas is coupled to even-numbered bit lines in the memory block and even-numbered bit lines in a second adjacent memory block.

10. 7. The memory device of claim 6, wherein the word line driver circuits in the first sub-area are coupled to odd-numbered word lines or even-numbered word lines in the memory block.

11. 11. The memory device of claim 10, wherein the word line driver circuits in the first sub-area are coupled to odd-numbered word lines or even-numbered word lines in adjacent memory blocks.

12. 2. The memory device of claim 1, wherein the first area comprises a first sub-area comprising the word line driver circuitry, a second sub-area comprising the sense amplifier circuitry, and a third sub-area comprising a decoder circuitry, the first sub-area being disposed between adjacent memory blocks in the plan view of the memory device, and the second sub-area and the third sub-area overlapping the second area of ​​the memory block in the plan view of the memory device.

13. 13. The memory device of claim 12, wherein the first area further comprises a fourth sub-area comprising control circuitry for the sense amplifier circuitry, the fourth sub-area being disposed between the second sub-area and the third sub-area.

14. 14. The memory device of claim 13, wherein the second sub-area, the third sub-area, and the fourth sub-area overlap the second area of ​​the memory block in the floor plan of the memory device.

15. 2. The memory device of claim 1, wherein the first area comprises a first sub-area comprising the word line driver circuitry and two second sub-areas each comprising the sense amplifier circuitry, the first sub-area being disposed between adjacent memory blocks in the plan view of the memory device, and the two second sub-areas overlapping the second areas of the memory blocks in the plan view of the memory device.

16. 16. The memory device of claim 15, wherein the first area further comprises a third sub-area comprising control circuitry for the sense amplifier circuitry, the third sub-area being disposed between the two second sub-areas.

17. 17. The memory device of claim 1, wherein the memory array structure is disposed in a first substrate and the peripheral structure is disposed in a second substrate different from the first substrate.

18. 20. The memory device of claim 17, wherein the memory array structure disposed on the first substrate is bonded to the peripheral structure disposed on the second substrate.

19. 19. The memory device of claim 1, wherein the memory array structure comprises a dynamic random access memory (DRAM).

20. 1. A memory device comprising: a memory array structure disposed on a first substrate comprising at least one memory bank, each memory bank comprising a plurality of memory blocks; a peripheral structure disposed on a second substrate different from the first substrate, the peripheral structure including a sense amplifier circuit and a word line driver circuit; A memory device, wherein the sense amplifier circuitry overlaps a memory block in a plan view of the memory device.

21. 21. The memory device of claim 20, wherein the word line driver circuitry is disposed between adjacent memory blocks in the plan view of the memory device.

22. 22. The memory device of claim 21, wherein the peripheral structure further comprises decoder circuitry that overlaps with the memory blocks in the floor plan of the memory device.

23. 22. The memory device of claim 21, wherein the peripheral structure further comprises control circuitry for the sense amplifier circuitry that overlaps with the memory blocks in the floor plan of the memory device.

24. 21. The memory device of claim 20, wherein the word line driver circuitry overlaps the memory blocks in the floor plan of the memory device.

25. 25. The memory device of claim 24, wherein the sense amplifier circuitry comprises a first sub-area and a second sub-area disposed on two sides of the word line driver circuitry in the plan view of the memory device.

26. 25. The memory device of claim 24, wherein the sense amplifier circuitry comprises a first sub-area and a second sub-area, the word line driver circuitry comprises a third sub-area and a fourth sub-area, the first sub-area and the third sub-area are disposed at diagonal corners that overlap with the memory blocks in the plan view of the memory device, and the second sub-area and the fourth sub-area are disposed at diagonal corners that overlap with the memory blocks in the plan view of the memory device.

27. 27. The memory device of claim 20, wherein the memory array structure comprises a dynamic random access memory (DRAM).

28. 1. A method for forming a memory device, comprising: forming a memory array structure on a first substrate, the memory array structure comprising at least one memory bank, each memory bank comprising a plurality of memory blocks; forming a peripheral structure in a second substrate different from the first substrate, the peripheral structure comprising word line driver circuitry and sense amplifier circuitry; and bonding the memory array structure and the peripheral structure so that the word line driver circuitry and the sense amplifier circuitry at least partially overlap memory blocks in a plan view of the memory device.

29. forming the peripheral structure on the second substrate, 30. The method of claim 28 comprising forming the word line driver circuitry in a first sub-area and the sense amplifier circuitry in a second sub-area.

30. joining the memory array structure and the peripheral structure so as to cause the word line driver circuitry and the sense amplifier circuitry to at least partially overlap the memory blocks in the plan view of the memory device; 30. The method of claim 29, comprising disposing the first sub-area and the second sub-area at diagonal corners of the memory block in the plan view of the memory device.

31. forming the peripheral structure on the second substrate, 30. The method of claim 28 comprising forming the word line driver circuitry in a first sub-area and the sense amplifier circuitry in a second sub-area and a third sub-area.

32. joining the memory array structure and the peripheral structure so as to cause the word line driver circuitry and the sense amplifier circuitry to at least partially overlap the memory blocks in the plan view of the memory device; 32. The method of claim 31 comprising disposing the second sub-area and the third sub-area on two sides of the first sub-area in the plan view of the memory device.

33. joining the memory array structure and the peripheral structure so as to cause the word line driver circuitry and the sense amplifier circuitry to at least partially overlap the memory blocks in the plan view of the memory device; 32. The method of claim 31 , comprising disposing the first sub-area between adjacent memory blocks in the floor plan of the memory device, the second sub-area and the third sub-area overlapping the memory blocks in the floor plan of the memory device.

34. forming the peripheral structure on the second substrate, 30. The method of claim 28 comprising forming the word line driver circuitry in a first sub-area, the sense amplifier circuitry in a second sub-area, and a decoder circuitry in a third sub-area.

35. joining the memory array structure and the peripheral structure so as to cause the word line driver circuitry and the sense amplifier circuitry to at least partially overlap the memory blocks in the plan view of the memory device; 35. The method of claim 34, comprising disposing the first sub-area between adjacent memory blocks in the floor plan of the memory device, the second sub-area and the third sub-area overlapping the memory blocks in the floor plan of the memory device.

36. 1. A memory device comprising: a memory array structure comprising at least one memory bank, each memory bank comprising a plurality of memory blocks; a peripheral structure including word line driver circuits and sense amplifier circuits; a first area comprising the word line driver circuitry and the sense amplifier circuitry at least partially overlapping a second area comprising memory blocks in a plan view of the memory device; A memory device; a memory controller coupled to the memory device and configured to control operation of the memory array structure through the peripheral structure.

37. 1. A memory device comprising: a memory array structure disposed on the first substrate, the memory array structure comprising at least one memory bank, each memory bank comprising a plurality of memory blocks; a peripheral structure disposed on a second substrate different from the first substrate, the peripheral structure including a sense amplifier circuit and a word line driver circuit; the sense amplifier circuitry overlaps with a memory block in a plan view of the memory device; A memory device; a memory controller coupled to the memory device and configured to control operation of the memory array structure through the peripheral structure.

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