Highly selective silicon etching

Abstract

An exemplary semiconductor processing method may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. The substrate may include at least one layer of a silicon-containing material and at least one layer of a silicon- and germanium-containing material along with the substrate. The method may include forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor in the processing region. The method may include contacting the at least one layer of the silicon-containing material and the at least one layer of the silicon- and germanium-containing material with plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor. The substrate may include removing the at least one layer of the silicon-containing material at a rate greater than the at least one layer of the silicon- and germanium-containing material.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 674,127, filed Feb. 17, 2022, the entire disclosure of which is incorporated by reference herein for all purposes.

[0002] Technical Field

[0002] The present technology relates to semiconductor systems, processes, and apparatus. More specifically, the present technology relates to processes and systems for selectively etching silicon materials relative to silicon and germanium materials. [Background technology]

[0003]

[0003] Integrated circuits are realized by processes that create intricately patterned layers of material on a substrate surface. Fabricating patterned materials on a substrate requires controlled methods for forming and removing materials. Memory, including stacked memories such as vertical NAND or 3D NAND, and transistor structures, including finFETs and gate-all-arounds, may include many layers and materials and may be processed to selectively remove some materials while preserving others. The material properties of the layers of material and the process conditions and materials for etching may affect the uniformity of the formed structures. Material defects may lead to inconsistent patterning, which may further affect the uniformity of the formed structures.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The above needs, and others, are addressed by the present technique. Summary of the Invention

[0005] An exemplary semiconductor processing method may include providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. The substrate may include at least one layer of a silicon-containing material and at least one layer of a silicon- and germanium-containing material along with the substrate. The method may include forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor in the processing region. The method may include contacting the at least one layer of the silicon-containing material and the at least one layer of the silicon- and germanium-containing material with plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor. The method may include removing the at least one layer of the silicon-containing material at a higher rate than the at least one layer of the silicon- and germanium-containing material.

[0006]

[0006] In some embodiments, the fluorine-containing precursor may be or include one or both of nitrogen trifluoride and carbon tetrafluoride. At least one layer of silicon-containing material may be selectively removed at a rate of greater than or about 2:1 relative to at least one layer of silicon and germanium-containing material. The plasma of the fluorine-containing precursor and the hydrogen-containing precursor may be generated at a source plasma power of less than or about 1,000 W. The bias applied to the plasma of the fluorine-containing precursor and the hydrogen-containing precursor may be generated at a bias power of less than or about 100 W. The plasma of the fluorine-containing precursor and the hydrogen-containing precursor may be generated at a duty cycle of less than or about 50%. The method may include pulsing the source plasma power while forming the plasma effluent of the fluorine-containing precursor and the hydrogen-containing precursor. The source plasma power may be pulsed at a frequency of less than or about 1000 Hz. The temperature in the semiconductor processing chamber may be maintained at or below 125° C. The pressure in the semiconductor processing chamber may be maintained at or below 200 mTorr. The method may include providing an inert precursor to a processing region of the semiconductor processing chamber along with a fluorine-containing precursor and a hydrogen-containing precursor. The inert precursor may be or may include a nitrogen-containing inert precursor, an argon-containing inert precursor, a helium-containing inert precursor, or combinations thereof. The flow ratio of the hydrogen-containing precursor to the fluorine-containing precursor may be greater than or about 2:1. The plasma may be oxygen-free.

[0007]

[0007] Some embodiments of the present technique may include a semiconductor processing method. The method may include providing a fluorine-containing precursor, a hydrogen-containing precursor, and a nitrogen-containing precursor. The method may include forming a plasma of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor. The method may include contacting at least one layer of a silicon-containing material and at least one layer of a silicon- and germanium-containing material along with a substrate with plasma effluents of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor. The contacting may selectively remove the at least one layer of the silicon-containing material.

[0008] In some embodiments, the fluorine-containing precursor may be or include carbon tetrafluoride. The nitrogen-containing precursor may be or include nitrogen trifluoride. The fluorine-containing precursor and the nitrogen-containing precursor may form a passivation compound and an etching compound when contacting the at least one layer of silicon-containing material and the at least one layer of silicon- and germanium-containing material. The passivation compound may include a carbon material, a hydrogen material, and a fluorine material. The etching compound may include a nitrogen material, a hydrogen material, and a fluorine material. During the semiconductor processing method, the pressure may be maintained at less than or about 70 mTorr. The at least one layer of silicon- and germanium-containing material may be characterized by a germanium concentration of less than or about 50 at.%. The etching compound may remove the at least one layer of silicon-containing material with a selectivity of greater than or about 3:2 relative to the at least one layer of silicon- and germanium-containing material. The method may include providing a hydrogen-containing precursor and an inert precursor together with a fluorine-containing precursor and a nitrogen-containing precursor. The fluorine-containing precursor, the nitrogen-containing precursor, the hydrogen-containing precursor, and the inert precursor may form a passivation compound and an etching compound. The passivation compound may passivate at least one layer of silicon- and germanium-containing material. The etching compound may remove at least one layer of silicon-containing material.

[0009] Some embodiments of the present technique may include a semiconductor processing method. The method may include providing a fluorine-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. The substrate may include at least one layer of a silicon-containing material and at least one layer of a silicon- and germanium-containing material along the substrate. The method may include forming a plasma of the fluorine-containing precursor and the nitrogen-containing precursor in the processing region. The plasma may be generated at a discontinuous plasma power of less than or about 1,000 W. The method may include contacting the at least one layer of the silicon-containing material and the at least one layer of the silicon- and germanium-containing material with plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor. The contacting may passivate the at least one layer of the silicon- and germanium-containing material. The substrate may include removing the at least one layer of the silicon-containing material at a rate greater than the at least one layer of the silicon- and germanium-containing material. The at least one layer of silicon-containing material may be selectively removed at a rate of greater than or about 3:2 relative to the at least one layer of silicon and germanium-containing material.

[0010]

[0010] Such techniques may provide numerous advantages over conventional methods and techniques. For example, the process may passivate materials, such as silicon and germanium materials, to further limit etching, thereby selectively etching a second material, such as a silicon material. Furthermore, by passivating one material, the process may bring the two different materials closer in stoichiometry, thereby reducing strain between the two materials. Furthermore, the process may not utilize oxygen, which may oxidize one or more layers of material. These and other embodiments, together with their numerous advantages and features, are described in further detail in conjunction with the following description and accompanying drawings.

[0011] A further understanding of the nature and advantages of the disclosed technology may be obtained by reference to the remainder of the specification and drawings. [Brief description of the drawings]

[0012] [Figure 1] 1 shows a schematic top view of an exemplary processing system in accordance with some embodiments of the present technique. [Diagram 2]

[0013] 1 shows a schematic cross-sectional view of an exemplary processing system, in accordance with some embodiments of the present technique. [Diagram 3]

[0014] 1 illustrates selected steps of a semiconductor processing method in accordance with some embodiments of the present technique. [Figure 4A-4B]

[0015] 1A-1C show exemplary schematic cross-sectional structures produced including layers of material in accordance with some embodiments of the present technique; [Figure 5A-5B]

[0016] 1 shows a graph of selected operating characteristics versus etch selectivity in accordance with some embodiments of the present technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0017] Some figures are included as schematics. It is understood that the figures are for illustrative purposes and should not be considered to scale unless specifically stated to be to scale. Furthermore, as schematics, the drawings are provided to aid in understanding and may not include all aspects or information compared to a realistic depiction and may include material that is emphasized for illustrative purposes.

[0014]

[0018] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any one of the similar components having the same first reference number, regardless of the letter.

[0015]

[0019] Many integrated circuit applications require selective removal of one material relative to another. For example, memory structures and gate-all-around devices may require selective removal of silicon material relative to silicon and germanium materials adjacent to the silicon material. In fabricating memory structures and gate-all-around devices, a stack of materials may be developed that may include adjacent layers of silicon and silicon and germanium materials. Subsequent fabrication steps may require selective removal of silicon material relative to silicon and germanium materials. Etch processes may be used to remove silicon material (which may be silicon or include silicon) while requiring limited removal of silicon and germanium materials (which may be silicon germanium). Because silicon and silicon and germanium are chemically similar, maintaining high etch selectivity for silicon removal relative to silicon and germanium removal may be difficult. Various precursors and process conditions have been employed to increase etch selectivity.

[0016]

[0020] As semiconductor processing seeks to utilize more materials to provide improved patterning and material properties for various devices, silicon and germanium are increasingly being used as materials for end devices as well as to pattern other materials, including silicon. Conventional techniques have difficulty selectively removing silicon material relative to silicon and germanium materials, and have typically been limited to etch rates approaching 1:1, especially for material layers with low germanium content, such as less than or about 50%. Removal of silicon material may result in excessive loss of some of the silicon and germanium materials. Removal of silicon and germanium materials may result in material defects that may ultimately lead to uniformity issues affecting the final device. Additionally, conventional techniques may require processing at high pressures and the use of precursors that contain oxygen to increase selectivity. High pressures may result in more isotropic etch profiles, which may affect device structures and generate particles. Additionally, the presence of oxygen may cause the remaining materials to at least partially oxidize, which may reduce charge carrier mobility and adversely affect device performance. Thus, many of the prior art techniques are limited in their ability to prevent structural defects or performance degradation in the final device.

[0017]

[0021] The present technology overcomes these problems by utilizing specific precursors that can be delivered under more specific processing conditions, allowing for increased silicon selectivity while advantageously allowing etching to be performed at lower pressures and without the use of oxygen-containing precursors. By providing specific precursor combinations, the present technology can at least partially passivate or protect one layer of material from removal during processing, while another layer of material can be more easily removed. Furthermore, by passivating or protecting one layer of material from removal during processing, the present technology can develop structures in which adjacent layers can feature more similar chemical compositions, which may reduce the strain that occurs between layers during formation while at the same time improving removal selectivity.

[0018]

[0022] While the following disclosure routinely identifies specific etching processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other processes that may be performed in the described chambers. Thus, the technology should not be considered limited to use with only the described etching processes. This disclosure describes one possible system and chamber that may be used with the technology before describing the systems and methods or processes of an exemplary process sequence according to some embodiments of the technology. It should be understood that the technology is not limited to the described apparatus, and the discussed processes may be performed in any number of processing chambers and systems.

[0019]

[0023] Figure 1 shows a top view of one embodiment of a processing system 10 for deposition, etch, bake, and / or cure chambers, according to an embodiment. The tool or processing system 10 depicted in Figure 1 may include multiple processing chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The processing chambers may include any number of structures or components and any number or combination of processing chambers.

[0020]

[0024] To transfer substrates between chambers, the transfer chamber 20 may include a robotic transfer mechanism 22. The transfer mechanism 22 may have a pair of substrate transfer blades 22a, each attached to a distal end of an extendable arm 22b. The blades 22a may be used to transport individual substrates to and from the processing chambers. In operation, one of the substrate transfer blades, such as blade 22a of the transfer mechanism 22, retrieves a substrate W from one of the load lock chambers, such as chambers 16a-b, and transports the substrate W to a first stage of processing in chambers 24a-d, such as a processing chamber described below. The chambers may be included to perform individual or combinational operations of the described techniques. For example, one or more chambers may be configured to perform a deposition or etching process, while one or more other chambers may be configured to perform a pre-processing and / or one or more post-processing processes described. Any number of configurations are encompassed by the present techniques, and any number of additional manufacturing processes typically performed in semiconductor processing may also be performed.

[0021]

[0025] If a chamber is in use, the robot may wait until processing is complete, then remove the processed substrate from the chamber using one blade 22a and insert a new substrate using a second blade. Once the substrate has been processed, it may be moved to a second stage of processing. For each transfer, the transfer mechanism 22 will generally carry the substrate with one blade and the other blade may be empty to perform a substrate exchange. The transfer mechanism 22 may wait at each chamber until the exchange is complete.

[0022]

[0026] Once processing in the processing chambers is completed, the transfer mechanism 22 may remove the substrate W from the last processing chamber and transport the substrate W to a cassette in the load lock chambers 16a-b. The substrate may be moved from the load lock chambers 16a-b into the factory interface. The factory interface 12 may operate to transfer substrates between the pod loaders 14a-d and the load lock chambers 16a-b, which are generally in a clean environment at atmospheric pressure. The clean environment in the factory interface 12 may generally be provided through an air filtration process, such as a HEPA filter. The factory interface 12 may also include a substrate orienter / aligner that may be used to properly align the substrate prior to processing. At least one substrate robot, such as robots 18a-b, may be disposed within the factory interface 12 to transfer substrates between various positions or locations within the factory interface 12 and to other locations in communication therewith. The robots 18a-18b may be configured to move along a track system within the factory interface 12 from a first end to a second end of the factory interface 12.

[0023]

[0027] The processing system 10 may further include an integrated metrology chamber 28 to obtain control signals that may provide adaptive control over any process performed in the processing chamber. The integrated metrology chamber 28 may include any of a variety of metrology devices for measuring various film properties such as thickness, roughness, composition, and may further be capable of characterizing lattice parameters such as critical dimensions, sidewall angles, and feature heights in an automated manner under vacuum.

[0024]

[0028] Each of the processing chambers 24a-d may be configured to perform one or more process steps in the fabrication of semiconductor structures, and any number and combination of processing chambers may be used on the multi-chamber processing system 10. For example, any of the processing chambers may be configured to perform a number of substrate processing operations, including any number of deposition processes, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations, such as etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate treatments. Some specific processes that may be performed in any of the chambers, or combinations of chambers, may be metal deposition, surface cleaning and treatment, thermal annealing, such as rapid thermal processing, and plasma treatment. As will be readily appreciated by those skilled in the art, any other process may be similarly performed in a particular chamber incorporated in the multi-chamber processing system 10, including any of the processes described below.

[0025]

[0029] FIG. 2 shows a schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a layer of material disposed on a substrate 302 within the processing chamber 100. While the exemplary processing chamber 100 is suitable for performing a patterning process, it should be understood that aspects of the present technique may be performed in any number of chambers, and substrate supports according to the present technique may be included in an etch chamber, a deposition chamber, a processing chamber, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 that defines a chamber volume 101 in which a substrate may be processed. The chamber body 105 may have sidewalls 112 and a bottom 118, which are coupled to a ground 126. The sidewalls 112 may have a liner 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and associated components of the plasma processing chamber 100 are not limiting and may generally be larger in proportion to the size of the substrate 302 to be processed therein. Examples of substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, among others, such as display or solar cell substrates.

[0026]

[0030] The chamber body 105 supports the chamber lid assembly 110 and encloses the chamber volume 101. The chamber body 105 may be fabricated from aluminum or other suitable materials. A substrate access port 113 is formed through a sidewall 112 of the chamber body 105 to facilitate transfer of the substrate 302 into and out of the plasma processing chamber 100. The access port 113 may be coupled to a transfer chamber and / or other chambers of a substrate processing system as previously described. A pumping port 145 is formed through the sidewall 112 of the chamber body 105 and may be connected to the chamber volume 101. A pumping device may be coupled to the chamber volume 101 through the pumping port 145 to evacuate and control the pressure in the processing space. The pumping apparatus may include one or more pumps and a throttle valve.

[0027]

[0031] The gas panel 160 may be coupled to the chamber body 105 by gas lines 167 to supply process gases into the chamber volume 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may further include inert, non-reactive, and reactive gases that may be used for any number of processes. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gases, including argon gas, chlorine, nitrogen, helium, and oxygen gas. Additionally, the process gases may include nitrogen, chlorine, fluorine, oxygen, and hydrogen-containing gases such as BCl3, CF4, C2F4, C4F8, C4F6, CHF3, CH2F2, CH3F, NF3, NH3, CO2, SO2, CO, N2, NO2, N2O, and H2, among any number of additional precursors.

[0028]

[0032] The valves 166 may control the flow of process gas from the sources 161, 162, 163, 164 of the gas panel 160 and may be managed by a controller 165. The flow of gas supplied from the gas panel 160 to the chamber body 105 may include a combination of gases from one or more sources. The lid assembly 110 may include a nozzle 114. The nozzle 114 may be one or more ports for introducing process gases from the sources 161, 162, 164, 163 of the gas panel 160 into the chamber volume 101. After the process gases are introduced into the plasma processing chamber 100, the gases may be activated to form a plasma. An antenna 148, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 100. The antenna power supply 142 may feed the antenna 148 via the matching network 141 to inductively couple energy (e.g., RF energy) to the process gas to maintain a plasma formed from the process gas within the chamber volume 101 of the plasma processing chamber 100. Alternatively or in addition to the antenna power supply 142, a process electrode below and / or above the substrate 302 may be used to capacitively couple RF power to the process gas to maintain a plasma within the chamber volume 101. The operation of the power supply 142 may be controlled by a controller (e.g., controller 165), which also controls the operation of other components in the plasma processing chamber 100.

[0029]

[0033] A substrate support pedestal 135 may be disposed in the chamber space 101 to support the substrate 302 during processing. The substrate support pedestal 135 may include an electrostatic chuck 122 for holding the substrate 302 during processing. The electrostatic chuck ("ESC") 122 may hold the substrate 302 to the substrate support pedestal 135 using electrostatic attraction. The ESC 122 may be powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 may include an electrode 121 embedded in a dielectric. The electrode 121 may be coupled to the RF power supply 125 to provide a bias that attracts plasma ions formed by the processing gas in the chamber space 101 to the ESC 122 and the substrate 302 secured on the pedestal. The RF power supply 125 may be cycled on and off or pulsed during processing of the substrate 302. The ESC 122 may have insulation 128 to reduce the attraction of the sidewalls of the ESC 122 to the plasma to extend the maintenance life of the ESC 122. Additionally, the substrate support pedestal 135 may have a cathode liner 136 to protect the sidewalls of the substrate support pedestal 135 from the plasma gases and to extend the maintenance intervals of the plasma processing chamber 100.

[0030]

[0034] The electrode 121 may be coupled to a power supply 150. The power supply 150 may provide a chucking voltage of about 200 volts to about 2000 volts to the electrode 121. The power supply 150 may also include a system controller for controlling the operation of the electrode 121 by directing a DC current to the electrode 121 for chucking and dechucking the substrate 302. The ESC 122 may include a heater disposed in a pedestal and connected to a power supply to heat the substrate. Meanwhile, the cooling base 129 supporting the ESC 122 may include a conduit for circulating a heat transfer fluid to maintain the temperature of the ESC 122 and the substrate 302 disposed thereon. The ESC 122 may be configured to operate within a temperature range required by the thermal budget of a device fabricated on the substrate 302. For example, the ESC 122 may be configured to maintain the substrate 302 at a temperature of about −150° C. or lower to about 500° C. or higher depending on the process being performed.

[0031]

[0035] A cooling base 129 may be provided to assist in temperature control of the substrate 302. To mitigate process drift and time, the temperature of the substrate 302 may be maintained substantially constant by the cooling base 129 throughout the time the substrate 302 is in the cleaning chamber. In some implementations, the temperature of the substrate 302 may be maintained throughout the subsequent cleaning steps at a temperature between about −150° C. and about 500° C., although any temperature may be utilized. A cover ring 130 may be disposed over the ESC 122 and along the periphery of the substrate support pedestal 135. The cover ring 130 may be configured to contain the etching gases in a desired portion of the exposed upper surface of the substrate 302 while shielding the upper surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. As previously described, lift pins may be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135 to facilitate access to the substrate 302 by a transfer robot or other suitable transfer mechanism.

[0032]

[0036] The controller 165 may be utilized to regulate gas flows and other process parameters from the gas panel 160 to the plasma processing chamber 100 and to control the process sequence. The software routines, when executed by the CPU, transform the CPU into a special purpose computer (such as a controller) that can control the plasma processing chamber 100, such that processes are performed according to the present disclosure. The software routines may also be stored and / or executed by a second controller associated with the plasma processing chamber 100.

[0033]

[0037] The above-mentioned processing chambers may be used during methods according to embodiments of the present technology. FIG. 3 illustrates a method 300 of semiconductor processing, which may be performed, for example, in one or more chambers 100 incorporated in a multi-chamber processing system 10 as described above. Other chambers may also be utilized to perform one or more of the methods or processes described. The method 300 may include one or more processes before the start of the described processes, including front-end processes, deposition, etching, polishing, cleaning, or any other process that may be performed before the described processes. The method may include a number of optional processes as shown in the drawings, which may or may not be specifically related to the method according to the present technology. For example, many of the processes are described to provide a broader scope of semiconductor processes, but are not critical to the technology or may be performed by alternative methodologies, as described further below.

[0034]

[0038] The method 300 may include multiple processes that may be performed in multiple variations, including starting with different processes of the process. The method 300 may generally include an etching process. Although the method 300 is described in a particular order, it should be understood that the method may be performed in multiple different variations according to the implementation of the present technology. The method 300 may describe the processes shown generally in FIGS. 4A-4B, which illustrations are described in conjunction with the processes of the method 300. It should be understood that the structure 400 in FIGS. 4A-4B shows only a partial schematic view, and that the substrate 405 may include any number of structural portions having the aspects as shown, and alternative structural aspects that may still benefit from the processes of the present technology.

[0035]

[0039] Referring to FIG. 4A, the structure 400 may include a substrate 405. The substrate 405 may be disposed in a processing region of a semiconductor processing chamber. The substrate 405 may have a substantially flat or textured surface in embodiments. The substrate 405 may be a material such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafer, patterned or unpatterned wafer, silicon-on-insulator, carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 405 may have a variety of dimensions, such as 200 mm or 300 mm diameter wafers, as well as rectangular or square panels. One or more layers of material may be formed along the substrate 405. As shown, the substrate 405 may include at least one layer 410 of silicon-containing material and at least one layer 415 of silicon and germanium-containing material. However, it is contemplated that the layers of material may be reversed such that at least one layer of silicon and germanium containing material 415 is disposed between the substrate 405 and at least one layer of silicon containing material 410. Additional layers may also be formed on the substrate 405. For example, the layers of silicon material and the layers of silicon and germanium material may be included in any number of layers and in any configuration, such as layers for gate-all-around formation with any number of wires, or layers for memory structures such as in a 3D NAND topography. In any number of embodiments, an additional layer of material 420 may be deposited on the at least one layer of silicon and germanium containing material 415 or the layer of silicon containing material for patterning or other processing. The additional layer of material 420 may be a photoresist material in some implementations of the present technology.

[0036]

[0040] The at least one layer 415 of silicon and germanium containing material may be characterized by any germanium concentration, but in some implementations, the material may be characterized by a germanium concentration of less than 50 at.% or about 50 at.%. In conventional techniques, the chemical similarity between silicon materials, such as polysilicon or amorphous silicon, and silicon and germanium containing materials, including silicon germanium, has prevented selective etching of silicon relative to silicon and germanium containing materials characterized by a germanium concentration of less than 50 at.% or about 50 at.%. When silicon and silicon germanium are generally exposed to an etchant, as the amount of Si-Si bonds increases in the silicon and germanium materials, the etch selectivity may decrease based on the reduced germanium concentration. However, as further described below, the precursors of the present technique may passivate the at least one layer 415 of silicon and germanium containing material and increase the etch selectivity of the at least one layer 410 of silicon containing material relative to the at least one layer 415 of silicon and germanium containing material. This may allow the technique to be applied to layers with low germanium concentrations. Thus, the at least one layer 415 of silicon and germanium containing material may be characterized by a germanium concentration of less than or about 45 at.%, less than or about 40 at.%, less than or about 35 at.%, less than or about 30 at.%, less than or about 25 at.%, less than or about 20 at.%, less than or about 15 at.%. In an embodiment, the at least one layer 415 of silicon and germanium containing material may be characterized by a germanium concentration of more than 50 at.%, which may result in an increased amount of germanium and therefore an increased etch selectivity compared to the at least one layer 410 of silicon containing material.

[0037]

[0041] In step 305, the method 300 may include providing one or more precursors. The precursors may be provided to a processing region of a semiconductor processing chamber. The method 300 may include providing a fluorine-containing precursor, a hydrogen-containing precursor, and / or a nitrogen-containing precursor. The fluorine-containing precursor that may be used in step 305 may be or may include any number of fluorine-containing precursors. For example, the fluorine-containing precursor may be or may include nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), fluoromethane (CH3F), difluoromethane (CH2F2), fluoroform (CHF3), any compound with carbon and fluorine, or any other fluorine compound including fluorine-containing compounds that do not contain oxygen. In some embodiments, the fluorine-containing precursor may include both NF3 and CF4. By introducing carbon such as CF4, the at least one layer 415 of silicon and germanium-containing material may be passivated and become more resistant to etching, as further described below. The hydrogen-containing precursor that may be used in step 305 may be or may include any number of hydrogen-containing precursors. The hydrogen-containing precursor may include diatomic hydrogen (H2), hydrazine (NH4), methane (CH4), or any other hydrogen compound, including hydrogen-containing precursors that do not contain oxygen. The nitrogen-containing precursor that may be used in step 305 may be or may include any number of nitrogen-containing precursors. The nitrogen-containing precursor may include diatomic nitrogen (N2), ammonia (NH3), NF3, or any other nitrogen compound that does not contain oxygen, although the nitrogen compound may include oxygen in some embodiments, such as nitrous oxide, nitric oxide, or other compounds. In some embodiments, any number of additional carrier gases may be included, such as helium, argon, or other materials that aid in the stability or generation of the plasma, although the precursors utilized in the embodiments may be limited to one or more fluorine-containing precursors, hydrogen-containing precursors, and / or nitrogen-containing precursors, as described above.

[0038]

[0042] The flow ratio of the hydrogen-containing precursor to any or all of the fluorine-containing precursors may be greater than or about 2.0:1, which may enable a polymerization reaction that aids in passivation of the silicon and germanium materials. At flow ratios less than 2.0:1, the plasma may not have enough hydrogen to passivate the at least one layer of silicon and germanium-containing material. As described further below, the precursors may interact to form a material having carbon, hydrogen, and fluorine on the at least one layer of silicon and germanium-containing material 415. The carbon, hydrogen, and fluorine materials may prevent the at least one layer of silicon and germanium-containing material 415 from being removed during subsequent processing. Thus, the flow ratio of hydrogen-containing precursor to fluorine-containing precursor can be greater than or about 2.5:1, greater than or about 3.0:1, greater than or about 3.5:1, greater than or about 4.0:1 for each fluorine-containing precursor, but the flow ratio can be less than or about 2.0:1 of the total flow of fluorine-containing precursor, such as when both carbon tetrafluoride and nitrogen trifluoride are utilized, and the flow ratio can be less than or about 1.8:1, less than or about 1.6:1, less than or about 1.5:1, less than or about 1.4:1, or less than the combined flow of all fluorine-containing precursors. In some embodiments, the hydrogen-containing flow rate can be controlled within a range that enhances the selectivity between silicon-containing materials and silicon and germanium-containing materials. As shown in Figure 5A, a particular hydrogen-containing precursor flow rate may result in higher etch selectivity than a lower and / or higher hydrogen-containing precursor flow rate. For example, a flow ratio of hydrogen-containing precursor to any individual fluorine-containing precursor less than or about 2.0:1 may result in lower etch selectivity due to reduced polymerization activity, although other embodiments are possible. Similarly, a flow ratio of individual fluorine-containing precursors greater than or about 6.0:1, for example, may result in lower etch selectivity due to effects on etchant generation and plasma creation.Thus, a flow rate of the hydrogen-containing precursor, and thus a flow rate ratio of the hydrogen-containing precursor to the fluorine-containing precursor between about 2.0:1 and about 6.0:1, may result in higher etch selectivity.

[0039]

[0043] The flow rate of each individual fluorine-containing precursor may be greater than or about 20 sccm. The flow rate of the fluorine-containing precursor may be measured as the cumulative flow rate of all fluorine-containing precursors. If the combined fluorine-containing precursor flow rate is less than 40 sccm, there may not be enough fluorine to passivate the at least one layer of silicon- and germanium-containing material 415 and / or etch the at least one layer of silicon-containing material 410, which may result in longer etching times and longer exposure of the silicon- and germanium-containing material to the etchant, resulting in reduced selectivity. Thus, the combined flow rate of the fluorine precursors may be greater than or about 50 sccm, greater than or about 60 sccm, greater than or about 70 sccm, greater than or about 80 sccm, greater than or about 90 sccm, greater than or about 100 sccm, greater than or about 110 sccm. Additionally, the flow rate of the fluorine-containing precursor may be adjusted depending on the amount of passivation and / or etching desired for a particular application.

[0040]

[0044] The flow rate of the hydrogen-containing precursor may be greater than or about 40 sccm. The flow rate of the hydrogen-containing precursor may be measured as the cumulative flow rate of all hydrogen-containing precursors. At flow rates below 40 sccm, there may not be enough hydrogen to promote polymerization for passivation of the at least one layer of silicon- and germanium-containing material 415 and / or etching of the at least one layer of silicon-containing material. Thus, the flow rate of the hydrogen-containing precursor may be greater than or about 50 sccm, greater than or about 60 sccm, greater than or about 70 sccmm, greater than or about 80 sccm, greater than or about 90 sccm, greater than or about 100 sccm, greater than or about 110 sccm, greater than or about 120 sccm, greater than or about 130 sccm, greater than or about 140 sccm, greater than or about 150 sccm, greater than or about 160 sccm, greater than or about 170 sccm, greater than or about 180 sccm, greater than or about 190 sccm, greater than or about 200 sccm, greater than or about 210 sccm, greater than or about 220 sccm, greater than or about 230 sccm, greater than or about 240 sccm, greater than or about 250 sccm, greater than or about 260 sccm, greater than or about 270 sccm, greater than or about 280 sccm, greater than or about 290 sccm, greater than or about 300 sccm, greater than or about 310 sccm, greater than or about 320 sccm, greater than or about 330 sccm, greater than or about 340 sccm, greater than or about 350 sccm, greater than or about 360 sccm, greater than or about 370 sccm, greater than or about 380 sccm, greater than or about 390 sccm, greater than or about 400 sccm, ccm, greater than or about 140 sccm, greater than or about 150 sccm, greater than or about 160 sccm, greater than or about 170 sccm, greater than or about 180 sccm, greater than or about 190 sccm, greater than or about 200 sccm, greater than or about 210 sccm, greater than or about 220 sccm, or greater than or about 220 sccm. Additionally, the flow rate of the hydrogen-containing precursor may be adjusted depending on the amount of passivation and / or etching desired for a particular application.

[0041]

[0045] The flow ratio of the nitrogen-containing precursor to the fluorine-containing precursor can be greater than or about 1:5. At flow rates less than 1:5, there may not be enough nitrogen present to passivate the at least one layer of silicon- and germanium-containing material 415 and / or etch the at least one layer of silicon-containing material. Thus, the flow ratio of the nitrogen-containing precursor to the fluorine-containing precursor may be greater than or about 1:4, greater than or about 1:3, greater than or about 1:2, greater than or about 1:1, greater than or about 3:2, or more.

[0042]

[0046] In embodiments, one or more inert precursor or carrier gases may also be provided in step 305. In embodiments, the inert precursor may be or include argon, helium, or other noble metals or inert materials. In embodiments using argon compared to helium, etch selectivity may be improved due to the lower activation energy of argon compared to helium. The lower activation energy of argon may be due to the higher ion bombardment energy of argon, which may increase the overall etch rate and facilitate the etching process.

[0043]

[0047] In an embodiment, the flow rate of the inert precursor may be less than or greater than the flow rate of the fluorine-containing precursor. In an embodiment, the flow rate of the inert precursor may be less than or about 200 sccm, less than or about 190 sccm, less than or about 180 sccm, less than or about 170 sccm, less than or about 160 sccm, less than or about 150 sccm, less than or about 140 sccm, less than or about 130 sccm, less than or about 120 sccm, less than or about 110 sccm, less than or about 100 sccm, or less than that. In an embodiment, the flow rate of the inert precursor may be decreased and the flow rate of the nitrogen-containing precursor may be increased. Increasing the flow rate of the nitrogen-containing precursor may generate additional salts at the surface of the at least one layer of silicon-containing material 410 and the at least one layer of silicon- and germanium-containing material 415 via the formation of NHF, as further described below.

[0044]

[0048] In step 310, the method 300 may include forming a plasma. The plasma may be formed from a fluorine-containing precursor, a hydrogen-containing precursor, a nitrogen-containing precursor, and / or an inert precursor. The plasma may be formed in a processing region of a semiconductor processing chamber. In an embodiment, a processing chamber, such as one of the chambers 100 incorporated in the multi-chamber processing system 10, may have two or more source plasma power sources or electrodes. The method 300 may include providing power to one or less than all of the source plasma power sources. The formation of the plasma may be performed with a source plasma power of less than or about 1,000 W. A source plasma power of more than or about 1,000 W may increase the plasma temperature and etching capacity, increasing the removal of silicon germanium by salt decomposition, and may decrease selectivity based on increased surface reactions, as described further below. Thus, the formation of plasma may be performed with a source plasma power of less than or about 950W, less than or about 850W, less than or about 800W, less than or about 750W, less than or about 650W, less than or about 600W, or less than or about 600W. Furthermore, if the source plasma power is less than or about 100W, the etching process may be slowed down, the residence time of the etchant may be increased, and the selectivity may be reduced. Thus, the formation of plasma may be performed with a source plasma power of more than or about 150W, more than or about 200W, more than or about 250W, more than or about 300W, more than or about 350W, more than or about 400W, or more than or about 400W. Figure 5B is a graphical representation of the relationship between source plasma power and etch selectivity. A higher source plasma power may result in a lower etch selectivity. Similarly, a lower source plasma power may result in a lower etch selectivity. Thus, a source plasma power between about 300 W and about 800 W may provide a higher etch selectivity.

[0045]

[0049] In an embodiment, the plasma of the carbon-containing precursor, the hydrogen-containing precursor, the nitrogen-containing precursor, and / or the inert precursor may or may not be biased. The bias applied to the plasma of the carbon-containing precursor, the hydrogen-containing precursor, the nitrogen-containing precursor, and / or the inert precursor may be generated with a bias power of less than or about 100 W. At a bias power of more than 100 W, the interaction between the precursor(s) and the structure 400 may become more physical and less chemical. A greater physical interaction may result in a decrease in the selectivity of removal, and the at least one layer of silicon-containing material 410 and the at least one layer of silicon- and germanium-containing material 415 may be removed at approximately equal rates, such as an etch selectivity approaching 1:1. Thus, the bias power applied to the plasma may be less than or about 90W, less than or about 80W, less than or about 70W, less than or about 60W, less than or about 50W, less than or about 40W, less than or about 30W, less than or about 20W, less than or about 10W, or in some embodiments, no bias may be applied at all, which may further improve selectivity.

[0046]

[0050] The plasma of the fluorine-containing precursor, hydrogen-containing precursor, nitrogen-containing precursor, and / or inert precursor may be generated at a duty cycle of less than or about 50%. By operating at a duty cycle of less than or about 50%, the plasma power of the effective source and bias, if used, may be reduced to maintain the reaction as a chemical reaction rather than a physical reaction. Thus, the plasma may be generated at a duty cycle of less than or about 45%, less than or about 40%, less than or about 35%, less than or about 30%, less than or about 25%, less than or about 20%, less than or about 15%, less than or about 10%, or less than or about 10%.

[0047]

[0051] In an embodiment, the method 300 can include pulsing the source plasma power while generating plasma effluent of the precursor. In embodiments, the source plasma power may be pulsed at frequencies of less than or about 1,000 Hz, less than or about 950 Hz, less than or about 950 Hz, less than or about 900 Hz, less than or about 850 Hz, less than or about 850 Hz, less than or about 800 Hz, less than or about 750 Hz, less than or about 700 Hz, less than or about 650 Hz, less than or about 600 Hz, less than or about 550 Hz, less than or about 500 Hz, less than or about 450 Hz, less than or about 400 Hz, less than or about 350 Hz, less than or about 300 Hz, less than or about 250 Hz, less than or about 200 Hz, or less than or about 200 Hz.

[0048]

[0052] In an embodiment, the plasma may be oxygen-free. In the prior art where oxygen may be present in the plasma, the at least one layer of silicon-containing material 410 and / or the at least one layer of silicon- and germanium-containing material 415 may oxidize to form Si-O bonds. Si-O bonds may have higher bond energy than Si-Si bonds, Si-Ge bonds, or Ge-Ge bonds and therefore may be less likely to be etched. If the at least one layer of silicon-containing material 410 is oxidized to form Si-O bonds, it may be more difficult to remove the at least one layer of silicon-containing material 410 and the etch selectivity may be reduced. Furthermore, the presence of oxygen may at least partially oxidize the at least one layer of silicon- and germanium-containing material and other materials 415, reducing the mobility of charge carriers.

[0049]

[0053] The plasma effluents may undergo a gas-phase reaction before contacting the structure 400. The gas-phase reaction may form intermediates that may react with the at least one layer of silicon-containing material 410 and the at least one layer of silicon- and germanium-containing material 415. For example, the precursors may react to form a passivation compound and an etching compound. The passivation compound may include a carbon material, a hydrogen material, and a fluorine material. The passivation compound may form a material on the at least one layer of silicon- and germanium-containing material 415. The material formed by the passivation compound may create a porous coating that may limit the removal of germanium. During the removal of the silicon material, some silicon may be removed through the openings or pores in the passivation material. The removal of silicon may result in an increase in the concentration of germanium at the surface of the at least one layer of silicon- and germanium-containing material 415. The germanium may not be easily removed through the passivation material. The etching compound may include a nitrogen material, a hydrogen material, and a fluorine material. The etching compound may simultaneously assist in passivating the at least one layer of silicon- and germanium-containing material 415 and increase the etch selectivity of the at least one layer of silicon-containing material 410 .

[0050]

[0054] In step 315, the method 300 may include contacting the at least one layer of silicon-containing material 410 and the at least one layer of silicon- and germanium-containing material 415 with plasma effluents of precursors, including fluorine-containing precursors and hydrogen-containing precursors. The nitrogen, hydrogen, and fluorine materials of the precursors may form salts, such as ammonium salts, on the at least one layer of silicon-containing material 410 and / or the at least one layer of silicon- and germanium-containing material 415. The salts formed on the at least one layer of silicon-containing material 410 may have a lower decomposition temperature than the salts formed on the at least one layer of silicon- and germanium-containing material 415.

[0051]

[0055] For example, the salt formed on the at least one layer of silicon-containing material 410 may be or include ammonium silicofluoride, and the salt formed on the at least one layer of silicon- and germanium-containing material 415 may be or include ammonium hexafluorogermanate. Ammonium silicofluoride may have a standard decomposition temperature of about 130° C., and ammonium hexafluorogermanate may have a standard decomposition temperature of about 380° C. Method 300 may be performed at temperatures and other process conditions that allow for the sublimation of ammonium silicofluoride while minimizing or preventing the sublimation of ammonium hexafluorogermanate. That is, method 300 may be performed at temperatures, pressures, and plasma powers that allow the ammonium hexafluorogermanate to remain on the at least one layer of silicon- and germanium-containing material 415. When method 300 is performed at a temperature below the decomposition temperature of ammonium silicofluoride, the plasma may raise the temperature in the processing region such that the ammonium silicofluoride may decompose. As the ammonium silicofluoride sublimes, the at least one layer 410 of silicon-containing material may be etched as ammonium silicofluoride, and the at least one layer 410 of silicon-containing material may be decomposed into one or more volatiles that may then be purged from the processing region.

[0052]

[0056] At step 320, the method 300 may include at least partially removing or recessing the at least one layer of silicon-containing material 410. The at least one layer of silicon-containing material 410 may be removed at a higher rate than the at least one layer of silicon- and germanium-containing material 415. The at least one layer of silicon-containing material 410 may be selectively removed at a rate of greater than or about 3:2 relative to the at least one layer of silicon- and germanium-containing material 415. In embodiments, the at least one layer of silicon-containing material 410 may be selectively removed at a rate of greater than or about 2:1, greater than or about 3:1, greater than or about 4:1, greater than or about 5:1, greater than or about 6:1, greater than or about 7:1, or more relative to the at least one layer of silicon- and germanium-containing material 415.

[0053]

[0057] The etch rate can be adjusted depending on the flow rate of the precursors and the characteristics of the plasma power including source plasma power, bias plasma power, duty cycle, and frequency. In an embodiment, the etch rate of the at least one layer 410 of silicon-containing material can be greater than or about 15.0 Å / s, greater than or about 16.0 Å / s, greater than or about 17.0 Å / s, greater than or about 18.0 Å / s, greater than or about 19.0 Å / s, greater than or about 20.0 Å / s, greater than or about 21.0 Å / s, 22.0 Å / s, or greater than or about 23.0 Å / s. The rate may be greater than or about 22.0 Å / s, greater than or about 23.0 Å / s, greater than or about 24.0 Å / s, greater than or about 25.0 Å / s, greater than or about 26.0 Å / s, greater than or about 27.0 Å / s, greater than or about 28.0 Å / s, greater than or about 29.0 Å / s, greater than or about 30.0 Å / s, or even greater.

[0054]

[0058] During the method 300, the temperature within the semiconductor processing chamber, such as the substrate support temperature or the substrate temperature, may be maintained below or at about 125° C. At temperatures above 125° C., etching by-products of both silicon and silicon and germanium may volatilize, increasing etching of silicon germanium material and decreasing the etch selectivity of at least one layer of silicon-containing material 410 relative to at least one layer of silicon- and germanium-containing material 415. Thus, the temperature within the semiconductor processing chamber may be maintained at less than or about 120°C, less than or about 115°C, less than or about 115°C, less than or about 110°C, less than or about 105°C, less than or about 100°C, less than or about 95°C, less than or about 80°C, less than or about 75°C, less than or about 70°C, less than or about 65°C, less than or about 60°C, less than or about 55°C, less than or about 50°C, or temperatures below that.

[0055]

[0059] Additionally, the pressure in the semiconductor processing chamber may be maintained at less than or about 200 mTorr. At pressures greater than 200 mTorr, forming a plasma may be more difficult and the method 300 may be more susceptible to producing unwanted by-products. Additionally, pressures greater than 200 mTorr may result in a more isotropic etch profile and may reduce etch selectivity. Thus, the pressure in the semiconductor processing chamber may be less than or about 190 mTorr, less than or about 180 mTorr, less than or about 170 mTorr, less than or about 160 mTorr, less than or about 150 mTorr, less than or about 140 mTorr, less than or about 130 mTorr, less than or about 120 mTorr, less than or about 110 mTorr, less than or about 110 mTorr, less than or about 12 ... In some embodiments, the pressure may be maintained at a pressure of less than or about 100 mTorr, less than or about 90 mTorr, less than or about 90 mTorr, less than or about 80 mTorr, less than or about 70 mTorr, less than or about 60 mTorr, less than or about 50 mTorr, less than or about 40 mTorr, less than or about 30 mTorr, less than or about 20 mTorr, less than or about 10 mTorr, or less than or about 10 mTorr.

[0056]

[0060] Although the above description, for purposes of explanation, includes numerous details to facilitate an understanding of various embodiments of the present technology, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details or with additional implementation details.

[0057]

[0061] Although several embodiments have been disclosed, it will be recognized by those skilled in the art that various modifications, alternative structures, and equivalents may be used without departing from the essence of the embodiments. In addition, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the technology. Therefore, the above description should not be interpreted as limiting the scope of the technology.

[0058]

[0062] Where a range of values ​​is provided, each intervening value between the upper and lower limits of that range is understood to be specifically disclosed to the smallest unit of the lower limit (unless the context clearly dictates otherwise). Narrower ranges between any stated or unstated intervening values ​​in a stated range, as well as all other stated or intervening values ​​in such stated range, are included. The upper and lower limits of the above narrower ranges may be individually included or excluded from the range. Each range in which either, neither or both limits are included in the narrower range is also encompassed within the technology, provided that there is a specifically excluded limit in the stated range. Where a stated range includes one or both limits, ranges excluding either or both of the included limits are also included.

[0059]

[0063] As used herein and in the appended claims, the singular forms "a," "an," and "the" include the plural (unless the context clearly dictates otherwise). Thus, for example, reference to "a fluorine-containing precursor" includes a plurality of such precursors, and reference to "the at least one layer of silicon-containing material" includes a reference to one or more such materials and equivalents known to those skilled in the art, and so forth.

[0060]

[0064] Additionally, the words "comprise(s) / comprising", "contain(s) / containing" and "include(s) / including" when used in this specification and the following claims are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, acts or groups.

Claims

1. 1. A semiconductor processing method comprising: providing a fluorine-containing precursor and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber, the substrate being disposed in the processing region of the semiconductor processing chamber, the substrate including at least one layer of a silicon-containing material and at least one layer of a silicon- and germanium-containing material along with the substrate; forming a plasma of the fluorine-containing precursor and the hydrogen-containing precursor in the processing region; contacting at least one layer of said silicon-containing material and at least one layer of said silicon- and germanium-containing material with plasma effluents of said fluorine-containing precursor and said hydrogen-containing precursor; removing the at least one layer of silicon-containing material at a rate greater than the at least one layer of silicon and germanium-containing material; A method comprising:

2. 10. The semiconductor processing method of claim 1, wherein the fluorine-containing precursor comprises one or both of nitrogen trifluoride and carbon tetrafluoride.

3. 10. The semiconductor processing method of claim 1, wherein the at least one layer of silicon-containing material is selectively removed at a rate greater than or about 2:1 relative to the at least one layer of silicon and germanium-containing material.

4. 10. The semiconductor processing method of claim 1, wherein the plasma of the fluorine-containing precursor and the hydrogen-containing precursor is generated at a source plasma power of less than or about 1,000W.

5. 10. The semiconductor processing method of claim 1, wherein a bias applied to the plasma of the fluorine-containing precursor and the hydrogen-containing precursor is generated with a bias power of less than or about 100W.

6. 10. The semiconductor processing method of claim 1, wherein the plasma of the fluorine-containing precursor and the hydrogen-containing precursor is generated at a duty cycle of less than or about 50%.

7. 5. The semiconductor processing method of claim 4, further comprising pulsing a source plasma power while forming the plasma effluents of the fluorine-containing precursor and the hydrogen-containing precursor, wherein the source plasma power is pulsed at a frequency of less than or about 1000 Hz.

8. a temperature within the semiconductor processing chamber is maintained at or below 125° C.; The pressure in the semiconductor processing chamber is maintained at less than or about 200 mTorr.

10. The semiconductor processing method of claim 1.

9. providing an inert precursor in the processing region of the semiconductor processing chamber comprising the fluorine-containing precursor and the hydrogen-containing precursor, the inert precursor comprising a nitrogen-containing inert precursor, an argon-containing inert precursor, a helium-containing inert precursor, or a combination thereof; The semiconductor processing method of claim 1 further comprising:

10. 10. The semiconductor processing method of claim 1, wherein the flow ratio of said hydrogen-containing precursor to said fluorine-containing precursor is greater than or about 2:

1.

11. The semiconductor processing method of claim 1 , wherein the plasma is oxygen-free.

12. 1. A semiconductor processing method comprising: providing a fluorine-containing precursor, a hydrogen-containing precursor, and a nitrogen-containing precursor; forming a plasma of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor; contacting at least one layer of silicon-containing material and at least one layer of silicon- and germanium-containing material along a substrate with plasma effluents of the fluorine-containing precursor, the hydrogen-containing precursor, and the nitrogen-containing precursor, wherein the contacting selectively removes the at least one layer of silicon-containing material; A semiconductor processing method comprising:

13. the fluorine-containing precursor comprises carbon tetrafluoride; the nitrogen-containing precursor comprises nitrogen trifluoride; 13. The semiconductor processing method of claim 12.

14. 13. The semiconductor processing method of claim 12, wherein the fluorine-containing precursor and the nitrogen-containing precursor, when contacted with the at least one layer of silicon-containing material and the at least one layer of silicon- and germanium-containing material, form a passivation compound and an etching compound, the passivation compound comprising a carbon material, a hydrogen material, and a fluorine material, and the etching compound comprising a nitrogen material, a hydrogen material, and a fluorine material.

15. 13. The semiconductor processing method of claim 12, wherein the pressure is maintained at less than or about 70 mTorr during the semiconductor processing method.

16. 13. The semiconductor processing method of claim 12, wherein the at least one layer of silicon and germanium containing material is characterized by a germanium concentration of less than or about 50 at. %.

17. 15. The semiconductor processing method of claim 14, wherein said etching compound removes said at least one layer of silicon-containing material with a selectivity of greater than or about 3:2 relative to said at least one layer of silicon and germanium-containing material.

18. 13. The semiconductor processing method of claim 12, further comprising providing a hydrogen-containing precursor and an inert precursor along with said fluorine-containing precursor and said nitrogen-containing precursor.

19. the fluorine-containing precursor, the nitrogen-containing precursor, the hydrogen-containing precursor, and the inert precursor form the passivation compound and the etching compound; the passivation compound passivates the at least one layer of silicon and germanium containing material; the etching compound removes at least one layer of the silicon-containing material; 15. The semiconductor processing method of claim 14.

20. 1. A semiconductor processing method comprising: providing a fluorine-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber, the substrate being disposed in the processing region of the semiconductor processing chamber, the substrate including at least one layer of a silicon-containing material and at least one layer of a silicon- and germanium-containing material along with the substrate; forming a plasma of the fluorine-containing precursor and the nitrogen-containing precursor in the processing region, the plasma being generated at a discontinuous plasma power of less than or about 1,000 W; contacting the at least one layer of silicon-containing material and the at least one layer of silicon- and germanium-containing material with plasma effluents of the fluorine-containing precursor and the nitrogen-containing precursor, wherein the contacting passivates the at least one layer of silicon- and germanium-containing material; removing the at least one layer of silicon-containing material at a rate greater than the at least one layer of silicon- and germanium-containing material, wherein the at least one layer of silicon-containing material is selectively removed at a rate greater than or about 3:2 relative to the at least one layer of silicon- and germanium-containing material; A method comprising:

Images