Embedded Magnetoresistive Random Access Memory

Abstract

An embodiment of a system is disclosed. The system includes a semiconductor structure including a wafer, a plurality of transistors, and a magnetoresistive random access memory (MRAM) cell disposed on a backside of the wafer. The transistors are disposed on a front-end-of-line (FEOL) of the wafer. The MRAM cell is connected to a source-drain of the transistor by contacts disposed on the backside of the wafer. The transistor is in direct electrical contact with the MRAM cell by at least one contact.

Description

[Technical field]

[0001] This disclosure relates to random access memories (RAMs), and more particularly to embedded magnetoresistive RAMs. [Background technology]

[0002] Magnetoresistive RAM (MRAM) is a type of solid-state non-volatile memory that uses tunneling magnetoresistance to store information and can be integrated into embedded non-volatile memory (ENVM) devices. Such ENVM devices can also be called embedded MRAM (EMRAM) and can include spin-transfer torque MRAM (STT-MRAM) or spin-orbit torque MRAM (SOT-MRAM). However, wafers with EMRAM can be fabricated in the back-end-of-line (BEOL) of the actual semiconductor wafer. BEOL can refer to the integration that takes place after transistor formation in the front-end-of-line (FEOL).

[0003] Moreover, due to the routing complexities in BEOL, STT-MRAM may be placed far back in the backend, which may result in high resistance. Backside EMRAM means that the embedded memory has the transistors on the opposite side. Commercially available memory devices typically have the transistors and memory on the same side. Such high resistance may result in area loss. Moreover, for SOT-MRAM, which may be configured in a three-terminal design, the area loss may be even greater. In addition, placing STT-MRAM far back in the backend may increase the cost of fabricating such devices due to integration complexities. Summary of the Invention

[0004] An embodiment is disclosed that relates to a system. The system includes a semiconductor structure. The semiconductor structure includes a wafer, a plurality of transistors, and a magnetoresistive random access memory (MRAM) cell disposed on a backside of the wafer. The transistors are disposed on a front end of the line (FEOL) of the wafer. The MRAM cell is connected to a source-drain of the transistor by contacts disposed on the backside of the wafer. The transistor is in direct electrical contact with the MRAM cell by at least one contact. Advantageously, such an embodiment reduces resistance and may be less expensive to fabricate than a wafer having MRAM cells on the same side of the wafer as the transistors.

[0005] Additionally, an embodiment is disclosed relating to a method of fabricating a semiconductor structure. The method includes performing a post wafer flip of a wafer having a plurality of transistors disposed on a front end of line (FEOL) of the wafer. The method also includes performing a back grinding of the wafer. The method further includes removing a sacrificial plug from the back side of the wafer. The method additionally includes forming a contact in place of the sacrificial plug. The method also includes performing a deposition of a heavy metal spin Hall effect (SHE) rail on the back side of the wafer to generate an SHE rail. Further, the method includes performing a deposition of a magnetic tunnel junction (MTJ) stack on the SHE rail to generate an MTJ stack. Additionally, the method includes performing a patterning of the MTJ on the MTJ stack. The method also includes performing a formation of an ion beam etched (IBE) pillar on the patterned MTJ stack to generate an IBE pillar. The method further includes performing a dielectric encapsulation on the SHE rail and the IBE pillar. The method additionally includes performing a reactive ion etch (RIE) of a self-aligned encapsulation dielectric and formation of the SHE rail. The method also includes performing an inter-layer dielectric (ILD) fill and chemical mechanical polishing (CMP) on the IBE pillar and the SHE rail. Further, the method includes performing a landing of the MTJ top contact on the IBE pillar. Advantageously, such an embodiment reduces resistance and can be less expensive to fabricate than a wafer having MRAM cells on the same side of the wafer as the transistors.

[0006] Further aspects of the invention are directed to computer program products having functionality similar to that discussed above with respect to the computer-implemented methods.This Summary is not intended to represent each aspect, every implementation, or every embodiment, or combination, of the invention.

[0007] The drawings contained in this application are incorporated in and form a part of this specification. These drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. These drawings are only illustrative of particular embodiments and are not intended to limit the invention. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram of an example embedded magnetoresistive random access memory (EMRAM) fabrication manager in accordance with some embodiments of the present invention. [Diagram 2] 1 is a cross-sectional view of an exemplary complementary metal oxide semiconductor (CMOS) device having backside EMRAM in accordance with some embodiments of the present invention. [Diagram 3] 1 is a process flow for a method of fabricating a CMOS device with backside EMRAM in accordance with some embodiments of the present invention. [Figure 4A] 1A-1D are cross-sectional views of an exemplary fabrication stage of a wafer according to some embodiments of the present invention. [Figure 4B] 1A-1D are cross-sectional views of an exemplary fabrication stage of a wafer according to some embodiments of the present invention. [Figure 4C] 1A-1D are cross-sectional views of an exemplary fabrication stage of a wafer according to some embodiments of the present invention. [Figure 4D] 1A-1D are cross-sectional views of an exemplary fabrication stage of a wafer according to some embodiments of the present invention. [Figure 4E] 1A-1D are cross-sectional views of an exemplary fabrication stage of a wafer according to some embodiments of the present invention. [Figure 4F] 1A-1D are cross-sectional views of an exemplary fabrication stage of a wafer according to some embodiments of the present invention. [Figure 4G] 1A-1D are cross-sectional views of an exemplary fabrication stage of a wafer according to some embodiments of the present invention. [Figure 4H] 1A-1D are cross-sectional views of an exemplary fabrication stage of a wafer according to some embodiments of the present invention. [Figure 4I]1A-1D are cross-sectional views of an exemplary fabrication stage of a wafer according to some embodiments of the present invention. [Figure 4J] FIG. 2 is a side perspective view of a wafer having CMOS devices including backside EMRAM according to some embodiments of the present invention. [Diagram 5] 1 is a cross-sectional view of an exemplary CMOS device having backside EMRAM in accordance with some embodiments of the present invention. [Figure 6A] 1 is a cross-sectional view of an exemplary CMOS device having backside EMRAM in accordance with some embodiments of the present invention. [Figure 6B] FIG. 2 is a side perspective view of a wafer having CMOS devices including backside EMRAM according to some embodiments of the present invention. [Figure 7] 1 is a cross-sectional view of an exemplary CMOS device having backside EMRAM in accordance with some embodiments of the present invention. [Figure 8] 1 is a cross-sectional view of an exemplary CMOS device having backside EMRAM in accordance with some embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] While the invention is susceptible to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It is to be understood, however, that the intention is not to limit the invention to the described embodiments. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the invention.

[0010] As mentioned above, embedded dynamic RAM (EDRAM) can incorporate non-volatile memory such as spin-transfer torque magnetoresistive RAM (STT-MRAM) or spin-orbit torque MRAM (SOT-MRAM). STT-MRAM can use spin-aligned ("polarized") electrons to directly apply a torque to a region of the MRAM cell. Specifically, electrons flowing into the layer can change their spin, producing a torque that is transferred to the adjacent layer of the memory device, thus writing to the MRAM cell. STT-MRAM can inject current perpendicularly into the magnetic tunnel junction. In contrast, SOT-MRAM devices can switch the MRAM cell in the free magnetic layer by injecting an in-plane current into the adjacent layer.

[0011] Also, as mentioned above, STT-MRAM may be placed far back on the back end of the wafer, which can be costly, cause high electromagnetic resistance, and lead to area loss, but for SOT-MRAM, which may be configured in a three-terminal design, the area loss can be even greater than for STT-MRAM.

[0012] Accordingly, some embodiments of the present invention may include backside EMRAM having transistors and MRAM cells. Backside EMRAM means that the embedded memory has transistors on the opposite side of the CMOS device, as opposed to commercially available memory devices that have the transistors and memory on the same side. Accordingly, some embodiments of the present invention may fabricate a wafer by placing the MRAM on the backside of the wafer, and may use backside contacts to connect the MRAM to front-end-of-line (FEOL) transistors. Furthermore, in such embodiments, the MRAM may be placed in contact with the backside of the transistors without an intervening metal layer. In this manner, some embodiments of the present invention may reduce the resistance penalty typically incurred by currently commercially available memory devices.

[0013] In this manner, some embodiments of the present invention may provide memory devices that represent an improvement over existing ENVM devices. In particular, such embodiments may reduce interconnect resistance, improve device performance, and reduce routing and wiring complexity in the BEOL.

[0014] FIG. 1 is a block diagram of an exemplary EDRAM fabrication manager 100 according to some embodiments of the present invention. In various embodiments, the exemplary EDRAM fabrication manager 100 can perform the method described in FIG. 3 or cause one or more machines to design, fabricate, or utilize, or combinations of, the components discussed in FIGS. 2, 4A-4J, 5, 6A, 6B, 7, and 8. In some embodiments, the exemplary EDRAM fabrication manager 100 provides instructions for the aforementioned methods and / or functions to a client machine, such that the client machine performs the method or portions of the method based on the instructions provided by the exemplary EDRAM fabrication manager 100. In some embodiments, the exemplary EDRAM fabrication manager 100 comprises software executing on hardware embedded in multiple devices.

[0015] The exemplary EDRAM fabrication manager 100 includes memory 125, storage 130, interconnect (e.g., bus) 120, one or more CPUs 105 (also referred to herein as processors 105), I / O device interface 110, I / O devices 112, and a network interface 115.

[0016] Each CPU 105 retrieves and executes programming instructions stored in memory 125 or storage 130. Interconnect 120 is used to move data, such as programming instructions, between CPU 105, I / O device interface 110, storage 130, network interface 115, and memory 125. Interconnect 120 may be implemented using one or more buses. In various embodiments, CPU 105 may be a single CPU, multiple CPUs, or a single CPU with multiple processing cores. In some embodiments, CPU 105 may be a digital signal processor (DSP). In some embodiments, CPU 105 includes one or more 3D integrated circuits (3DICs) (e.g., 3D wafer level packaging (3DWLP), 3D interposer based integration, 3D stacked integrated circuits (3D-SIC), monolithic 3D integrated circuits, 3D heterogeneous integration, 3D system-in-package (3DSiP), and / or package-on-package (PoP) CPU configurations). The memory 125 is generally representative of random access memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), or flash). The storage 130 is generally representative of non-volatile memory, such as a hard disk drive, a solid state device (SSD), a removable memory card, optical storage, or a flash memory device, or a combination thereof. In addition, the storage 130 may include a storage area network (SAN) device, cloud, or other device, and is connected to the exemplary EDRAM fabrication manager 100 via the I / O device interface 110 or to a network 150 via the network interface 115.

[0017] In some embodiments, memory 125 stores instructions 160. However, in various embodiments, instructions 160 are stored partially in memory 125 and partially in storage 130, or entirely in memory 125 or entirely in storage 130, or accessed by network 150 via network interface 115.

[0018] The instructions 160 may be processor-executable instructions for performing any portion or all of the methodology described in FIG. 3, or may cause one or more machines to design, make, or utilize, or combinations of, the components discussed in FIGS. 2, 4A-4J, 5, 6A, 6B, 7, and 8, or both.

[0019] In various embodiments, the I / O device 112 includes an interface capable of presenting information and receiving input. For example, the I / O device 112 can present information to and receive input from a listener that interacts with the exemplary EDRAM fabrication manager 100.

[0020] The exemplary EDRAM fabrication manager 100 is connected to a network 150 via a network interface 115. The network 150 may comprise a physical, wireless, cellular, or different network.

[0021] In some embodiments, the exemplary EDRAM fabrication manager 100 may be a multi-user mainframe computer system, a single-user system, or a server computer, or similar device, that has little or no direct user interface but receives requests from other computer systems (clients). Additionally, in some embodiments, the exemplary EDRAM fabrication manager 100 may be implemented as a desktop computer, a portable computer, a laptop or notebook computer, a tablet computer, a pocket computer, a telephone, a smartphone, a network switch or router, or any other suitable type of electronic device.

[0022] It should be noted that Figure 1 is intended to depict representative major components of an exemplary EDRAM fabrication manager 100. However, in some embodiments, the individual components may have greater or less complexity than depicted in Figure 1, there may be other or additional components than those shown in Figure 1, and the number, type, and configuration of such components may vary.

[0023] FIG. 2 is a cross-sectional view of an exemplary complementary metal oxide semiconductor (CMOS) device 200 having backside EMRAM in accordance with some embodiments of the present invention. The term EMRAM refers to embedded magnetoresistance RAM (MRAM). As previously mentioned, MRAM is a type of solid-state non-volatile memory that uses tunneling magnetoresistance to store information. The exemplary CMOS device 200 can include a backside 201, a bitline (BL) 202, contacts 204, a hard mask (HM) 206, a reference layer (RL) 208, a tunnel barrier (TB) 210, a free layer (FL) 212, a spin-Hall effect (SHE) rail 214, a BOX 216, contacts 218, a contact layer 220, a channel layer 222, a float layer 224, a high-k metal gate 226, a wordline 228, a bitline layer 230, a substrate 232, a dielectric encapsulation 234, and a dielectric fill 236.

[0024] Backside 201 represents the region of the transistors of exemplary CMOS device 200 opposite substrate 232. Bitlines 202 may be long lengths of conductive material useful for writing to a single bit of memory. Contacts 204 may be conductive structures that provide electrical contact between bitlines 202 and the transistors of exemplary CMOS device 200. Hard mask 206 may be a metal or dielectric material used to protect underlying layers from the etching process used to fabricate exemplary CMOS device 200.

[0025] The reference layer 208 can be a fixed layer whose magnetization does not change. Accordingly, when a current flows through the reference layer 208, the reference layer 208 produces a spin polarized current. Accordingly, the reference layer 208 can be made of cobalt iron boron (CoFeB). The tunnel barrier 210 can be a relatively thin insulating layer that increases the tunnel magnetoresistance. Accordingly, the tunnel barrier 210 can be made of magnesium oxide (MgO). The free layer 212 can be a layer whose magnetization can be changed. For example, when the magnetization direction of the free layer 212 is the same as the magnetization direction of the reference layer 208, the current through the junction is relatively high. However, when the magnetization direction of the free layer 212 is opposite to the magnetization direction of the reference layer 208, the current through the junction is relatively low, which is how a bit of memory is stored. Accordingly, the free layer 212 can be made of cobalt iron boron (CoFeB). The SHE rail 214 can provide a net transverse spin current and can be made of tantalum (Ta). The BOX 216 can represent a separation layer and can be made of silicon dioxide (SiO 2). In this manner, the reference layer 208, the tunnel barrier 210, and the free layer 212 can give rise to a magnetic tunnel junction (MTJ). The magnetic tunnel junction (MTJ) can include two magnetic metal layers (e.g., the reference layer 208 and the free layer 212) with an insulating layer (e.g., the tunnel barrier 210) that is thin enough to allow electrons to flow between the reference layer 208 and the free layer 212 when a bias voltage is applied between them. The MTJ can represent an MRAM cell. Accordingly, the MRAM cell is connected to the source-drain of the transistor by contacts 218 disposed on the backside of the wafer 200.

[0026] The contacts 218 may be similar to the contacts 204. The contact layer 220 includes the BOX 216 and the contacts 218. The channel layer 222 may include the five transistors of the exemplary CMOS device 200. The float layer 224 may hold the charge of the floating gate transistors of the channel layer 222. The high-k metal gate 226 allows current flow between the source and drain of the exemplary CMOS device 200. The word lines 228 are long conductive materials and may represent addresses in the memory. In response, a processing device may read a word of the memory by reading a particular word line 228. The bit line layer 230 may include bit lines (e.g., BL1 and BL2) for reading individual bits. The substrate 232 may be a layer of dielectric material such as silicon nitride (SiN). The channel layer 222, the float layer 224, and the bit line layer 230 may represent the FEOL of the wafer 200. The dielectric encapsulation 234 can be a dielectric material that encapsulates the hard mask 206, the reference layer 208, the tunnel barrier 210, and the free layer 212. The dielectric fill 236 can be silicon dioxide (SiO 2 ) may be a dielectric material.

[0027] 3 is a process flow of a method 300 of fabricating a CMOS device with backside EMRAM according to some embodiments of the present invention. In some embodiments, an example EMRAM fabrication manager, such as the example EMRAM fabrication manager 100 described with respect to FIG 1, may perform the method 300. For clarity, the method 300 is described with respect to FIGS. 4A-4J.

[0028] 4A is a block diagram of an exemplary fabrication state 400A of a wafer 400 according to some embodiments of the present invention. The wafer 400 may be a silicon wafer for a semiconductor device. In addition, the wafer 400 may include a BOX 416, a sacrificial plug 418-1, a contact 418, a contact layer 420, a float layer 424, a high-k metal gate 426, a word line 428, a bit line layer 430, and a substrate 432. The BOX 416, the contact 418, the contact layer 420, the float layer 424, the high-k metal gate 426, the word line 428, the bit line layer 430, and the substrate 432 may be similar to the BOX 216, the contact 218, the contact layer 220, the float layer 224, the high-k metal gate 226, the word line 228, the bit line layer 230, and the substrate 232 described with respect to FIG. The sacrificial plugs 418-1 may be silicon structures that a fabrication tool temporarily places in a wafer to create openings for placing contacts. In the exemplary fabrication state 400A, the backside 401 of the wafer 400 may point to the top of the contact layer 420. The exemplary fabrication state 400A may represent the wafer 400 after operation 302.

[0029] 3, in operation 302, the example EMRAM fabrication manager 100 can instruct the fabrication tool to perform a post-wafer flip and backside grind. The post-wafer flip can involve reversing the position of the wafer 400 within the fabrication tool (not shown). The backside grind can involve applying a polishing device to the backside 401 of the wafer 400 to remove silicon substrate material.

[0030] 4B is a block diagram of an exemplary fabrication state 400B of a wafer 400 according to some embodiments of the present invention. The wafer 400 may include a BOX 416, contacts 418, contact layer 420, float layer 424, high-k metal gate 426, word lines 428, bit line layer 430, and substrate 432. The BOX 416, contact layer 420, float layer 424, high-k metal gate 426, word lines 428, bit line layer 430, and substrate 432 may be similar to the BOX 216, contact layer 220, float layer 224, high-k metal gate 226, word lines 228, bit line layer 230, and substrate 232 described with respect to FIG. 2. The exemplary fabrication state 400B may represent the wafer 400 after operation 304.

[0031] 3, in operation 304, the EMRAM fabrication manager 100 can instruct the fabrication tool to perform sacrificial plug removal and backside contact formation. In response, the EMRAM fabrication manager 100 can instruct the fabrication tool to remove the sacrificial plug 418-1 described with respect to FIG. 4A and form the contact 418 in its place in the contact layer 420.

[0032] 4C is a block diagram of an exemplary fabrication state 400C of a wafer 400 according to some embodiments of the present invention. The wafer 400 can include a SHE rail 414, a BOX 416, contacts 418, a contact layer 420, a float layer 424, a high-k metal gate 426, a word line 428, a bit line layer 430, and a substrate 432. The SHE rail 414, the BOX 416, the contact layer 420, the float layer 424, the high-k metal gate 426, the word line 428, the bit line layer 430, and the substrate 432 can be similar to the SHE rail 214, the BOX 216, the contact layer 220, the float layer 224, the high-k metal gate 226, the word line 228, the bit line layer 230, and the substrate 232, respectively, described with respect to FIG. 2. The exemplary fabrication state 400C can represent the wafer 400 after operation 306.

[0033] 3, in operation 306, the EMRAM fabrication manager 100 can instruct the fabrication tool to perform a heavy metal SHE rail deposition. Performing a heavy metal SHE rail deposition can involve depositing a metal rail on the contact layer 420 to form the SHE rail 414.

[0034] 4D is a block diagram of an exemplary fabrication state 400D of a wafer 400 according to some embodiments of the present invention. The wafer 400 can include a hard mask 406, a reference layer 408, a tunnel barrier 410, a free layer 412, a SHE rail 414, a BOX 416, contacts 418, a contact layer 420, a float layer 424, a high-k metal gate 426, a wordline 428, a bitline layer 430, and a substrate 432. The hard mask 406, the reference layer 408, the tunnel barrier 410, the free layer 412, the SHE rail 414, the BOX 416, the contact layer 420, the float layer 424, the high-k metal gate 426, the word lines 428, the bit line layer 430, and the substrate 432 may be similar to the hard mask 206, the reference layer 208, the tunnel barrier 210, the free layer 212, the SHE rail 214, the BOX 216, the contact layer 220, the float layer 224, the high-k metal gate 226, the word lines 228, the bit line layer 230, and the substrate 232, respectively, described with respect to Figure 2. The exemplary fabrication state 400D may represent the wafer 400 after operation 308.

[0035] 3, in operation 308, the EMRAM fabrication manager 100 can direct the fabrication tool to perform a magnetic tunnel junction (MTJ) stack deposition. Performing the MTJ stack deposition can involve depositing a free layer 412, a tunnel barrier 410, a reference layer 408, and a hard mask 406 on a SHE rail 414.

[0036] 4E is a block diagram of an exemplary fabrication state 400E of a wafer 400 according to some embodiments of the present invention. The wafer 400 can include a hard mask 406, a reference layer 408, a tunnel barrier 410, a free layer 412, a SHE rail 414, a BOX 416, contacts 418, a contact layer 420, a float layer 424, a high-k metal gate 426, a wordline 428, a bitline layer 430, a substrate 432, and an ion beam etched (IBE) pillar 438. The hard mask 406, the reference layer 408, the tunnel barrier 410, the free layer 412, the SHE rail 414, the BOX 416, the contact layer 420, the float layer 424, the high-k metal gate 426, the word lines 428, the bit line layer 430, and the substrate 432 may be similar to the hard mask 206, the reference layer 208, the tunnel barrier 210, the free layer 212, the SHE rail 214, the BOX 216, the contact layer 220, the float layer 224, the high-k metal gate 226, the word lines 228, the bit line layer 230, and the substrate 232, respectively, described with respect to FIG. 2. The IBE pillars 438 may be patterning of the hard mask 406, the reference layer 408, the tunnel barrier 410, and the free layer 412. The exemplary fabrication state 400E may represent the wafer 400 after operation 310.

[0037] 3, in operation 310, the EMRAM fabrication manager 100 can instruct a fabrication tool to perform MTJ patterning and IBE pillar formation. Performing MTJ patterning and IBE pillar formation can involve directing a beam of charged particles (ions) to the MTJ with a patterned mask (e.g., the hard mask 406, reference layer 408, tunnel barrier 410, and free layer 412 described with reference to FIG. 4D) in an elevated chamber. In this manner, the fabrication tool can form the IBE pillars 438.

[0038] 4F is a block diagram of an exemplary fabrication state 400F of a wafer 400 in accordance with some embodiments of the present invention. The wafer 400 can include a hard mask 406, a reference layer 408, a tunnel barrier 410, a free layer 412, a SHE rail 414, a BOX 416, contacts 418, a contact layer 420, a float layer 424, a high-k metal gate 426, a wordline 428, a bitline layer 430, a substrate 432, an IBE pillar 438, and a dielectric encapsulation 434. The hard mask 406, the reference layer 408, the tunnel barrier 410, the free layer 412, the SHE rail 414, the BOX 416, the contact layer 420, the float layer 424, the high-k metal gate 426, the word lines 428, the bit line layer 430, and the substrate 432 may be similar to the hard mask 206, the reference layer 208, the tunnel barrier 210, the free layer 212, the SHE rail 214, the BOX 216, the contact layer 220, the float layer 224, the high-k metal gate 226, the word lines 228, the bit line layer 230, and the substrate 232, respectively, described with respect to FIG. 2. The dielectric encapsulation 434 may be a layer of dielectric material. The exemplary fabrication state 400F may represent the wafer 400 after operation 312.

[0039] 3, in operation 312, the EMRAM fabrication manager 100 can instruct the fabrication tool to perform a dielectric encapsulation. Performing the dielectric encapsulation can involve depositing a layer of dielectric material over the IBE pillars 438 and the SHE rails 414 to leave a dielectric encapsulation 434.

[0040] 4G is a block diagram of an exemplary fabrication state 400G of a wafer 400 in accordance with some embodiments of the present invention. The wafer 400 can include a hard mask 406, a reference layer 408, a tunnel barrier 410, a free layer 412, a SHE rail 414, a BOX 416, contacts 418, a contact layer 420, a float layer 424, a high-k metal gate 426, a wordline 428, a bitline layer 430, a substrate 432, and a dielectric encapsulation 434. The hard mask 406, reference layer 408, tunnel barrier 410, free layer 412, SHE rail 414, BOX 416, contact layer 420, float layer 424, high-k metal gate 426, wordline 428, bitline layer 430, substrate 432, and dielectric encapsulation 434 may be similar to the hard mask 206, reference layer 208, tunnel barrier 210, free layer 212, SHE rail 214, BOX 216, contact layer 220, float layer 224, high-k metal gate 226, wordline 228, bitline layer 230, substrate 232, and dielectric encapsulation 234, respectively, described with respect to Figure 2. Exemplary fabrication state 400G may represent the wafer 400 after operation 314.

[0041] 3, in operation 314, the EMRAM fabrication manager 100 can instruct the fabrication tool to perform a reactive ion etch (RIE) of the self-aligned encapsulation dielectric and the formation of the SHE rails. Performing the reactive ion etch (RIE) of the self-aligned encapsulation dielectric and the formation of the SHE rails can involve a plasma etch that accelerates ions toward the dielectric encapsulation 434 and the SHE rails 414 to remove deposited material, as shown.

[0042] 4H is a block diagram of an exemplary fabrication state 400H of a wafer 400 according to some embodiments of the present invention. The wafer 400 can include a backside surface 401, a hard mask 406, a reference layer 408, a tunnel barrier 410, a free layer 412, a SHE rail 414, a BOX 416, contacts 418, a contact layer 420, a float layer 424, a high-k metal gate 426, a wordline 428, a bitline layer 430, a substrate 432, a dielectric encapsulation 434, and a dielectric fill 436. The hard mask 406, the reference layer 408, the tunnel barrier 410, the free layer 412, the SHE rail 414, the BOX 416, the contact layer 420, the float layer 424, the high-k metal gate 426, the word lines 428, the bit line layer 430, the substrate 432, the dielectric encapsulation 234, and the dielectric fill 436 may be similar to the hard mask 206, the reference layer 208, the tunnel barrier 210, the free layer 212, the SHE rail 214, the BOX 216, the contact layer 220, the float layer 224, the high-k metal gate 226, the word lines 228, the bit line layer 230, the substrate 232, the dielectric encapsulation 234, and the dielectric fill 236, respectively, described with respect to Figure 2. The exemplary fabrication state 400H may represent the wafer 400 after operation 316.

[0043] 3, in operation 316, the EMRAM fabrication manager 100 can instruct the fabrication tool to perform inter-layer dielectric (ILD) fill and chemical mechanical polishing (CMP). Performing the ILD fill can involve depositing a dielectric material layer (e.g., dielectric fill 436) on the backside 401 of the wafer 400. Additionally, CMP can involve smoothing the surfaces of the dielectric encapsulation 434 and the dielectric fill 436 by application of chemicals and mechanical forces.

[0044] 4I is a block diagram of an exemplary fabrication state 400I of a wafer 400 according to some embodiments of the present invention. The wafer 400 can include a backside 401, bitlines 402, contacts 404, a hard mask 406, a reference layer 408, a tunnel barrier 410, a free layer 412, a SHE rail 414, a BOX 416, contacts 418, a contact layer 420, a float layer 424, a high-k metal gate 426, wordlines 428, a bitline layer 430, a substrate 432, a dielectric encapsulation 434, and a dielectric fill 436. The bitlines 402, contacts 404, hard mask 406, reference layer 408, tunnel barrier 410, free layer 412, SHE rail 414, BOX 416, contact layer 420, float layer 424, high-k metal gate 426, wordlines 428, bitline layer 430, substrate 432, dielectric encapsulation 434, and dielectric fill 436 may be similar to the bitlines 202, contacts 204, hard mask 206, reference layer 208, tunnel barrier 210, free layer 212, SHE rail 214, BOX 216, contact layer 220, float layer 224, high-k metal gate 226, wordlines 228, bitline layer 230, substrate 232, dielectric encapsulation 234, and dielectric fill 236, respectively, described with respect to Figure 2. Exemplary fabrication state 400I may represent the wafer 400 after operation 318.

[0045] 3, in operation 318, the EMRAM fabrication manager 100 can instruct the fabrication tool to perform MTJ top contact landing. Performing the MTJ top contact landing can involve forming contacts 404 on a hard mask 406 and forming bitlines 402 on the contacts 404. Accordingly, the wafer 400 can be similar to the exemplary CMOS device 200 with backside EMRAM described with respect to FIG.

[0046] 4J is a side perspective view of a wafer 400J having a CMOS device including backside EMRAM according to some embodiments of the present invention. The wafer 400J may be similar to the wafer 400 in an exemplary fabrication state 400I and the exemplary CMOS device 200 having backside EMRAM. Additionally, the wafer 400J represents the path of electrons during read and write operations to the wafer 400J. Accordingly, the wafer 400J includes a bit line 402, a contact 404, a reference layer 408, a tunnel barrier 410, a free layer 412, a channel layer 422, a word line 428, a bit line 1 (BL1), and a bit line 2 (BL2). The flow of electrons during a read operation is represented by line 400R. Additionally, the flow of electrons during a write operation is represented by line 400W.

[0047] Additionally, method 300 may be performed for additional contacts and / or MTJ stacks in embodiments having more than those shown in wafer 400. Such embodiments are described with respect to Figures 5, 6A, 6B, 7, and 8.

[0048] 5 is a cross-sectional view of an exemplary CMOS device 500 having backside EMRAM in accordance with some embodiments of the present invention. The exemplary CMOS device 500 can include a backside 501, a bitline 502, a contact 504, a hard mask 506, a reference layer 508, a tunnel barrier 510, a free layer 512, a SHE rail 514, a BOX 516, a contact 518, a contact layer 520, a channel layer 522, a float layer 524, a high-k metal gate 526, a wordline 528, a bitline layer 530, a substrate 532, a dielectric encapsulation 534, and a dielectric fill 536. The bitline 502, contact 504, hard mask 506, reference layer 508, tunnel barrier 510, free layer 512, SHE rail 514, BOX 516, contact layer 520, channel layer 522, float layer 524, high-k metal gate 526, wordline 528, bitline layer 530, substrate 532, dielectric encapsulation 534, and dielectric fill 536 may be similar to the bitline 202, contact 204, hard mask 206, reference layer 208, tunnel barrier 210, free layer 212, SHE rail 214, BOX 216, contact layer 220, channel layer 222, float layer 224, high-k metal gate 226, wordline 228, bitline layer 230, substrate 232, dielectric encapsulation 234, and dielectric fill 236, respectively, described with respect to FIG. 2 .

[0049] In contrast to the exemplary CMOS device 200 with backside EMRAM, the contact layer 520 can include four BOXes 516, the channel layer 522 can include seven transistors, and the float layer 524 can include four contacts 518. In addition, the bit line layer 530 can include four bit lines, each bit line being associated with one of the contacts 518 in the float layer 524. In this manner, the CMOS device 500 can include one more transistor for each contact 518 than the CMOS device 200. Accordingly, the additional transistor can improve the flow of current to the SHE rail 514, and thus the ability to flip the MTJ (e.g., the free layer 512, the tunnel barrier 510, and the reference layer 508). In this manner, the wafer 500 allows for more current to be driven into the SHE rail 514 than the SHE rail 414 described with respect to FIG. 4. This capability is also referred to herein as a high drive current.

[0050] 6A is a cross-sectional view of an exemplary CMOS device 600A having backside EMRAM in accordance with some embodiments of the present invention. The exemplary CMOS device 600A can include a backside 601, a bitline 602, a contact 604, a hard mask 606, a reference layer 608, a tunnel barrier 610, a free layer 612, a SHE rail 614, a BOX 616, a contact 618, a contact layer 620, a channel layer 622, a float layer 624, a high-k metal gate 626, a wordline 628, a bitline layer 630, a substrate 632, a dielectric encapsulation 634, and a dielectric fill 636. The bitline 602, contact 604, hard mask 606, reference layer 608, tunnel barrier 610, free layer 612, SHE rail 614, BOX 616, contact layer 620, channel layer 622, float layer 624, high-k metal gate 626, wordline 628, bitline layer 630, substrate 632, dielectric encapsulation 634, and dielectric fill 636 may be similar to the bitline 202, contact 204, hard mask 206, reference layer 208, tunnel barrier 210, free layer 212, SHE rail 214, BOX 216, contact layer 220, channel layer 222, float layer 224, high-k metal gate 226, wordline 228, bitline layer 230, substrate 232, dielectric encapsulation 234, and dielectric fill 236, respectively, described with respect to FIG. 2 .

[0051] In contrast to the exemplary CMOS device 200 with backside EMRAM, the backside 601 can include two IBE pillars 638. Accordingly, one contact 604 and bitline 602 can be disposed on top of each IBE pillar 638. In some embodiments of the present invention, the exemplary CMOS device 600A can represent a spin-transfer torque MRAM or a voltage-controlled MRAM (VC-MRAM). VC-MRAM is a type of spin-orbit torque MRAM with a three-terminal design.

[0052] 6B is a side perspective view 600B of a CMOS device 600A with backside EMRAM. Accordingly, the side perspective view 600B shows the bit line 602, the contact 604, the hard mask 606, the free layer 612, and the tunnel barrier 610. Additionally, when performing read and write operations, the flow of electrons can follow lines 600R and 600W, respectively.

[0053] 7 is a cross-sectional view of an exemplary CMOS device 700 having backside EMRAM in accordance with some embodiments of the present invention. The exemplary CMOS device 700 can include a backside 701, a bitline 702, a contact 704, a hard mask 706, a reference layer 708, a tunnel barrier 710, a free layer 712, a SHE rail 714, a BOX 716, a contact 718, a contact layer 720, a channel layer 722, a float layer 724, a high-k metal gate 726, a wordline 728, a bitline layer 730, a substrate 732, a dielectric encapsulation 734, and a dielectric fill 736. The bitline 702, contact 704, hard mask 706, reference layer 708, tunnel barrier 710, free layer 712, SHE rail 714, BOX 716, contact 718, contact layer 720, channel layer 722, float layer 724, high-k metal gate 726, wordline 728, bitline layer 730, substrate 732, dielectric encapsulation 734, and dielectric fill 736 may be similar to the bitline 202, contact 204, hard mask 206, reference layer 208, tunnel barrier 210, free layer 212, SHE rail 214, BOX 216, contact 218, contact layer 220, channel layer 222, float layer 224, high-k metal gate 226, wordline 228, bitline layer 230, substrate 232, dielectric encapsulation 234, and dielectric fill 236, respectively, described with respect to FIG. 2 .

[0054] In contrast to the exemplary CMOS device 200 with backside EMRAM, the backside 701 may include two IBE pillars 738. Accordingly, one contact 704 and bitline 702 may be disposed on top of each IBE pillar 738. In addition, the contact layer 720 includes five BOXes 716 and four contacts 718. Accordingly, the bitline layer 730 includes four bitlines.

[0055] 8 is a cross-sectional view of an exemplary CMOS device 800 having backside EMRAM in accordance with some embodiments of the present invention. The exemplary CMOS device 800 can include a backside 801, a bitline 802, a contact 804, a hard mask 806, a reference layer 808, a tunnel barrier 810, a free layer 812, a SHE rail 814, a BOX 816, a contact 818, a contact layer 820, a channel layer 822, a float layer 824, a high-k metal gate 826, a wordline 828, a bitline layer 830, a substrate 832, a dielectric encapsulation 834, and a dielectric fill 836. The bitline 802, contact 804, hard mask 806, reference layer 808, tunnel barrier 810, free layer 812, SHE rail 814, BOX 816, contact 818, contact layer 820, channel layer 822, float layer 824, high-k metal gate 826, wordline 828, bitline layer 830, substrate 832, dielectric encapsulation 834, and dielectric fill 836 may be similar to the bitline 202, contact 204, hard mask 206, reference layer 208, tunnel barrier 210, free layer 212, SHE rail 214, BOX 216, contact 218, contact layer 220, channel layer 222, float layer 224, high-k metal gate 226, wordline 228, bitline layer 230, substrate 232, dielectric encapsulation 234, and dielectric fill 236, respectively, described with respect to FIG. 2 .

[0056] In contrast to the exemplary CMOS device 200 with backside EMRAM, the backside 801 may include two IBE pillars 838. Accordingly, one contact 804 and bitline 802 may be disposed on top of each IBE pillar 838. In addition, the contact layer 820 includes five BOXes 816 and two contacts 818. Further, accordingly, the float layer 824 includes four contacts 818 and the bitline layer 830 includes four bitlines.

[0057] The present invention may be a system, method, and / or computer program product at any possible level of integration of technical detail. The computer program product may include a computer readable storage medium (or multiple computer readable storage media) having computer readable program instructions for causing a processor to implement aspects of the present invention.

[0058] A computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media includes: portable computer diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or grooved structures having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transitory signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over electrical wires.

[0059] The computer readable program instructions described herein may be downloaded from a computer readable storage medium into each computing / processing device or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing / processing device.

[0060] The computer readable program instructions for carrying out the operations of the present invention may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state configuration data, configuration data for integrated circuits, or object oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer as a standalone software package, partly on the user's computer and partly on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions to individualize the electronic circuitry by utilizing state information of the computer readable program instructions to perform aspects of the invention.

[0061] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0062] These computer readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute on the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may also be stored on a computer readable storage medium having instructions stored thereon to instruct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer readable storage medium having the instructions stored thereon comprises an article of manufacture including instructions for implementing aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0063] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operable steps to create a computer-implemented process such that the instructions, which execute on the computer, other programmable apparatus, or other device, implement the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0064] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may actually be performed as one step, or may be performed simultaneously, substantially simultaneously, partially or fully in a time-overlapping manner, or the blocks may sometimes be performed in reverse order depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flow diagrams, as well as combinations of blocks in the block diagrams and / or flow diagrams, may be implemented by a system based on special purpose hardware that performs the specified functions or operations or executes a combination of special purpose hardware and computer instructions.

[0065] A non-limiting list of examples consistent with embodiments of the invention is provided below: Example 1 is a system. The system includes a wafer, a plurality of transistors disposed on the front end of the line (FEOL) of the wafer, and a magnetoresistive random access memory (MRAM) cell disposed on the wafer, the MRAM cell disposed on a backside of the wafer, the MRAM cell connected to a source-drain of the transistor by a contact disposed on the backside of the wafer, and the plurality of transistors in direct electrical contact with the MRAM cell by at least one contact.

[0066] Example 2 includes the system of example 1 and includes or excludes optional features. In this example, the MRAM cell includes a magnetic tunnel junction, the magnetic tunnel junction including a reference layer, a tunnel barrier, and a free layer.

[0067] Example 3 includes the system of any one of examples 1-2, including or excluding optional features. In this example, the transistors are in direct electrical contact with the MRAM cells by contacts for high drive current.

[0068] Example 4 includes the system of any one of examples 1-3, including or excluding optional features. In this example, the plurality of transistors are in direct electrical contact with the plurality of word and bit lines by the plurality of contacts for high drive current.

[0069] Example 5 includes the system of any one of examples 1-4, including or excluding optional features. In this example, the system includes an additional MRAM cell including an additional magnetic tunnel junction. Optionally, the plurality of transistors are in direct electrical contact with the additional MRAM cell by at least one contact. Optionally, the MRAM cell comprises spin transfer torque MRAM. Optionally, the MRAM cell comprises voltage-controlled MRAM.

[0070] Example 6 is a system including a wafer, a plurality of transistors disposed on a front end of line (FEOL) of the wafer, a first magnetoresistive random access memory (MRAM) cell disposed on a backside of the wafer, the first MRAM cell being connected to a source-drain of the transistor by a first contact disposed on the backside of the wafer, the plurality of transistors being in direct electrical contact with the first MRAM cell, and a second MRAM cell disposed on the backside of the wafer, the second MRAM cell being connected to a source-drain of the transistor by a second contact disposed on the backside of the wafer, the plurality of transistors being in direct electrical contact with the second MRAM cell.

[0071] Example 7 includes the system of Example 6, including or excluding optional features. In this example, the first MRAM cell and the second MRAM cell comprise a magnetic tunnel junction, the magnetic tunnel junction including a reference layer, a tunnel barrier, and a free layer.

[0072] Example 8 includes the system of any one of examples 6-7, including or excluding optional features. In this example, the plurality of transistors are in direct electrical contact with the first MRAM cell and the second MRAM cell by the plurality of contacts for high drive current.

[0073] Example 9 includes the system of any one of examples 6-8, including or excluding optional features. In this example, the plurality of transistors are in direct electrical contact with the plurality of word and bit lines by a plurality of contacts for high drive current.

[0074] Example 10 includes the system of any one of examples 6-9, including or excluding optional features. In this example, the first MRAM cell and the second MRAM cell comprise spin-transfer torque MRAM.

[0075] Example 11 includes the system of any one of examples 6 to 10, including or excluding optional features. In this example, the first MRAM cell and the second MRAM cell comprise voltage-controlled MRAM.

[0076] Example 12 is a system including a wafer, a plurality of transistors disposed on a front end of line (FEOL) of the wafer, a first magnetoresistive random access memory (MRAM) cell disposed on a backside of the wafer, the first MRAM cell being connected to a source-drain of the transistor by a first contact disposed on the backside of the wafer, the plurality of transistors being in direct electrical contact with the first MRAM cell, and a second MRAM cell disposed on the backside of the wafer, the second MRAM cell being connected to a source-drain of the transistor by a second contact disposed on the backside of the wafer, the plurality of transistors being in direct electrical contact with the second MRAM cell, the plurality of transistors being in direct electrical contact with the first MRAM cell and the second MRAM cell by a plurality of contacts for high drive current. Optionally, the first MRAM cell and the second MRAM cell comprise magnetic tunnel junctions, the magnetic tunnel junctions including a reference layer, a tunnel barrier, and a free layer.

[0077] Example 13 includes the system of example 12, including or excluding optional features. In this example, the plurality of transistors are in direct electrical contact with the plurality of word and bit lines by the plurality of contacts for high drive current.

[0078] Example 14 includes the system of any one of examples 12-13, including or excluding optional features. In this example, the first MRAM cell and the second MRAM cell comprise spin-transfer torque MRAM.

[0079] Example 15 includes the system of any one of examples 12-14, including or excluding optional features. In this example, the first MRAM cell and the second MRAM cell comprise voltage-controlled MRAM.

[0080] Example 16 is a computer program product including program instructions stored on a computer readable storage medium, the computer readable medium including instructions to direct a processor to perform post-wafer flip of a wafer including a plurality of transistors disposed at a front end of line (FEOL) of the wafer, perform backside grinding of the wafer, remove a plurality of sacrificial plugs from a backside of the wafer and form a plurality of contacts in place of the sacrificial plugs, perform deposition of a heavy metal spin Hall effect (SHE) rail at the backside of the wafer to generate the SHE rail, perform deposition of a magnetic tunnel junction (MTJ) stack on the SHE rail to generate the MTJ stack, perform patterning of the MTJs on the MTJ stack, perform formation of an IBE pillar on the patterned MTJ stack to generate the IBE pillar, perform dielectric encapsulation on the SHE rail and the IBE pillar, perform reactive ion etching (RIE) of a self-aligned encapsulation dielectric and formation of the SHE rail, perform interlayer dielectric (ILD) fill and chemical mechanical polishing (CMP) on the IBE pillar and the SHE rail, and perform landing of the MTJ top contact on the IBE pillar.

[0081] Example 17 includes the computer-readable medium of Example 16, including or excluding optional features. In this example, the computer-readable medium includes instructions directing a processor to perform deposition of an additional MTJ stack on the SHE rail to generate an additional MTJ stack, perform MTJ patterning on the additional MTJ stack, perform formation of an IBE pillar on the patterned additional MTJ stack to generate an additional IBE pillar, perform dielectric encapsulation on the SHE rail and the additional IBE pillar, perform ILD fill and CMP on the additional IBE pillar, and perform landing of an MTJ top contact on the additional IBE pillar.

[0082] Example 18 includes the computer-readable medium of any one of Examples 16-17, including or excluding optional features. In this example, forming the plurality of contacts in place of the sacrificial plug includes forming a plurality of contacts to one of the transistors, such that the plurality of contacts formed are configured to carry a high drive current.

[0083] Example 19 is a method of fabricating a complementary metal oxide semiconductor (CMOS) with backside MRAM, the method including performing post-wafer flip of a wafer with a plurality of transistors disposed on a front-end-of-line (FEOL) of the wafer, performing backside grinding of the wafer, removing a plurality of sacrificial plugs from a backside of the wafer, forming a plurality of contacts in place of the sacrificial plugs, performing deposition of a heavy metal spin-hall-effect (SHE) rail on the backside of the wafer to generate the SHE rail, performing deposition of a magnetic tunnel junction (MTJ) stack on the SHE rail to generate the MTJ stack, performing patterning of the MTJ on the MTJ stack, performing formation of an IBE pillar on the patterned MTJ stack to generate the IBE pillar, performing dielectric encapsulation on the SHE rail and the IBE pillar, performing reactive ion etching (RIE) of a self-aligned encapsulation dielectric and formation of the SHE rail, performing interlayer dielectric (ILD) fill and chemical mechanical polishing (CMP) on the IBE pillar and the SHE rail, and performing landing of the MTJ top contact on the IBE pillar.

[0084] Example 20 includes the method of example 19, including or excluding optional features. In this example, the method includes performing deposition of an additional MTJ stack on the SHE rail to produce an additional MTJ stack, performing MTJ patterning on the additional MTJ stack, performing IBE pillar formation on the patterned additional MTJ stack to produce an additional IBE pillar, performing dielectric encapsulation on the SHE rail and the additional IBE pillar, performing ILD fill and CMP on the additional IBE pillar, and performing MTJ top contact landing on the additional IBE pillar.

[0085] Example 21 includes the method of any one of examples 19-20, including or excluding optional features. In this example, forming a plurality of contacts in place of the sacrificial plug includes forming a plurality of contacts to one of the transistors, such that the plurality of contacts formed are configured to carry a high drive current.

Claims

1. A wafer; a plurality of transistors disposed on a front end of line (FEOL) of the wafer; a magnetoresistive random access memory (MRAM) cell disposed on the wafer; Equipped with the MRAM cell is disposed on a backside of the wafer; the MRAM cells are connected to the source-drain of the transistor by contacts disposed on the backside of the wafer; the plurality of transistors are in direct electrical contact with the MRAM cells; system.

2. The MRAM cell comprises a magnetic tunnel junction, the magnetic tunnel junction comprising: A reference layer; A tunnel barrier; The free class The system of claim 1 , comprising:

3. 10. The system of claim 1, wherein the plurality of transistors are in direct electrical contact with the MRAM cells by a plurality of contacts for high drive current.

4. 2. The system of claim 1, wherein the plurality of transistors are in direct electrical contact with a plurality of word bitlines by a plurality of contacts for high drive current.

5. The system of claim 1 , wherein the system comprises an additional MRAM cell including an additional magnetic tunnel junction.

6. The system of claim 5 , wherein the plurality of transistors are in direct electrical contact with the additional MRAM cell by at least one contact.

7. The system of claim 5 , wherein the MRAM cell comprises a spin transfer torque MRAM cell.

8. The system of claim 5 , wherein the MRAM cells comprise voltage-controlled MRAM cells.

9. 2. The system of claim 1, wherein the MRAM cell is a first MRAM cell connected to the source-drain of the transistor by a first contact disposed on the backside of the wafer, the system further comprising a second MRAM cell disposed on the backside of the wafer, the second MRAM cell connected to the source-drain of the transistor by a second contact disposed on the backside of the wafer, and the plurality of transistors in direct electrical contact with the second MRAM cell.

10. The first MRAM cell and the second MRAM cell comprise a magnetic tunnel junction, the magnetic tunnel junction comprising: A reference layer; A tunnel barrier; The free class The system of claim 9 , comprising:

11. 10. The system of claim 9, wherein the plurality of transistors are in direct electrical contact with the first MRAM cell and the second MRAM cell by a plurality of contacts for high drive current.

12. 10. The system of claim 9, wherein the plurality of transistors are in direct electrical contact with a plurality of word bitlines by a plurality of contacts for high drive current.

13. The system of claim 9 , wherein the first MRAM cell and the second MRAM cell comprise spin transfer torque MRAM.

14. 10. The system of claim 9, wherein the first MRAM cell and the second MRAM cell comprise voltage-controlled MRAM.

15. 2. The system of claim 1, wherein the MRAM cell is a first MRAM cell connected to a source-drain of the transistor by a first contact disposed on the backside of the wafer, the system further comprising a second MRAM cell disposed on the backside of the wafer, the second MRAM cell connected to the source-drain of the transistor by a second contact disposed on the backside of the wafer, the plurality of transistors in direct electrical contact with the second MRAM cell, and the plurality of transistors in direct electrical contact with the first MRAM cell and the second MRAM cell by a plurality of contacts for high drive current.

16. The first MRAM cell and the second MRAM cell comprise a magnetic tunnel junction (MTJ), the MTJ comprising: A reference layer; A tunnel barrier; The free class The system of claim 15 , comprising:

17. 17. The system of claim 16, wherein an ion beam etched (IBE) pillar comprises the MTJ.

18. The system of claim 15 , wherein the first MRAM cell and the second MRAM cell comprise spin transfer torque MRAM.

19. 16. The system of claim 15, wherein the first MRAM cell and the second MRAM cell comprise voltage-controlled MRAM.

20. 1. A method for fabricating a complementary metal oxide semiconductor (CMOS) with backside MRAM, comprising: performing a post-wafer flip of the wafer, the wafer comprising a plurality of transistors disposed at a front end of line (FEOL) of the wafer; performing back grinding of the wafer; removing a plurality of sacrificial plugs from a backside of the wafer; forming a plurality of contacts in place of the sacrificial plug; generating a heavy metal spin Hall effect (SHE) rail by performing a deposition of a SHE rail on the backside of the wafer; performing deposition of a magnetic tunnel junction (MTJ) stack on the SHE rail to produce an MTJ stack; performing MTJ patterning on the MTJ stack; performing an IBE pillar formation on the patterned MTJ stack to generate an IBE pillar; performing a dielectric encapsulation on the SHE rail and the IBE pillar; performing a reactive ion etch (RIE) of a self-aligned encapsulation dielectric and formation of an SHE rail; performing an inter-layer dielectric (ILD) fill and chemical mechanical polishing (CMP) on the IBE pillars and the SHE rails; performing a landing of an MTJ top contact on the IBE pillar; The method includes:

21. performing deposition of an additional MTJ stack on the SHE rail to create an additional MTJ stack; performing MTJ patterning on the additional MTJ stack; and performing an IBE pillar formation on the patterned additional MTJ stack to generate an additional IBE pillar; performing a dielectric encapsulation on the SHE rail and the additional IBE pillar; performing ILD fill and CMP on the additional IBE pillars; performing a landing of an MTJ top contact on the additional IBE pillar; 21. The method of claim 20, further comprising:

22. 21. The method of claim 20, wherein forming the plurality of contacts in place of the sacrificial plug comprises forming a plurality of contacts to one of the transistors, such that the formed plurality of contacts are configured to carry a high drive current.

23. 23. A computer program product comprising program instructions stored on a computer readable storage medium, said program instructions being executable by a processor to cause said processor to perform a method according to any one of claims 20 to 22.

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